HK1199139B - Non-volatile semiconductor memory having multiple external power supplies - Google Patents

Description

Non-volatile semiconductor memory with multiple external power supplies

The present application is a divisional application entitled "nonvolatile semiconductor memory having a plurality of external power supplies" having application No. 200880005233.3, and having an application date of 2008, month 2 and 12.

Background

Today, many electronic devices include memory systems to hold information. For example, some memory systems store digitized audio or video information for playback by a corresponding media player. Other memory systems store software and related information to perform different types of processing functions.

In many electronic devices, a memory system typically includes a controller and one or more corresponding flash memory devices. The controller typically includes circuitry configured to generate signals to the memory device to save and retrieve data from the flash memory device.

Conventional flash memory devices typically include a single power input pin to receive power from an external power source. Power is typically received at a selected voltage level, such as 3.3 volts. Because the access and programming operations associated with flash memory require different voltages, flash memory devices are typically configured to include one or more power-to-voltage converters to generate any internal voltages necessary to operate the flash memory device. For example, conventional flash memory devices typically include power converter circuitry to convert a 3.3 volt input to other internally used voltages, such as 5 volts, 7 volts, 12 volts, and so forth.

Drawings

By way of example, reference will be made to the accompanying drawings in which:

FIG. 1 is a diagram of an example of a memory device including multiple power inputs according to embodiments herein;

FIG. 2 is a diagram of an example of a memory device including cross-sharing of multiple power inputs and voltages according to embodiments herein;

FIG. 3 is an example diagram of a memory device including a detector circuit for selecting an input power source for generating an internal voltage according to embodiments herein;

FIG. 4 is an example diagram illustrating a memory device and corresponding example components according to embodiments herein;

FIG. 5 is a diagram of an example of a memory system including one or more memory devices according to an embodiment herein;

FIG. 6 is a diagram illustrating an example of a voltage converter circuit;

FIG. 7 is a diagram illustrating an example of a power management circuit according to embodiments herein;

FIG. 8 is a diagram illustrating an example of an erase operation with respect to a memory cell;

FIG. 9 is a diagram illustrating an example of a cell programming operation;

FIG. 10 is a diagram illustrating an example of a read of an erased cell;

FIG. 11 is a diagram illustrating an example of a read of a programmed cell;

FIG. 12 is a diagram illustrating an example of bias conditions during reading a page;

FIG. 13 is a diagram illustrating an example of a block erase operation;

FIG. 14 is a diagram illustrating an example of a page program operation;

FIG. 15 is a diagram illustrating an example of page program bias conditions;

fig. 16 is a diagram illustrating an example of a block decoder; and

17-19 are example methods associated with one or more memory devices and/or memory systems according to embodiments herein.

Detailed Description

There are certain deficiencies associated with generating internal power signals in conventional memory devices. For example, as discussed above, conventional memory devices now use a single primary input voltage, such as 3.3 volts, to power flash memory in the memory device. Internally, the 3.3 volt input is converted to a plurality of higher voltage levels that are used for operations such as reading data from the flash memory, programming the flash memory, erasing the flash memory, and the like.

In order to convert this primary input voltage to a higher voltage, conventional memory devices typically include one or more so-called charge pump circuits. During operation, each of the one or more charge pumps converts the primary input voltage (i.e., 3.3 volts) to a particular higher voltage level for use by the flash memory to perform different memory operations.

Generally, the conversion efficiency of a charge pump deteriorates exponentially for large differences between the input voltage and the generated output voltage. For example, the conversion efficiency of a charge pump that converts an input of 3.3 volts to an output of 20 volts is lower than the conversion efficiency of a charge pump that converts an input of 3.3 volts to an output of 7 volts.

There is a current trend to produce circuit devices that operate at lower and lower voltages. For example, previous techniques required a 5 volt power supply to operate the core memory of the corresponding memory device. As mentioned above, the technology of conventional flash memory devices currently requires a 3.3 volt power supply in order to provide power to the corresponding core memory. It is expected that future memory devices will operate at an input of, for example, 1.8 volts or even lower power sources. Currently, the high voltage required to perform memory operations with respect to the core memory is not reduced proportionally with the voltage required to power the core memory. In other words, even if the core memory is operating at a lower voltage, such as 1.8 volts, the core memory may still require a voltage in the range between 5 and 20 volts in order to perform the memory operation.

Configuring the core flash memory to operate at low voltages, such as 1.8 volts (or even lower), reduces the amount of power expended to power the core memory device. However, converting this low or lower voltage input (e.g., 1.8 volts) to a higher voltage in the same range, e.g., between 5 and 20 volts, to enable memory operation would result in a negative impact of reducing the converter efficiency, increasing the size and complexity of the corresponding charge pump circuitry required to convert the range of 1.8 volts to a higher voltage, and/or reducing the read/program/erase performance of the memory device.

In general, embodiments herein include memory devices and/or memory systems that overcome the deficiencies discussed above, and/or other deficiencies known in the art. For example, according to embodiments herein, the memory device includes a core memory for storing data, such as a flash memory. The memory device includes a first power input to receive a first voltage for providing power to at least the core memory (e.g., flash memory). In addition, the memory device includes a second power input for receiving a second voltage. A power management circuit (e.g., one or more voltage converter circuits) in the memory device receives the second voltage and obtains one or more internal voltages that are transferred to the flash memory.

Thus, embodiments herein include memory devices configured with appropriate inputs (e.g., power input pins, pads, conductive paths, etc.) to receive not just a single voltage, but a plurality of different voltages (e.g., a first voltage, a second voltage, a third voltage, etc.) for providing power to and operating the memory device.

According to one embodiment, a first voltage provides power to a flash memory (e.g., core memory) in a memory device, while a second voltage power is "up" or "down" converted to one or more input voltages that are transmitted (e.g., provided) to the flash memory to support, for example: i) programming cells in the flash memory, ii) erasing cells in the flash memory, iii) reading data from cells in the flash memory, and iv) programming data to cells of the flash memory. That is, the received second voltage can be "down" converted to a set of one or more lower voltages that are used to perform operations with respect to the core memory. Additionally, or alternatively, the second voltage can be "up" converted to a set of one or more higher voltages that are used to perform operations with respect to the core memory.

To convert the second voltage to a higher voltage, a power management circuit (e.g., a power converter circuit) may include one or more charge pump circuits that convert the second voltage to one or more voltages greater than the second voltage. For example, the first voltage may be 1.8 volts or 3.3 volts; the second voltage may be about 5 volts or more, but these voltages will vary depending on the application. The power management circuit receives the second voltage (e.g., 5 volts) and converts it to within a range of different voltage levels, e.g., 7 volts, 10 volts, 18 volts, and/or 20 volts. Note again that these internally generated voltages can be provided to the flash memory to support different types of data access operations with respect to the flash memory in the memory device.

In a further exemplary embodiment, the power management circuitry in the memory device includes one or more charge pump circuits. For example, the power management circuit may include a first charge pump circuit for converting a second voltage to a first internal voltage (e.g., 7 volts) that is higher than the second voltage (e.g., 5 volts) and a second charge pump circuit for converting the second voltage (e.g., 5 volts) to a second internal voltage (e.g., 10 volts) that is higher than the first internal voltage (e.g., 7 volts).

As mentioned above, the first internal voltage and the second internal voltage may be used to support different data access operations with respect to the flash memory. For example, the first internal voltage may be a signal of 7 volts used to support a read operation with respect to data held in a memory cell of the flash memory; the second internal voltage may be a 20-volt signal that supports an erase operation with respect to a memory cell in the flash memory, and so on. More specific uses of the different generated voltages will be discussed later in this specification.

In still other example embodiments, the memory device may include a substrate (e.g., a semiconductor substrate, a circuit board, etc.) on which one or both of a power management circuit (e.g., a voltage converter circuit) and a flash memory are present.

The memory device and/or the substrate may include a respective first conductive pad or power input pin to receive a first voltage from a first power source external to the memory device. The memory device and/or the substrate may include a second conductive pad or a power input pin to receive a second voltage from a second power source external to the memory device. Thus, instead of receiving only a single voltage as in conventional applications, embodiments herein support receiving and using power received from multiple external power sources.

To support the delivery of the first and second voltages to the suitable embodiments discussed herein, a substrate (e.g., a semiconductor substrate) may include i) a first conductive path that delivers the first voltage to the flash memory, and ii) a second conductive path that delivers the second voltage to the power management circuit. Additionally, the substrate may include a plurality of conductive paths to carry the voltage generated by the power management circuit to the flash memory.

It is again noted that a memory device as described herein may be configured to sense the presence or magnitude of one or more input voltages and automatically select an appropriate input voltage for generating one or more internal voltages used to operate the flash memory. For example, the memory device may include a detector circuit for monitoring the second voltage. During the time that the second voltage is below the threshold, the detector circuit can generate a signal to notify or control the power management circuit to obtain one or more internally generated voltages (e.g., internal voltages in the memory device generated by the power management circuit) based on the first voltage instead of the second voltage. During the period when the second voltage is above the threshold, the detector circuit can generate a signal to inform the power management circuit to obtain at least one internal voltage (e.g., an internal voltage in the memory device generated by the power management circuit) based on the second voltage instead of the first voltage. Thus, the power management circuit generates an internal voltage based on a selected one of a plurality of input voltages according to embodiments herein.

Additional embodiments support electrical selection by controlling registers or logic inputs of specific external voltages used to generate internal voltages.

These and other embodiments will be discussed in more detail later in this specification.

As discussed above, the techniques herein are well suited for use in memory devices and systems, such as those that support the use of flash memory technology, electrically erasable semiconductor memory, non-volatile memory, and the like. However, it should be noted that the embodiments herein are not limited to use in such applications and that the techniques discussed herein are well suited for other applications as well.

Additionally, although each of the various features, techniques, structures, etc. herein may be discussed in different places of this disclosure, it is generally contemplated that each of these concepts can be performed independently of each other or in any combination that is feasible. Thus, at least some example embodiments of this invention are capable of being embodied and envisioned in a variety of different forms.

Now, more specifically, FIG. 1 is a diagram illustrating an example of a memory device 110 according to embodiments herein.

In the context of the present example, memory device 110 includes an input 112 (e.g., input 112-1, input 112-2, and input 112-3), a power management circuit 120, and a memory management circuit 130. The power management circuit 120 includes a set of one or more voltage converter circuits 122 (e.g., voltage converter circuits such as voltage converter circuit 122-1, voltage converter circuits 122-2, … …, voltage converter circuit 122-K) to convert the input voltage Vpp (e.g., the second voltage) into internal voltages V1, V2, … …, Vk. The memory management circuit 130 includes a memory 135 (e.g., a non-volatile semiconductor memory such as a flash memory) for storing data.

Memory management circuitry 130 also includes I/O logic 138 and associated circuitry for accessing memory 135.

During operation, input 112-1 (e.g., one or more power input pins, pads, conductive paths, etc.) of memory device 110 receives a first voltage (e.g., Vcc) that is used to power at least flash memory 135. Vcc can be used to provide power to other circuits such as I/O logic 138 and associated circuitry that supports access to memory 135.

Note that in alternative embodiments, memory device 110 may include yet another voltage input for powering portions of I/O logic 138. Thus, memory device 110 is not limited to receiving only two different input supply voltages.

In the context of the present example, the voltage Vss represents one or more ground signals that provide one or more corresponding return paths for the first voltage Vcc and/or the second voltage Vpp. The return path is not considered to be the power input. In addition, an input 112-2 (e.g., one or more power input pins, pads, conductive paths, etc.) of the memory device 110 receives a second voltage (e.g., Vpp), which is provided or communicated to the power management circuit 120. In one embodiment, Vpp is greater than Vcc.

Input 112-3 of memory device 110 receives a ground voltage (e.g., one or more return paths) or voltage Vss.

Thus, as shown in FIG. 1, memory device 110 includes different inputs 112 to receive voltages from multiple external power sources. For example, a first power source provides a voltage Vcc to memory device 110; the second power source provides Vpp to memory device 110. It is noted that other embodiments may also include additional power inputs as mentioned above.

As shown, memory device 110 and the corresponding substrate in memory device 110 may include i) a conductive path 105-1 that delivers the first voltage Vcc to flash memory 135 and associated circuitry in memory management circuit 130, and ii) a conductive path 105-2 that delivers the second voltage Vpp to power management circuit 120.

Additionally, note that memory device 110 and the corresponding substrate on which power management circuit 120 and memory management circuit 130 reside may include multiple conductive paths (e.g., conductive path 126-1, conductive path 126-2, … …, conductive path 126-K) to communicate internal voltages V1, V2, … …, Vk generated by power management circuit 120 to flash memory 135.

Thus, through conductive path 105-2, power management circuit 120 of memory device 110 receives voltage Vpp (e.g., a second external power source). Based on Vpp, power management circuit 120 obtains one or more internal voltages V1, V2, … …, Vk, which are transferred (through conductive paths 126 in memory device 110) to memory 135 in order to support memory operations.

In one example embodiment, the power management circuit 120 receives and converts the second voltage Vpp (e.g., 5 volts) to different voltage levels, such as V1 ═ 7 volts (e.g., to support a read operation), V2 ═ 10 volts (e.g., to support a pass operation), … …, Vk-1 ═ 18 volts (e.g., to support a program operation), and Vk ═ 20 volts (e.g., to support an erase operation). As mentioned above, one or more internally generated voltages V1, V2, … …, Vk are transferred (e.g., provided) to memory 135 to support operations such as i) programming cells in flash memory, ii) erasing cells in memory 135, iii) reading data from cells in memory 135.

Note again that the above voltages are merely examples, and the actual voltages generated by the power management circuit 120 may vary depending on the application.

To convert Vpp to internal voltages V1, V2, … …, Vk, power pipe circuit 120 includes a voltage converter circuit 122, such as, for example, one or more charge pump circuits.

Generally, one type of charge pump is an electronic circuit that uses multiple stages of capacitors as energy storage elements to produce a higher voltage or a lower voltage. Charge pumps use various forms of switching devices to control the connection of voltages to capacitors. In one embodiment, the voltage converter circuit 122 includes a Dickson type charge pump, as shown and discussed with respect to fig. 6.

Note that the charge pumping action typically operates in the kilohertz to megahertz range, but the actual operating frequency varies depending on the application. Also, in addition to producing a higher voltage or a lower voltage, it should be noted that the charge pump can be configured to invert the voltage and produce a very small voltage output depending on the controller and circuit topology in the power management circuit 120.

Still referring to fig. 1, when a charge pump is used to generate the internal voltages V1, V2, … …, Vk, the charge pump is typically more efficient at generating higher voltages where the difference between the input voltage and the output voltage is smaller. In other words, as discussed above, the conversion efficiency for a charge pump that converts a 3.3 volt input to a 20 volt output is lower than the conversion efficiency for a charge pump that converts a 5 volt input to a 20 volt output. Therefore, as described herein, generating the internal voltages V1, V2, … …, Vk based on the higher input voltage Vpp (instead of Vcc) improves the power conversion efficiency of the power management circuit 120.

Accordingly, the size and complexity of the power management circuit 120 can be reduced at the expense of adding another voltage input (e.g., Vpp) to the memory device 110 described herein, but still providing the appropriate voltage to perform different memory operations. More specifically, using Vpp (instead of Vcc) to power the power management circuit 120 and generate the internal voltages V1, V2, … …, Vk can reduce the number of stages required in the charge pump to generate the same output voltage. For example, a 24-level charge pump may be required to convert a 3.3 volt input to 20 volts, while a 10-level charge pump may only be required to convert a 5 volt input to 20 volts. Accordingly, embodiments herein reduce the size and complexity of the corresponding voltage converter circuits used to generate the internal voltages V1, V2, … …, Vk.

To perform the embodiments described herein, memory device 110 may include a substrate (e.g., a semiconductor substrate, a printed circuit board, a flexible circuit board, etc.) on which one or both of power management circuit 120 and flash memory 135 are located. The memory device 110 and/or the substrate may include respective conductive pads or power input pins for receiving a first voltage from a first power source external to the memory device and second conductive pads or power input pins for receiving a second voltage from a second power source external to the memory device.

As an exemplary voltage range, input 112-1 is capable of supporting a received voltage Vcc, such as a voltage between 1.5 and 3.5 volts, depending on the power requirements associated with memory 135. The input terminal 112-2 can be configured to support receiving a higher input voltage Vpp (e.g., Vpp can be greater than Vcc, as previously discussed).

It is again noted that the exemplary voltage values and ranges discussed above are for illustrative purposes only, and that the actual values of the input voltages (e.g., Vpp and Vcc) can vary depending on the application.

Based on the above discussion, embodiments herein include a memory device 110 configured to overcome the deficiencies as discussed above and/or other deficiencies known in the art. For example, according to embodiments herein, memory device 110 includes memory 135 for holding data. Instead of powering both the memory 135 and the voltage translator circuit 122 with the same input voltage (e.g., Vcc) received on input 112-1, the memory device 110 includes an additional input 112-2 for receiving the voltage Vpp.

In summary, as mentioned above, the use of a separate and/or higher input voltage Vpp to generate internal voltages V1, V2, … …, Vk for operating memory functions (e.g., read, program, erase, … …) provides advantages over conventional memory devices. For example, the power management circuit 120 and corresponding voltage converter circuit 122 are more efficient in generating the internal voltages V1, V2, … …, Vk based on a higher input voltage than the voltage powering the memory 135. In other words, the memory 135 and/or the I/O logic 138 are capable of operating at relatively low voltages Vcc; the power management circuit 120 and corresponding voltage converter circuit 122 are capable of operating at higher voltages. Using a higher input voltage Vpp increases the efficiency of the converter (e.g., reduces power consumption) and thus reduces the size and complexity of the corresponding converter circuitry (e.g., charge pump circuitry) required to generate the internal voltages V1, V2, … …, Vk.

The use of a higher voltage Vpp (as opposed to Vcc) also enables improved read/program/erase performance for the memory 135 of the memory device 110 because it is easier to generate the higher internal voltages V1, V2, … …, Vk needed to more quickly perform memory operations for the memory 135. That is, the generation of higher internal voltages V1, V2, … …, Vk supports faster read/program/erase operations. When the power management circuit 120 generates the internal voltages V1, V2, … …, Vk based on the input voltage Vcc (instead of Vpp), the internal voltages V1, V2, … …, Vk are reduced proportionally, reducing the overall performance of performing memory operations. In other words, in circumstances where an additional voltage input, such as Vpp, is not available in the corresponding memory system, the memory device 110 is able to receive the voltage Vcc on the input terminal 112-2, resulting in lower internal voltages V1, V2, … …, Vk, and still operate, but at slower read/program/erase speeds. However, most applications will benefit from another voltage, such as Vpp, for providing power to the power management circuit 120.

FIG. 2 is a diagram of an example of a memory device 110 including multiple power inputs according to embodiments herein. Generally, memory device 110 in FIG. 2 supports the same operations discussed above with respect to FIG. 1. However, memory device 110 in FIG. 2 illustrates that Vpp can be used as the first power source for power management circuitry 120 and that Vcc is the first power source for the memory core (e.g., memory 135) and corresponding control and I/O logic 138. Additionally, however, as shown in FIG. 2, Vcc may be used in a portion of internal power management circuitry 120 to support functions such as a reference generator, a master oscillator, and a clock driver. Note also that Vpp can be used in a portion of memory 135 to perform the functions of a local charge pump, for example, in a row decoder and a row predecoder.

FIG. 3 is a diagram of an example of a memory device including a detector circuit to select input power and generate internal voltages according to embodiments herein. In such embodiments, memory device 110 as described herein can be configured to sense the presence or magnitude of one or more input voltages and automatically select the appropriate input voltage to generate one or more internal voltages for operating memory 135. In other words, a user or manufacturer may include memory device 110 in a corresponding memory system and apply both Vcc and Vpp to the device during operation. In this example, as discussed above, the power management circuit 120 generates the internal voltages V1, V2, … …, Vk based on the input voltage Vpp. According to another example, if the voltage Vpp fails or a user or manufacturer grounds (or makes it open) Vpp, the detector circuit 310 (via switch 305) can detect such a condition and deliver the voltage Vcc (the substitute voltage Vpp) to the input of the voltage translator circuit 122 to generate the corresponding internal voltages V1, V2, … …, Vk. Therefore, the voltage Vcc can be used as a backup for generating the internal voltages V1, V2, … …, Vk when Vpp is not available.

In one embodiment, the exemplary pump as shown can be designed to operate based on a lower voltage. However, if a higher voltage is used to operate the voltage converter circuit 122 (e.g., a charge pump circuit), the pump will shut down faster and earlier.

One way in which the detector circuit 310 can determine whether to automatically select the input voltage Vcc or the input voltage Vpp is to compare the voltage at the input terminal 112-2 to a threshold reference value. If the voltage at the input 112-2 is greater than the threshold, the detector circuit 310 controls the switch 305 to pass the voltage at the input 112-2 to the voltage converter circuit 122. If the voltage at input 112-2 is less than the threshold, detector circuit 310 controls switch 305 to pass the voltage at input 112-1 to voltage converter circuit 122.

Another way in which the detector circuit 310 can determine whether to automatically select the voltage Vcc or the voltage Vpp is to compare the voltage at the input 112-2 to the voltage at the input 112-1. If the voltage at the input 112-2 is higher than the voltage at the input 112-1, the detector circuit 310 controls the switch 305 to pass the voltage Vpp to the voltage translator circuit 122. If the voltage at the input 112-2 is lower than the voltage at the input 112-1, the detector circuit 310 controls the switch 305 to deliver the voltage Vcc to the voltage translator circuit 122 to generate the internal voltages V1, V2, … …, Vk. Accordingly, the detector circuit 310 of the power management circuit 120 is capable of generating the internal voltages V1, V2, … …, Vk based on the states of the plurality of input voltages.

In one embodiment, if the input voltages are equal, memory device 110 can operate as discussed above and shown in FIG. 2.

Based on the different modes of operation discussed above, mode switching between a single power mode (e.g., Vcc is used to power management circuitry 120 and memory management circuitry) and a multiple power mode (e.g., Vcc and Vpp as shown in fig. 1) can be automatically initiated by detecting the voltage level or state of Vpp using, for example, a comparator that compares the level at the Vpp pin to the Vcc power supply voltage. Thus, if the user has grounded the Vpp pin (0V), the memory will use the Vcc power supply to power the internal high voltage pump. If the user has connected Vpp to a suitable voltage (5-12V), the memory can use the Vpp supply to power the pump for more efficient operation.

In another embodiment, memory management circuitry 130 of memory device 110 may include a control register for manually or electronically selecting (e.g., via configuration commands) a so-called single power mode in which power management circuitry 120 generates internal voltages V1, V2, … …, Vk based on Vcc, or a so-called dual mode in which power management circuitry generates internal voltages V1, V2, … …, Vk based on Vpp while providing power to memory 135 via Vcc.

More specifically, as an alternative to using detector circuit 310 and switch 305 to switch between different power modes, memory management circuit 130 may include a configuration register (e.g., a device control configuration register) for selectively switching between a single power mode and a multiple power mode based on software commands. A variety of additional functions to the register as described below enable flexible use of multiple external power sources. The digital controller device (either internal or external to the memory device) can be configured to write to the control register and select which mode should be used to operate the memory device 110 as in table 1 below. To select Vcc as the source for generating the internal voltages V1, V2, … …, Vk, the controller associated with memory device 110 writes a logic 0 to bit 0 of the device control register in table 1 below. To select Vpp as the source for generating the internal voltages V1, V2, … …, Vk, the controller writes a logic 1 to bit 0 of the device control register in table 1 below.

TABLE 1 device control register

According to some example embodiments, a read device information register in flash memory device 135 (as in table 2 below) may provide information about the possible configurations of memory device 110 based on bits 6 and 7. For example, when bits 6 and 7 are logic "0," this indicates that the given memory device 110 uses the input voltage Vcc to generate the internal voltage. When bit 6 is a "0" and bit 7 is a "1," this indicates that the given memory device 110 uses the input voltage Vpp to generate the internal voltage. Finally, when bit 6 is a "1" and bit 7 is a "0," this indicates that a given memory device 110 can be configured by the controller to generate an internal voltage using either the input voltage Vpp or the input voltage Vcc. Thus, the device configuration register can be used to indicate which items providing power are supported by memory device 110. TABLE 2 device configuration register

FIG. 4 is an example diagram illustrating component form factors for a sample associated with memory device 110 according to embodiments herein. For clarity, the vertical sequence of dots represents connections from the pins to the memory device 110.

As shown, the component 410 can be embodied as a 48 pin TSOP1 type component (12 mm X20 mm), for example. Pin 1 of component 410 is dedicated to receiving the input voltage Vpp that is transferred to the input 112-2 of the memory device 110. Pin 12 of component 410 is dedicated to receiving the voltage Vcc that is transmitted to input 112-1 of memory device 110. Pin 13 will be connected to a corresponding ground voltage (e.g., input 112-3).

Pins 28 and 44 are examples of additional inputs for providing power for a portion of each of the self-contained I/O logic 138, as previously discussed. Pins 30 and 43 will be connected to ground associated with voltage Vccq.

Additional details associated with component 410 in fig. 4 can be found in U.S. provisional patent application serial No. 60/902,003.

FIG. 5 is a diagram of an example of a memory system 500 including one or more memory devices 110 according to an embodiment herein. As shown, memory system 500 includes a power converter circuit 550 for receiving a voltage V provided from a source_INPUTSuch as, for example, the motherboard of a computer system, a 120 volt wall outlet, a power supply associated with a USB connector. Based on V input to power converter 550_INPUTAnd possibly one or more other voltages, the power converter 550 generates one or more different voltages (e.g., Vcc and Vpp). The generated voltages Vcc and Vpp are applied to provide power to one or more memory devices 110 (e.g., memory device 110-1, memory device 110-2, … … memory device 110-X).

As an alternative to the above embodiments, it is noted that the voltage Vpp and the voltage Vcc can be received from an external source without having to be converted by a power supply device on the substrate 505. Thus, power converter 550 is optional depending on the availability of different supply voltages Vcc and Vpp.

As previously discussed, each of the one or more memory devices in the memory system 500 may include a respective flash memory 135 powered by the voltage Vcc, and a respective power management circuit 120 for receiving and converting the voltage Vpp to at least one voltage used by the respective flash memory to perform memory operations in order to manage data stored in the corresponding memory device.

The memory system 500 can include a substrate 505 (e.g., a circuit substrate, a printed circuit board, a flex tape, multiple chips in a single assembly, etc.) on which a set of memory devices reside. Optional circuitry, such as a power converter 550 and an access controller 560, can also be present on the substrate 505 or at one or more remote locations with respect to the substrate 505 (e.g., on a motherboard, controller, etc.).

To transfer the voltages Vcc and Vpp to the memory device, the substrate may include conductive paths 510. As shown, conductive path 510-1 carries voltage Vcc to a memory device on substrate 505. Conductive path 510-2 transfers the voltage Vpp to the memory device on substrate 505.

According to embodiments as previously discussed, each memory device on the substrate 505 may include a corresponding first power input pin for delivering the voltage Vcc to the flash memory of the respective memory device. In addition, each memory device on the substrate 505 may include a corresponding second power input pin for delivering the voltage Vpp to the power management circuitry of the respective memory device.

As previously discussed, one or more internal voltages generated by the respective power management circuits can function, for example: i) programming cells in the respective flash memory, ii) erasing cells in the respective flash memory, iii) reading data from cells in the respective flash memory.

The memory system 500 can be used in a variety of different types of consumer and business applications. For example, in one embodiment, memory system 500 is a flash drive device, such as a memory stick that plugs into a USB port of a computer. In such an example, the USB port may provide a voltage, such as Vpp, that is locally down-converted to Vcc. Vpp and locally generated Vcc in a flash disk device are applied to a corresponding one or more memory devices in the flash disk device (e.g., so-called memory stick) to perform functions as described herein.

According to another embodiment, memory system 500 may be a single rank or dual in-line memory board removably connected to a motherboard.

According to another embodiment, the memory system 500 is a solid state internal memory drive associated with a computer system.

According to another embodiment, memory system 500 is an external drive accessible by a computer system. Thus, the memory system 500 can be configured in a number of different form factors depending on the application.

Fig. 6 is a diagram illustrating an example of a voltage translator circuit 122 that translates an input voltage, such as Vpp or Vcc, to one of the internal voltages V1, V2, … …, Vk, according to embodiments herein. The power management circuit 120 generates and applies signals CLK and CLK # to the inputs of each charge pump stage (e.g., stage 1, stage 2, … …, stage N). For higher efficiency, CLK and CLK # can be Vcc level signals as shown, or selectable Vpp level signals. Based on the application of the clock signal and the input voltage as shown, the voltage converter circuit 122 generates an internal voltage V1. As previously discussed, the power management circuit 120 may include a plurality of other voltage converter circuits 122 (similar to that shown in fig. 6) to generate other internal voltages V2, … …, Vk.

More specifically, fig. 6 includes an illustration of an exemplary N-stage multiplier (e.g., one of the plurality of voltage converters) and a typical voltage waveform of a corresponding operation associated with the one of the plurality of voltage converters. Note again that according to embodiments herein, the voltage converter circuit 122 can be used in the power management circuit 120.

As shown in fig. 6, the two clocks (i.e., CLK and CLK #) are out of phase and have amplitude Vcc, and are capacitively coupled to corresponding gates in the switch chain. In the context of this example, the voltage converter circuit 122 (e.g., multiplier) operates in a similar manner to a banked delay line, however, the voltage at the node between the switches in the switch chain is not reset after each pumping cycle, such that the average node voltage potential (e.g., the voltage at the node between one switch and the next switch in the switch chain) is stepped up from the input to the output of the switch chain to produce the voltage V1. This operation is similar in principle to the well-known "bootstrap" technique often used in MOS (metal oxide semiconductor) integrated circuits in order to increase the voltage.

Note again that the voltage converter circuit 122 as shown in fig. 6 is shown by way of example only and other converter circuits or lines can be used in the power management circuit 120 to convert an input voltage to an output voltage.

Fig. 7 is an example diagram illustrating a power management circuit 120 and associated circuitry according to embodiments herein. As shown, power management circuit 120 includes a power supply controller 702 for initiating operation of the various voltage converter circuits. Based on the input from the power controller 702, the reference generator 710 generates a different reference voltage for each converter 122. The master oscillator generates a clock signal.

Each regulator 715 (e.g., regulator 715-1, regulator 715-2, regulator 715-3, regulator 715-4, regulator 715-5) receives a corresponding reference voltage based on the corresponding voltage generated by a given voltage converter. For example, regulator 715-1 receives the voltage reference Verase _ ref, regulator 715-2 receives the voltage reference Vprogram _ ref, and so on. The voltage regulator 715 provides an indication to the corresponding driver 720 whether the corresponding generated voltage is within regulation.

Each of drivers 720 (e.g., driver 720-1, driver 720-2, driver 720-3, driver 720-4, driver 720-5) outputs one or more control signals to a corresponding charge pump unit 730, depending on the master clock signal from oscillator 705 and the corresponding input control received from corresponding regulator 715. The charge pump unit 730 (e.g., charge pump 730-1, charge pump 730-2, charge pump 730-3, charge pump 730-4, and charge pump 730-5) then generates the respective internal voltages V1, V2, … …, V5 that are used to support the different memory operations.

Flash memory cells (NAND flash or NOR flash) in memory 135 of memory device 110 are typically erased and programmed by Folwer-Nordheim (F-N) tunneling or hot electron injection. Erase, program and read operations and the use of internal voltages V1, V2, … …, Vk to perform such operations at the cell level are shown in the example NAND flash memory embodiments of fig. 8-11 that follow.

As will be discussed in more detail later in this specification, to perform read and program verify operations associated with memory 135, power management circuit 120 is capable of generating the voltages for Vread and Vread 7:

vread (in some examples, 4.5V-5.5V): word line voltage to unselected cell gates in a selected NAND string

Vread7 (6V-7V in some examples): vread pass voltages in selected block decoders

To perform a program operation, the power management circuit can generate Vpgm and Vpass:

vpgm (in some examples, 14V-20V): word line voltage to selected cell gate in selected NAND string

Vpass (8V-14V in some examples): word line voltage to unselected cell gates in a selected NAND string

To perform an erase operation, the power management circuit can generate Verase:

verase (in some examples, 20V): erase voltage to cell substrate

As will be appreciated by those skilled in the art, the high voltage levels as mentioned above may be varied by cell technology, device technology and process technology.

FIG. 8 is a diagram illustrating an example of an erase operation with respect to a memory cell according to an embodiment herein.

In a NAND flash memory embodiment, the erasing and programming of cells in memory 135 is managed by F-N tunneling. During an erase operation, the top poly 815 (i.e., the top gate) of the corresponding cell 810 of memory 135 is biased to Vss (ground) while the substrate 830 of cell 810 is biased to an erase voltage Vers (e.g., 20 volts) generated by power management circuit 120. The source and drain of cell 810 are floating (the source and drain are automatically biased to Vers (e.g., Verase) due to the forward bias of the junction from the P-substrate 830 to the n + source/drain). With this erase bias condition, trapped electrons (charges) in the floating poly (floating gate) 820 are uniformly sent to the substrate 830 via the tunnel oxide 825 as shown.

The Vth (e.g., voltage threshold) of the cell of the erased cell becomes negative as shown in graph 850 of fig. 8. In other words, the erased cell is a transistor in the on state (i.e., typically turned on with a gate bias Vg of 0V).

Fig. 9 is a diagram illustrating an example of a cell programming operation according to an embodiment herein.

As shown, during a programming operation, the top poly 915 (i.e., top gate) of an exemplary cell 910 of memory 135 is biased to a programming voltage Vpgm, while the substrate 930, source and drain of the cell 910 are biased to Vss (ground). With this programming bias condition, electrons (charges) in the substrate 930 are uniformly injected into the floating poly 920 (i.e., floating gate) via the tunnel oxide 925. The voltage threshold of the programmed cell becomes positive as shown in graph 950 of FIG. 9. In other words, the cell being programmed is an off-state transistor (i.e., normally turned off with a gate bias Vg of 0V).

FIG. 10 is a diagram illustrating an example of a read of an erased cell according to embodiments herein.

To read cell data of a cell in the memory 135, the corresponding gate and source of a selected cell (e.g., cell 1010) are biased to 0V.

If a cell 1010, such as an erased cell, is shown in FIG. 10, the erased cell 1010 has a negative threshold voltage (as shown in graph 1050) and thus there is a cell current (Icell) from drain to source at the given bias condition.

FIG. 11 is a diagram illustrating an example of a read of a programmed cell according to embodiments herein.

To read the cell data of the cells in the memory 135 as discussed above, the corresponding gate and source of the selected cell (e.g., cell 1110) are biased to 0V.

If cell 1110 is programmed, as shown in FIG. 11, the programmed cell 1110 has a positive threshold voltage (as shown in graph 1150) and no cell current exists from drain to source under the given bias condition. A sense amplifier connected to each bit line senses and latches cell data; an erased cell (on cell) such as cell 1010 in fig. 10 is read as a logic "1" and a programmed cell (off cell) such as cell 1110 in fig. 11 is read as a logic "0".

FIG. 12 is an example diagram illustrating bias conditions during a read page operation associated with a memory device 110 and NAND cell strings using an internal voltage (e.g., Vread) generated by the power management circuit 120 according to embodiments herein.

The selected word line (e.g., word line 27) in memory 135 is set to 0V, while the unselected word lines (e.g., word lines 0-26 and 28-31), SSL, and GSL are biased to a voltage Vread (e.g., 7 volts). Vread is generated by the power management circuit 120 and is high enough to cause unselected cell transistors, such as those on word lines 0-26 and 28-31, to conduct regardless of their programmed state (i.e., cell Vth). The Common Source Line (CSL) is set to ground. In the case of applying the read bias condition, the voltage threshold (e.g., Vth) of the selected cell determines the cell current Icell. The cell current Icell is sensed by a bit line sense amplifier in the page buffer. Thus, the bit line sense amplifier is able to detect the state of the cell 1210.

FIG. 13 is a diagram illustrating an example of a block erase operation according to an embodiment herein.

The flash memory cells in memory 135 must be erased prior to programming. According to one embodiment, the erase operation is performed on a block basis rather than on a cell-by-cell basis.

To perform a block erase operation of the cells of the memory 135 shown in fig. 13, the p-well (PP-well) substrate 1325 of the pocket type is biased to the erase voltage Vers generated by the power management circuit 120, while the bit lines (B/Ls) and the Common Source Line (CSL) in the selected block are set to a floating state. While in the above state, all word lines in the selected block are biased to 0V, the String Select Line (SSL) and Ground Select Line (GSL) are floated and raised to the erase voltage Vers by capacitive decoupling that occurs between them (e.g., SSL and GSL) and the substrate 1325. With this technique, the entire set of cells in the selected block can be erased by F-N tunneling.

FIG. 14 is an example diagram illustrating a page program operation according to embodiments herein. Note that the selected page in the selected block must be erased prior to page programming and the erased cell is read as a logical "1".

The following voltages generated by the power management circuit 120 are used to perform the page programming operation as discussed below: vpgm, Vpass, and Vpi.

Vpgm (e.g., -18V in the context of this example) used for programming is set to a programming voltage high enough to cause F-N tunneling using a drain voltage of 0V on the selected cell.

Vpass for the "pass" Vpi (e.g., -10V in the context of this example) is set to a pass voltage high enough to cause the unselected cell transistors in the selected string to conduct, regardless of their programmed state (i.e., cell Vth). At the same time, Vpass should be low enough so as not to cause F-N tunneling on unselected cells.

Vpi used to inhibit programming (e.g., -8V in the context of this example) is set to a program inhibit voltage high enough to prevent F-N tunneling across the selected cell. Vpi is typically higher than the supply voltage Vcc and lower than Vpass.

In the case of logic "0" programming, the selected bit line is set to 0V and the channel of the selected cell is grounded. The gate of the selected cell is biased to a first voltage Vpgm. Thus, the selected cell is programmed by injecting electrons from the drain (F-N tunneling) to the floating gate.

In the case of logic "1" programming, the erased cell prior to programming must maintain the cell state (i.e., the threshold voltage Vth of the erased cell). In other words, cell programming is prevented. To prevent cell programming, the selected cell bitline is set to Vpi and the Vpi level is passed to the drain of the selected cell via the unselected cells. The voltage difference across the selected cell (Vpgm-Vpi) prevents F-N tunneling from the drain to the floating gate.

In the previous example, the high program inhibit voltage Vpi is provided directly to the NAND string channel via the bit line. In the worst case, all bit lines corresponding to all selected pages are set to Vpi (i.e., the case where all cells on the selected page are programmed to logic '1'), which creates the following problem:

vpi is provided by an internal high voltage generator during a programming operation and requires a large capacity charge pump to provide Vpi to the high capacity bit lines. This results in a dramatic increase in power consumption and chip size.

The page buffer connected to the bit line must be provided with a high voltage transistor in order to provide Vpi. The high voltage transistors are larger than the regular voltage (i.e., Vcc) transistors, which increases the page buffer size (and hence chip size).

Further scaling of the memory is afforded by high voltage bitline isolation requirements.

The programming speed is slow because the high capacity bit lines are charged to Vpi by a built-in voltage generator with a limited current source.

FIG. 15 is an example diagram illustrating page program bias conditions according to embodiments herein.

To solve the problem described in fig. 14, the self-boosting program inhibit scheme shown in fig. 15 may be used.

In the case where the SSL transistor is turned on and the GSL transistor is turned off, the bitline voltage of the cell to be programmed is set to 0V, while the bitline voltage of the cell to be program-inhibited is set to Vcc. The 0V bit line connects the channel of the associated cell NAND string to ground. When a program voltage Vpgm is applied to the gate of a selected cell, the large potential difference between the gate and the channel causes electrons F-N to tunnel onto the floating gate, programming the cell.

In program-inhibited cells (e.g., cells in which Vcc is applied to the corresponding bit line), the bit line initially precharges the associated channel. When the word line voltage of the cell NAND string is raised to the program voltage Vpgm at the selected word line and to the pass voltage Vpass at the unselected word lines, the series capacitances through the control gate, floating gate, channel and body are coupled and the channel potential is automatically raised.

In the program inhibit string, when the coupled channel voltage rises to [ Vcc-Vth ] (Vth: threshold voltage of SSL transistor), the SSL transistor turns off and the channel becomes a floating node. The floating channel voltage can rise to about 80% of the gate voltage. Thus, when the program voltage Vpgm (e.g., 15.5-20 volts in the context of this example) and the pass voltage (Vpass, e.g., 10V in the context of this example) are applied to the control gate, the channel voltage of the program inhibit cell in the context of this example is raised to approximately 8V. This high channel voltage prevents F-N tunneling in the program-inhibited cells. Using this technique, all the disadvantages caused by the requirement to apply the higher voltage Vpi (8V in the context of this example) to the bit line can be eliminated.

Fig. 16 is a diagram illustrating an example of a block decoder according to an embodiment herein. Note that there are many variations to the circuit implementation of the block decoder.

The string selection line SSL, the word lines WL0 to WL31, the ground selection line GSL, and the common source line CSL are driven by common signals SS, S0 to S31, GS, and CS via transfer transistors TSS, TS0 to TS31, TGS, and TCS, which are commonly controlled by an output signal BD _ out of the block decoder.

The local charge pump is a high voltage switching circuit for controlling the transfer transistors TSS, TS0 to TS31, TGS and TCS. It typically includes an enhancement NMOS transistor, a depletion NMOS transistor (DEP), an intrinsic NMOS transistor (NAT) and a NAND gate with 2 inputs. When the block decoder latch output BDLCH _ out is Vdd, HVenb is 0V, and the input OSC is oscillating (note: local charge pump is a well known circuit technology), the block decoder's output signal BD _ out is raised to Vhv.

The latch output BDLCH _ out is reset to 0V when RST _ BD pulse is input high (short pulse), and the decode address is latched when the LCHBD pulse is input high (short pulse) in the case of the active row predecode address signals Xp, Xq, Xr, and Xt.

FIG. 17 is an example flow diagram 1700 illustrating a method associated with the memory device 110 according to embodiments herein. Generally, flow diagram 1700 records some concepts as discussed above. It is noted that the order of steps in all flowcharts is merely exemplary, and steps can generally be performed in any order. For example, there is no reason to consider that step 1710 below must precede step 1715, and so on.

In step 1710, the memory device 110 receives a voltage Vcc.

In step 1715, memory device 110 uses voltage Vcc to power flash memory 135 in memory device 110.

In step 1720, the memory device 110 receives the voltage Vpp.

In step 1725, the memory device 110 converts the voltage Vpp to one or more internal voltages V1, V2, … …, Vk that enable memory control operations associated with the flash memory 135.

FIG. 18 is an example flowchart 1800 illustrating a method associated with the memory device 110 according to embodiments herein. Generally, flow diagram 1800 records some concepts as discussed above.

In step 1810, memory device 110 receives a voltage Vcc.

In step 1815, the memory device 110 uses the voltage Vcc to provide power to the memory 135.

In step 1820, the memory device 110 receives the voltage Vpp.

In step 1825, the memory device 110 generates a set of internal voltages V1, V2, … …, Vk, each of which is greater than or equal to the voltage Vpp. As previously discussed, the internal voltages are used by the memory 135 to perform various data access operations. To generate the internal voltages V1, V2, … …, Vk, the power management circuitry of the memory device 110 performs the following substeps.

In sub-step 1830, the power management circuit 120 of the memory device 110 operates a power supply circuit (e.g., the voltage converter circuit 122) present on the same substrate as the flash memory 135 to generate a first internal voltage (e.g., Verase) greater than Vpp.

In sub-step 1835, the power management circuit 120 of the memory device 110 provides or transmits the first internal voltage to the memory 135.

In sub-step 1840, the power management circuit 120 of the memory device 110 operates the voltage translator circuit 122 residing on the same substrate as the flash memory to generate a second internal voltage greater than Vpp.

In sub-step 1845, memory device 110 provides a second internal voltage (e.g., Vprogram) to memory 135.

FIG. 19 is an example flow diagram 1900 associated with memory system 500 according to embodiments herein.

In step 1910, a user, manufacturer, operator, owner of memory device 110 provides voltage Vcc to memory device 110 to power flash memory in memory device 110. In one embodiment, this includes applying Vcc to a first pin of a memory device to power flash memory and/or associated circuitry.

In step 1915, the user, manufacturer, operator, owner of the memory device 110 provides the voltage Vpp to the memory device 110 to power the power converter circuitry in the memory device 110. In one embodiment, providing the voltage Vpp includes applying Vpp to a second pin of the memory device 110. As discussed, the power management circuit (e.g., power converter circuit) receives Vpp and converts Vpp to one or more internal voltages V1, V2, … …, Vk that are used by the corresponding flash memory 135 to support data management operations. For example, applying the voltage Vpp enables one or more of the following selected data management operations: i) programming cells in the flash memory, ii) erasing cells in the flash memory, iii) reading data from cells in the flash memory.

Certain adaptations and modifications of the described embodiments are possible. Accordingly, the embodiments discussed above are to be considered illustrative rather than restrictive.

Claims (12)

1. A memory device, comprising:

a non-volatile memory for storing data;

input/output logic to enable access to data in the non-volatile memory;

a first power input pin for receiving a first external voltage for powering the input/output logic;

a second power input pin for receiving a second external voltage for powering the non-volatile memory;

a third power input pin for receiving a third external voltage, a level of the third external voltage being greater than a level of the second external voltage;

a power management circuit for receiving the second external voltage and optionally the third external voltage and converting the second external voltage or the third external voltage to more than one internal voltage, said more than one internal voltage being greater than the level of the third external voltage; and

wherein modification of data in the non-volatile memory is enabled, at least in part, by the more than one internal voltage provided by the power management circuit; and

a configuration register that configures the power management circuit to provide the more than one internal voltage using the second external voltage and the third external voltage.

2. The memory device of claim 1, further comprising: a device information register indicating that the memory device supports using the third external voltage.

3. The memory device of claim 1, wherein the non-volatile memory is flash memory.

4. The memory device of claim 1, wherein the non-volatile memory is a NAND flash memory.

5. The memory device of claim 1, wherein the power management circuit comprises at least more than one regulator, the more than one regulator to regulate the more than one internal voltage.

6. The memory device of claim 1, wherein the power management circuit comprises a first regulator circuit to:

i) receiving one of the more than one internal voltages; and

ii) generating an output to indicate whether the one of the more than one internal voltages is within the first regulation.

7. The memory device of claim 6, wherein the power management circuit further comprises a reference generator circuit to generate a reference voltage to be provided to the first regulator circuit.

8. The memory device according to claim 1, wherein the first external voltage is Vccq, the second external voltage is Vcc, and the third external voltage is Vpp.

9. The memory device according to claim 4, wherein one of the more than one internal voltage is a program voltage for programming data of the NAND flash memory.

10. The memory device according to claim 4, wherein one of the more than one internal voltage is an erase voltage for erasing data of the NAND flash memory.

11. The memory device of claim 9, wherein the program voltage is applied to a selected page of the NAND flash memory, the selected page including program cells and program inhibit cells.

12. The memory device according to claim 11, wherein the program unit is coupled to a bit line having 0V, and the program inhibit unit is coupled to a bit line having a level of the second external voltage.