HK1197503B - Conversion circuitry for reducing pixel array readout time - Google Patents

Abstract

The subject application relates to conversion circuitry for reducing pixel array readout time. An image sensor includes a pixel array having pixels arranged in rows and columns, a first successive-approximation-register ("SAR") analog-to-digital-converter ("ADC"), a second SAR ADC, and first and second control circuitry. The first SAR ADC includes a first capacitor array ("FCA") that shares a first common terminal coupled to a first comparator and coupled to receive first analog pixel signals. The second SAR ADC includes a second capacitor array ("SCA") that shares a second common terminal selectably coupled to a second comparator and coupled to receive second analog pixel signals. The first and second control modules are coupled to selectably switch bottom plates of the FCA from a low reference voltage to the high reference voltage at a same time as selectably switching bottom plates of the SCA from a high reference voltage to the low reference voltage.

Description

Conversion circuit for reducing pixel array readout time

Technical Field

The present disclosure relates generally to optics and more particularly, but not exclusively, to image sensors.

Background

Image sensors are used in many applications, for example, digital cameras, cellular telephones, cameras, and various other medical, automotive, military, and other applications. As image sensors become prevalent in everyday life, consumers and industries desire faster, smaller, and lower power image sensors. In some applications, the image sensor must capture images sequentially and preferably at a high frame rate. However, conventional image sensors are limited by a number of factors and cannot produce high quality images at high frame rates.

One of the factors limiting the frame rate of a given image sensor is the speed of the conversion circuitry that converts the analog pixel signals from the pixel array into digital image values. Within the conversion circuitry, some image sensors rely on successive approximation registers ("SAR") analog-to-digital converters ("ADC") to convert analog pixel signals into digital image values. Therefore, it would be advantageous to increase the speed of the SAR ADC within the conversion circuit.

Disclosure of Invention

An image sensor, comprising: a pixel array having pixels arranged in rows and columns; a first successive approximation register ("SAR") analog-to-digital converter ("ADC") coupled to convert a first analog pixel signal to first digital data, the first SAR ADC comprising a first capacitor array ("FCA") having binary weighted values, wherein a top plate of the FCA is coupled in common to a first common terminal of a first comparator input and a bottom plate of the FCA is coupled to switch from a low reference voltage to a high reference voltage, and wherein the first common terminal is selectively coupleable to receive the first analog pixel signal generated by a first column of the pixel array; a second SAR ADC coupled to convert a second analog pixel signal to second digital data, the second SAR ADC comprising a second capacitor array ("SCA") having binary weighted values, wherein a top plate of the SCA shares a second common terminal coupled to a second comparator input and a bottom plate of the SCA is coupled to switch from the high reference voltage to the low reference voltage, and wherein the second common terminal is selectively coupleable to an inverter output of an inverter that inverts the second analog pixel signal generated by a second column of the pixel array; and a first control circuit of the first SAR ADC is coupled to selectively switch the backplane of the FCA from the low reference voltage to the high reference voltage in response to a control signal at substantially the same time as a second control circuit of the second SAR ADC selectively switches the backplane of the SCA from the high reference voltage to the low reference voltage in response to the control signal.

A method of reading out an array of pixels, the method comprising: sampling a first analog pixel signal onto a first common terminal of a first capacitor array ("FCA") coupled to a first comparator, wherein the first analog pixel signal is generated by a first column of the pixel array; sampling a second analog pixel signal onto a second common terminal of a second capacitor array ("SCA") coupled to a second comparator, wherein the second analog pixel signal is generated by a second column of the pixels; switching a first bottom plate of a most significant bit ("MSB") capacitor of the FCA from a low reference voltage to a high reference voltage to initiate a first binary search sequence for determining a first digital value of the first analog pixel signal; and switching a second bottom plate of a second MSB capacitor of the SCA from the high reference voltage to the low reference voltage to initiate a second binary search sequence for determining a second digital value of the second analog pixel signal, wherein the first bottom plate and the second bottom plate are respectively opposite the first and second common terminals, and wherein the first bottom plate is switched from the low reference voltage to the high reference voltage at substantially the same time as the second bottom plate is switched from the high reference voltage to the low reference voltage to redistribute charge between the FCA and the SCA to reduce an additional amount of charge drawn from the low voltage reference and the high voltage reference.

A non-transitory machine-accessible storage medium that provides instructions that, when executed by a machine, will cause the machine to perform operations comprising: sampling a first analog pixel signal onto a first common terminal of a first capacitor array ("FCA") coupled to a first comparator, wherein the first analog pixel signal is generated by a first column of the pixel array;

sampling a second analog pixel signal onto a second common terminal of a second capacitor array ("SCA") coupled to a second comparator, wherein the second analog pixel signal is generated by a second column of the pixels; switching a first bottom plate of a most significant bit ("MSB") capacitor of the FCA from a low reference voltage to a high reference voltage to initiate a first binary search sequence for determining a first digital value of the first analog pixel signal; and switching a second bottom plate of a second MSB capacitor of the SCA from the high reference voltage to the low reference voltage to initiate a second binary search sequence for determining a second digital value of the second analog pixel signal, wherein the first bottom plate and the second bottom plate are respectively opposite the first and second common terminals, and wherein the first bottom plate is switched from the low reference voltage to the high reference voltage at substantially the same time as the second bottom plate is switched from the high reference voltage to the low reference voltage to redistribute charge between the FCA and the SCA to reduce an additional amount of charge drawn from the low voltage reference and the high voltage reference.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise explicitly indicated.

FIG. 1 illustrates a system diagram of an image sensor including an example conversion circuit for reading out an array of pixels, according to an embodiment of the invention.

Fig. 2A and 2B illustrate example configurations of SAR ADCs disposed within the conversion circuit illustrated in fig. 1, according to embodiments of the invention.

Fig. 3A and 3B illustrate example timing associated with the SAR ADC of fig. 2A and 2B, respectively, according to embodiments of the disclosure.

FIG. 4 shows a flow diagram of an example method of reading out an array of pixels, according to an embodiment of the invention.

Detailed Description

Embodiments of systems and methods for reducing pixel array readout time are described herein. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

Reference throughout this specification to "one embodiment" or "an example" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

FIG. 1 is a block diagram of an image sensor 100 including a pixel array 105 coupled to a digital control and image processor ("DCIP") 120. The pixel array 105 is coupled to a pixel bias circuit 107, the pixel bias circuit 107 being coupled to a conventional conversion circuit 110. DCIP120 is coupled to pixel array 105 to control the operating characteristics of pixel array 105. For example, DCIP120 may generate a shutter signal for controlling image acquisition. The shutter signal may be a global shutter signal or a rolling shutter signal.

As illustrated, pixel array 105 comprises a two-dimensional array of pixels arranged in rows and columns. During image acquisition, each of the pixels in pixel array 105 may generate an image charge from photons striking a photosensitive element of the pixel. Each pixel in pixel array 105 may be a Complementary Metal Oxide Semiconductor (CMOS) pixel.

After each pixel has acquired its image charge, the conversion circuit 110 reads out an analog pixel signal representative of the generated image charge and converts the analog pixel signal into digital image data 163. DCIP120 is coupled to conversion circuitry 110 to receive digital image data 163 from conversion circuitry 110. Pixel bias circuitry 107 may be coupled between conversion circuitry 110 and pixel array 105 to bias analog pixel signals before conversion circuitry 110 converts the analog pixel signals.

The conversion circuit 110 may read out a row of image data at a time along readout column lines 125. In fig. 1, conversion circuitry 110 includes conversion modules 112 and 113 for each column of pixel array 105 to convert analog pixel signals generated in each of the columns. In the illustrated embodiment, the even column conversion module 112 is configured to receive analog pixel signals generated by even columns (column 2j) of the pixel array 105, and the odd column conversion module 113 is configured to receive analog pixel signals generated by odd columns (column 2j-1) of the pixel array 105.

An enlarged view of conversion module 112/113 (as indicated by the dashed lines) shows that even column conversion module 112 includes SAR ADC116 and odd column conversion module 113 includes SAR ADC 117. Each SAR ADC 116/117 is coupled to receive a low reference voltage 141 and a high reference voltage 142. Further, each conversion module 112/113 includes column memory circuitry 114 coupled to receive control signals 153 from DCIP 120. Example control signals may include address signals 167. The column memory circuit 114 may also be coupled to output an output data signal 165 comprising a digital image signal.

Fig. 2A illustrates SAR ADC116 that may be included in even column conversion module 112 of conversion circuit 110. The top plate of each of the capacitors (234A-234N) in FCA230 is connected to common terminal 222 and common terminal 222 is coupled to the input of comparator 250. In the illustrated embodiment, the common terminal 222 can be selectively coupled to receive analog pixel signals generated in a first column (e.g., 2j) of the pixel array 105. The bottom plate of FCA230 may be selectively switched from low reference voltage 141 to high reference voltage 142 via a coupling to charge a capacitor (e.g., MSB capacitor 234N) of FCA230 when initiating a binary search sequence. In one embodiment, as illustrated, the backplane of the FCA230 may be selectively coupled to switch from the low reference voltage 141 to the high reference voltage 142 through switches 233A-233N. The switches 233A to 233N may be implemented using transistors.

FCA230 may include a number N of capacitors, where N is the number of bits of resolution of SAR ADC 116. The capacitor values within the FCA230 are configured to perform a binary search sequence. In fig. 2A, the capacitors are binary weighted, meaning that the least significant bit ("LSB") capacitor 234A has a value of C, and each next capacitor in the FCA230 has a value about twice as large as the last capacitor, until the most significant bit ("MSB") capacitor 234N has a value of about 2^ (N-1) × C, where N is the number of bits of resolution in the SAR ADC 116.

Fig. 3A illustrates a timing sequence associated with SAR ADC116 of fig. 2A. To complete the analog/digital conversion, a binary search sequence is performed. Initially, an input voltage (e.g., biased pixel signal 108) from a column is sampled onto the common terminal 222 of the FCA 230. After the input voltage has been sampled onto the common terminal 222 of the FCA230, a charge proportional to the input voltage is stored on the FCA 230. Switch 233N then couples the bottom plate of MSB capacitor 234N from low reference voltage 141 to high reference voltage 142, which charges MSB capacitor 234N from low to high. MSB capacitor 234N is charged with 1/2 representing high reference voltage 142. The voltage on comparator input 251 is then compared to a common voltage (e.g., ground) on the positive input of comparator 250, and comparator 250 outputs a digital bit indicating whether the input voltage is 1/2 below high reference voltage 142 or 1/2 above high reference voltage 142. If the input voltage is higher than 1/2 of the high reference voltage 142, register 242A is set and switch 233 continues to couple the bottom plate of MSB capacitor 234N to the high reference voltage 142. Otherwise, register 242N is not set and switch 233N couples the bottom plate of MSB capacitor 234N to low reference voltage 141. As is known in the art, the binary search sequence continues in the capacitors in the FCA230 until the digital value of the input voltage is determined by setting the registers 242A-242N.

Fig. 2B illustrates SAR ADC 117 that may be included in odd column conversion module 113 of conversion circuit 110. The top plate of each of the capacitors (239A-239N) in the second capacitor array ("SCA") 231 is connected to the common terminal 223 and the common terminal 223 is coupled to an input of the comparator 260. In the illustrated embodiment, the common terminal 223 can be selectively coupled to receive analog pixel signals generated in a second column (e.g., 2j-1) of the pixel array 105. SCA 231 includes a number N of capacitors, where N is the number of bits of resolution of SAR ADC 117, which is the same as the number of bits of SAR ADC 116. The capacitor values within SCA 231 are configured for performing a binary search sequence. In fig. 2B, the capacitors are binary weighted.

The bottom plate of SCA 231 is coupled to switch from a high reference voltage 142 to a low reference voltage 141 to charge the capacitor (e.g., MSB capacitor 239N) of SCA 231 when initiating the binary search sequence. Thus, it should be noted that SAR ADC116 and SAR ADC 117 charge their capacitors to opposite voltage references, which may have opposite polarities. SAR ADC116 and SAR ADC 117 are also coupled to charge their capacitors at substantially the same time in response to control signal 153 from DCIP 120. First control circuitry 270 is coupled to selectively switch the backplane of FCA230 from VLO 141 to VHI142 in response to a control signal (e.g., control signal 153) at substantially the same time that second control circuitry 280 selectively switches the backplane of SCA 231 from VHI142 to VLO 141 in response to the control signal.

To correct for the fact that SCA 231 is charged to the opposite reference of FCA230, adjustments are made to SAR ADC 117 (as compared to SAR ADC 116) to still produce a suitable digital voltage output. In the illustrated embodiment of fig. 2B, inverter 255 is coupled to invert the analog pixel signal (VIN <2j-1>) generated by the second column in pixel array 105 and to remove inverter 257 coupled to the output of comparator 250 in SAR ADC 116. Further, the Q _ B signal from registers 247A-247N is inverted to appropriately control the switching of switches 238A-238N between VLO 141 and VHI 142. Using these adjustments to SAR ADC 117, SAR ADC116 and SAR ADC 117 may generate the same desired digital value for a given analog pixel signal in response to the same control signal. In other words, even with their capacitors charged to opposite voltage references, if SAR ADC116 and SAR ADC 117 are configured as in fig. 2A and 2B, adjustments to the rest of the system (e.g., different control signals) may not be required. In one embodiment, inverter 255 is implemented as an inverting amplifier (having a gain of minus 1).

Conventional image sensors are not configured to have conversion circuits with SAR ADCs having capacitors charged to opposite voltage references. In some conventional image sensors, all SAR ADCs in the conversion circuit are the same and the capacitor array is charged to the same voltage reference. This may result in a longer settling time for the voltage reference because the capacitor arrays inside the SAR ADC all load the same voltage reference (at about the same time) by drawing charge from the voltage reference during the binary search sequence of the SAR ADC.

In the illustrated embodiments of fig. 1-3, charging the capacitor arrays of SAR ADC116 and SAR ADC 117 to opposite voltage references (at substantially the same time) during the respective binary search sequences may reduce the charging time of the capacitors by simply redistributing the charge between FCA230 and SCA 231 rather than by re-drawing all of the charge required to charge the capacitors from the voltage references (VLO 141 and VHI 142). Thus, the charge already stored within the conversion circuit 110 is used to quickly recharge the capacitor, rather than waiting for a voltage reference to supply all of the required charge as occurs in conventional image sensors. By reducing the charging time of the capacitor, the settling time between comparisons in the binary search sequence is reduced, which results in faster analog-to-digital conversion, which makes higher frame rates possible for the image sensor.

To illustrate, fig. 3A and 3B illustrate example binary search timing associated with the SAR ADC of fig. 2A and 2B, respectively, according to embodiments of the invention. In fig. 3A, the settling time of SAR ADC116 is illustrated. The settling time dominates the time it takes for the voltage buffer (low voltage reference 141 and high reference voltage 142) to charge the capacitance (associated with a given bit) from reference 141 to reference 142. Specifically, time period 391 represents the time it takes to charge MSB capacitor 234N and stabilize the voltage reference, and time period 393 illustrates the time it takes to charge LSB capacitor 234A and stabilize the voltage reference. In the case of MSB capacitor 234N, it has the maximum value (and takes the longest time to charge) and is the first capacitor to be charged in the binary search sequence. Reducing the charge time of MSB capacitor 234N will increase the speed of the SAR ADC because it is charged for each binary search sequence. This in turn will contribute to higher frame rate capabilities in the image sensor.

Fig. 3A and 3B show that SAR ADCs 116 and 117 may use the same control signals to generate digital values even though FCA230 and SCA 231 are charged to opposite references during their respective binary search sequences. FIG. 3A shows that at the beginning of the binary search sequence, VDAC <2j > is responsive to the input voltage VIN <2j > being sampled onto common terminal 222. Signal SEL < N-1> selects MSB capacitor 234N and its bottom plate switches from VLO 141 to VHI142, as shown by the reduced voltage at node VDAC <2j > during time period 391. Similarly, at the end of the binary search sequence, signal SEL <0> selects LSB capacitor 234A and its bottom plate switches from VLO 141 to VHI142, as shown by the rising voltage at node VDAC <2j > during time period 393. Because of the smaller capacitance value of LSB 234A compared to MSB 234N, the voltage change across VDAC <2j > is lower during time period 393 compared to time period 391. Those skilled in the art will understand the timing not illustrated that occurs between time period 391 and time period 393.

Fig. 3B shows a second binary search sequence occurring in synchronization (at substantially the same time) with the binary search sequence shown in fig. 3A. At the beginning of the second binary search sequence, VDAC <2j-1> is responsive to the input voltage VIN <2j-1> being sampled onto the common terminal 223. Signal SEL < N-1> selects MSB capacitor 239N and its bottom plate switches from VHI142 to VLO 141 as shown by the reduced voltage at node VDAC <2j-1> during time period 396. Similarly, at the end of the binary search sequence, signal SEL <0> selects LSB capacitor 239A and its bottom plate switches from VHI142 to VLO 141 as shown by the reduced voltage at node VDAC <2j-1> during time period 398. As stated above, charging the capacitors in the FCA230 and SCA 231 to different references at substantially the same time may accelerate the settling times 391, 393, 396, and 398 (compared to the prior art) by reducing the charging time of the capacitors. The reduced charge time of the capacitor may make faster frame rates possible for the pixel array 105.

Referring back to fig. 1, conversion circuit 110 may include a plurality of even column conversion modules 112 coupled to receive analog pixel signals generated by even columns of pixel array 105, and conversion circuit 110 may include a plurality of odd column conversion modules 113 coupled to receive analog pixel signals generated by odd columns of pixel array 105. As shown, pixel array 105 may include even and odd columns arranged in every other configuration. In other arrangements within the scope of the disclosure, SAR ADC116 and SAR ADC 117 may not have to be strictly paired with even and odd columns of pixel array 105. In these other arrangements, it may be advantageous to have one half of the conversion circuit include SAR ADC116 and the other half include SAR ADC 117, so that the capacitances charged to the opposing references are balanced, which may reduce settling time by reducing the charge that needs to be drawn from the voltage reference.

In some embodiments, pixel array 105 may include pixels configured to receive different colors of light. In one embodiment, the analog pixel signals generated by the green pixels of the pixel array may be converted to digital signals by a SAR ADC configured as SAR ADC116, and the analog pixel signals generated by the red and blue pixels of the pixel array may be converted to digital signals by a SAR ADC configured as SAR ADC 117.

FIG. 4 illustrates a flow diagram 400 illustrating an example method of reading out an array of pixels, according to an embodiment of the invention. The order in which some or all of the process blocks appear in process 400 should not be considered limiting. Rather, those skilled in the art, having the benefit of this disclosure, will appreciate that some of the process blocks may be performed in a variety of sequences not illustrated, or even performed in parallel.

In process block 405, a first analog pixel signal generated in a first column of the pixel array is sampled onto a common terminal (e.g., common terminal 222) of a first capacitor array ("FCA"). The first analog pixel signal may be generated in even columns of a pixel array and the capacitor array may be coupled to a first comparator. In process block 410, a second analog pixel signal generated in a second column of the pixel array is sampled onto a common terminal (e.g., common terminal 223) of a second capacitor array ("SCA"). A second analog pixel signal may be generated in odd columns of the same pixel array and the capacitor array may be coupled to a second comparator different from the first comparator. The second analog pixel signal may be inverted prior to sampling the second analog pixel signal onto the second capacitor array. FCA and SCA may comprise capacitors with binary weighted values.

In process block 415, the bottom plate of the MSB capacitor of the FCA (e.g., capacitor 234N) is switched from a low reference voltage to a high reference voltage to initiate a binary search sequence for determining the digital value of the first analog pixel signal. In process block 420, the bottom plate of the MSB capacitor of the SCA (e.g., capacitor 239N) is switched from a high reference voltage to a low reference voltage to initiate a binary search sequence for determining the digital value of the second analog pixel signal. The bottom plate of the MSB capacitor is physically opposite the top plate of the MSB capacitor coupled to the respective common terminal. The bottom plates of the two MSB capacitors are switched at substantially the same time, which redistributes charge between the FCA and SCA and reduces the amount of charge that needs to be drawn from the low and high reference voltages.

In one embodiment of the process 400, the first comparator is reset before the first analog signal is sampled onto the common terminal of the FCA and the second comparator is reset before the second analog signal is sampled onto the second common terminal of the SCA. The pixels in the pixel array may be arranged in rows and columns, and the columns of the pixel array may include even and odd columns that are staggered in every other configuration. The first column of the pixel array may be even and the second column of the pixel array may be odd.

The first comparator and FCA may be included in a first SAR ADC and the second comparator and SCA may be included in a second SAR ADC. In one embodiment, the first SAR ADC or the second SAR ADC is coupled to receive an analog pixel signal generated by each column of the pixel array. The total number of the first and second SAR ADCs may be synchronously controlled such that the capacitors in the total number of FCAs and SCAs are switched at substantially the same time to properly redistribute charge on the capacitors. The analog pixel signals generated by the green pixels of the pixel array may be converted to digital signals by the first SAR ADC, and the analog pixel signals generated by the red and blue pixels of the pixel array may be converted to digital signals by the second SAR ADC.

In discussing fig. 2B above, a modification of SAR ADC 117 to charge SCA 231 to the opposite polarity of FCA230 is described. In one embodiment, to correct for the opposite polarity, the inverter 255 in the SAR ADC 117 may be eliminated and the order in which the pixel signals are sampled is reversed instead.

Typically, for a four transistor ("4T") pixel architecture, sampling may begin with the floating diffusion ("FD") and photodiode ("PD") reset, which may be referred to as correlated double sampling "CDS. This depletes the PD of free charge so that the reset operation does not store noise charge in the PD. Second, the pixels integrate image light. Third, the FD is reset and the FD reset value is read out. Fourth, charge is then transferred from the PD to the FD. Fifth, the FD value (which represents the light integrated by the pixel) is read out. In summary, the reset value is read first and the signal value is read second.

To reverse the order in which pixels having a 4T architecture are sampled, FD and PD may be reset to begin the sampling sequence. Second, the pixels integrate image light. Third, FD is reset. Third, charge is transferred from the PD to the FD. Fifth, the signal value is read. Sixth, FD is reset and the reset value is read out.

Reversing the sequence of how the pixels are read out effectively achieves the same result as inverting the analog pixel signals. Thus, the SAR ADC 117 may be read out in reverse sequence rather than including the inverter 255.

It is worth noting that making the sequence of readout pixels instead CDS, which may contribute to a more noisy readout, is not the case. However, CDS may be implemented while the signal value before the reset value is still supplied to the SAR ADC 117 by storing the reset value in a storage element (e.g., a sample and hold circuit).

The processes explained above are described with respect to computer software and hardware. The described techniques may constitute machine-executable instructions embodied in a tangible or non-transitory machine (e.g., computer) readable storage medium, which when executed by a machine, cause the machine to perform the described operations. Further, the processes may be implemented within hardware, such as an application specific integrated circuit ("ASIC") or other hardware.

A tangible, non-transitory, machine-readable storage medium includes any mechanism that provides (i.e., stores) information in a form accessible by a machine (e.g., a computer, network device, personal digital assistant, manufacturing tool, any device with a set of one or more processors, etc.). For example, a machine-readable storage medium includes recordable/non-recordable media (e.g., Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.).

The above description of illustrated embodiments of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (20)

1. An image sensor, comprising:

a pixel array having pixels arranged in rows and columns;

a first successive approximation register, SAR, analog-to-digital converter, ADC, coupled to convert a first analog pixel signal to first digital data, the first SAR ADC comprising a first capacitor array, FCA, having binary weighted values, wherein a top plate of the FCA is commonly coupled to a first common terminal of a first comparator input and a bottom plate of the FCA is coupled to switch from a low reference voltage to a high reference voltage, and wherein the first common terminal is selectively coupleable to receive the first analog pixel signal generated by a first column of the pixel array;

a second SAR ADC coupled to convert a second analog pixel signal to second digital data, the second SAR ADC comprising a second capacitor array SCA having binary weighted values, wherein a top plate of the SCA shares a second common terminal coupled to a second comparator input and a bottom plate of the SCA is coupled to switch from the high reference voltage to the low reference voltage, and wherein the second common terminal is selectively coupleable to an inverter output of an inverter that inverts the second analog pixel signal generated by a second column of the pixel array; and is

A first control circuit of the first SAR ADC is coupled to selectively switch the backplane of the FCA from the low reference voltage to the high reference voltage in response to a control signal at substantially the same time as a second control circuit of the second SAR ADC selectively switches the backplane of the SCA from the high reference voltage to the low reference voltage in response to the control signal.

2. The image sensor of claim 1, wherein the first SAR ADC is one of a plurality of first SAR ADCs and the second SAR ADC is one of a plurality of second SAR ADCs, and wherein a given SAR ADC of the plurality of first SAR ADCs is coupled to receive odd column pixel signals generated by odd columns of the pixel array and a given SAR ADC of the plurality of second SAR ADCs is coupled to receive even column pixel signals generated by even columns of the pixel array, the columns of the pixel array including the even columns and the odd columns interleaved in every other configuration, the first column being one of the even columns and the second column being one of the odd columns.

3. The image sensor of claim 2, wherein green pixels of the pixel array are disposed in the odd columns and red and blue pixels of the pixel array are disposed in the even columns.

4. The image sensor of claim 1, wherein the FCA comprises a Most Significant Bit (MSB) capacitor and the SCA comprises another MSB capacitor, the first control circuit is coupled to sequentially switch the bottom plate of the FCA from the low reference voltage to the high reference voltage starting from the MSB capacitor in a first binary search sequence, and wherein the second control circuit is coupled to sequentially switch the bottom plate of the SCA from the high reference voltage to the low reference voltage starting from another MSB capacitor in a second binary search sequence.

5. The image sensor of claim 1, wherein the first SAR ADC and the second SAR ADC both have a number N of bits of resolution and the FCA comprises at least N capacitors and the SCA comprises at least N capacitors.

6. The image sensor of claim 5, wherein a first Most Significant Bit (MSB) in the FCA has a first value of about 2 to the power of (N-1) C1, wherein C1 is a first capacitance value of a first Least Significant Bit (LSB) capacitor in the FCA, and wherein a second MSB capacitor in the SCA has a second value of about 2 to the power of (N-1) C2, wherein C2 is a second capacitance value of a second LSB capacitor in the SCA.

7. The image sensor of claim 1, wherein the first control circuitry comprises a first register coupled to selectively switch a first switch coupled to individually switch the backplane of the FCA from the low reference voltage to the high reference voltage in response to the control signal, and wherein the second control circuitry comprises a second register coupled to selectively switch a second switch coupled to individually switch the backplane of the SCA from the high reference voltage to the low reference voltage in response to the control signal.

8. A method of reading out an array of pixels, the method comprising:

sampling a first analog pixel signal onto a first common terminal of a first capacitor array FCA coupled to a first comparator, wherein the first analog pixel signal is generated by a first column of the pixel array;

sampling a second analog pixel signal onto a second common terminal of a second capacitor array SCA coupled to a second comparator, wherein the second analog pixel signal is generated by a second column of the pixel array;

switching a first bottom plate of a Most Significant Bit (MSB) capacitor of the FCA from a low reference voltage to a high reference voltage to initiate a first binary search sequence for determining a first digital value of the first analog pixel signal; and

switching a second bottom plate of a second MSB capacitor of the SCA from the high reference voltage to the low reference voltage to initiate a second binary search sequence for determining a second digital value of the second analog pixel signal, wherein the first bottom plate and the second bottom plate are respectively opposite the first and second common terminals, and wherein the first bottom plate is switched from the low reference voltage to the high reference voltage at substantially the same time as the second bottom plate is switched from the high reference voltage to the low reference voltage to redistribute charge between the FCA and the SCA to reduce an additional amount of charge drawn from the low reference voltage and the high reference voltage.

9. The method of claim 8, further comprising inverting the second analog pixel signal prior to sampling the second analog pixel signal onto the second common terminal.

10. The method of claim 8, further comprising:

resetting the first comparator prior to sampling the first analog pixel signal onto the common terminal of the FCA; and

resetting the second comparator before sampling the second analog pixel signal onto the second common terminal of the SCA.

11. The method of claim 8, wherein the array of pixels is arranged in rows and columns and the columns of the array of pixels comprise even columns and odd columns that are staggered in every other configuration, the first columns being even columns and the second columns being odd columns.

12. The method of claim 11, wherein green pixels of the pixel array are disposed in the odd columns and red and blue pixels of the pixel array are disposed in the even columns.

13. The method of claim 8, wherein a green pixel signal from a green pixel of the pixel array is sampled onto the FCA but not onto the SCA.

14. The method of claim 8, wherein the FCA and the SCA comprise capacitors having binary weighted values.

15. An apparatus for reading out an array of pixels, comprising:

means for sampling a first analog pixel signal onto a first common terminal of a first capacitor array FCA coupled to a first comparator, wherein the first analog pixel signal is generated by a first column of the pixel array;

means for sampling a second analog pixel signal onto a second common terminal of a second capacitor array SCA coupled to a second comparator, wherein the second analog pixel signal is generated by a second column of the pixel array;

means for switching a first bottom plate of a Most Significant Bit (MSB) capacitor of the FCA from a low reference voltage to a high reference voltage to initiate a first binary search sequence for determining a first digital value of the first analog pixel signal; and

means for switching a second bottom plate of a second MSB capacitor of the SCA from the high reference voltage to the low reference voltage to initiate a second binary search sequence for determining a second digital value of the second analog pixel signal, wherein the first bottom plate and the second bottom plate are opposite the first and second common terminals, respectively, and wherein the first bottom plate is switched from the low reference voltage to the high reference voltage at substantially the same time as the second bottom plate is switched from the high reference voltage to the low reference voltage to redistribute charge between the FCA and the SCA to reduce an additional amount of charge drawn from the low reference voltage and the high reference voltage.

16. The apparatus of claim 15, further comprising:

means for inverting the second analog pixel signal prior to sampling the second analog pixel signal onto the second common terminal.

17. The apparatus of claim 15, further comprising:

means for resetting the first comparator prior to sampling the first analog pixel signal onto the first common terminal of the FCA; and

means for resetting the second comparator prior to sampling the second analog pixel signal onto the second common terminal of the SCA.

18. The apparatus of claim 15, wherein the array of pixels is arranged in rows and columns and the columns of the array of pixels comprise even columns and odd columns that are staggered in every other configuration, the first columns being even columns and the second columns being odd columns.

19. The apparatus of claim 18, wherein green pixels of the pixel array are disposed in the odd columns and red and blue pixels of the pixel array are disposed in the even columns.

20. The apparatus of claim 15, wherein the FCA and the SCA comprise capacitors having binary weighted values.