HK1197115B - Adaptive multiple conversion ramp analog-to-digital converter - Google Patents

Abstract

The subject application relates to adaptive multiple conversion ramp analog-to-digital converter. An example ramp analog-to-digital converter (ADC) for generating at least one bit of a digital signal includes a modified ramp signal generator, a comparator, and a control circuit. The modified ramp signal generator receives a ramp signal and generates a modified ramp signal in response thereto. The comparator compares an analog input with the modified ramp signal. The control circuit controls the modified ramp signal generator, such that the analog input is converted a variable M number of times for each period of the ramp signal. The number M is dependent on a magnitude of the analog input. In one example, the number M is greater for analog inputs of a lower magnitude, such that the analog inputs of the lower magnitude are converted more times than analog inputs of a higher magnitude.

Description

Adaptive multi-conversion ramp analog-to-digital converter

Technical Field

The present invention relates generally to ramp analog-to-digital converters, and particularly, but not exclusively, to those used in readout circuits of Complementary Metal Oxide Semiconductor (CMOS) image sensors.

Background

Image sensors are ubiquitous. It is widely used in digital still cameras, digital video cameras, cellular phones, security cameras, medical devices, automobiles, and other applications.

Many image sensors have image quality that is limited by several factors. One example of such a factor is temporal noise. For example, temporal noise (including various readout noise and quantization noise) can significantly limit the image quality of image sensor applications. Various methods may be implemented to reduce noise. One example for reducing temporal noise is to amplify the physical device area on the substrate. However, in many image sensors, this is generally not feasible given layout and size constraints.

Another approach for reducing temporal noise in image sensors is by means of an oversampled analog-to-digital converter (ADC) with noise shaping, e.g. by means of a sigma-delta ADC. In yet another approach, multiple samples of the pixel output having a fixed number of samples are averaged with an integrator (e.g., analog multi-sampling) or after an ADC (e.g., digital multi-sampling). However, conventional multi-sampling is often accompanied by additional circuit cost and multiple analog-to-digital conversions inherently become slower than an ADC that samples only once.

Disclosure of Invention

One technical problem to be solved by the present application is how to obtain a better signal-to-noise ratio (SNR) and a higher ADC resolution at a given rate or to obtain an equal SNR at a faster rate as a conventional ADC.

In one embodiment, the present application provides an adaptive analog-to-digital converter, ADC, for generating at least one bit of a digital signal, the adaptive ADC comprising: a modified ramp signal generator coupled to receive a ramp signal and to generate a modified ramp signal in response to the ramp signal; a comparator coupled to compare an analog input to the modified ramp signal; and a control circuit coupled to control the modified ramp signal generator such that the analog input is converted a variable number M of times for each period of the ramp signal, wherein the number M depends on a magnitude of the analog input, wherein the modified ramp signal includes M number of complete periods for each period of the ramp signal. In this embodiment, the ramp ADC takes less time to convert small signals than large signals. As soon as the previous conversion is completed, the proposed ADC starts a new conversion. The number of transitions (samples) is inversely proportional to the signal amplitude for a given total time. The reduced quantization noise equates to higher ADC resolution, e.g., a 10-bit ramp ADC can act as a 12-bit ADC while taking only a quarter of the conversion time.

In another embodiment, the present application provides an image sensor for generating digital image data, the image sensor comprising: a pixel array including a plurality of pixel cells arranged in rows and columns for capturing analog image data; a bit line coupled to at least one of the pixels within a column of the pixel array; and readout circuitry coupled to the bit lines to readout the analog image data from the at least one pixel, the readout circuitry including at least one adaptive analog-to-digital converter (ADC) for generating at least one bit of the digital image data, the adaptive ADC including: a modified ramp signal generator coupled to receive a ramp signal and to generate a modified ramp signal in response to the ramp signal; a comparator coupled to compare an analog input to the modified ramp signal; and a control circuit coupled to control the modified ramp signal generator such that the analog input is converted a variable number M of times for each period of the ramp signal, wherein the number M depends on a magnitude of the analog input, wherein the modified ramp signal includes M number of complete periods for each period of the ramp signal. In this embodiment, the number of samples taken for each pixel is adaptive to its signal level. Small signals are sampled more times, where small signals mean darker images and large signals mean brighter images. Thus, the overall read and quantization noise is reduced.

In yet another embodiment, the present application provides a method of converting analog image data to digital image data with an adaptive analog-to-digital converter (ADC), the method comprising: receiving a ramp signal and generating a modified ramp signal in response to the ramp signal; receiving analog image data at an input of a comparator of the adaptive ADC, wherein the comparator is coupled to compare the analog image data with the modified ramp signal; and controlling the modified ramp signal generator such that the analog image data is converted a variable number M of times for each period of the ramp signal, wherein the number M depends on a magnitude of the analog image data, wherein generating the modified ramp signal comprises generating the modified ramp signal to include M number of full periods for each period of the ramp signal. To reduce noise, each pixel output is converted multiple times, and the number of times of conversion is adaptive to the amplitude of the input signal, with small signals being converted more times and large signals being converted less times.

Drawings

The invention may be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments. In the drawings:

fig. 1 is a block diagram illustrating an image sensor having multiple adaptive ADCs according to an embodiment of the present invention.

Fig. 2 is a block diagram illustrating an example adaptive ADC according to an embodiment of the invention.

FIG. 3 is a block diagram illustrating an example adaptive ADC utilizing a global counter, according to an embodiment of the present disclosure.

Fig. 4 is a block diagram illustrating an example adaptive ADC according to an embodiment of the invention.

Fig. 5A and 5B are timing diagrams illustrating various waveforms of the adaptive ADC of fig. 4.

Fig. 6 is a flow diagram illustrating an example analog-to-digital conversion process using an adaptive ADC according to an embodiment of the invention.

Detailed Description

In the following description, numerous specific details are set forth, such as specific sensing circuits, voltage ramp signals, calibration circuit operational sequences, etc. However, it is understood that embodiments may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

Fig. 1 is a block diagram illustrating an image sensor 100 having multiple adaptive ADCs 118 in accordance with an embodiment of the present invention. Image sensor 100 includes a pixel array 110, control circuitry 120, readout circuitry 130, and optional digital processing logic 150. For simplicity of illustration, the illustrated embodiment of the pixel array 110 shows only two columns 112 each having four pixel cells 114. However, it should be understood that actual image sensors typically include from hundreds to thousands of columns, and each column typically includes from hundreds to thousands of pixels. Moreover, the illustrated pixel array 110 is regularly shaped (e.g., each column 112 has the same number of pixels), but in other embodiments the array may have a regular or irregular arrangement different from that shown and may include more or fewer pixels, rows, and columns than that shown. Moreover, in different embodiments, pixel array 110 can be a color image sensor including red, green, and blue pixels (or other color patterns) designed to capture images in the visible portion of the spectrum or can be a black and white image sensor and/or an image sensor designed to capture images in the invisible portion of the spectrum (e.g., infrared or ultraviolet). In one embodiment, image sensor 100 is a Complementary Metal Oxide Semiconductor (CMOS) image sensor.

During use, after a pixel cell 114 has acquired its image data or charge, analog image data (e.g., analog signals) or charge may be read out of the pixel cell to readout circuitry 130 via a column readout line or bit line 116. Analog image data from the pixel cells 114 of each column 112 is read out one pixel at a time via the bit lines 116 to the readout circuitry 130 and then transferred to the adaptive ADC 118.

In one embodiment, row-by-row readout is implemented using correlated double sampling ("CDS"). Each pixel in the selected row is reset prior to reading out image data from a row of pixels in pixel array 110. Resetting may include charging or discharging the floating diffusion region to a predetermined voltage potential, such as VDD.

CDS requires each pixel to provide two readouts to readout circuitry 130: reset reading and image signal reading. A reset read is performed to measure the voltage potential at the floating diffusion region with no image charge. Image signal reading is performed to measure a voltage potential at the floating diffusion region having image charge after transferring the image charge to the floating diffusion region. Subtracting the reset read measurement from the image signal read measurement results in a reduced noise value indicative of the image charge at the floating diffusion region. In one embodiment, the CDS is an analog CDS, where the subtraction of reset measurements from image signal readings is done in the analog domain prior to analog-to-digital conversion. In another embodiment, the CDS is digital, with each of the reset read measurements and the image signal read measurements converted via the adaptive ADC118 and stored in memory. The subtraction of the two values can then be performed in the digital domain to derive digital image data.

The adaptive ADC118 is a multi-conversion ramp ADC in which each analog image data output from a pixel is converted multiple times. However, as described above, the ADC118 is adaptive. Thus, the number of transitions made for each pixel depends on its signal level. In one embodiment, the darker signal is converted more times than the lighter signal. Generally, as the signal level increases, shot noise gradually becomes the dominant noise component of the signal. Multiple transitions may not reduce shot noise because it is correlated across all transitions. Thus, at large signal levels, the benefits of multi-sampling are diminished. Thus, embodiments of the present invention adapt the number of conversions by the magnitude of the analog image data.

In a ramp ADC, a small signal typically completes its conversion faster than a large signal. Thus, during the same period of the ramp signal, once the output is determined for the previous transition, the adaptive ADC118 starts a new transition. If the signal level is less than half of the full swing of the ramp signal, more than one transition will be completed. The smaller the signal, the more times the signal will be converted by the adaptive ADC 118. If the last transition is interrupted by the end of the ramp signal period, the transition is discarded. The average of the multiple conversions is then taken and output as digital image data.

Embodiments of ADC118 may include reduced quantization noise, which allows ADC118 to function as if it were a higher resolution conventional ramp ADC. For example, the 10-bit ramp ADC of the embodiments discussed herein may act as a conventional 12-bit ramp ADC while taking only a quarter of the conversion time. For low signal levels, the ADC118 may even perform better than a conventional 12-bit ramp ADC because the readout noise is also reduced. However, for high signal levels, the SNR may only increase to a certain extent, since the shot noise is dominant at these levels. In the illustrated embodiment, the adaptive ADC118 is used in the image sensor 100. However, in other embodiments, the adaptive ADC118 may be used in other semiconductor circuits.

Fig. 2 is a block diagram illustrating an example adaptive ADC200 according to an embodiment of the invention. The illustrated example of the adaptive ADC200 is shown to include an input stage 202, a modified ramp signal generator 204, a comparator 206, a control circuit 208, a transition counter 210, a summing counter 212, and a memory 214. ADC200 is one possible implementation of ADC118 of fig. 1.

As shown in fig. 2, input stage 202 is coupled to receive analog input, which in one example may be analog image data from column bitlines of a CMOS image sensor. Once received, the input stage 202 provides an analog signal to the input of the comparator 206. In one embodiment, the input stage 202 couples the transient changes in the analog signal to the inverting input of the comparator 206.

FIG. 2 further illustrates a coupling to receive a ramp signal V_RAMPAnd is responsive to a ramp signal V_RAMPTo generate a modified ramp signal V_{MOD_RAMP}The modified ramp signal generator 204. In one embodiment, the ramp signal V_RAMPIs a global ramp signal provided to several adaptive ADCs, such as each of the adaptive ADCs 118 of fig. 1. As can be seen from the embodiment of FIG. 1, the modified ramp signal V_{MOD_RAMP}May have a specific ramp signal V_RAMPPeriod T of₁Short period T_{MOD_RAMP}So as to be directed to the ramp signal V_RAMPEach cycle of (a) has a modified ramp signal V_{MOD_RAMP}A plurality of cycles of (a). Modified ramp signal V_{MOD_RAMP}Each complete cycle (i.e., one period) of (a) may represent an analog inputOne of (2). That is, the analog input may be converted M number of times, where M is for the ramp signal V_RAMPOf a single period T₁Modified ramp signal V_{MOD_RAMP}Complete period T of_{MOD_RAMP}The number of (2). In one embodiment, as will be discussed in more detail below, the number M depends on the magnitude of the analog input. For example, the analog input M for a lower magnitude may be larger such that the lower magnitude analog input is converted more times than the higher magnitude analog input.

In the illustrated embodiment, the comparator 206 is coupled to couple the analog input with the modified ramp signal V_{MOD_RAMP}A comparison is made. In operation, the comparator output COMP OUT will be responsive to the modified ramp signal V_{MOD_RAMP}The magnitude of which reaches the magnitude of the analog input to change state. The control circuit 208 is coupled to control the modified ramp signal generator 204 in response to the comparator output COMP OUT such that the analog input is converted M number of times. For example, fig. 2 illustrates that control circuit 208 generates a modified ramp control signal in response to comparator output COMP OUT, where modified ramp signal generator 204 is configured to generate a modified ramp signal V in response to the control signal_{MOD_RAMP}. As will be discussed in more detail below, the modified ramp signal generator 204 may include circuitry to generate the modified ramp signal V_{MOD_RAMP}The capacitor and the switch arrangement of (1). For example, the control circuit 208 may control the switch to ramp the signal V_RAMPSelectively and capacitively coupled to a comparator, wherein a comparator output COMP OUT indicates a modified ramp signal V_{MOD_RAMP}When the magnitude of the analog input has been reached. The smaller the magnitude of the analog input, the smaller the magnitude of the ramp signal V_RAMPEach period T of₁Modified ramp signal V_{MOD_RAMP}Complete period T of_{MOD_RAMP}The more.

Transition counter 210 and summing counter 212 are further illustrated in fig. 2. The transition counter 210 is coupled to count each period T for the ramp signal₁Comparator output COMP OUT indicates modified rampThe magnitude of the signal has reached the magnitude of the analog input M number of times. For example, comparator output COMP OUT may be coupled to a clock input of transition counter 210 such that transition counter 210 counts each pulse of comparator output COMP OUT. In one embodiment not shown in FIG. 2, in the ramp signal V_RAMPEach period T of₁The transition counter 210 is reset.

The summing counter 212 is coupled to generate a modified ramp signal V at the modified ramp signal V_{MOD_RAMP}Each period T of_{MOD_RAMP}During which it is enabled when the comparator output COMP OUT indicates that the magnitude of the modified ramp signal is less than the magnitude of the analog input. The summing counter 212 is disabled when the comparator output COMP OUT indicates that the magnitude of the modified ramp signal has reached the magnitude of the analog input.

When enabled, summing counter 212 counts cycles of the clock signal such that the count of the summing counter represents the magnitude of the analog input. For a ramp signal V_RAMPEach period T of₁The summing counter 212 is reset only once so that it keeps a running total of all M number of samples.

The adaptive ADC200 is further shown as including a memory 214. A memory 214 is coupled to the transition counter 210 and the summing counter 212. An output of memory 214 is coupled to digital processing logic 150. In one embodiment, digital processing logic 150 includes arithmetic operators 218. The arithmetic operator 218 may perform a divide operation to divide the running total count of the sum counter 212 via the memory 214 by the number of M conversions counted by the conversion counter 210, also via the memory 214. The arithmetic operator 218 may then generate a signal representing the ramp signal V_RAMPPeriod T of₁A digital output of an average of the magnitudes of the analog signals. In a column-parallel ADC architecture for an image sensor, counter contents from all columns may be transferred to memory at the same time; the memory can then be read out column by column as the ADC performs the next conversion.

FIG. 3 is a diagram illustrating an implementation utilizing a global counter 302 according to an embodiment of the present inventionA block diagram of an exemplary adaptive ADC 300. Adaptive ADC 300 is one possible implementation of adaptive ADC118 of fig. 1. The adaptive ADC 300 is similar in configuration and operation to the adaptive ADC200 of fig. 2. However, the adaptive ADC200 of fig. 2 includes a summing counter 212 local to the adaptive ADC 200. Instead of using the local sum counter 212, the adaptive ADC 300 may utilize a global counter 302. In one embodiment, the global count is a global signal provided to a number of adaptive ADCs, such as each of the adaptive ADCs 118 of fig. 1. Thus, in operation, the modified ramp signal V may be present_{MOD_RAMP}Each period T of_{MOD_RAMP}The start and end of global counter 302 writes the count of global counter 302 to translation logic 216 in order to determine the corresponding translated digital value. The translation logic 216 may include memory blocks and arithmetic operators. The memory block stores each stored converted digital value, while the arithmetic operator may sum and divide the taken M number of samples indicated by the arithmetic operator to produce an average converted value of the digital output. There may be a bi-directional data path between the memory block and the arithmetic operator.

In this embodiment, one arithmetic operator is required for each adaptive ADC 300, whereas in the adaptive ADC200 of fig. 2, multiple adaptive ADCs may share one arithmetic operator 218.

Fig. 4 is a block diagram illustrating an example adaptive ADC400 according to an embodiment of the invention. Adaptive ADC400 is one possible implementation of adaptive ADC200 of fig. 2. That is, the adaptive ADC400 includes an input stage implemented as a capacitor C0, a comparator 402 with an auto-zero switch AZ, a modified ramp signal generator implemented as capacitors C1, C2, and a switch SW1, a control circuit 404, a transition counter 406, a summing counter 408, a memory 410, and a memory 412. Fig. 5A and 5B are timing diagrams illustrating various waveforms of the adaptive ADC of fig. 4. Fig. 6 is a flow diagram illustrating an example analog-to-digital conversion process 600 using the adaptive ADC 400. The operation of the adaptive ADC400 will now be described with reference to fig. 4 to 6.

First, in process block 605, an analog input is received at capacitor C0, which capacitor C0 then provides to the inverting input of comparator 402. Further, at time t0, in process block 610, the ramp signal V is received at capacitors C1 and C2_RAMP. In the case where the output of the comparator 402 is initially low, the control circuit 404 opens the switch SW1 to ramp the signal V through the capacitors C1 and C2_RAMPIs coupled to the comparator 402 to generate a modified ramp signal V_{MOD_RAMP}(i.e., process block 615). At the ramp signal V_RAMPWith coupling to comparator 402 through capacitors C1 and C2, the voltage at node 401 (i.e., modified ramp signal V)_{MOD_RAMP}) And starts to rise.

Next, in process block 620, the comparator 402 compares the analog image data with the generated modified ramp signal V_{MOD_RAMP}A comparison is made. Initially low at the output of comparator 402 (i.e., modified ramp signal V)_{MOD_RAMP}Is less than the magnitude of the analog input), the sum counter 408 will be enabled. Thus, at time t0, the summing counter 408 will begin counting the clock signal U_CLOCKClock cycles of (c). Next, at time t1, the modified ramp signal V_{MOD_RAMP}Has reached the magnitude of the analog input. Thus, the output of comparator 402 changes state (e.g., logic high). In the case where the output of comparator 402 is high, several events then occur: first, transition counter 406 is clocked such that its count is incremented by 1; second, the control circuit 404 sends an enable input to the summing counter 408, which is de-asserted to halt counting on the summing counter 408; third, the control circuit 404 closes the switch SW1 to decouple the ramp signal V_RAMP(ii) a And fourth, the control circuit 404 signals the write input of the memory 412 to store the current count 502 of the summing counter 408.

In one embodiment, the control circuit 404 includes a delay circuit (not shown) for generating one or more of the illustrated control signals in response to the comparator output signal COMPOUT. Further, with respect to this embodiment, the drawings5B illustrates the comparator output signal COMPOUT and the modified ramp signal V when a delay circuit is included_{MOD_RAMP}And an expanded view of a portion of the additional control signals generated by the control circuit 404. The timing diagram of FIG. 5B is illustrated as beginning at time t1, which corresponds to comparator output COMPOUT changing to logic high at time t1 in FIG. 5A. The timing diagram of FIG. 5B further extends until time t1C, which is associated with modified ramp signal V_{MOD_RAMP}Begins at time t 1C. As shown in fig. 5B, at time t1, the output of comparator 402 changes state to logic high, which begins at least three delays. The first delay is the delay from time t1 to time t1A and is the delay associated with disabling the summing counter 406 and closing the switch SW1 in response to the comparator output signal COMPOUT changing state. The second delay is from time t1 to time t1B and is provided to allow time for summing counter 406 to settle before a write command is asserted to write the contents of summing counter 406 to memory 412. The third delay is from time t1 to time t1C and will prevent the summing counter 412 from being enabled and the switch SW1 from being opened (via the local ramp control signal) until the comparator output COMPOUT stabilizes.

Decoupling the ramp signal by means of switch SW1 to reflect the modified ramp signal V_{MOD_RAMP}Of the first complete period T2. At the ramp signal V_RAMPWith the decoupling at time t1A, as shown in fig. 5B, after a delay, the output of comparator 402 reverts to its low state, thereby opening switch SW1 to couple capacitors C1 and C2 and enabling summing counter 408 to restart its count. The process 600 repeats itself at decision block 630 until the ramp signal has reached its maximum value (i.e., the end of period T1 is reached). However, at time T2 (i.e., the end of the RAMP signal period T1), the modified RAMP signal VMOD _ RAMP has not yet reached the value of the analog input. Thus, transition counter 406 is not incremented and the current count on summing counter 408 is ignored. The count on transition counter 406 is then stored in memory 410. The arithmetic operator 414 then divides the value 502 stored in the memory 412 by the count stored in the memory 410 to derive an average of the digital data. In thatAt the end of ramp signal period T1 at time T2, a global reset signal (e.g., reset signal 405) resets both transition counter 406 and summing counter 408 to prepare adaptive ADC400 for the next transition. The embodiment described above illustrates a large signal sample from time t0 to time t2, where the number of M complete conversions made is equal to 1, such that the average is the value 502 divided by 1.

The embodiment illustrated in fig. 5A illustrates small signal sampling from time T2 to time T4, where the analog input is converted multiple times during a single ramp signal period T1. In particular, the small-signal analog input is converted six times such that the summing counter 408 has a value of 504 and the count on the conversion counter is 6. Thus, at time t4, the arithmetic operator 414 calculates the average digital data value as the value 504 divided by 6. As can be seen from this embodiment, small signal levels (i.e., low magnitude analog inputs) are converted more times than large signal levels. In one embodiment, the number of transitions M increases as the magnitude of the analog input decreases.

The image sensors disclosed herein may be included in digital still cameras, digital video cameras, camera phones, video phones, camcorders, webcams, video cameras in computer systems, security cameras, medical imaging devices, optical mice, toys, game consoles, scanners, automotive image sensors, or other types of electronic image and/or video acquisition devices. Depending on the implementation, the electronic image and/or video acquisition device may also include other components, such as a light source to emit light, one or more lenses optically coupled to focus the light on the pixel array, shutters optically coupled to allow the light to pass through the one or more lenses, a processor to process image data, and a memory to store the image data, to name a few examples.

In the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. For example, the calibration circuit may be coupled with the column ADC circuit via intervening switches.

In the description above, for purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiments. It will be apparent, however, to one skilled in the art that one or more other embodiments may be practiced without some of these specific details. The particular embodiments described are not provided to limit the invention but to illustrate it. The scope of the invention is not to be determined by the specific examples provided above but only by the claims below. In other instances, well-known circuits, structures, devices, and operations have been shown in block diagram form or without detail in order to avoid obscuring the understanding of the description.

Those skilled in the art will also appreciate that modifications may be made to the embodiments disclosed herein, e.g., in the arrangement, function, and manner of operation and use of the components of the embodiments. All equivalent relationships to the relationships illustrated in the drawings and described in the specification are encompassed within the embodiments. Further, where considered appropriate, reference numerals or terminal portions of reference numerals have been repeated among the figures to indicate corresponding or analogous elements, which optionally may have similar characteristics.

Various operations and methods have been described. Although some of the methods have been described in a flow diagram in a basic form, operations may optionally be added to and/or removed from the methods. Additionally, while the flow diagrams show a particular order of operation according to example embodiments, it is understood that the particular order is exemplary. Alternative embodiments may optionally perform the operations in a different order, combine certain operations, overlap certain operations, or the like. Many modifications and variations can be made to the method and are covered by the present invention.

One or more embodiments include an article of manufacture (e.g., a computer program product) comprising a machine-accessible and/or machine-readable medium. The medium may include mechanisms that provide (e.g., store) information in a form that can be accessed and/or read by a machine. The machine-accessible and/or machine-readable medium may provide, or have stored thereon, one or more instructions and/or data structures, or sequences of instructions and/or data structures, which if executed by a machine, cause or result in the machine performing and/or causing the machine to perform one or more or a portion of the operations or methods or techniques shown in the figures disclosed herein.

In one embodiment, the machine-readable medium may comprise a tangible, non-transitory machine-readable storage medium. For example, a tangible, non-transitory, machine-readable storage medium may include a floppy disk, an optical storage medium, an optical disk, a CD-ROM, a magnetic disk, a magneto-optical disk, a read-only memory (ROM), a programmable ROM (prom), an erasable and programmable ROM (eprom), an electrically erasable and programmable ROM (eeprom), a Random Access Memory (RAM), a static RAM (sram), a dynamic RAM (dram), a flash memory, a phase change memory, or a combination thereof. The tangible media may include one or more solid or tangible physical materials, such as semiconductor materials, phase change materials, magnetic materials, and the like.

Examples of suitable machines include, but are not limited to: digital cameras, digital video cameras, cellular telephones, computer systems, other electronic devices having arrays of pixels, and other electronic devices capable of capturing images. Such electronic devices typically include one or more processors coupled with one or more other components, such as one or more storage devices (non-transitory machine-readable storage media). Thus, the storage device of a given electronic device may store code and/or data for execution on one or more processors of the electronic device. Alternatively, one or more portions of an embodiment may be implemented using different combinations of software, firmware, and/or hardware.

It should also be appreciated that reference throughout this specification to "one embodiment," "an embodiment," or "one or more embodiments," for example, means that a particular feature may be included in the practice of the invention (e.g., in at least one embodiment). Similarly, it should be appreciated that various features are sometimes grouped together in a description herein in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the appended claims reflect: inventive aspects may lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment.

Claims (16)

1. An adaptive analog-to-digital converter (ADC) for generating at least one bit of a digital signal, the ADC comprising:

a modified ramp signal generator coupled to receive a ramp signal and to generate a modified ramp signal in response to the ramp signal;

a comparator coupled to compare an analog input to the modified ramp signal; and

a control circuit coupled to control the modified ramp signal generator such that the analog input is converted a variable number M of times for each period of the ramp signal, wherein the number M depends on a magnitude of the analog input, wherein the modified ramp signal includes M number of complete periods for each period of the ramp signal, and wherein the modified ramp signal has a constant voltage-time slope.

2. The adaptive analog-to-digital converter, ADC, of claim 1 wherein the number M is greater for lower magnitude analog inputs, such that the lower magnitude analog inputs are converted more times than higher magnitude analog inputs.

3. The adaptive analog-to-digital converter (ADC) of claim 1, wherein the modified ramp signal generator comprises:

a capacitor to capacitively couple the ramp signal to an input of the comparator; and

a switch coupled to control charging and discharging of the capacitor in response to the control circuit.

4. The adaptive analog-to-digital converter (ADC) of claim 3, wherein the control circuit enables the switch to discharge the capacitor in response to an output of the comparator indicating that a magnitude of the modified ramp signal has reached the magnitude of the analog input.

5. The adaptive analog-to-digital converter (ADC) of claim 4, further comprising a first counter coupled to the comparator to count the M number of times that the output of the comparator indicates, for each cycle of the ramp signal, that the magnitude of the modified ramp signal has reached the magnitude of the analog input.

6. The adaptive analog-to-digital converter (ADC) of claim 5, further comprising a second counter coupled to the control circuit to be enabled when the output of the comparator indicates that the magnitude of the modified ramp signal is less than the magnitude of the analog input at each period of the modified ramp signal, wherein when enabled, the second counter counts cycles of a clock signal such that a count of the second counter represents the magnitude of the analog input.

7. The adaptive analog-to-digital converter (ADC) of claim 6, further comprising an arithmetic operator coupled to divide the count of the second counter by the count of the first counter to produce a digital output representative of an average of the magnitude of an analog signal over the period of the ramp signal.

8. An image sensor for generating digital image data, the image sensor comprising:

a pixel array including a plurality of pixel cells arranged in rows and columns for capturing analog image data;

a bit line coupled to at least one of the pixels within a column of the pixel array; and

a readout circuit coupled to the bit line to readout the analog image data from the at least one pixel, the readout circuit including at least one adaptive analog-to-digital converter (ADC) for generating at least one bit of the digital image data, the adaptive analog-to-digital converter (ADC) including:

a modified ramp signal generator coupled to receive a ramp signal and to generate a modified ramp signal in response to the ramp signal;

a comparator coupled to compare an analog input to the modified ramp signal; and

a control circuit coupled to control the modified ramp signal generator such that the analog input is converted a variable number M of times for each period of the ramp signal, wherein the number M depends on a magnitude of the analog input, wherein the modified ramp signal includes M number of complete periods for each period of the ramp signal, and wherein the modified ramp signal has a constant voltage-time slope.

9. The image sensor of claim 8, wherein the number M is greater for lower magnitude analog image data such that the lower magnitude analog image data is converted more times than higher magnitude analog image data.

10. The image sensor of claim 8, wherein the modified ramp signal generator comprises:

a capacitor to capacitively couple the ramp signal to an input of the comparator; and

a switch coupled to control charging and discharging of the capacitor in response to the control circuit.

11. The image sensor of claim 10, wherein the control circuit enables the switch to discharge the capacitor in response to an output of the comparator indicating that a magnitude of the modified ramp signal has reached the magnitude of the analog image data.

12. The image sensor of claim 11, wherein the adaptive analog-to-digital converter (ADC) further comprises a first counter coupled to the comparator to count the M number of times that the output of the comparator indicates, for each cycle of the ramp signal, that the magnitude of the modified ramp signal has reached the magnitude of the analog image data.

13. The image sensor of claim 12, wherein the adaptive analog-to-digital converter (ADC) further comprises a second counter coupled to be enabled when the output of the comparator indicates that the magnitude of the modified ramp signal is less than the magnitude of the analog image data each period of the modified ramp signal, wherein when enabled, the second counter counts cycles of a clock signal such that a count of the second counter represents the magnitude of the analog image data.

14. The image sensor of claim 13, further comprising an arithmetic operator coupled to divide the count of the second counter by the count of the first counter to generate the digital image data representing an average of the magnitudes of the analog image data over the period of the ramp signal.

15. A method of converting analog image data to digital image data with an adaptive analog-to-digital converter, ADC, the method comprising:

receiving a ramp signal and generating a modified ramp signal in response to the ramp signal;

receiving analog image data at an input of a comparator of the adaptive analog-to-digital converter (ADC), wherein the comparator is coupled to compare the analog image data with the modified ramp signal; and

controlling the modified ramp signal generator such that the analog image data is converted a variable number M of times for each period of the ramp signal, wherein the number M depends on a magnitude of the analog image data, wherein generating the modified ramp signal comprises generating the modified ramp signal to include M number of complete periods for each period of the ramp signal, and wherein the modified ramp signal has a constant voltage-time slope.

16. The method of claim 15, wherein the number M is greater for lower magnitude analog image data such that the lower magnitude analog image data is converted more times than higher magnitude analog image data.