HK1196898A

HK1196898A - Field-effect transistor structures and related radio-frequency switches

Info

Publication number: HK1196898A
Application number: HK14109613.2A
Authority: HK
Inventors: Jonathan Christian CRANDALL
Original assignee: 天工方案公司
Priority date: 2011-11-09
Filing date: 2012-11-08
Publication date: 2014-12-24

Description

Field effect transistor structure and related radio frequency switch

CROSS-APPLICATION OF RELATED APPLICATIONS

Priority OF U.S. provisional application No.61/557,709 entitled "DEVICES ANDMETHOLOLOGIES RELATED TO A FET-BASED RF SWITCH HAVING AREDUCED PRODUCT OF RDS-ON AND AREA", filed ON 9/11/2011, is expressly incorporated herein in its entirety by reference.

Technical Field

The present disclosure relates generally to Field Effect Transistor (FET) structures and Radio Frequency (RF) devices, e.g., switches having such FET structures.

Background

Field Effect Transistors (FETs) may be used as switches for Radio Frequency (RF) applications. FET-based switches, such as silicon-on-insulator (SOI) switches, are used, for example, in antenna switching modules and front-end modules. Such applications typically benefit from ideal SOI transistor structures or near ideal isolation.

SOI devices are typically rated for only a few volts. Thus, several SOI switches having a relatively large width/length ratio may be arranged in series to provide the RF conversion function. Such a configuration divides the (voltage-frequencies) converted RF signal, thus mitigating the breakdown problem and improving reliability under relevant conditions, such as high RF power/voltage or high Voltage Standing Wave Ratio (VSWR).

Disclosure of Invention

In various embodiments, the present disclosure relates to a transistor including a semiconductor substrate, a plurality of first diffusion regions formed on the semiconductor substrate, and a plurality of second diffusion regions formed on the semiconductor substrate. The transistor further includes a gate layer disposed over the first and second diffusion regions. The gate layer defines a first opening over each of the first diffusion regions and a second opening over each of the second diffusion regions. At least some of the first openings and the second openings have a shape other than a rectangle.

In some embodiments, the transistor may further include a contact structure formed on each of the first and second diffusion regions. In some embodiments, the transistor may further include a first conductor electrically connecting the contact structure on the first diffusion region. In some embodiments, the transistor may further include a second conductor electrically connecting the contact structure on the second diffusion region. The first conductor may be further connected to the source terminal, and the second conductor may be further connected to the drain terminal.

In some embodiments, at least some of the first and second openings have a first shape defined by an outline of an elongated shape having a center and a long axis along the first direction and a diamond shape having a center located substantially at the center of the elongated shape. The diamond shape may be oriented such that one set of opposing corners is along the major axis and the other set of opposing corners is substantially perpendicular to the major axis.

In certain embodiments, the elongated shape may comprise a rectangle having a length along the first direction. In some embodiments, the elongated shape may comprise a hexagon elongated along the first direction. The plurality of first openings having the first shape may form a first column, wherein the first openings in the first column are arranged along a second direction, the second direction being substantially perpendicular to the first direction. The plurality of second openings having the first shape may form a second column, wherein the second openings in the second column are aligned along a second direction and offset from the first openings along the first direction. The first openings of the first columns and the second openings of the second columns may be staggered along the first direction and along the second direction. Each of the first and second conductors may extend along the second direction.

In some embodiments, the transistor may further include a third column having additional first openings, the third column of the first openings being staggered from the second openings of the second column along the first direction and the second direction. In some embodiments, the transistor may further include a fourth column having additional second openings, the fourth column of additional second openings being staggered from the first openings of the third column along the first direction and the second direction.

In certain embodiments, an adjacent pair of the first and second openings may include a first facing portion for the first opening and a second facing portion for the second opening. At least one of the first and second facing portions may have a plurality of segments extending in different directions.

In certain embodiments, an adjacent pair of the first and second openings may include a first facing portion for the first opening and a second facing portion for the second opening. The first and second facing portions may define opposite sides of a quadrilateral other than a rectangle.

In some embodiments, the transistor may be a Field Effect Transistor (FET) having a plurality of first diffusion regions as a source of the FET and a plurality of second diffusion regions as a drain of the FET. The FET may comprise an n-type FET or a p-type FET. The FET may comprise a Metal Oxide Semiconductor FET (MOSFET).

In some embodiments, the transistor may also include an insulator layer disposed below the semiconductor substrate. The semiconductor substrate may comprise a silicon substrate to form a silicon-on-insulator (SOI) structure.

In some embodiments, the shape may be dimensioned to yield a reduced value of Rds-on per unit area when compared to a transistor having a similarly sized rectangular opening.

According to various embodiments, the present disclosure relates to a method of manufacturing a transistor. The method includes providing a semiconductor substrate. The method also includes forming a plurality of first diffusion regions on the semiconductor substrate and forming a plurality of second diffusion regions on the semiconductor substrate. The method also includes forming a gate layer disposed over the first and second diffusion regions. The gate layer defines a first opening over each of the first diffusion regions and a second opening over each of the second diffusion regions. At least some of the first and second openings have a shape other than rectangular.

According to certain teachings, the present disclosure relates to a mask for fabricating a semiconductor transistor. The mask includes a plurality of structures that allow a gate layer to be formed over a semiconductor substrate such that the formed gate layer defines a first opening and a second opening, wherein at least some of the first and second openings have a shape other than a rectangle.

In various embodiments, the present disclosure relates to a semiconductor chip including a semiconductor substrate and a plurality of transistors implemented on the substrate. Each transistor includes a plurality of first diffusion regions and a plurality of second diffusion regions. Each transistor further includes a gate layer disposed over the first and second diffusion regions, wherein the gate layer defines a first opening over each of the first diffusion regions and a second opening over each of the second diffusion regions. At least some of the first and second openings have a shape other than rectangular.

In certain embodiments, a plurality of transistors may be connected in series to form a switchable conductive path for a Radio Frequency (RF) signal.

In some embodiments, the present disclosure relates to a semiconductor module having a package substrate configured to accommodate a plurality of components and a chip mounted on the package substrate. The chip includes a plurality of transistors implemented on a semiconductor substrate. Each transistor includes a plurality of first diffusion regions and a plurality of second diffusion regions. Each transistor further includes a gate layer disposed over the first and second diffusion regions, wherein the gate layer defines a first opening over each of the first diffusion regions and a second opening over each of the second diffusion regions. At least some of the first and second openings have a shape other than rectangular. The module also includes a plurality of connectors configured to provide electrical connections between the chip and the package substrate.

According to certain embodiments, the present disclosure relates to a Radio Frequency (RF) device having a transceiver configured to process RF signals, a power amplifier configured to amplify the RF signals generated by the transceiver, and an antenna in communication with the transceiver and configured to facilitate transmission of the amplified RF signals. The RF device also includes a switching module coupled to the power amplifier and the antenna. The conversion module is configured to transmit the amplified RF signal from the power amplifier to the antenna. The conversion module has a switching circuit including a plurality of transistors connected in series. Each transistor includes a plurality of first diffusion regions and a plurality of second diffusion regions. Each transistor further includes a gate layer disposed over the first and second diffusion regions, wherein the gate layer defines a first opening over each of the first diffusion regions and a second opening over each of the second diffusion regions. At least some of the first and second openings have a shape other than rectangular.

In certain embodiments, the present disclosure relates to a Radio Frequency (RF) switch that includes a semiconductor substrate and an input component having a plurality of source regions formed on the semiconductor substrate, a source contact formed on each of the source regions, and an input conductor electrically connected to each of the source contacts. The RF switch also includes an output component having a plurality of drain regions formed on the semiconductor substrate, a drain contact formed on each of the drain regions, and an output conductor electrically connected to each of the drain contacts. The RF switch also includes a gate layer disposed over the source and drain regions, wherein the gate layer defines a first opening over each of the source regions and a second opening over each of the drain regions. At least some of the first and second openings are arranged in a two-dimensional array.

In certain embodiments, the RF switch may also include an input terminal connected to the input conductor and an output terminal connected to the output conductor.

In certain embodiments, each of the first and second openings may have a parallelogram shape. The first and second openings may be arranged such that adjacent sides of a pair of openings are substantially parallel, wherein each of the input and output conductors extends diagonally over a corresponding one of the first and second openings. In some embodiments, the parallelogram shape may be a square shape, such that the array of squares defines a pattern of squares.

In some embodiments, at least some of the first and second openings may have a first shape defined by an outline of an elongated shape having a center and a long axis along the first direction and a diamond shape having a center located substantially at the center of the elongated shape. The diamond shape may be oriented such that one set of opposing corners is along the major axis and the other set of opposing corners is substantially perpendicular to the major axis. The elongated shape may comprise a rectangle having a length along the first direction. The elongated shape may comprise a hexagon elongated along the first direction. The plurality of first openings having the first shape may form a first column, wherein the first openings in the first column are aligned along a second direction that is substantially perpendicular to the first direction. The plurality of second openings having the first shape may form a second column, wherein the second openings in the second column are aligned along a second direction and offset from the first openings along the first direction. The first openings of the first columns and the second openings of the second columns may be staggered along the first direction and along the second direction. Each of the input conductor and the output conductor may extend along the second direction.

In some embodiments, the RF switch may further include a third column having additional first openings, the third column of additional first openings being staggered from the second openings of the second column along the first direction and the second direction. In some embodiments, the RF switch may further include a fourth column having additional second openings, the fourth column of second openings being staggered from the first openings of the third column along the first direction and the second direction.

In some embodiments, the source region, the drain region, and the gate may be configured as a metal oxide semiconductor fet (mosfet).

In some embodiments, the RF switch may further include an insulator layer disposed below the semiconductor substrate. The semiconductor substrate may comprise a silicon substrate, forming a silicon-on-insulator (SOI) structure.

In certain embodiments, the shape is dimensioned to produce a reduced value of Rds-on per unit area when compared to a rectangular opening of similar size.

According to various embodiments, the present disclosure relates to a method of manufacturing a Radio Frequency (RF) switch. The method includes providing a semiconductor substrate, forming a plurality of source regions on the semiconductor substrate, and forming a plurality of drain regions on the semiconductor substrate. The method also includes forming a gate layer over the source and drain regions, wherein the gate layer defines a first opening over each of the source regions and a second opening over each of the drain regions. At least some of the first and second openings are arranged in a two-dimensional array. The method also includes forming a contact on each of the source and drain regions and forming an input conductor electrically connected to the source contact and an output conductor electrically connected to the drain contact.

In accordance with many teachings, the present disclosure is directed to a Radio Frequency (RF) switch chip having a semiconductor substrate and a plurality of transistors implemented on the substrate. Each transistor includes a plurality of source regions and a plurality of drain regions. Each transistor may further include a gate layer disposed over the source and drain regions, wherein the gate layer defines a first opening over each of the source regions and a second opening over each of the drain regions. At least some of the first and second openings are arranged in a two-dimensional array. The chip also includes a source contact formed on each source region and a drain contact formed on each drain region. The chip also includes an input conductor electrically connected to the source contact and an output conductor electrically connected to the drain contact.

In many embodiments, the present disclosure relates to a Radio Frequency (RF) conversion module having a package substrate configured to accommodate a plurality of components and a chip mounted on the package substrate. The chip has a plurality of transistors implemented on a semiconductor substrate. Each transistor includes a plurality of source regions and a plurality of drain regions. Each transistor further includes a gate layer disposed over the source and drain regions, wherein the gate layer defines a first opening over each of the source regions and a second opening over each of the drain regions. At least some of the first and second openings are arranged in a two-dimensional array. Each transistor also includes a source contact formed on each source region and a drain contact formed on each drain region. The chip also includes an input conductor electrically connected to the source contact and an output conductor electrically connected to the drain contact. The module also includes a plurality of connectors configured to provide electrical connections between the chip and the package substrate.

In certain embodiments, the present disclosure relates to Radio Frequency (RF) devices. The RF device includes a transceiver configured to process an RF signal, a power amplifier configured to amplify the RF signal generated by the transceiver, and an antenna in communication with the transceiver and configured to facilitate transmission of the amplified RF signal. The RF device also includes a switching module connected to the power amplifier and the antenna. The conversion module is configured to transmit the amplified RF signal from the power amplifier to the antenna. The conversion module has a switching circuit including a plurality of transistors connected in series. Each transistor includes a plurality of source regions and a plurality of drain regions. Each transistor further includes a gate layer disposed over the source and drain regions, wherein the gate layer defines a first opening over each of the source regions and a second opening over each of the drain regions. At least some of the first and second openings are arranged in a two-dimensional array. Each transistor also includes a source contact formed on each source region and a drain contact formed on each drain region. The source contact is connected to the input conductor for receiving the amplified RF signal, and the drain contact is connected to the output conductor for outputting the amplified RF signal.

In certain embodiments, the present disclosure relates to a conversion apparatus that includes a semiconductor substrate having a surface. The apparatus also includes a plurality of diffusion regions formed on the substrate to define one or more shapes on a surface of the substrate. The device also includes one or more first conductors electrically connected to the selected diffusion regions, wherein the one or more first conductors are connectable together as an input to the conversion device. The device also includes one or more second conductors electrically connected to the remaining diffusion regions, wherein the one or more second conductors are connectable together as an output of the conversion device. At least some of the one or more shapes associated with the one or more first conductors and at least some of the one or more shapes associated with the one or more second conductors are dimensioned to include first and second facing portions that substantially face each other and thus belong to a pair of adjacent diffusion regions. At least one of the first and second facing portions has a plurality of segments extending in different directions, or the first and second facing portions define opposite sides of a quadrilateral other than a rectangle.

In certain embodiments, the device may further include a structure formed between the plurality of diffusion regions and configured to allow control of charge flow between a region connected to the one or more first conductors and a region connected to the one or more second conductors. Such structures may include gate structures, and the plurality of diffusion regions connected to the one or more first conductors may correspond to sources of Field Effect Transistors (FETs). The plurality of diffusion regions may be connected to one or more second conductors corresponding to the drains of the FETs. Such FETs may include n-type FETs or p-type FETs. Such FETs may include metal oxide semiconductor FETs (mosfets).

In some embodiments, the device may further include terminals formed on the plurality of diffusion regions to provide electrical connections between the diffusion regions and their respective conductors. The device may also include a source conductor layer configured to electrically connect the one or more first conductors and a drain conductor layer configured to electrically connect the one or more second conductors.

In some embodiments, the apparatus may further include an insulator layer disposed below the semiconductor substrate. Such a semiconductor substrate may comprise a silicon substrate to form a silicon-on-insulator (SOI) structure.

In some embodiments, the one or more shapes may include a first cross shape associated with the diffusion region connected to the first conductor, wherein the first cross shape has extensions that are substantially perpendicular along the X and Y directions, and the diffusion region of the first cross shape is disposed along the X direction. The one or more shapes may also include a second cross-shape associated with the diffusion region connected to the second conductor, wherein the second cross-shape has substantially perpendicular extensions along the X and Y directions, and the second cross-shape diffusion region is disposed along the X direction and offset from the first cross-shape diffusion region along the X direction.

In some embodiments, the one or more shapes may further include a square shape associated with the diffusion region connected to the second conductor, wherein the square shape has sides along the X and Y directions, and the square shaped diffusion region is disposed along the X direction and offset from the first cross shaped diffusion region along the X direction. The one or more first cross shapes may also include a diamond shape in the center of the first cross shape.

In some embodiments, the first cross shape may include a bevel at the end of the extension. The one or more shapes may also include a snowflake shape associated with the diffusion region connected to the second conductor, wherein the snowflake shape has a perimeter defined by a combination of first and second squares, and the first square has sides along the X and Y directions, and the second square is rotated about 45 degrees relative to the first square.

In some embodiments, the one or more shapes associated with the diffusion region connected to the first conductor may include a first hexagonal shape, and the one or more first hexagonal shaped diffusion regions may be disposed along the X direction. The one or more shapes associated with the diffusion region connected to the second conductor may include a second hexagonal shape, and the one or more second hexagonal shaped diffusion regions may be disposed along the X-direction and offset from the first hexagonal shaped diffusion region along the X-direction.

In some embodiments, the one or more shapes may include a first double diamond shape associated with the diffusion region connected to the first conductor, and the first double diamond shape has first and second rhombus shapes that may be connected along the X-direction. One or more first double-diamond shaped diffusion regions may be arranged in a zigzag pattern along the X-direction. The one or more shapes may include a second double diamond shape associated with the diffusion region connected to the second conductor, and the second double diamond shape has first and second rhombus shapes connectable along the Y-direction. One or more second double diamond shaped diffusion regions may be arranged in a zigzag pattern along the X direction, thereby along a given X line.

In some embodiments, the one or more shapes may include a first double diamond shape associated with the diffusion region connected to the first conductor, and the first double diamond shape has first and second rhombus shapes connectable along a direction at an angle of about 45 degrees to the X-direction. One or more first double-diamond shaped diffusion regions may be disposed along the X-direction. The one or more shapes may include a second double diamond shape associated with the diffusion region connected to the second conductor, and the second double diamond shape has first and second rhombus shapes connectable along a direction at an angle of about 45 degrees to the X-direction. One or more second double diamond-shaped diffusion regions may be disposed along the X-direction and offset from the first double diamond-shaped diffusion regions along the X-direction.

In some embodiments, the one or more shapes may include a first hexagonal shape associated with the diffusion region connected to the first conductor, wherein the first hexagonal shape is elongated along the Y-direction, and the one or more first hexagonal shaped diffusion regions may be disposed along the X-direction. The one or more shapes can include a second hexagonal shape associated with a diffusion region connected to the second conductor, wherein the second hexagonal shape is elongated along the Y-direction, and the one or more second hexagonal-shaped diffusion regions can be disposed along the X-direction and offset from the first hexagonal-shaped diffusion regions along the X-direction. The one or more shapes may also include a diamond shape at a center of each of the first and second hexagonal shapes. Each of the first and second hexagonal shapes may include tapered corners of the diamond shape along the X-direction. The one or more shapes may also include a second elongated hexagonal shape at a center of each of the first and second elongated hexagonal shapes and having a Y dimension between dimensions of the respective elongated hexagonal shape and its corresponding diamond shape.

In some embodiments, the one or more shapes may include a first rectangular shape associated with the diffusion region connected to the first conductor, wherein the first rectangular shape is elongated along the Y-direction, and the one or more first rectangular shaped diffusion regions may be disposed along the X-direction. The one or more shapes may include a second rectangular shape associated with the diffusion region connected to the second conductor, wherein the second rectangular shape is elongated along the Y-direction, and the one or more second rectangular shaped diffusion regions may be disposed along the X-direction and offset from the first rectangular shaped diffusion region along the X-direction. The one or more shapes may also include a diamond shape at a center of each of the first and second elongated rectangular shapes.

In some embodiments, the one or more shapes may include a first cross shape associated with the diffusion region connected to the first conductor, wherein the first cross shape has a substantially perpendicular extension along a direction about 45 degrees relative to the X and Y directions, and the one or more first cross shaped diffusion regions may be disposed along the X direction. The one or more shapes may include a second cross shape associated with the diffusion region connected to the second conductor, wherein the second cross shape has a substantially perpendicular extension along a direction about 45 degrees relative to the X and Y directions, and the one or more second cross shaped diffusion regions may be disposed along the X direction and offset from the first cross shaped diffusion region along the X direction. The dimensions of each of the first and second cross shapes may be formed so that two extensions from the center of the shape along a given 45 degree direction are offset on opposite sides along a 45 degree line. Each offset extension may include a beveled end corner on the side of the extension further away from the 45 degree line. Each of the first and second cross shapes may also include a diamond shape about a center of each cross shape.

In some embodiments, the one or more shapes may include an octagonal shape associated with the diffusion region connected to the first conductor, and the one or more octagonal shaped diffusion regions may be disposed along the X direction. The octagonal shape can include a first elongated octagonal shape with a first elongated direction being a direction angled at about 45 degrees relative to the X-direction. The one or more shapes may include a second elongated octagonal shape associated with a diffusion region connected to the second conductor, wherein the elongated direction is at an angle of about 45 degrees relative to the X-direction, and the one or more second elongated octagonal shaped diffusion regions may be disposed along the X-direction and offset from the first elongated octagonal shaped diffusion region along the X-direction.

According to various embodiments, the present disclosure relates to a Radio Frequency (RF) conversion device having a plurality of transistor switches arranged in series. Each switch has an input and an output, such that the output of an intermediate switch serves as the input of its neighboring switch. Each switch includes a structure configured to allow control of charge flow between an input and an output. Each switch further comprises: a semiconductor substrate having a surface; a plurality of diffusion regions formed on the substrate to define one or more shapes on a surface of the substrate; one or more first conductors electrically connected to the selected diffusion regions, wherein the one or more first conductors are connectable together as an input to the conversion device; and one or more second conductors electrically connected to the remaining diffusion regions, wherein the one or more second conductors are connectable together as an output of the conversion device. At least some of the one or more shapes associated with the one or more first conductors and at least some of the one or more shapes associated with the one or more second conductors are dimensioned to include first and second facing portions that substantially face each other and thus belong to a pair of adjacent diffusion regions. At least one of the first and second facing portions has a plurality of segments extending in different directions, or the first and second facing portions define opposite sides of a quadrilateral other than a rectangle.

In some embodiments, the semiconductor substrate may comprise a silicon substrate. The RF conversion device may further include an insulator layer below the silicon substrate to form a silicon-on-insulator (SOI) structure to provide high isolation and high R_ON/C_OFFA quality factor. Each transistor switch may comprise a MOSFET switch such that the input comprises a source. The structure for controlling the flow of charge may comprise a gate and the output may comprise a drain. The number of switches may be selected to allow for a division of the high power RF signal, where each division is selected to be less than the breakdown voltage of the SOI structure. The dimensions and arrangement of the first and second facing portions may be selected to produce R_DS-ONAnd a relatively low product of the area of each switch.

According to certain embodiments, the present disclosure relates to an antenna switching module for a wireless device. The module includes a conversion device configured to convert one or more RF signals to and from one or more antennas. The conversion means comprises a plurality of transistor switches, wherein each switch has an input and an output, such that the output of an intermediate switch serves as the input of its neighbouring switch, and each switch comprises a structure configured to allow control of the flow of charge between the input and the output. Each switch further comprises: a semiconductor substrate having a surface; a plurality of diffusion regions formed on the substrate to define one or more shapes on a surface of the substrate; one or more first conductors electrically connected to the selected diffusion regions, wherein the one or more first conductors are connectable together as an input for the conversion device; and one or more second conductors electrically connected to the remaining diffusion regions, wherein the one or more second conductors are connectable together as an output for the conversion device. At least some of the one or more shapes associated with the one or more first conductors and some of the one or more shapes associated with the one or more second conductors are dimensioned to include first and second facing portions that face each other and thus belong to a pair of adjacent diffusion regions. At least one of the first and second facing portions has a plurality of segments extending in different directions, or the first and second facing portions define opposite sides of a rectangular outer quadrilateral. The module also includes one or more antenna ports configured to allow connection to one or more antennas. The module also includes one or more RF ports configured to allow transmission of one or more RF signals to and/or from one or more antennas.

In many embodiments, the present disclosure relates to a front-end module for a wireless device. The module includes a switching arrangement configured to switch one or more RF signals to and from one or more antennas, wherein the switching arrangement includes a plurality of transistor switches, and each switch has an input and an output, such that the output of an intermediate switch serves as the input of its neighboring switch. Each switch includes a structure configured to allow control of charge flow between an input and an output. Each switch further comprises: a semiconductor substrate having a surface; a plurality of diffusion regions formed on the substrate so as to define one or more shapes on a surface of the substrate; one or more first conductors electrically connected to the selected diffusion regions, wherein the one or more first conductors are connectable together as an input for the conversion device; and one or more second conductors electrically connected to the remaining diffusion regions, wherein the one or more second conductors are connectable together as an output for the conversion device. At least some of the one or more shapes associated with the one or more first conductors and at least some of the one or more shapes associated with the one or more second conductors are dimensioned to include first and second facing portions that substantially face each other and thus belong to a pair of adjacent diffusion regions. At least one of the first and second facing portions has a plurality of segments extending in different directions, or the first and second facing portions define opposite sides of a quadrilateral other than a rectangle. The module also includes one or more input RF ports configured to receive and provide one or more RF signals to the conversion device. The module also includes one or more output RF ports configured to receive RF signals output from the conversion device and to transmit the output RF signals to a desired destination.

According to various embodiments, the present disclosure relates to a wireless device having a transceiver configured to process received RF signals and transmit RF signals. The wireless device also includes an antenna configured to facilitate reception of the received RF signal and transmission of the transmission signal. The wireless device also includes at least one conversion module configured to allow a desired RF signal to be transmitted between the transceiver and the antenna. The conversion means has one or more inputs and one or more outputs. The switching device also includes one or more mosfet soi transistor switches arranged in series, wherein each switch includes one or more diffusion regions having a first shape on a surface of the substrate and the one or more diffusion regions have a second shape on the surface of the substrate. The first and second shapes are dimensioned to include first and second facing portions that generally face each other. At least one of the first and second facing portions has a plurality of segments extending in different directions, or the first and second facing portions define opposite sides of a quadrilateral other than a rectangle. The conversion device also includes one or more source conductors interconnecting the one or more first shaped diffusion regions and one or more drain conductors interconnecting the one or more second shaped diffusion regions. MOSFET SOI transistor switches can be configured to provide high isolation and high R_ON/C_OFFA quality factor. The first and second shapes of the diffusion region may be selected to produce a relatively low R_DS-ONAnd the area of the conversion module.

In certain embodiments, the present disclosure relates to methods for manufacturing Radio Frequency (RF) conversion devices. The method includes providing or forming a silicon-on-insulator (SOI) structure having an isolation well on an insulator layer. The method also includes forming one or more source regions and one or more drain regions in the well, wherein the one or more source regions comprise a first shape and the one or more drain regions comprise a second shape. The first and second shapes are dimensioned to include first and second facing portions that generally face each other. At least one of the first and second facing portions has a plurality of segments extending in different directions, or the first and second facing portions define opposite sides of a quadrilateral other than a rectangle. The method also includes forming a gate between the one or more source regions and the one or more drain regions. The method also includes forming one or more electrical conductors interconnecting each of the one or more source regions. The method also includes forming one or more electrical conductors interconnecting each of the one or more drain regions.

In certain embodiments, the present disclosure relates to a Radio Frequency (RF) switch having a semiconductor substrate and a diffusion layer formed on the substrate. The RF switch also includes a gate layer formed over the diffusion layer. The gate layer defines a plurality of shaped openings arranged in a two-dimensional form and exposes an opening-shaped region of the diffusion layer. Each of the opening-like regions is grouped into a source region or a drain region. The RF switch further includes an electrical contact formed on each of the opening-like regions. The RF switch also includes one or more source conductors configured to electrically connect electrical contacts associated with the source regions and one or more drain conductors configured to electrically connect electrical contacts associated with the drain regions.

For the purpose of summarizing the disclosure, certain aspects, advantages and novel structures of the invention have been described herein. It is to be understood that not necessarily all such advantages may be achieved in any particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

Drawings

Fig. 1A schematically illustrates a wireless device having a switch component that can be configured to include one or more structures of the present disclosure.

FIG. 1B schematically illustrates a more specific example of the wireless device of FIG. 1A.

Fig. 2A schematically illustrates a conversion module that may be configured to include one or more structures of the present disclosure.

Fig. 2B shows a plan view of a more specific example of the conversion module of fig. 2A.

Fig. 2C shows a side view of the conversion module of fig. 2B.

Fig. 3 schematically illustrates a chip having a switch array, which may be configured to include one or more structures of the present disclosure.

Fig. 4 shows an example of a switch array having a plurality of Field Effect Transistors (FETs) along a given switch arm.

Fig. 5 illustrates that in certain embodiments, an RF switch having one or more structures of the present disclosure can be an N-pole, M-throw configuration.

Fig. 6A and 6B show plan and cross-sectional views of an exemplary silicon-on-insulator (SOI) metal oxide semiconductor fet (mosfet) device having a finger configuration.

Fig. 7A and 7B show plan and cross-sectional views of an exemplary SOI MOSFET device array having a multi-finger configuration.

Fig. 8A and 8B illustrate an exemplary array of diamond shaped FET devices arranged in a checkered configuration.

Fig. 9 shows an exemplary array of hexagonal shaped FET devices.

Fig. 10 shows an exemplary array of octagonal-shaped FET devices.

Fig. 11 shows an exemplary array of double diamond shaped FET devices.

Fig. 12 shows an example of the array variation of fig. 11.

Fig. 13 shows an exemplary array of cross-shaped FET devices.

Fig. 14 shows an exemplary array of cross-shaped FET devices and diamond-shaped FET devices.

Fig. 15 shows an exemplary array of cross-shaped FET devices and star-shaped FET devices.

Fig. 16 shows an exemplary array of modified star FET devices.

Fig. 17 shows an exemplary array of FET devices having a combination of rectangular and diamond shapes.

Fig. 18A shows an exemplary array of FET devices, the shape of which is a variation of the exemplary shape of fig. 17.

Fig. 18B shows an example of how the edges and/or corners of the exemplary array of fig. 18A may be configured.

Fig. 19 shows an exemplary array of FET devices, the shape of which is a variation of the exemplary shape of fig. 18.

Fig. 20 shows an example of a metal interconnect configuration for interconnecting the source and drain regions of an array of FET devices.

Fig. 21 shows an example of a configuration variation of fig. 20.

Fig. 22 shows an equipotential line graph pattern between the source and drain of a rectangular shaped FET device.

Fig. 23 shows an equipotential line graph pattern between the source and drain of a diamond shaped FET device.

Fig. 24 illustrates a process that can be implemented to fabricate one or more FET devices having one or more structures as described herein.

Fig. 25 illustrates various stages of manufacture associated with the process of fig. 24.

Detailed Description

The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the invention as claimed.

Disclosed herein are apparatus and methods relating to semiconductor transistors having one or more desired performance structures. Such transistors are described herein in the context of Field Effect Transistors (FETs) implemented as silicon-on-insulator (SOI) devices. However, it should be understood that one or more structures of the present disclosure may also be implemented with other types of transistors and/or other process technologies. For example, a Bipolar Junction Transistor (BJT) may be constructed to include one or more structures of the present disclosure. In another example, a transistor associated with non-SOI process technology may be constructed to include one or more structures of the present disclosure.

Various examples of FETs are described herein in the context of Radio Frequency (RF) signal conversion. However, it should be understood that one or more structures of the present disclosure may also be implemented in other types of applications.

Fig. 1A illustrates that, in certain embodiments, one or more structures of the present disclosure may be implemented in a wireless device 100, such as a mobile phone, smart phone, tablet, or other portable device configured for voice and/or data communications. The wireless device 100 is illustrated as including a battery 102 or receptacle for receiving a battery. Such a battery may provide power to many other components in wireless device 100.

Wireless device 100 is shown to further include a component 104, where component 104 is configured to generate a transmission signal and/or process a received signal. In some embodiments, such transmission and reception functions may be implemented in separate components (e.g., a transmission module and a reception module) or in the same module (e.g., a transceiver module).

In certain embodiments, one or more structures of the present disclosure may be implemented in a device configured to perform both transmission and reception of RF signals (e.g., a wireless transceiver), in a device configured to receive only (e.g., a wireless receiver), or in a device configured to transmit only (e.g., a wireless transmitter).

Wireless device 100 is shown to also include a switch component 106. Such components may include, for example, an antenna switching module and/or a front end module. In certain embodiments, one or more structures associated with the FET switches described herein may be implemented in the switching component 106.

Wireless device 100 is shown to further include an antenna assembly 108. Such components may include one or more antennas to facilitate transmission and/or reception of RF signals.

Fig. 1B shows a more specific example of how the wireless device 100 of fig. 1A may be implemented. In fig. 1B, exemplary wireless device 100 is shown to include one or more switches having a configuration described herein. For example, the switch 106 may be configured to switch between different bands and/or modes, transmission and reception modes, and the like, for example.

In exemplary wireless device 100, Power Amplifier (PA) module 96 having multiple power amplifiers may provide the amplified RF signal to switch 106 (via duplexer or duplexer 93), and switch 106 may transmit the amplified RF signal to antenna 108. PA module 96 may receive un-amplified RF signals from transceiver 104, and transceiver 104 may be constructed and operated in a known manner. The transceiver 104 may also be configured to process received signals. The transceiver 104 is shown interacting with the baseband subsystem 93, the baseband subsystem 93 being configured to provide conversion between data and/or voice signals appropriate for the user and RF signals appropriate for the transceiver 104. Transceiver 104 is also shown connected to power management component 92, which is configured to manage power for operation of wireless device 100. Such power management components may also control the operation of the baseband subsystem 93 and other components of the wireless device 100.

The baseband subsystem 93 is shown connected to the user interface 90 to facilitate various inputs and outputs of voice and/or data being provided to or received from a user. The baseband subsystem 93 may also be connected to a memory 91 that is configured to store data and/or instructions to facilitate operation of the wireless device and/or to provide storage of user information.

In some embodiments, the duplexer 94 may allow transmit and receive operations to be simultaneously implemented using a common antenna (e.g., 108). In FIG. 1B, the received signal is shown as being sent to an "Rx" path (not shown), which may include, for example, a Low Noise Amplifier (LNA).

The exemplary duplexer or duplexer 94 is typically used for Frequency Division Duplex (FDD) operation. It should be understood that other types of duplex configurations may be implemented. For example, a wireless device having a Time Division Duplex (TDD) configuration may include respective Low Pass Filters (LPFs) instead of duplexers, and a switch (e.g., 106 in fig. 1B) may be configured to provide a band selection function as well as a Tx/rx (tr) conversion function.

Many other wireless device configurations may utilize one or more of the structures described herein. For example, the wireless device need not be a multi-band device. In another example, the wireless device may include additional antennas, such as diversity antennas, and additional connectivity structures, such as Wi-Fi, bluetooth, and GPS.

Fig. 2A illustrates that in certain embodiments, one or more structures of the present disclosure may be implemented in a module, such as conversion module 110. Such a module may be implemented, for example, as the switch component 106 described with reference to fig. 1A and 1B.

In fig. 2A, the conversion module 110 is depicted as including a chip 112, a connectivity component 114, and a packaging component 116. Chip 112 may include one or more FETs having one or more structures as described herein. The connectivity components 114 may include portions and/or structures such as connectors and terminals that allow signals to be transmitted to and from the chip 112 and transmit power to circuitry on the chip 112. Package components 116 may include, for example, portions and/or structures that provide mounting substrate and protection for chip 112.

Fig. 2B and 2C show plan and side views of the module 110, which may be a more specific example of the module 110 of fig. 2A. Exemplary module 110 may include a package substrate 81 configured to house a plurality of components. In certain embodiments, such components may include a chip 112 having one or more structures as described herein. For example, the chip 112 may include the switching circuit 106 having one or more of the structures described herein. A plurality of connection pads 84 may facilitate electrical connection, such as wire connections 83, to connection pads 82 on substrate 81 to facilitate the passage of various signals to and from chip 112.

In some embodiments, components mounted on the package substrate 81 or formed on or in the package substrate 81 may also include, for example, one or more Surface Mount Devices (SMDs) (e.g., 87) and one or more matching networks (e.g., 86). In some embodiments, package substrate 81 may comprise a laminate substrate.

In some embodiments, for example, the module 110 may also include one or more packaging structures to provide protection of the module 110 and facilitate easier control thereof. Such a package structure may include an exterior film (over mold)88 formed over the package substrate 81 and dimensioned to substantially encapsulate various circuits and components thereon.

It should be understood that although the module 110 is described in the context of having wire-based electrical connections, one or more structures of the present disclosure may also be implemented in other package configurations, including flip-chip configurations.

Fig. 3 illustrates that in some embodiments, chip 120 (e.g., chip 112 of fig. 2) may include one or more Integrated Circuits (ICs). For example, the transceiver 122 may be provided on the chip 120 along with the power amplifier 124 and the switch array 126. Such functional components may be implemented as separate ICs, in a single IC, or some combination thereof. In certain embodiments, switch array 126 may include one or more FETs having one or more structures as described herein.

Fig. 4 schematically illustrates an example of an RF transistor switch array 130 in which FETs having one or more structures as described herein may be implemented. An array 134 of transistors 146, represented as series arms, may be provided between the RF port 132 and the antenna port 138. In some embodiments, an array 140 of transistors 146, shown as parallel arms, may also be provided between the RF port 132 and the common ground 144.

The RF ports 132 may include a dedicated Transmit (TX) port, a dedicated Receive (RX) port, a transmit/receive (TRX) port, or a Wideband (WB) port. For the TX example, the RF port 132 may be connected to the output of a power amplifier. For the RX example, the RF port 132 may be connected to a filter, which in turn may be connected to an ADC for baseband processing. For the TRX and WB examples, the RF port 132 may be connected to respective input(s) and output(s) for a bidirectional channel of RF signals. The antenna port 138 may be connected to one or more antennas.

As shown in fig. 4, series gate control 136 and parallel gate control 142 may be coupled to their respective arrays to provide control signals to turn on or off the series or parallel transistor stacks, respectively. When the RF port 132 is to be connected to the antenna port 138, the series gate control signal may be asserted and the parallel gate control signal may be de-asserted. On the other hand, when it is desired to close the RF port 132 from the antenna port 138 and provide electrical isolation, the series gate control signal may be deactivated and the parallel gate control signal may be asserted. The presence of such parallel arm and parallel gate control is selective to the RF switch and may provide greater isolation when the RF switch is in the off state.

In the exemplary RF transistor switch array 130 of fig. 4, a resistance may be provided between the transistor 146 and the gate control (136 or 142), thereby providing isolation between the relatively high RF voltage established on the transistor 146 and the relatively low voltage control logic or level shifter driving the switch arm. In some embodiments, additional RC filtering may be provided in the control circuit to further reduce the high RF voltage.

In the exemplary RF transistor switch array 130 of fig. 4, the body connection in each transistor switch is shown as unconnected. Such body connections may be constructed in many ways including, for example, floating body, dynamic (active) biasing, and diode biasing.

In the exemplary configuration of fig. 4, the FET devices are arranged in series. In some embodiments, FET devices having one or more structures as described herein may be provided in other configurations. For example, such FET devices may be implemented as N-pole M-throw switches. Fig. 5 shows an example 150 of such a switch, with a single pole (e.g., for antenna port 158) and ten throws (e.g., for TX, RX, and wideband channels 152). For such an example with ten channels, switches 154 (denoted as WB1, WB2, WB3, WB4, WB5, WB6, RX2, RX1, TX2, and TX1) may include FETs. In the example shown, the wideband channel and the RX channel may be provided with an additional enable switch 156 to provide improved isolation between the channels. Such additional enable switches may also include FETs.

As described with reference to fig. 4 and 5, the conversion of the RF signal may involve many FET-based switches. In the case of SOI (silicon on insulator) process technology, FET devices may provide advantages such as improved isolation between adjacent devices due to the insulator under each device. Such improved isolation may result in, for example, low parasitic capacitance, improved power dissipation for a given performance level, and improved resistance to latch-up. SOI transistors are therefore finding increasing application as high frequency RF switches.

In the case of SOI devices, where the breakdown voltage may be relatively low, the switching device may include multiple SOI FET switches arranged in series to provide the function of a single RF switch from a divided RF signal. Such a configuration may allow for switching of high power RF signals or switching under high VSWR (voltage standing wave ratio) conditions. Thus, the number of SOI FET devices may be increased.

In some SOI FET constructions, each transistor may be constructed as a comb/finger-based device in which the source and drain are rectangular in shape (in plan view) and the gate structure extends between the source and drain, similar to a rectangular shaped comb or finger. Fig. 6A and 6B show plan and side cross-sectional views of an exemplary comb/finger-based FET device, implemented as an SOI configuration. As shown, the FET devices described herein may include p-type FETs or n-type FETs. Thus, although certain FET devices are described herein as p-type devices, it should be understood that various concepts related to such p-type devices may also be applied to n-type devices.

As shown in fig. 6A and 6B, the pMOSFET may include an insulator layer formed on a semiconductor substrate. The insulator layer may be formed of a material such as silicon dioxide or sapphire. The n-well is shown formed in the insulator such that the exposed surfaces generally define a rectangular region. The source (S) and drain (D) are shown as p-doped regions, the exposed surfaces of which generally define a rectangle. As shown, the S/D regions may be configured to reverse the function of the source and drain.

Fig. 6A and 6B also show that the gate (G) may be formed on the n-well so as to be disposed between the source and the drain. The gate is shown as having a rectangular shape that extends along the source and drain. Also shown is an n-type body contact. The formation of the rectangular shaped well, source and drain regions, and body contacts may be accomplished by a number of known techniques. Furthermore, the operation of such MOSFET devices can be realized in many known ways.

Fig. 7A and 7B show plan and side cross-sectional views of an example multi-comb FET device implemented on SOI. The formation of rectangular shaped n-wells, rectangular shaped p-doped regions, rectangular shaped gates, and n-type body contacts may be accomplished in a manner similar to that described with reference to fig. 6A and 6B.

The exemplary multi-finger FET device of fig. 7A and 7B may operate such that the drain of one FET serves as the source of its neighboring FET. Thus, the multi-finger FET device may generally provide the voltage division function described with reference to fig. 4. For example, the RF signal may be provided at one of the outermost p-doped regions (e.g., the leftmost p-doped region); and as the signal passes through the FETs in series, the voltage of the signal can be shared among the FETs. In such an example, the rightmost p-doped region may serve as the full drain of the multi-finger FET device.

The exemplary rectangular shape configuration of fig. 6 and 7 typically results in a relatively high Rds-on (resistance in the linear operating region) for a given area associated with the device. To reduce Rds-on, FET devices may be made larger, which in turn may undesirably increase the size of the chip on which many such FET devices are formed. In the case of increasing the number of SOI FET devices, such an increase in the size of the FET devices and chips is generally undesirable.

Disclosed herein are a number of non-limiting examples of how FET devices may be constructed that provide advantageous characteristics, including reduced Rds-on per unit area of the FET. Such a characteristic can also be expressed as the product of Rds-on and FET area.

Fig. 8A shows a plan view of a configuration 200 in which multiple implant/diffusion regions are designated 202 and 212. Such regions may be n-doped or p-doped, as described herein. In the case of SOI process technology, such regions may be formed in a well (p-well or n-well) (not shown) formed on an insulator (not shown). In this exemplary configuration, each of the diffusion regions 202, 212 has a right-angled rhombus shape (also referred to herein as a diamond shape) relative to the conductors 206 and 216. The diamond-shaped diffusion regions are arranged such that the sides of two adjacent regions face each other substantially squarely, forming a checkerboard arrangement.

The exemplary construction 200 is shown to include a gate material 210 formed between the diffusion regions 202, 212. In this particular example, a single gate structure with openings for the diffusion regions 202, 212 may be provided to simultaneously turn on or off charge flow between the diffusion regions. Such a gate configuration may be implemented in a voltage divider series of transistors such as described with reference to fig. 7. In other embodiments, different gates may be provided to allow separate control of groups of diffusion regions.

The exemplary construction 200 is shown to include electrical contact structures 204, 214 on each of the diffusion regions 202, 212. Such contact structures may include, for example, pads/pads and/or vias. The contact structures 204, 214 are shown electrically connected in groups by conductors 206, 216.

In this particular example, the conductors 206, 216 are configured to extend along the X-axis diagonally through the opposite corners of the diamond. In some embodiments, exemplary device 200 may be configured as a single FET device with every other conductor representing the source (or drain) and the other conductor representing the drain (or source) of the single FET device. In such embodiments, a plurality of such source/drain regions may be connected in parallel. For example, if the first conductor 206 is a source, all diffusion region(s) connected thereto may serve as source region(s). The second conductor 216 and its connected diffusion region may then serve as a drain. Thus, the third, fifth and seventh conductors and their respective diffusion regions may serve as sources connected in parallel to the first conductor. Similarly, the fourth, sixth, and eighth conductors and their respective diffusion regions may serve as drains connected in parallel to the second conductor. In some embodiments, such a component with its source and drain connected in parallel and providing a single FET function may be used as a stage of an RF switch having multiple stages. Such multiple stages may include multiple like-configured FETs, or a combination of differently-configured FETs.

In certain embodiments, the exemplary apparatus 200 may be configured to provide a plurality of cascaded stages of transistors arranged in series. For example, if the first conductor 206 is a source, all diffusion region(s) connected thereto may serve as source region(s). The second conductor 216 and its connected diffusion region may serve as a drain with respect to the first conductor 206. Similarly, the second conductor 216 and the third conductor may serve as a source and a drain, respectively, with respect to each other. Such a repeated source/drain configuration can be constructed in series to produce a desired number of transistor cascaded stages, which can be used as a series of RF switches.

In some embodiments, diamond shaped diffusion regions arranged in a checkerboard configuration may produce an RF switch with a reduced (Rds-on) (area) product compared to a rectangular finger configuration. Examples of such reductions are described in more detail herein.

Fig. 8A also shows that a given diamond-shaped diffusion region includes a portion of its boundary, generally facing an adjacent diffusion region belonging to an adjacent source or drain. For example, region 218 includes edges of two adjacent diffusion regions (belonging to respective source and drain groups) that substantially face each other.

Fig. 8B shows an isolation diagram of such two adjacent diffusion regions. In this example, two adjacent diffusion regions are denoted as 212 and 202. Diffusion region 212 includes an edge 232 that generally faces edge 222 belonging to diffusion region 202. In this particular example where the diamond-shaped diffusion regions are arranged in a checkerboard configuration, the two facing sides of adjacent diffusion regions are the opposite sides of a rectangle.

As described herein, there are other shapes of diffusion regions and/or arrangements of such diffusion regions that may provide improved performance, such as a greater reduction in (Rds-on) (area) product. Various non-limiting examples described with reference to fig. 9-19 include implanted diffusion regions of various shapes, which may be n-type doped or p-type doped. In the case of SOI process technology, such regions may be formed in a well (p-well or n-well) (not shown) formed on an insulator (not shown). In some embodiments, such diffusion regions arranged in different configurations may produce RF switches, for example, having a reduced (Rds-on) (area) product when compared to the rectangular finger configuration and/or the diamond/checkerboard configuration of fig. 8.

In the examples shown in fig. 9-19, a gate material is provided for each of the exemplary constructions. Such gate materials are shown formed as a unitary structure between diffusion regions, allowing for the simultaneous flow of charge on and off between the diffusion regions. It will be appreciated that such a gate configuration may be implemented, for example, in the voltage divider series transistor described with reference to fig. 7. In other embodiments, different gates may be provided to allow separate control of the sets of diffusion regions.

Fig. 9 shows a plan view of a construction 300 having a plurality of implant/diffusion regions designated 302 and 312. In this exemplary configuration, each of the diffusion regions 302, 312 has a hexagonal shape. In some embodiments, such a hexagonal shape is elongated along the direction of conductors 306 and 316. As shown, the hexagonal-shaped diffusion regions may be arranged such that the sides of two adjacent regions face each other, as indicated at 318. In this particular example, such facing sides are represented as opposing sides of a non-rectangular parallelogram.

The exemplary construction 300 is shown to include a gate material 310 formed between diffusion regions 302, 312. Further, exemplary construction 300 is shown to include electrical contact structure 304 on each of diffusion regions 302 and electrical contact structure 314 on each of diffusion regions 312. In other embodiments, each diffusion region may include a greater or lesser number of such electrical contact structures. Such contact structures may include, for example, pads and/or vias. The contact structures 304, 314 are shown electrically connected in groups by conductors 306, 316.

In this particular example, the conductors 306, 316 are configured to extend along the X-direction, along the direction of elongation of the hexagonal shape. In some embodiments, exemplary device 300 may be configured as a single FET device with every other conductor representing the source (or drain) of the single FET device and the other conductors representing the drain (or source) of the single FET device. In such embodiments, a plurality of such source/drain regions may be connected in parallel. For example, if the first conductor 306 is a source, all diffusion regions connected thereto may be used as source regions. The second conductor 316 and its connected diffusion region may then serve as a drain. Thus, the third, fifth and other odd conductors and their respective diffusion regions may serve as sources connected in parallel to the first conductor. Similarly, the fourth, sixth, and other even conductors and their respective diffusion regions may serve as drains connected in parallel to the second conductor. In some embodiments, such a component with its source and drain connected in parallel and providing a single FET function may be used as a stage of an RF switch having multiple stages. Such multiple stages may include multiple like-configured FETs, or a combination of differently-configured FETs.

In certain embodiments, the exemplary apparatus 300 may be configured to provide a plurality of cascaded stages of transistors arranged in series. For example, if the first conductor 306 is a source, all diffusion region(s) connected thereto may serve as source region(s). The second conductor 316 and its connected diffusion region may serve as a drain with respect to the first conductor 306. Similarly, the second conductor 316 and the third conductor may serve as a source and a drain, respectively, with respect to each other. Such repeated source/drain configurations may be continued to produce a desired number of cascaded stages of transistors, which may be used as a series of RF switches.

Fig. 10 shows a plan view of a construction 320 having a plurality of implant/diffusion regions denoted 322 and 332. In this exemplary configuration, each of the diffusion regions 322, 332 has an octagonal shape. In some embodiments, such an octagonal shape may be elongated in one direction, and conductors 306 and 316 may extend in a direction that passes through opposite sides of adjacent elongated sides of the octagonal shape. As shown, the octagonal-shaped diffusion regions can be arranged such that a given octagon includes two sides facing two different adjacent regions. Such facing arrangements are shown as 338a and 338 b. In this particular example, the opposite side 338a is depicted as the opposite side of a rectangle, and the facing side 338b is depicted as the opposite side of a non-rectangular parallelogram.

Exemplary construction 320 is shown to include a gate material 330 formed between diffusion regions 322, 332. Further, exemplary construction 320 is shown to include electrical contact structures 324, 334 on each of diffusion regions 322, 332. In other embodiments, each diffusion region may include other numbers of such electrical contact structures. Such contact structures may include, for example, pads and/or vias. The contact structures 324, 334 are shown electrically connected in groups by conductors 326, 336.

In some embodiments, exemplary device 320 may be configured as a single FET device with every other conductor representing the source (or drain) and the other conductor representing the drain (or source) of the single FET device. In such embodiments, a plurality of such source/drain regions may be connected in parallel. For example, if the first conductor 326 is a source, all diffusion regions connected thereto may be used as source regions. The second conductor 336 and its connected diffusion region may then serve as a drain. Thus, the third, fifth and other odd conductors and their respective diffusion regions may serve as sources connected in parallel to the first conductor. Similarly, the fourth, sixth, and other even conductors and their respective diffusion regions may serve as drains connected in parallel to the second conductor. In some embodiments, such a component with its source and drain connected in parallel and providing a single FET function may be used as a stage of an RF switch having multiple stages. Such multiple stages may include multiple like-configured FETs, or a combination of differently-configured FETs.

In some embodiments, the exemplary device 320 may be configured to provide multiple cascaded stages of transistors arranged in series. For example, if the first conductor 326 is a source, all diffusion region(s) connected thereto may be used as source region(s). The second conductor 336 and its connected diffusion region may serve as a drain with respect to the first conductor 326. Similarly, the second and third conductors 336, respectively, may serve as a source and a drain with respect to each other. Such repeated source/drain configurations may be continued to produce a desired number of cascaded stages of transistors, which may be used as a series of RF switches.

Fig. 11 shows a plan view of a construction 340 having a plurality of implant/diffusion regions denoted as 342 and 352. In this exemplary configuration, each of the diffusion regions 342, 352 has a double diamond shape, which may be defined as two rhombus shapes whose corners overlap. In certain embodiments, such double diamond shapes may be oriented in perpendicular directions (e.g., in the X and Y directions) in an alternating manner. For a pair of rows so alternately oriented, one row is offset along the X direction, so that the alternate direction also exists along the Y direction. In the example shown, conductors 346 connect the X-direction oriented double diamond shape in a pair of rows; and conductor 356 connects the Y-oriented double diamond shapes in a pair of rows. As shown, the double diamond shaped diffusion regions are arranged such that a given pair of X-direction and Y-direction double diamond shapes includes a facing region denoted 358. In this particular example, the end corners of one double diamond shape and their adjacent sides generally face the adjoining portions of the other double diamond shape. Thus, the facing area may be generally defined as a "V" shape.

Exemplary construction 340 is shown to include gate material 350 formed between diffusion regions 342, 352. Further, the exemplary construction 340 is shown to include electrical contact structures 344, 354 on each of the two diamonds of the double diamond shaped diffusion regions 342, 352. In other embodiments, each diffusion region may include other numbers of such electrical contact structures. Such contact structures may include, for example, pads and/or vias. The contact structures 344, 354 are shown electrically connected in groups by conductors 346, 356.

In some embodiments, exemplary device 340 may be configured as a single FET device with every other conductor representing the source (or drain) of the single FET device and the other conductors representing the drain (or source) of the single FET device. In such embodiments, a plurality of such source/drain regions may be connected in parallel. For example, if the first conductor 346 is a source, all diffusion regions connected thereto may be used as source regions. The second conductor 356 and its connected diffusion region may then serve as the drain. Thus, any other odd-numbered conductor and its respective diffusion region may serve as a source connected in parallel to the first conductor. Similarly, any other even-numbered conductor and its respective diffusion region may serve as a drain connected in parallel to the second conductor. In some embodiments, such a component with its source and drain connected in parallel and providing a single FET function may be used as a stage of an RF switch having multiple stages. Such multiple stages may include multiple like-configured FETs, or a combination of differently-configured FETs.

In certain embodiments, the exemplary apparatus 340 may be configured to provide a plurality of cascaded stages of transistors arranged in series. For example, if the first conductor 346 is a source, all diffusion region(s) connected thereto may be used as source region(s). The second conductor 356 and its connected diffusion region may serve as a drain with respect to the first conductor 346. Similarly, the second conductor 356 and the third conductor may serve as a source and a drain, respectively, with respect to each other. Such repeated source/drain configurations may be continued to produce a desired number of cascaded stages of transistors, which may be used as a series of RF switches.

Fig. 12 shows a plan view of a construction 360 having a plurality of implant/diffusion regions designated 362 and 372. In this exemplary configuration, each of the diffusion regions 362, 372 has a double diamond shape similar to that of fig. 11. However, in this example, such double diamond shapes may be oriented such that for a set of connected diffusion regions, a lower edge of one region adjacent to an end corner faces an upper edge of an adjacent diffusion region adjacent to an opposite end corner. Such a pattern is repeated but offset for the next set of connected diffusion regions such that the connected recessed corners of the diffusion regions of the first set face the protruding corners between the connected corners and the end corners of the diffusion regions of the second set. Thus, this exemplary arrangement creates facing areas, including those areas designated 378a and 378 b. The facing region 378a may include end sides that are opposite sides of a non-rectangular parallelogram. The facing region 378b can include offset jagged edges of a pair of diffusion regions belonging to different groups, thereby creating a jagged facing region.

Exemplary construction 360 is shown to include a gate material 370 formed between diffusion regions 362, 372. Further, the exemplary construction 360 is shown as including electrical contact structures 364, 374 on each of the two diamonds of the double diamond shaped diffusion region 362, 372. In other embodiments, each diffusion region may include other numbers of such electrical contact structures. Such contact structures may include, for example, pads and/or vias. The contact structures 364, 374 are shown electrically connected in sets by conductors 366, 376.

In some embodiments, exemplary device 360 may be configured as a single FET device, with every other conductor representing the source (or drain) and the other conductors representing the drain (or source) of the single FET device. In such embodiments, a plurality of such source/drain regions may be connected in parallel. For example, if first conductor 366 is a source, all diffusion regions connected thereto may serve as source regions. The second conductor 376 and its connected diffusion region may then serve as a drain. Thus, any other odd-numbered conductor and its respective diffusion region may serve as a source connected in parallel to the first conductor. Similarly, any other even-numbered conductor and its respective diffusion region may serve as a drain connected in parallel to the second conductor. In some embodiments, such a component with its source and drain connected in parallel and providing a single FET function may be used as a stage of an RF switch having multiple stages. Such multiple stages may include multiple like-configured FETs, or a combination of differently-configured FETs.

In certain embodiments, the exemplary apparatus 360 may be configured to provide a plurality of cascaded stages of transistors arranged in series. For example, if first conductor 366 is a source, all diffusion region(s) connected thereto may serve as source region(s). The second conductor 376 and its connected diffusion region may serve as a drain with respect to the first conductor 366. Similarly, the second and third conductors 376 and 376 may serve as a source and a drain, respectively, with respect to each other. Such repeated source/drain configurations may be continued to produce a desired number of cascaded stages of transistors, which may be used as a series of RF switches.

Fig. 13 shows a plan view of a construction 380 having a plurality of implant/diffusion regions designated 382 and 392. In this exemplary configuration, each of the diffusion regions 382, 392 has a cross-shape. In some embodiments, such a cross shape may be oriented with the vertical extensions oriented in the X and Y directions. For a set of a pair of cross-shaped diffusion regions along the X-direction, one set is offset along the X-direction such that the cross-shape of one set is positioned approximately midway (along the X-direction) between the two cross-shapes of the other set. A pair of cross-shaped diffusion portions are offset in a similar manner along a group in the Y direction. In the example shown, conductors 386 and 396 are shown as extending along the X-direction. As shown, the cross-shaped diffusion regions may be arranged such that two adjacent regions belonging to two groups face each other, as indicated at 398. In this particular example, the right lower concave corner (of one cross shape) and its adjacent edge are shown facing the left upper concave corner (of the other cross shape) and its edge.

Exemplary construction 380 is shown to include a gate material 390 formed between diffusion regions 382, 392. Further, the exemplary construction 380 is shown as including electrical contact structures 384, 394 on each of the diffusion regions 382, 392. In other embodiments, each diffusion region may include other numbers of such electrical contact structures. Such contact structures may include, for example, pads and/or vias. The contact structures 384, 394 are shown electrically connected in groups by conductors 386, 396.

In this particular example, the conductors 386, 396 are configured to extend along the X-direction. In some embodiments, exemplary device 380 may be configured as a single FET device with every other conductor representing the source (or drain) and the other conductor representing the drain (or source) of the single FET device. In such embodiments, a plurality of such source/drain regions may be connected in parallel. For example, if the first conductor 386 is a source, all diffusion regions connected thereto may be used as source regions. The second conductor 396 and its connected diffusion region may then serve as a drain. Thus, any other odd-numbered conductor and its respective diffusion region may serve as a source connected in parallel to the first conductor. Similarly, any other even-numbered conductor and its respective diffusion region may serve as a drain connected in parallel to the second conductor. In some embodiments, such a component with its source and drain connected in parallel and providing a single FET function may be used as a stage of an RF switch having multiple stages. Such multiple stages may include multiple like-configured FETs, or a combination of differently-configured FETs.

In certain embodiments, the exemplary device 380 may be configured to provide multiple cascaded stages of transistors arranged in series. For example, if the first conductor 386 is a source, all diffusion region(s) connected thereto may be used as source region(s). Second conductor 396 and its connected diffusion region may serve as a drain with respect to first conductor 386. Similarly, second conductor 396 and third conductor may serve as a source and drain, respectively, with respect to each other. Such repeated source/drain configurations may be continued to produce a desired number of cascaded stages of transistors, which may be used as a series of RF switches.

Fig. 14 and 15 illustrate that in some embodiments, the first and second sets of diffusion regions corresponding to the source and drain need not have the same shape.

Fig. 14 shows a plan view of a configuration 400 having a plurality of implant/diffusion regions 402 and a plurality of implant/diffusion regions 412 having a different shape than the regions 402. In this exemplary configuration, each of the diffusion regions 402 has a shape that may be defined by a profile resulting from a combination of a cross and a generally centered rhombus, with opposite corners of the rhombus extending along an extension of the cross. In addition, each of the diffusion regions 412 has a rectangular shape (e.g., square) that extends along a vertical direction of the cruciform extension. In this exemplary configuration, the square regions 412 are offset approximately half way between the centers of the crosses 402, such that a given square is approximately centered between four adjacent crosses 402. In the example shown, conductor 406 is shown extending through cross 402 in a direction along one of two perpendicular directions associated with the extension of cross 402; and conductor 416 is shown extending through square region 412 in a direction generally parallel to conductor 406. As shown, the cross-shaped and square diffusion regions may be arranged such that two adjacent regions belonging to two groups face each other, as indicated at 418. In this particular example, the inner portion of the upper extension of cross shape 402 is shown facing two lower adjacent sides of square shape 412, thereby generally defining a "V" shaped facing area.

The exemplary construction 400 is shown to include a gate material 410 formed between diffusion regions 402, 412. Further, the exemplary construction 400 is shown to include electrical contact structures 404, 414 on each of the respective diffusion regions 402, 412. In other embodiments, each diffusion region may include other numbers of such electrical contact structures. Such contact structures may include, for example, pads and/or vias. Contact structures 404, 414 are shown electrically connected in groups by conductors 406, 416.

In some embodiments, exemplary device 400 may be configured as a single FET device with every other conductor representing the source (or drain) of the single FET device and the other conductors representing the drain (or source) of the single FET device. In such embodiments, a plurality of such source/drain regions may be connected in parallel. For example, if the first conductor 406 is a source, all diffusion regions connected thereto may be used as source regions. The second conductor 416 and its connected diffusion region may then serve as a drain. Thus, any other odd-numbered conductor and its respective diffusion region may serve as a source connected in parallel to the first conductor. Similarly, any other even-numbered conductor and its respective diffusion region may serve as a drain connected in parallel to the second conductor. In some embodiments, such a component with its source and drain connected in parallel and providing a single FET function may be used as a stage of an RF switch having multiple stages. Such multiple stages may include multiple like-configured FETs, or a combination of differently-configured FETs.

In certain embodiments, the exemplary apparatus 400 may be configured to provide a plurality of cascaded stages of transistors arranged in series. For example, if the first conductor 406 is a source, all diffusion region(s) connected thereto may be used as source region(s). The second conductor 416 and its connected diffusion region may serve as a drain with respect to the first conductor 406. Similarly, the second conductor 416 and the third conductor may serve as a source and a drain, respectively, with respect to each other. Such repeated source/drain configurations may be continued to produce a desired number of cascaded stages of transistors, which may be used as a series of RF switches.

Fig. 15 shows a plan view of a construction 420, which is similar to the exemplary construction 400 of fig. 14. The implant/diffusion region 422 has a cross shape that does not include the center of the rhombus shape, but includes chamfered corners at the ends of the extensions. Implant/diffusion area 432 has a star-like shape that may be defined by a contour formed by two concentric squares, one of which is rotated about 45 degrees. The arrangement of diffusion regions 422 and 432 is similar to the example of fig. 14. As shown, the cross-shaped and star-shaped diffusion areas may be arranged such that two adjacent areas belonging to two groups face each other, as indicated at 438. In this particular example, the inner portion of the left side extension of cross shape 422 is shown facing the right corner and adjacent sides of star shape 432.

Exemplary construction 420 is shown to include a gate material 430 formed between diffusion regions 422, 432. Further, exemplary construction 420 is shown to include electrical contact structures 424, 434 on each of the respective diffusion regions 422, 432. In other embodiments, each diffusion region may include other numbers of such electrical contact structures. Such contact structures may include, for example, pads and/or vias. The contact structures 424, 434 are shown electrically connected in groups by conductors 426, 436.

In some embodiments, exemplary device 420 may be configured as a single FET device, with every other conductor representing the source (or drain) and the other conductors representing the drain (or source) of the single FET device. In such embodiments, a plurality of such source/drain regions may be connected in parallel. For example, if the first conductor 426 is a source, all diffusion regions connected thereto may be used as source regions. The second conductor 436 and its connected diffusion region may then serve as a drain. Thus, any other odd-numbered conductor and its respective diffusion region may serve as a source connected in parallel to the first conductor. Similarly, any other even-numbered conductor and its respective diffusion region may serve as a drain connected in parallel to the second conductor. In some embodiments, such a component with its source and drain connected in parallel and providing a single FET function may be used as a stage of an RF switch having multiple stages. Such multiple stages may include multiple like-configured FETs, or a combination of differently-configured FETs.

In certain embodiments, the exemplary apparatus 420 may be configured to provide a plurality of cascaded stages of transistors arranged in series. For example, if the first conductor 426 is a source, all diffusion region(s) connected thereto may serve as source region(s). The second conductor 436 and its connected diffusion region may serve as a drain with respect to the first conductor 426. Similarly, the second and third conductors 436 and 436 may serve as a source and a drain, respectively, with respect to each other. Such repeated source/drain configurations may be continued to produce a desired number of cascaded stages of transistors, which may be used as a series of RF switches.

Fig. 16 shows a plan view of a construction 440 in which the implant/diffusion regions 442, 452 have a modified cross-shape. Each of the four extended portions of the cross shape is shown as being shifted toward the clockwise side from the vertical center line. Further, the clockwise side corner at the end of each extension is shown as including a bevel. As shown, the diffusion region 442 is disposed along the general direction of extension of the conductor 446 at an angle of about 45 degrees relative to the two parallel extensions of the cross shape. Diffusion region 452 is similarly disposed and oriented; and offset from the diffusion region 442 to provide staggered centers for the two sets of regions 442,452. As shown, the modified cross-shaped diffusion region may be arranged such that two adjacent regions belonging to two groups face each other, as indicated at 458. In this particular example, the edge associated with one extension of one cross is shown facing a recessed portion defined by two adjacent extensions of an adjacent cross.

Exemplary construction 440 is shown to include a gate material 450 formed between diffusion regions 442, 452. Further, the exemplary construction 440 is shown as including electrical contact structures 444, 454 on each of the respective diffusion regions 442, 452. In other embodiments, each diffusion region may include other numbers of such electrical contact structures. Such contact structures may include, for example, pads and/or vias. The contact structures 444, 454 are shown electrically connected in groups by conductors 446, 456.

In some embodiments, exemplary device 440 may be configured as a single FET device, with every other conductor representing the source (or drain) and the other conductors representing the drain (or source) of the single FET device. In such embodiments, a plurality of such source/drain regions may be connected in parallel. For example, if the first conductor 446 is a source, all diffusion regions connected thereto may be used as source regions. The second conductor 456 and its connected diffusion region may then serve as a drain. Thus, any other odd-numbered conductor and its respective diffusion region may serve as a source connected in parallel to the first conductor. Similarly, any other even-numbered conductor and its respective diffusion region may serve as a drain connected in parallel to the second conductor. In some embodiments, such a component with its source and drain connected in parallel and providing a single FET function may be used as a stage of an RF switch having multiple stages. Such multiple stages may include multiple like-configured FETs, or a combination of differently-configured FETs.

In certain embodiments, the exemplary device 440 may be configured to provide a plurality of cascaded stages of transistors arranged in series. For example, if the first conductor 446 is a source, all diffusion region(s) connected thereto may serve as source region(s). The second conductor 456 and its connected diffusion region may serve as a drain with respect to the first conductor 446. Similarly, the second and third conductors 456, respectively, may serve as a source and a drain with respect to each other. Such repeated source/drain configurations may be continued to produce a desired number of cascaded stages of transistors, which may be used as a series of RF switches.

Fig. 17 shows a plan view of a construction 460 in which the implant/diffusion regions 462, 472 comprise shapes defined by the outline of rectangles and generally concentric rhombus-shaped shapes. The rhombus is oriented with its two opposite corners along the length of the rectangle. As shown, the diffusion regions 462, 472 are disposed such that the length direction of the rectangle is along the X-direction. Conductors 466 and 476 are shown extending along the Y direction connecting the centers of their respective diffusion regions. Diffusion regions 462 and 472 are offset from each other so as to be staggered from each other along both the X and Y directions. As shown, the diffusion regions may be arranged such that two adjacent regions belonging to two groups face each other, as indicated at 478. In this particular example, the upper left edge of the rectangle of one region and the upper left edge of its rhombus are shown facing the lower right edge of the rectangle of the other region and the lower right edge of the rhombus.

An exemplary construction 460 is shown including a gate material 470 formed between diffusion regions 462, 472. Further, the exemplary construction 460 is shown as including electrical contact structures 464, 474 on each of the respective diffusion regions 462, 472. In other embodiments, each diffusion region may include other numbers of such electrical contact structures. Such contact structures may include, for example, pads and/or vias. The contact structures 464, 474 are shown electrically connected in groups by conductors 466, 476.

In some embodiments, exemplary device 460 may be configured as a single FET device, with every other conductor representing the source (or drain) and the other conductor representing the drain (or source) of the single FET device. In such embodiments, a plurality of such source/drain regions may be connected in parallel. For example, if the first conductor 466 is a source, all diffusion regions connected thereto may be used as source regions. The second conductor 476 and its connected diffusion region may then serve as a drain. Thus, any other odd-numbered conductor and its respective diffusion region may serve as a source connected in parallel to the first conductor. Similarly, any other even-numbered conductor and its respective diffusion region may serve as a drain connected in parallel to the second conductor. In some embodiments, such a component with its source and drain connected in parallel and providing a single FET function may be used as a stage of an RF switch having multiple stages. Such multiple stages may include multiple like-configured FETs, or a combination of differently-configured FETs.

In certain embodiments, the exemplary apparatus 460 may be configured to provide a plurality of cascaded stages of transistors arranged in series. For example, if the first conductor 466 is a source, all diffusion region(s) connected thereto may be used as source region(s). Second conductor 476 and its connected diffusion region may serve as a drain with respect to first conductor 466. Similarly, the second conductor 476 and the third conductor may serve as a source and a drain, respectively, with respect to each other. Such repeated source/drain configurations may be continued to produce a desired number of cascaded stages of transistors, which may be used as a series of RF switches.

Fig. 18A shows a plan view of a construction 480 in which implant/diffusion regions 482, 492 comprise shapes that may be variations of the diffusion regions 462, 472 of fig. 17. The corners of the rectangular shaped end are shown as beveled, resulting in a sharp end. As shown, the diffusion regions 482, 492 are disposed such that their lengthwise directions are along the X direction. Conductors 486 and 496 are shown extending along the Y direction connecting the centers of their respective diffusion regions. Diffusion regions 482 and 492 are offset from each other so as to be staggered from each other in both the X and Y directions. As shown, the diffusion regions may be disposed such that two adjacent regions belonging to two groups face each other, as indicated at 498. In this particular example, the upper left edge of the rectangle and the upper left edge of the rhombus of one region are shown facing the lower right edge of the rectangle and the lower right edge of the rhombus of the other region.

Exemplary construction 480 is shown to include a gate material 490 formed between diffusion regions 482, 492. Further, an exemplary construction 480 is shown including electrical contact structures 484, 494 on each of the respective diffusion regions 482, 492. In other embodiments, each diffusion region may include other numbers of such electrical contact structures. Such contact structures may include, for example, pads and/or vias. The contact structures 484, 494 are shown electrically connected in groups by conductors 486, 496.

In some embodiments, exemplary device 480 may be configured as a single FET device with every other conductor representing the source (or drain) and the other conductor representing the drain (or source) of the single FET device. In such embodiments, a plurality of such source/drain regions may be connected in parallel. For example, if the first conductor 486 is a source, all diffusion regions connected thereto may be used as source regions. The second conductor 496 and its connected diffusion region may then serve as a drain. Thus, any other odd-numbered conductor and its respective diffusion region may serve as a source connected in parallel to the first conductor. Similarly, any other even-numbered conductor and its respective diffusion region may serve as a drain connected in parallel to the second conductor. In some embodiments, such a component with its source and drain connected in parallel and providing a single FET function may be used as a stage of an RF switch having multiple stages. Such multiple stages may include multiple like-configured FETs, or a combination of differently-configured FETs.

In certain embodiments, the exemplary device 480 may be configured to provide multiple cascaded stages of transistors arranged in series. For example, if the first conductor 486 is a source, all diffusion region(s) connected thereto may be used as source region(s). Second conductor 496 and its connected diffusion region may serve as a drain with respect to first conductor 486. Similarly, second conductor 496 and the third conductor may function as a source and a drain, respectively, with respect to each other. Such repeated source/drain configurations may be continued to produce a desired number of cascaded stages of transistors, which may be used as a series of RF switches.

Fig. 18B shows an example of how the edges and corners of an FET device 480 (e.g., the example of fig. 18A) may be constructed. In this example, the implant/diffusion regions (e.g., 492) not along the edges are shown to have a similar shape as in fig. 18A. In some embodiments, the implant/diffusion regions along the edges of the FET device may be shaped to maintain a similar facing configuration (e.g., 498 in fig. 18A) as the corresponding adjacent interior implant/diffusion regions and accommodate the edges. For example, each of the edge regions (denoted as 482') has a right side shape similar to interior region 482 and a left side shape that is squared to accommodate the left edge of the FET device. In another example, each of the edge regions along the upper edge (denoted as 482 ") has a lower side shape similar to interior region 482 and an upper side shape that is squared to accommodate the left edge of the FET device.

In some embodiments, the implant/diffusion regions at the corners of the FET device may be shaped to maintain a similar facing configuration (e.g., 498 in fig. 18A) as one or more adjacent internal implant/diffusion regions, as well as accommodate the corners. For example, the corner region (designated 482' ") has a selected lower right corner shape to create a facing configuration similar to the other (e.g., 498 in fig. 18A) having one or more corresponding interior implant/diffusion regions; and the remainder of corner regions 482 '"are shown as accommodating edges, corners, and adjacent regions (e.g., 482' and 482").

As with the example configuration of fig. 18A, electrical contact structures 484, 494 are shown as being provided at each of the implant/diffusion regions (482, 482', 482 "', 492) in fig. 18B. Such contact structures may include, for example, pads and/or vias. The contact structures 484, 494 are shown electrically connected in groups by conductors 486, 496. In certain embodiments, the conductors 486, 496 may be dimensioned to accommodate the shape of the contact structures 484, 494 and/or the shape of the injection/diffusion regions. For example, contact structures in non-corner edge regions as well as interior regions can be shaped to accommodate the contact structures 484, 494. In another example, the contact structure at corner region 482 '"is shaped to accommodate the contact structure 484 as well as corner region 482'".

In the example shown in fig. 18B, the first set of conductors 486 may be connected to a first common terminal that serves as a terminal for one of the source and drain. In some embodiments, such a common terminal (not shown) may be formed over the gate material (e.g., along one of the edges of the FET device). Similarly, a second set of conductors 496 may be connected to a second common terminal, which serves as a terminal for the other of the source and drain. In some embodiments, such a common terminal (not shown) may be formed over the gate material (e.g., along one of the edges of the FET device).

In some embodiments, the body of the FET device may be floating or may be provided with a bias. In the example shown in fig. 18B, the latter may be accommodated by a connection port 488 connected to a plurality of contact structures 489. Such contact structures (489) may be connected to a conductive layer (not shown) in electrical contact with the body portion of the FET (e.g., through a body contact).

Fig. 19 shows a plan view of a configuration 500 in which implant/diffusion regions 502, 512 comprise shapes that may be variations of diffusion regions 482, 492 of fig. 18. The longitudinal portion extending along the X direction is shown to start at a given width at the center, taper to a smaller width portion, and end at opposite pointed ends. Conductors 506 and 516 are shown extending along the Y direction, connecting the centers of their respective diffusion regions. Diffusion regions 502 and diffusion regions 512 are offset from each other so as to be staggered from each other in both the X and Y directions. As shown, the diffusion regions may be arranged such that two adjacent regions belonging to two groups face each other, as indicated at 518. In this particular example, the upper right edge of the tapered portion and the upper right edge of the rhombus of one region are shown facing the lower left edge of the tapered portion and the lower left edge of the rhombus of the other region.

The exemplary construction 500 is shown to include a gate material 510 formed between diffusion regions 502, 512. Further, the exemplary construction 500 is shown to include electrical contact structures 504, 514 on each of the respective diffusion regions 502, 512. In other embodiments, each diffusion region may include other numbers of such electrical contact structures. Such contact structures may include, for example, pads and/or vias. The contact structures 504, 514 are shown electrically connected in groups by conductors 506, 516.

In some embodiments, exemplary device 500 may be configured as a single FET device with every other conductor representing the source (or drain) and the other conductor representing the drain (or source) of the single FET device. In such embodiments, a plurality of such source/drain regions may be connected in parallel. For example, if the first conductor 506 is a source, all diffusion regions connected thereto may be used as source regions. The second conductor 516 and its connected diffusion region may then serve as a drain. Thus, any other odd-numbered conductor and its respective diffusion region may serve as a source connected in parallel to the first conductor. Similarly, any other even-numbered conductor and its respective diffusion region may serve as a drain connected in parallel to the second conductor. In some embodiments, such a component with its source and drain connected in parallel and providing a single FET function may be used as a stage of an RF switch having multiple stages. Such multiple stages may include multiple like-configured FETs, or a combination of differently-configured FETs.

In certain embodiments, the exemplary apparatus 500 may be configured to provide a plurality of cascaded stages of transistors arranged in series. For example, if the first conductor 506 is a source, all diffusion region(s) connected thereto may serve as source region(s). The second conductor 516 and its connected diffusion region may serve as a drain with respect to the first conductor 506. Similarly, the second conductor 516 and the third conductor may function as a source and a drain, respectively, with respect to each other. Such repeated source/drain configurations may be continued to produce a desired number of cascaded stages of transistors, which may be used as a series of RF switches.

In some implementations, some or all of the example configurations described with reference to fig. 8-19 may be configured to accommodate edges and/or corners of their respective FET devices in a manner similar to the example described with reference to fig. 18B.

Fig. 20 shows an example of how multiple FET devices may be connected into an assembly to provide a desired voltage division function. For purposes of describing the example of fig. 20, it is assumed that a single FET device may be constructed with every other conductor connected to one or more source (or drain) regions, and the other conductors connected to one or more drain (or source) regions (such as those described with reference to fig. 8-19), such that a plurality of such source/drain regions are electrically connected in parallel.

Fig. 20 shows an exemplary configuration 600 in which three FET devices 602, 604, 606 are connected in series. Conductive layer 610 is assumed to be the source terminal for three FET constructions 600. Thus, the conductive layer 616 may be a drain terminal. The source layer 610 may be connected to the source conductor (e.g., every other conductor strip) of the first FET602, but electrically isolated from the drain conductor of the first FET. The conductive layer 612 may be configured to be connected to the drain conductor of the first FET602 and the source conductor of the second FET604, but electrically isolated from the source conductor of the first FET and the drain conductor of the second FET. Similarly, conductive layer 614 may be configured to connect to a drain conductor of second FET604 and a source conductor of third FET 606. But is electrically isolated from the source conductor of the second FET and the drain conductor of the third FET. The drain layer 616 may be connected to the drain conductor of the third FET606, but electrically isolated from the source conductor of the third FET.

Fig. 21 shows another example of how a given FET device may be configured to provide an integral source and an integral drain. For purposes of describing the example of fig. 21, it is assumed that the FET device may be configured such that every other conductor is connected to one or more source (or drain) regions, and the other conductors are connected to one or more drain (or source) regions (such as those described with reference to fig. 8-19), such that a plurality of such source/drain regions are electrically connected in parallel.

Fig. 21 illustrates an exemplary configuration 620 in which a single FET device 630 may be separated into a bulk source and a bulk drain. Conductive layer 660 is shown connected to source terminal 662 and conductive layer 670 is shown connected to drain terminal 672. Assume that the source layer 660 is connected to the first 640 and third 644 conductors and their respective diffusion regions 650, 654 (e.g., through vias 638) from the left, but is electrically isolated from the second 642 and fourth 646 conductors and their respective diffusion regions 652, 656. The drain layer 670 may then be connected to the second (642) and fourth (646) conductors and their respective diffusion regions (652, 656) (e.g., by vias 648), but electrically isolated from the first (640) and third (644) conductors and their respective diffusion regions (650, 654).

As understood in the art, the main factors contributing to Rds-on of a FET may include the channel characteristics, the contact resistance of the terminals of the two S/D regions, and the characteristics associated with the two S/D regions. Assuming that the contact resistance remains substantially the same, the effect of the differently shaped S/D regions has been evaluated for different shapes.

The performance of the rectangular shaped source/drain configuration and the diamond shaped source/drain configuration were compared. The Rds-on of the channel feature was evaluated with Hspice numbers on a single finger configuration (rectangular shape) NMOS device. An exemplary device has an aspect ratio W/L of about 10 μm/0.32 μm. This particular exemplary NMOS aspect ratio corresponds approximately to the single finger of a typical RF switch TX-arm stack. A numerical calculation of Rds-on of about 2.46 Ω was obtained from the Hspice evaluation, and such values were then used to calibrate the effective channel doping of the device geometry using 2-D EM simulations. This can be achieved on finger geometry by repeating the PISCES operation and varying the channel doping until the Rds-on of the cell approximately matches the 2.46 Ω value. Once calibrated, the corresponding doping levels can be used in a model of a diamond geometry NMOS device.

Exemplary dimensions of the aforementioned rectangular and diamond geometries (700 and 710) are shown in fig. 22 and 23. In FIG. 22, rectangular shaped diffusion regions are shown as 702 and 704; and their dimensions and spacing are shown in scale. In fig. 23, portions of the diamonds (712, 714) facing each other are shown; and their dimensions and spacing are shown in scale. In each of fig. 22 and 23, the values associated with the contour scale on the right side of the graph are the potential/potential volts.

Fig. 22 and 23 also show equipotential plots for the rectangular and diamond configurations. Such an equipotential line plot is obtained by generating a PISCES geometry file (×. mesh) by a suitably constructed open source program such as EasyMesh. Such a program may divide a two-dimensional area into an array of triangles, for example as shown in fig. 22 and 23.

According to the foregoing example analysis, the rectangular configuration yields approximately (33.8k Ω) (0.84) (0.44 μm) ═ 12.5k Ω · μm²And Rds-on and the calculated product of the area. For the diamond configuration, the product of Rds-on and the area is calculated to be about (17.5k Ω) (0.594 μm) (0.887 μm) ═ 9.2k Ω · μm²About 26% less than the rectangular case.

In certain embodiments, some or all of the examples described herein with reference to fig. 9-21 may have a product (Rds-on) (area) that is lower than the rectangular and diamond cases. Different configurations other than the rectangular and diamond configurations may also be provided to produce such a desired reduction in the product of (Rds-on) (area).

Fig. 24 shows a process 800 that may be performed to fabricate FET structures in connection with examples described herein. Fig. 25 shows the structure at various stages corresponding to the steps of process 800 of fig. 24.

In block 812, an SOI structure having isolated wells of an insulator layer may be formed or provided, resulting in structure 820, where the wells are designated 828 and the insulator layer is designated 824. Also shown is the substrate 822 under the insulator layer 824 and the insulator 826 isolating the well 828.

In block 814, a diffusion region may be formed in the well such that the region has a footprint that includes a facing portion that either includes at least a portion having a plurality of segments extending in different directions or defines opposing sides of a non-rectangular quadrilateral. In some embodiments, such facing portions may define opposite sides of a rectangle. Such a step may result in a structure 830 having a first diffusion region 832 and a second diffusion region 834 formed over the well 828. Such diffusion regions may be configured to act as source and drain alone or in conjunction with other diffusion regions.

In block 816, one or more electrical contact terminals may be formed on each of the diffusion regions. Such a step may result in structure 840 having electrical contact terminals disposed on first diffusion region 832 and electrical contact terminals 844 disposed on second diffusion region 834. Such electrical contact terminals may be connected to separate source and drain electrodes or joined with other contact terminals.

Block 818 illustrates that in some embodiments, a gate may be formed between the first diffusion region and the second diffusion region. Such a step may result in a structure 850 having a gate 852 disposed over the well 828 and between the first and second diffusion regions 832, 834.

In some embodiments, various exemplary shapes associated with diffusion regions, gate openings, contact pads, and/or conductors may be fabricated using a number of process techniques. Such process techniques may include, for example, one or more masks having a selected shape to facilitate process steps, such as photolithography-based steps, involving etching, masking, deposition, and the like.

Unless the context requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is meant to be "including but not limited to". The term "coupled" as used generally herein means that two or more elements may be connected directly or through one or more intermediate elements. Additionally, the words "herein," "above," "below," and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. Words in the above detailed description using the singular or plural number may also include the plural or singular number, respectively, if the context permits. The word "or" relates to a list of two or more items, and covers all of the following interpretations of the word: any one of the items in the list, all of the items in the list, and any combination of the items in the list.

The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or modules are presented in a given order, alternative embodiments may perform procedures having steps or employ systems having modules in a different order, and certain processes or modules may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or modules may be implemented in a variety of different ways. Also, while processes or modules are sometimes shown as being performed in series, the processes or modules may instead be performed in parallel, or may be performed at different times.

The teachings of the invention provided herein are applicable to other systems, not necessarily the systems described above. The elements and acts of the above-described embodiments may be combined to provide further embodiments.

While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the present disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other ways; in addition, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.

Claims

1. A transistor, comprising:

a semiconductor substrate;

a plurality of first diffusion regions formed on the semiconductor substrate;

a plurality of second diffusion regions formed on the semiconductor substrate; and

a gate layer disposed over the first and second diffusion regions, the gate layer defining a first opening over each of the first diffusion regions and a second opening over each of the second diffusion regions, at least some of the first and second openings having a shape other than a rectangle.

2. The transistor of claim 1, further comprising a contact structure formed on each of the first diffusion region and the second diffusion region.

3. The transistor of claim 2, further comprising a first conductor electrically connected to the contact structure on the first diffusion region and a second conductor electrically connected to the contact structure on the second diffusion region.

4. The transistor of claim 3, wherein the first conductor is also connected to a source terminal and the second conductor is also connected to a drain terminal.

5. The transistor of claim 4, wherein at least some of the first and second openings have a first shape defined by an outline of an elongated shape having a center and a major axis along a first direction and a diamond shape having a center approximately at the center of the elongated shape, the diamond shape oriented such that one set of opposing corners is along the major axis and the other set of opposing corners is substantially perpendicular to the major axis.

6. The transistor of claim 5, wherein the elongated shape comprises a rectangle having a length along the first direction.

7. The transistor of claim 5, wherein the elongated shape comprises a hexagon elongated along the first direction.

8. The transistor of claim 7, wherein the plurality of first openings having the first shape form a first column, the first openings in the first column being arranged along a second direction that is substantially perpendicular to the first direction.

9. The transistor of claim 8, wherein the plurality of second openings having the first shape form a second row, the second openings in the second row being arranged along the second direction and offset from the first openings along the first direction.

10. The transistor of claim 9, wherein the first openings of the first column and the second openings of the second column are staggered along the first direction and along the second direction.

11. The transistor of claim 10, wherein each of the first and second conductors extends along the second direction.

12. The transistor of claim 11, further comprising at least one additional column having additional first openings that continue the staggered configuration along the first direction and the second direction.

13. The transistor of claim 1, wherein an adjacent pair of first and second openings includes a first facing portion for the first opening and a second facing portion for the second opening, at least one of the first facing portion and the second facing portion having a plurality of segments extending in different directions.

14. The transistor of claim 1, wherein an adjacent pair of first and second openings includes a first facing portion for the first opening and a second facing portion for the second opening, the first facing portion and the second facing portion defining opposite sides of a quadrilateral other than a rectangle.

15. The transistor of claim 1, wherein the transistor is a metal oxide semiconductor fet (mosfet).

16. The transistor of claim 1, further comprising an insulator layer disposed below a semiconductor substrate comprising a silicon substrate to form a silicon-on-insulator (SOI) structure.

17. The transistor of claim 1, wherein the shape is dimensioned to produce a reduced value of Rds-on per unit area compared to a rectangular opening of similar dimensions.

18. A semiconductor chip, comprising:

a semiconductor substrate; and

a plurality of transistors implemented on the substrate, each transistor including a plurality of first diffusion regions and a plurality of second diffusion regions, each transistor further including a gate layer disposed over the first and second diffusion regions, the gate layer defining a first opening over each of the first diffusion regions and a second opening over each of the second diffusion regions, at least some of the first and second openings having a shape other than rectangular.

19. A Radio Frequency (RF) device, comprising:

a transceiver configured to process an RF signal;

a power amplifier configured to amplify the RF signal generated by the transceiver;

an antenna in communication with the transceiver and configured to facilitate transmission of the amplified RF signal; and

a conversion module connected to the power amplifier and the antenna, the conversion module configured to transmit the amplified RF signal from the power amplifier to the antenna, the conversion module having a switching circuit comprising a plurality of transistors connected in series, each transistor comprising a plurality of first diffusion regions and a plurality of second diffusion regions, each transistor further comprising a gate layer disposed over the first diffusion regions and the second diffusion regions, the gate layer defining a first opening over each of the first diffusion regions and a second opening over each of the second diffusion regions, at least some of the first openings and the second openings having a shape other than rectangular.

20. The RF device of claim 19 wherein the RF device is a portable wireless device.

21. A Radio Frequency (RF) switch, comprising:

a semiconductor substrate;

an input element including a plurality of source regions formed on the semiconductor substrate, a source contact formed on each of the source regions, and an input conductor electrically connected to each of the source contacts;

an output assembly including a plurality of drain regions formed on the semiconductor substrate, a drain contact formed on each of the drain regions, and an output conductor electrically connected to each of the drain contacts; and

a gate layer disposed over the source regions and the drain regions, the gate layer defining first openings over each of the source regions and second openings over each of the drain regions, at least some of the first openings and the second openings being disposed in a two-dimensional array.

22. The RF switch of claim 21 further comprising an input terminal connected to the input conductor and an output terminal connected to the output conductor.

23. The RF switch of claim 21 wherein each of the first and second openings has a parallelogram shape, the first and second openings being arranged such that adjacent sides of a pair of openings are substantially parallel, each of the input and output conductors extending diagonally over a corresponding one of the first and second openings.

24. The RF switch of claim 23 wherein the parallelogram shape is a square shape such that the array of squares defines a checkered pattern.

25. The RF switch of claim 21 wherein at least some of the first and second openings have a first shape defined by an outline of an elongated shape having a center and a major axis along a first direction and a diamond shape having a center approximately at the center of the elongated shape, the diamond shape oriented with one set of opposing corners along the major axis and the other set of opposing corners substantially perpendicular to the major axis.

26. The RF switch of claim 25 wherein the elongated shape includes a rectangle having a length along the first direction.

27. The RF switch of claim 25 wherein the elongated shape includes a hexagon elongated along the first direction.

28. The RF switch of claim 27 wherein the plurality of first openings having the first shape form a first column, the first openings in the first column being arranged along a second direction that is substantially perpendicular to the first direction.

29. The RF switch of claim 28 wherein the plurality of second openings having the first shape form a second row, the second openings in the second row being arranged along the second direction and offset from the first openings along the first direction.

30. The RF switch of claim 29 wherein the first openings of the first column and the second openings of the second column are staggered along the first direction and along the second direction.

31. The RF switch of claim 30 wherein each of the input conductor and the output conductor extends along the second direction.

32. The RF switch of claim 31 further comprising at least one additional column having additional first openings that continue the staggered configuration along the first direction and the second direction.

33. The RF switch of claim 21 wherein an adjacent pair of first and second openings includes a first facing portion for the first opening and a second facing portion for the second opening, at least one of the first and second facing portions having a plurality of segments extending in different directions.

34. The RF switch of claim 21 wherein an adjacent pair of first and second openings includes a first facing portion for the first opening and a second facing portion for the second opening, the first and second facing portions defining opposite sides of a quadrilateral other than a rectangle.

35. The RF switch of claim 21 wherein the source region, the drain region and the gate are configured as a metal oxide semiconductor fet (mosfet).

36. The RF switch of claim 21 further comprising an insulator layer disposed below the semiconductor substrate including the silicon substrate to form a silicon-on-insulator (SOI) structure.

37. The RF switch of claim 21 wherein the shape is dimensioned to produce a reduced value of Rds-on per unit area compared to a rectangular opening of similar size.

38. A Radio Frequency (RF) conversion module, comprising:

a package substrate configured to accommodate a plurality of components;

a chip mounted on the package substrate, the chip having a plurality of transistors implemented on a semiconductor substrate, each transistor including a plurality of source regions and a plurality of drain regions, each transistor further including a gate layer disposed over the source and drain regions, the gate layer defining a first opening over each of the source regions and a second opening over each of the drain regions. At least some of the first openings and the second openings are arranged in a two-dimensional array, each transistor further comprising a source contact formed on each source region and a drain contact formed on each drain region, the chip further comprising an input conductor electrically connected to the source contact and an output conductor electrically connected to the drain contact; and

a plurality of connectors configured to provide electrical connections between the chip and the package substrate.

39. A Radio Frequency (RF) device, comprising:

a transceiver configured to process an RF signal;

a conversion module connected to the power amplifier and the antenna, the conversion module configured to transmit the amplified RF signal from the power amplifier to the antenna, the conversion module has a switching circuit including a plurality of transistors connected in series, each transistor including a plurality of source regions and a plurality of drain regions, each transistor further including a gate layer disposed over the source region and the drain region, the gate layer defines a first opening over each of the source regions and a second opening over each of the drain regions, at least some of the first openings and the second openings are arranged in a two-dimensional array, each transistor further comprising a source contact formed on each source region and a drain contact formed on each drain region, the source contact is connected to an input conductor that receives the amplified RF signal, and the drain contact is connected to an output conductor that outputs the amplified RF signal.

40. The RF device of claim 39 wherein the RF device is a portable wireless device.