HK1196485B - System and method for sensor failure detection - Google Patents

Description

System and method for sensor fault detection

RELATED APPLICATIONS

This application is a divisional application of a pending U.S. patent application No. 13/763, 498 filed on 8.2.2013 by the same inventor, application No. 13/763, 498, entitled "system and method for sensor fault detection", which is incorporated herein by reference in its entirety.

Technical Field

The present invention relates generally to image sensors and, more particularly, to fault detection of image sensors.

Background

Electronic image sensors are often incorporated into a variety of devices including, for example, cell phones, computers, Digital cameras, Personal Digital Assistants (PDAs), and the like. In addition to traditional user-controlled still video camera applications, more and more image sensor applications are emerging. For example, overall machine vision applications are rapidly expanding in the automotive, manufacturing, medical, security, and defense industries. In these applications, machines typically perform certain operational tasks (e.g., collision prevention tasks) based on information captured by an image capture system of the machine (e.g., the position of an object relative to another object). In order for the machine to perform the appropriate tasks associated with a particular situation, the image sensor must reliably capture, process, and output image data that accurately represents the observed situation.

A Complementary Metal Oxide Semiconductor (CMOS) image sensor generally includes: a sensor array, control circuitry, row control circuitry (e.g., row address decoders, pixel drivers, etc.), column sampling circuitry, and image processing circuitry. The image sensor is typically used in conjunction with a lens assembly aligned with the sensor array to focus an image thereon. The sensor array converts incident light into electrical data representing an image. The sensor array is comprised of a plurality of light sensitive pixels arranged in a plurality of rows and columns. The pixels are electrically coupled to a row control circuit and a column sampling circuit via a grid of row and column signal lines, respectively. That is, each individual pixel row is connected to and controlled by a row control circuit via an associated group of row signal lines including, for example, a transmission line, a reset line (reset line), and a row select line. Each individual column of pixels is connected to a column sampling circuit via a separate column sampling line. The column sampling circuit typically includes sampling elements such as amplifiers, analog-to-digital converters, and data storage elements coupled to the column sample lines for digitizing and storing the electrical signals output from the pixels. In an image sensor having a column parallel read architecture, the column sampling circuit includes a discrete set of these sampling elements for each column sampling line so that an entire row of pixels can be sampled simultaneously. In a column parallel read architecture, the column sampling circuit also includes various signal lines routed to various sampling elements to deliver control signals thereto. (non-column parallel read architectures also require various level signal lines, although not as many as column parallel architectures.) the image processing circuit receives the digitized data output from the column sampling circuit and produces image data in a readable format. The interface enables the image sensor to communicate (e.g., output formatted image/video data, receive operating instructions, etc.) with a host system (e.g., a cell phone motherboard, an on-board computer system, a manufacturing machine computer system, etc.). Typically, the control circuitry of the image sensor is connected to row control circuitry, column sampling circuitry, image processing circuitry, and interfaces to perform various timing and control operations.

Each pixel includes: a light sensitive element (e.g., a photodiode, photogate, etc.), a transfer transistor, a floating diffusion region, a reset transistor, a source-follower transistor, and a row select transistor. The photosensitive element operates to accumulate charge proportional to the intensity of incident light to which it is exposed during shutter operation. The transfer transistor connects the photosensitive element to the floating diffusion region and includes a gate connected to and thus controlled by a single transfer line dedicated to an entire row of pixels. When a logic high voltage signal is applied to the transfer line, charge from the photosensitive element is transferred to the floating diffusion region. The reset transistor connects the floating diffusion region to a voltage source terminal and includes a gate connected to and thus controlled by a reset line of the row signal line. When a logic high voltage signal is applied to the reset line, the reset transistor connects the floating diffusion region to the voltage source terminal, thus resetting any previously stored charge to a known state. The source follower transistor couples a voltage source terminal to the row select transistor and includes a gate coupled to the floating diffusion region to produce an amplified voltage signal representative of charge accumulated in the floating diffusion region. The row select transistor connects a source follower transistor to the pixel output line for the column line and includes a gate connected to the row select line for the row line. When a logic low voltage is applied to the row select line, the row select transistor acts as a turn-on switch between the source follower transistor and the pixel output line. Conversely, a logic high voltage applied at the gate of the row select line causes the row select transistor to act as a closed switch between the source follower transistor and the column sample line so that the state of the floating diffusion can be sampled through the column sample line.

While conventional image sensors meet the needs of many image and video capture applications, the current designs suffer from drawbacks. For example, CMOS pixels are constructed from integrated circuit elements (e.g., transistors, diodes, capacitors, etc.) that are prone to failure. As another example, pixel row signal lines (e.g., transmission lines, reset lines, row select lines, etc.), column sampling lines, and column sampling element control lines (e.g., gain amplifier control lines, analog-to-digital converter control lines, digitized pixel data storage device control lines, etc.) are susceptible to damage, particularly those that are subject to large amounts of distributed stress-induced loading. As another problem, the row control circuit is also prone to failure. In the case where any one of the above-described malfunctions occurs in the conventional image sensor, it generally outputs erroneous image data to the host system. Of course, the host system typically does not recognize the difference between the erroneous image data and the correct image data. This may be particularly problematic in certain applications (i.e., overall machine vision applications) where the image data indicates operational tasks performed by the host system. Certain applications (e.g., automotive applications) require systems with extremely high reliability even when the circuit is not very susceptible to damage or failure.

Accordingly, there is a need for image sensor designs with improved image data output reliability.

Disclosure of Invention

The present invention overcomes the problems associated with the prior art by providing an image sensor with integrated fault detection. Aspects of the present invention detect faults in photosensitive pixels, control lines of a pixel array, and sample/hold circuits.

An exemplary image capture device includes a plurality of pixels. Each pixel has a photosensor, a charge storage region, a signal output terminal, and a test signal input terminal. The charge storage region is selectively coupled to receive a photocurrent from the photosensor. The signal output terminal is coupled to the charge storage region and outputs a signal indicative of an amount of charge stored in the charge storage region. The test signal input is also coupled to the charge storage region. The test signal injection circuit is coupled to provide a test signal to a test signal input of the pixel, and the sampling circuit is selectively coupled to receive an output signal from an output of the pixel. The comparison circuit compares a test signal provided to the pixel with an output signal received from the pixel and provides an error signal if the output signal does not correspond to the test signal. Optionally, the test signal injection circuit is coupled to the comparison circuit to provide the test signal provided to the pixel directly to the comparison circuit. Various means are disclosed to compare a test signal provided to a pixel with an output signal received from the pixel and to provide an error signal in response to the output signal not corresponding to the test signal.

In the disclosed embodiment, the pixels are arranged in a plurality of columns, and the image capturing apparatus includes a plurality of charge injection lines. Each charge injection line couples a test signal input of a corresponding column of pixels to the test signal injection circuit. The charge storage region of each pixel is coupled to a corresponding one of the charge injection lines via a capacitor, and there is no switching device interposed between the charge storage region of the pixel and the charge injection line.

In the disclosed embodiments, the test signal injection circuit is capable of providing different test signals on different charge injection lines, and also capable of providing different test signals on the same charge injection line at different timings.

An exemplary test signal injection circuit includes a plurality of test signal storage elements and a test signal generator. Each test signal storage element is selectively coupled to a respective one of the charge injection lines. The test signal generator is coupled to the test signal storage element and operates to generate a test signal value and store the test signal value in the storage element.

In a particular embodiment, the test signal generator operates to generate digital test signal values and each of the storage elements is a single-bit storage element. The test signal generator includes a random bit generator. The storage elements are coupled together in series and bits from the random bit generator are shifted to the storage elements.

The pixels may operate in an image capture mode or a test mode. The charge storage region of each pixel is selectively coupled to the photosensor of each pixel by the switching device of each pixel. The controller is coupled to provide the transmission signal to the switching device of the pixel. In response to a first value of the transmission signal, the switching device conducts a photocurrent between the photosensor and the charge storage region to facilitate image capture. In response to a second value of the transmit signal, the switching device blocks photocurrent between the photosensor and the charge storage region to facilitate test signal injection. In operation, the image capture device performs a repeated image capture process over successive frame times to capture frames of image data. The controller applies the second value of the transmission signal for the duration of an image capture process to facilitate test signal injection every N frame times, where N is an integer greater than 1.

Also disclosed is an apparatus for detecting a failure in a control circuit of an image capturing apparatus. In an exemplary image capture device, a controller provides a control signal. In response to the control signal, the driver operates to generate a drive signal based on the control signal and apply the drive signal on a control line of the image capture device. The comparator generates an error signal in response to a first input based on the control signal and in response to a second input based on the drive signal if the control signal does not correspond in a predetermined manner to the applied drive signal. In a particular embodiment, the comparator directly compares the control signal with the drive signal to determine whether the drive signal corresponds to the control signal. Various means are disclosed for comparing a first input based on a control signal with a second input based on a drive signal and generating an error signal if the control signal does not correspond in a predetermined manner to the applied drive signal.

In one example, the driver is a row control driver of the image sensor array. In another example, the drivers are elements of an image data sampling circuit that receive rows of data from an image sensor array.

Various means for comparing the control signal to the drive signal are disclosed. In an exemplary embodiment, the image capture device further includes a second driver coupled to receive the control signal and operative to generate a second drive signal based on the control signal, and the comparator compares the second drive signal with the drive signal.

In another exemplary embodiment, a first encoder is coupled to the plurality of control lines at a first point and generates a first encoded value based on drive signals detected on the plurality of control lines. A second encoder is coupled to the plurality of control lines at a second point at a distance from the first point and generates a second encoded value based on the drive signals detected on the plurality of control lines. The comparator is operative to compare the first encoded value and the second encoded value.

A method for detecting a fault in an image capture device is also disclosed. An exemplary method comprises: an image capture device is provided that includes a sensor array, focuses an image on the sensor array, and repeatedly captures frames of image data using the sensor array. The image data represents an image focused on the sensor array. The method further comprises the following steps: periodically injecting test data into the sensor array between repeated captures of the image data, reading the test data from the image capture device, and comparing the read test data with the injected test data. If the read test data does not correspond to the injected test data, an error signal is generated.

Another exemplary method comprises: the control signal is received, a drive signal is generated based on the control signal, and the drive signal is applied to a control line of the image capture device. The method further comprises the following steps: the applied drive signal is compared to the control signal and an error signal is generated if the control signal does not correspond in a predetermined manner to the applied drive signal. In a particular method, the step of applying the drive signal on the control line of the image capturing device comprises: the driving signals are applied to row control lines of the image sensor array. In another particular method, the step of applying the drive signal on the control line of the image capture device includes: the driving signal is applied to the control line of the image data sampling circuit. In yet another particular method, the step of comparing the applied drive signal to the control signal includes: a second drive signal is generated based on the control signal and compared to the drive signal.

In another exemplary method, the step of comparing the applied drive signal with the control signal comprises: the first encoded value is generated based on the drive signals applied at a first point on the plurality of control lines and the second encoded value is generated based on the drive signals applied at a second point on the plurality of control lines. The first encoded value is then compared to the second encoded value.

Additional methods for detecting failure of an image capture device are disclosed. An exemplary method comprises: the method includes receiving a control signal, generating a drive signal based on the control signal, applying the drive signal to a control line of the image capture device, and comparing the applied drive signal to the control signal. The method further comprises the following steps: if the control signal does not correspond in a predetermined manner to the applied drive signal, an error signal is generated.

In a particular method, the step of applying the drive signal on the control line of the image capture device comprises: the driving signals are applied to row control lines of the image sensor array. In another particular method, the step of applying the drive signal on the control line of the image capture device includes: the driving signal is applied to the control line of the image data sampling circuit.

Optionally, the step of comparing the applied drive signal with the control signal may comprise: a second drive signal is generated based on the control signal and compared to the drive signal. Alternatively, the step of comparing the applied drive signal with the control signal may comprise: generating a first encoded value based on a drive signal applied at a first point on a plurality of control lines and a second encoded value based on the drive signals applied at a second point on the plurality of control lines, and comparing the first encoded value to the second encoded value.

Various methods may also be used in combination. For example, the method summarized above may further include: the method includes receiving a second control signal, generating a second drive signal based on the second control signal, applying the second drive signal to a second control line of the image capture device, and comparing inputs based on the second drive signal and the second control signal. A second error signal is generated if the second control signal does not correspond to the second drive signal in a predetermined manner.

In an exemplary method, the image capture device further includes an image sensor array and an image data sampling circuit coupled to receive rows of data from the image sensor array. In the exemplary method, the drive signal is a row control drive signal in the image sensor array, and the second drive signal is a drive signal in the image data sampling circuit.

Another exemplary method further comprises: periodically injecting test data into the image sensor array; and comparing the test data injected into the image sensor array with the test data received from the sensor array through the image data sampling circuit. The exemplary method further comprises: a third error signal is generated if the test data injected into the image sensor array does not correspond in a predetermined manner to the test data received from the sensor array by the image data sampling circuit.

An exemplary image capture device is also disclosed. The exemplary image capturing apparatus includes: a controller operative to provide a control signal; a driver and a comparator. The driver is responsive to the control signal and operative to generate a drive signal based on the control signal and apply the drive signal on a control line of the image capture device. The comparator is responsive to a first input based on the control signal and a second input based on the drive signal. The comparator generates an error signal if the control signal does not correspond in a predetermined manner to the applied drive signal.

Various means are disclosed for comparing a first input based on a control signal with a second input based on a drive signal and generating an error signal if the control signal does not correspond in a predetermined manner to the applied drive signal.

In a particular exemplary embodiment, the comparator directly compares the control signal with the drive signal to determine whether the drive signal corresponds to the control signal.

In an example, the image capture device further includes an image sensor array, and the driver controls a driver for rows of the image sensor array. In another example, the image capture device further includes an image data sampling circuit coupled to receive a row of data from the image sensor array, and the driver is an element of the image data sampling circuit.

A plurality of means for determining whether the control signal corresponds to the drive signal is disclosed. For example, in an exemplary embodiment, the image capture device further includes a second driver coupled to receive the control signal. The second driver is operative to generate a second drive signal based on the control signal, and the comparator is operative to compare the second drive signal with the drive signal.

In another exemplary embodiment, the image capturing apparatus further includes a plurality of control lines. A first encoder is coupled to the plurality of control lines at a first point and is operative to generate a first encoded value based on drive signals detected on the plurality of control lines. A second encoder is coupled to the plurality of control lines at a second point a distance from the first point and is operative to generate a second encoded value based on the drive signals detected on the plurality of control lines. The comparator then compares the first encoded value and the second encoded value.

Various exemplary embodiments of the present invention may be implemented in a single image capture device. For example, in addition to the first driver, the disclosed embodiments include a second driver responsive to a second control signal. The second driver is operated to generate a second drive signal and apply the second drive signal on a second control line of the image capture device. A second comparator is responsive to a first input based on the second control signal and a second input based on the second drive signal. The second comparator is operated so as to generate a second error signal if the second control signal does not correspond to the second drive signal in a predetermined manner. In addition, the image capture device includes an image sensor array and an image data sampling circuit coupled to receive rows of data from the image sensor array. The driver is a row control driver for the image sensor array and the second driver is an element of the image data sampling circuit. In addition, the exemplary image capture device further includes a test data injection circuit operative to periodically inject test data into the image sensor array. A third comparator is operative to compare test data injected into the image sensor array with test data received from the sensor array by the image data sampling circuit. The third comparator also generates a third error signal if the test data injected into the image sensor array does not correspond in a predetermined manner to the test data received from the sensor array by the image data sampling circuit.

Drawings

The present invention is described with reference to the following figures, wherein like reference numerals represent substantially similar elements:

FIG. 1 is a perspective view of an image sensor mounted on a host device circuit board;

FIG. 2 is a block diagram of the image sensor of FIG. 1;

FIG. 3 is a schematic diagram of a pixel of the image sensor of FIG. 1;

FIG. 4 is a schematic diagram of a test signal injection circuit of the image sensor of FIG. 1;

FIG. 5 is a circuit diagram of two adjacent column injection circuits of the test signal injection circuit of FIG. 4;

FIG. 6 is a circuit diagram of a pixel array, a first row controller, a second row controller, and a comparison circuit of the image sensor of FIG. 1;

fig. 7 is a circuit diagram showing features of the comparison circuit of fig. 6;

fig. 8 is a circuit diagram illustrating a control circuit, a pixel array, a sampling circuit, and a comparison circuit of the image sensor of fig. 1;

FIG. 9 is a circuit diagram showing additional details of the comparison circuit of FIG. 8;

FIG. 10 is a circuit diagram of another comparison circuit of the image sensor of FIG. 1;

FIG. 11 is a timing diagram illustrating operation of the image sensor of FIG. 1 in an image capture mode;

FIG. 12 is a timing diagram illustrating operation of the image sensor of FIG. 1 in a test mode;

FIG. 13 is a circuit diagram of the comparison circuit of FIG. 7 in an alternative embodiment in accordance with the invention; and

fig. 14 is a circuit diagram of an alternate sampling circuit and an alternate comparison circuit in another embodiment in accordance with the invention.

Detailed Description

The present invention overcomes the problems associated with the prior art by providing an image sensor that includes a fault detection circuit. In the following description, numerous specific details are set forth (e.g., image sensor types, pixel types, transistor types, number of pixels, etc.) in order to provide a thorough understanding of the present invention. However, it will be appreciated by one skilled in the art that the invention may be practiced without these specific details. In other instances, well-known integrated circuit image sensor production practices (e.g., transistor formation, color filter formation, wafer dicing, semiconductor doping, etc.) and details of components have been omitted, so as not to unnecessarily obscure the present invention.

Fig. 1 is a perspective view of an image sensor 100 mounted on a portion of a Printed Circuit Board (PCB) 102, where the PCB 102 represents a PCB of a camera host device (e.g., an automobile, a manufacturing machine, a medical device, a cell phone, etc.). The image sensor 100 is in electrical communication with other components of the host device via a plurality of conductive traces 104. In an exemplary embodiment, the image sensor 100 is depicted as part of a camera module 106, which further includes an optical element 108 and a housing 110. As shown, the housing 110 is mounted to the image sensor 100 with the optical element 108 secured therebetween. Those skilled in the art will appreciate that the particular design and/or presence of PCB 102, trace 104, optical element 108, and housing 110 will depend on the particular application and is not particularly relevant to the present invention. Thus, PCB 102, traces 104, optical elements 108, and housing 110 are merely representational.

Fig. 2 is a block diagram of an image sensor 100, and in this exemplary embodiment, the image sensor 100 is a Backside Illuminated (BSI) CMOS image sensor System-On-Chip (SOC). The image sensor 100 includes: control circuit 200, pixel array 202, test signal injection circuit 204, first row controller 206, second row controller 208, first comparison circuit 210, sampling circuit 212, second comparison circuit 214, image processor 216, and third comparison circuit 218.

The control circuit 200 provides the primary means for coordinating and controlling the various elements of the image sensor 100. For example, the control circuit 200 operates to cause the test signal injection circuit 204 to operate in a test mode or an image capture mode. As another example, the control circuit 200 operates to provide row control signals to the first row controller 206 and the second row controller 208. As yet another example, the control circuit 200 provides a sampling control signal to the sampling circuit 212.

Pixel array 202 includes a plurality of pixels 220 arranged in a plurality of rows 222 and a plurality of columns 224_i,j. That is, pixel array 202 includes M +1 rows 222, the first of which is represented as row 222₀And the last one is represented as row 222_M. Similarly, pixel array 202 includes N +1 columns 224, the first of which is represented as column 224₀And the last one is represented as column 224_N. Pixel 220_i,jEach has a unique address i, j, where i represents a row of the address and j represents a column of the address.

Test signal injection circuit 204 includes an N +1 column injection circuit 226 that is connected to column 224 and is represented in the same manner as column 224. Thus, the first of the column injection circuits 226 is denoted as column injection circuit 226₀And the last one is denoted as column injection circuit 226_N. When the test signal injection circuit 204 receives a command to control the circuit 200 to perform the operation, the column injection circuit 226₀To 226_NOperates to inject test signals into the pixel columns 224₀To 224_NA respective column of (a). All column injection circuits 226 when test signal injection circuit 204 is commanded to operate in image capture mode₀To 226_NInjecting the same reference signal into the corresponding column 224₀To 224_NEach of (a).

The first row controller 206 operates to generate row control signals defined by row control signal instructions output from the control circuit 200. In addition, first row controller 206 is electrically coupled to each of rows 222 to directly apply the generated row control signals thereto. The second row controller 208 also operates to generate the same row control signals defined by the same row control signal instructions output from the control circuit 200. Unlike the first row controller 206, the row control signals generated by the second row controller 208 are not intended to drive the rows 222. Instead, it is used by the first comparison circuit 210 to check whether the control signals generated by the first row controller 206 have been properly distributed across the rows 222. That is, the first comparison circuit 210 receives the control signal generated by the second row controller 208 and then compares it to the electrical state of the row 222. If the electrical state of the row 222 does not correspond to the control signal generated by the second row controller 208, the first comparison circuit 210 outputs an error signal indicating that the control signal generated by the first row controller 206 was not properly distributed across one or more rows 222.

The sampling circuit 212 operates to perform sampling operations in accordance with column sampling instructions from the control circuit 200. Because each row 222 is sequentially selected by the first row controller 206, the sampling circuit 212 acquires digital data representing the electrical state of each column 224. Thus, each pixel 220 for the pixel array 202 is acquired_i,jThe digital data of (2) requires a total of M +1 samples of each of the N +1 columns 224 per frame. Each time the sampling circuit 212 takes a row sample, it outputs the digital data via data line 228 to the image processor 216 for further processing.

The second compare circuit 214 receives the same column sampling instructions provided to the sampling circuit 212 by the control circuit 200. The second comparison circuit 214 compares the sampling instruction with the actual control signal driving sampling circuit 212. If the actual signal drives sampling circuit 212 not corresponding to the sampling instruction, the second comparison circuit outputs an error signal.

Image processor 216 operates to convert the digital data acquired by sampling circuit 212 into readable image data via known image processing techniques.

The third comparison circuit 218 operates to compare the test signal injected into the column 224 via the test signal injection circuit 204 with the resulting digital data acquired by the sampling circuit 212. If the resulting digital data acquired by the sampling circuit 212 does not properly correspond to the test signal, the third comparison circuit 218 outputs an error signal. The third comparison circuit 218 may receive the digital data from the sampling circuit 212 directly via the data line 228 or alternatively via the image processor 216 and the data line 230.

FIG. 3 shows a row control signal line 300_iCharge injection line 302_jAnd a pixel 220 of the pixel array 202 coupled by a read line 304j_i,jSchematic representation of (a). Row control signal line 300_iThe method comprises the following steps: row select line 306_iReset line 308_iAnd a transmission line 310_i. The row control signal lines 300 may extend across the entire row 222_iSo that the first row controller 206 can provide the same control signals to the rows 222_iPixel 220 of (2)_i,0To 220_i,N. Similarly, a charge injection line 302_jAnd a read line 304_jMay be along the entire column 224_jAnd (4) extending. Charge injection line 302_jEnabling the test signal injection circuit 204 to inject test signals into the pixels 220_0,jTo 220_M,j. Read line 304_jEnabling the sampling circuit 212 to sample the pixels 220_0,jTo 220_M,jElectrical state of (c).

In the exemplary embodiment, pixel 220_i,jIs a four-transistor (4T) pixel comprising: photosensor 312, charge storage area 314, pixel voltage source terminal (V)_dd) 316, a reset transistor 318, a transfer transistor 320, a source follower transistor 322, a row select transistor 324, and a coupling capacitor 326. The photosensor 312 is, for example, a Photodiode (PD) and operates to convert incident light into charged charges. The charge storage region 314 is a floating diffusion element that operates to store charge generated by the photosensor 312. The pixel voltage supply terminal 316 provides a voltage to a reset transistor 318 and a source follower transistor 322. The reset transistor 318 includes: a first terminal 328 coupled to the pixel voltage source terminal 316; a second terminal 330 coupled to the charge storage region 314; and a gate 332 coupled to the reset line 308_i. When the first row controller 206 passesReset line 308_iWhen a reset signal, in this case a high voltage pulse, is applied to gate 332, transistor 318 is temporarily placed in a conductive state, wherein charge storage region 314 is coupled to pixel voltage supply terminal 316. Thus, the previous charge state of charge storage region 314 returns to the known reference charge state. Once reset line 308_iReturning to the low voltage state, reset transistor 318 returns to a non-conductive state in which charge storage region 314 is electrically isolated from pixel voltage supply terminal 316. The pass transistor 320 includes: a first terminal 334 coupled to the light sensor 312; a second terminal 336 coupled to charge storage region 314; and a gate 338 coupled to the transmission line 310_i. When the first row controller 206 passes through the transmission line 310_iWhen a transfer signal (in this case, a high voltage) is applied to gate 338, transfer transistor 320 is placed in an on state in which photosensor 312 is coupled to charge storage region 314. Accordingly, the charge generated by the photosensor 312 is transferred to the charge storage region 314. Once the transmission line 310 is established_iReturning to the low voltage state, the pass transistor 320 returns to a non-conductive state in which the charge storage region 314 is electrically isolated from the photosensor 312. The source follower transistor 322 includes: a first terminal 340 coupled to the pixel voltage source terminal 316; a second terminal 342 coupled to the row select transistor 324; and a gate 344 coupled to the charge storage region 314. Those skilled in the art will appreciate that the electrical state of second terminal 342 will be indicated by the charge state of gate 344 and, in turn, charge storage region 314. Thus, the second terminal 342 may serve as the pixel 220_i,jIs operated to output an electrical signal representative of the charge stored in the charge storage region 314. The row select transistor 324 includes: a first terminal 346 coupled to the second terminal 342 of the source follower transistor 322; a second terminal 348 coupled to the read line 304_j(ii) a And a third terminal 350 coupled to the row select line 306_i. When the first row controller 206 applies a row select signal (in this case, a high voltage) to the row select line 306_iIn the up state, the row select transistor 324 operates in an on state, in which the first terminal 346 and the second terminal 348 are electrically coupled to each other, thereby applying a signal output from the second terminal 342 to the read line 304_jThe above. When the row select signal is not applied to the row select line 306_iIn the up state, the row select transistor 324 operates in the on state, thereby enabling the pixel 220_i,jIs not connected to the read line 304_jAnd (4) connecting. The coupling capacitor 326 includes: a first terminal 352 coupled to charge storage region 314; and a second terminal 354 coupled to the charge injection line 302_j. The coupling capacitor 326 can be controlled to be applied to the charge injection line 302_jThe voltage on causes test signal injection circuit 204 (from fig. 2) to control the charge state of charge storage region 314. When the image sensor 100 operates in the image capture mode, the voltage of the charge injection line 302 is maintained at a known reference level before and after the charge generated by the photosensor 312 is transferred to the charge storage region 314. Since charge injection line 302 is held at a fixed voltage, the amount of charge generated by photosensor 312 in a given time is measured as the difference between the charge states of charge storage region 314 before and after the charge from photosensor 312 is transferred to charge storage region 314.

When the image sensor 100 is operating in the test mode, the test signal injection circuit 204 transmits a test signal to the pixel 220 by varying the voltage applied on the charge injection line 302 (and thus at the terminal 354 of the capacitor 326). By varying the voltage level, the charge state of the charge storage region 314 is adjusted to a value that simulates a known light intensity. For example, if the same reference voltage applied on charge injection line 302 during the image capture mode is applied on charge injection line 302 during the test mode, then line 304 is read_jAppears as if the photosensor 312 has generated a minimum charge. As will be explained in further detail below, the sampling circuit 212 (from FIG. 2) samples the read line 304 as it normally would during an image capture mode_jAnd the third comparison circuit 218 compares the data sample with the injected test signal and outputs an error signal when it does not coincide.

In the exemplary embodiment of fig. 3, a test signal is injected into the charge storage region 314. However, the test signal may be selectively injected to the photosensor 312, for example, via the reset transistor 318 and the pass transistor 320.

FIG. 4 is a diagram of the test signal injection circuit 204 according to an embodiment of the invention. Column removal injection circuit 226₀To 226_NIn addition, the test signal injection circuit 204 includes: random bit generator 400, random bit supply line 402, logic high voltage supply line 404, and logic low voltage supply line 406. In addition, the test signal injection circuit 204 is coupled to the buffered clock signal line 408 and the charge injection reset signal line 410. A buffered clock signal line 408 is routed from the control circuit 200 into the test signal injection circuit 204 to supply a clock signal to the column injection circuit 226₀To 226_NAnd a random bit generator 400. A buffer 420 may be coupled between the control circuit 200 and the column injection circuit 204 to buffer and/or amplify the clock signal from the control circuit 200.

Charge injection reset line 410 is routed from control circuit 200 into test signal injection circuit 204 to supply a reset signal to column injection circuit 226₀To 226_N. Random bit generator 400 includes an input terminal 412 and an output terminal 414 coupled to buffered clock signal line 408 and random bit supply line 402, respectively. In one embodiment, random bit generator 400 may be a Linear Feedback Shift Register (LFSR) that is operated such that randomly generated data bits are applied to random bit supply line 402 in response to receiving a clock signal from buffered clock signal line 408. Random bit supply line 402 is routed to supply random data bits to column injection circuit 226₀To 226_NAnd also from the test signal injection circuit 204 to a third comparison circuit 218 (from fig. 2). The high voltage supply line 404 and the low voltage supply line 406 are routed across the test signal injection circuit 204 to the column injection circuit 226₀To 226_N。

FIG. 5 shows a column injection circuit 226_jAnd adjacent column injection circuit 226_j-1Schematic representation of (a). Each columnInjection circuit 226_NTo 226₀The method comprises the following steps: a memory element 500, a first switch circuit 502, and a second switch circuit 504. In the illustrated embodiment, each storage element 500 is a flip-flop circuit having a clock input terminal 506, a data bit input terminal 508, and a data bit output terminal 510 coupled to the buffered clock signal line 408. Memory element 500_N(not shown) data bit input terminal 508 is coupled to random bit supply line 402 (from FIG. 4). Memory removal element 500_NIn addition, subsequent memory element 500_N-1To 500₀Is coupled to the output terminal 510 of the adjacent memory element 500. For example, memory element 500_jIs coupled to the adjacent memory element 500_j+1To the data bit output terminal 510. Also, memory element 500_j-1Is coupled to the adjacent memory element 500_jTo the data bit output terminal 510. Thus, memory element 500 is a flip-flop cascaded together to form a single serial-in shift register, in which data bits are serially shifted in from random bit generator 400 via random bit supply line 402. Those skilled in the art will appreciate that when buffered clock signal line 408 is clocked, random bit generator 400 applies a new data bit at data bit input terminal 508_NTo store previously in the memory element 500_NTo the memory element 500_N-1. Thus, the newly generated data bits are loaded into storage element 500₀The N +1 clock signal needs to be applied to the buffered clock signal line 408. In the exemplary embodiment of fig. 5, the storage element 500 is a flip-flop, and in other embodiments, the storage element 500 may be a burst-mode latch or a Random Access Memory (RAM).

The first switching circuit 502 includes: a control terminal 512 coupled to the charge injection reset signal line 410; a first input terminal 514 coupled to a logic high voltage line 404; a second input terminal 516 coupled to the second switching circuit 504; and an output terminal 518 coupled to the charge injection line 302. The first switching circuit 502 selectively couples the charge injection line 302 to either the logic high voltage line 404 or the second switching circuit 504 under control of the charge injection reset signal line 410. The second switching circuit 504 includes: a control terminal 520 coupled to the input terminal 508 of the memory element 500; a first input terminal 522 coupled to the logic high voltage supply line 404; a second input terminal 524 coupled to the logic low voltage supply line 406; and an output terminal 526 coupled to the second input terminal 516 of the first switching circuit 502. Under control of input terminal 508, second switch circuit 504 selectively couples second input terminal 516 of first switch 502 to either logic high voltage supply line 404 or logic low voltage supply line 406.

Fig. 6 is a circuit diagram showing features of the pixel array 202, the first row controller 206, the second row controller 208, and the first comparison circuit 210. First row controller 206 and second row controller 208 are coupled to receive row control instructions in the form of data bits output from control circuit 200. In the illustrated embodiment, the row control instructions output from the control circuit 200 include: a row address instruction for controlling the row select line 306₀To 306_M(ii) a A reset line control command for controlling the reset line 308₀To 308_M(ii) a And transmission line control instructions for controlling the transmission line 310₀To 310_M. The row address instruction is in the form of a data bit representing a row select line 306₀To 306_MWhich is to be applied. Row select line 306₀To 306_MEach of which comprises: a first terminal 600 and a second terminal 602 coupled to the first row controller 206 and the first comparison circuit 210, respectively. Reset line 308₀To 308_MEach of also comprising: a first terminal 604 and a second terminal 606 are coupled to the first row controller 206 and the first comparison circuit 210, respectively. Transmission line 310₀To 310_MEach of also comprising: a first terminal 608 and a second terminal 610 are coupled to the first row controller 206 and the first comparison circuit 210, respectively.

The first row controller 206 includes a main row decoder 612 and a row driver 614. The main row decoder 612 includes an input terminal 616 coupled to receive signals from the control circuit 200The row control signal commands. A row driver 614 is coupled to the main row decoder 612 and is operative to apply row select signals to the row select lines 306 in accordance with row control instructions decoded by the main row decoder 612₀To 306_MA reset signal is applied to the reset line 308₀To 308_MAnd applies a transmission signal to the transmission line 310₀To 310_MThe above. The row driver 614 includes a plurality of output terminals 618₀To 618_M、620₀To 620_MAnd 622₀To 622_M. Output terminal 618₀To 618_MIs operated to output and correspond to row select line 306₀To 306_MThe associated row select signal. First end 600₀To 600_MAre respectively coupled to the output terminals 618₀To 618_M. Output terminal 620₀To 620_MIs operated to output and correspond to the reset line 308₀To 308_MThe associated reset signal. First end 604₀To 604_MAre respectively coupled to the output terminals 620₀To 620_M. Output terminal 622₀To 622_MIs operated to output and correspond to the transmission line 310₀To 310_MThe associated transmission signal. First end 608₀To 608_MAre respectively coupled to the output terminals 622₀To 622_M。

The second row controller 208 includes a secondary row decoder 624, the secondary row decoder 624 including input terminals 626. The second row controller 208 further includes a plurality of output terminals 628₀To 628_M、630₀To 630_MAnd 632₀To 632_MCollectively referred to as output terminals 628, 630, and 632, respectively. The input terminals 626 of the secondary row decoder 624 are coupled to receive the same row control signal commands through the control circuit 200 as are provided to the input primary row decoder 612. Thus, the primary row decoder 612 and the secondary row decoder 624 decode the same row control signal commands at the same time to cause the output terminal 628₀To 628_MAnd the corresponding output terminal 618₀To 618_MAre matched to make the output terminal 630 output₀To 630_MLogic ofStatus and corresponding output terminal 620₀To 620_MAnd makes the output terminal 632 match₀To 632_MAnd corresponding output terminal 622₀To 622_MMatch the logic state of. For example, when the output terminal 618₀When changing from a low voltage state to a high voltage state, the output terminal 628₀Also changes from the low voltage state to the high voltage state at substantially the same time.

The first comparison circuit 210 is operated to control the row control signal line 300₀To 300_MIs compared with the control signal output from the sub row decoder 624, wherein the row control signal line 300₀To 300_MIncluding row select lines 306₀To 306_MReset line 308₀To 308_MAnd a transmission line 310₀To 310_M. If a given row is selected (e.g., row select line 306)₀) Does not AND the output terminal 628₀Is consistent, the first comparison circuit 210 outputs an error signal from the error signal output line 634.

The first comparison circuit 210 includes a plurality of first input terminals including an input terminal 636₀To 636_M、638₀To 638_MAnd 640₀To 640_M. Input terminal 636₀To 636_MAre electrically coupled to respective output terminals 628₀To 628_MAnd input terminal 638₀To 638_MAre electrically coupled to the respective output terminals 630₀To 630_MAnd an input terminal 640₀To 640_MAre electrically coupled to the respective output terminals 632₀To 632_M. The first comparison circuit 210 further comprises a plurality of second input terminals including an input terminal 642₀To 642_M、644₀To 644_MAnd 646₀To 646_M. Input terminal 642₀To 642_MIs electrically coupled to a respective row select line 306₀To 306_MRespective second end 602₀To 602_M. Also, input terminal644₀To 644_MIs electrically coupled to the corresponding reset line 308₀To 308_MRespective second end 606₀To 606_M. Finally, input terminal 646₀To 646_MAre electrically coupled to respective transmission lines 310₀To 310_MRespectively second end 610 of₀To 61O_M。

During operation, first comparison circuit 210 determines input terminal 636₀To 636_MAnd the corresponding input terminal 642₀To 642_MWhether the logic state of (b) has a predetermined correspondence, determines the input terminal 638₀To 638_MAnd corresponding input terminal 644₀To 644_MAnd determines whether the logic states of (c) correspond to (d) and (d) input terminal 640₀To 640_MAnd corresponding input terminal 646₀To 646_MWhether or not the logic state of (c) corresponds. If not, error output line 634 outputs an error signal indicating that image sensor 100 is malfunctioning.

In the control signal line 300₀To 300_MIn the event that one of them is defective, the row control signal applied to the row driver 614 may not be properly distributed to all pixels in the associated row. It is important to understand that each set of row control signal commands is decoded simultaneously via the primary row decoder 612 and the secondary row decoder 624, and then the electrical states of the output terminals 628, 630, 632 and the respective second ends 602, 606, 610 of the control signal lines 300 are compared, ensuring that the row control signals from the row drivers 614 are properly distributed across the row control signal lines 300. In contrast, prior art image sensors typically do not have a way to detect such failures, and therefore are more likely to output inaccurate image data to a host device.

Fig. 7 is a circuit diagram illustrating features of the first comparison circuit 210 according to an exemplary embodiment of the present invention. The first comparison circuit 210 includes a plurality of comparison circuits and an error signal line 706. In the illustrated embodiment, the comparison circuit may comprise an XOR gate. In other embodiments of the invention, other logic gates, such as NAND or NOR gates, may be used. If the two inputs of each comparison circuit do not have a predetermined relationship (e.g., match), an error signal will be output.

In the illustrated embodiment, each set of the comparison circuits includes a comparison circuit 700₀To 700_MComparison circuit 702₀To 702_MAnd a comparison circuit 704₀To 704_M. Comparison circuit 700₀To 700_MEach of which comprises: a first input terminal 708, a second input terminal 710, and an output terminal 712, as relevant. As shown, each comparison circuit 700 and each associated set of first input terminal 708, second input terminal 710, and output terminal 712 are uniquely identified with similar subscripts. For example, comparison circuit 700₁₀(not shown) includes a first input terminal 708₁₀A second input terminal 710₁₀And an output terminal 712₁₀. First input terminal 708₀To 708_MAre respectively electrically coupled to the input terminals 636₀To 636_M. Second input terminal 710₀To 710_MAre respectively electrically coupled to the input terminals 642₀To 642_M. All output terminals 712₀To 712_MElectrically coupled to the error signal line 706. Comparison circuit 702₀To 702_MEach of which comprises: a first input terminal 714, a second input terminal 716, and an output terminal 718, as relevant.

First input terminal 714₀To 714_MAre respectively electrically coupled to the input terminals 638₀To 638_M. Second input terminal 716₀To 716_MAre respectively electrically coupled to the input terminals 644₀To 644_M. All output terminals 718₀To 718 of_MElectrically coupled to the error signal line 706. Comparison circuit 704₀To 704_MEach of which comprises: a first input terminal 720, a second input terminal 722, and an output terminal 724, as relevant. First input terminal 720₀To 720_MAre respectively electrically coupled to the input terminals 640₀To 640_M. Second input terminal 722₀To 722_MIs electrically coupled to the input terminal 646₀To 646_M. All output terminals 724₀To 724_MElectrically coupled to the error signal line 706. It will be appreciated that when the first and second input terminals of the associated comparator circuit do not correspond, the associated output terminal will output an error signal in the form of a logic high voltage state. Since the error signal line 706 is connected to all the output terminals 712₀To 712_MOutput terminal 718₀To 718 of_MAnd an output terminal 724₀To 724_MAnd outputs an error signal if one or more of them has a logic high voltage state. In other embodiments of the invention, the compare circuits of each group may be coupled to their own respective error signal lines. For example, first comparison circuit 210 may include three error signal lines, one of which is coupled to all output terminals of a set of comparison circuits, comparison circuit 700₀To 700_MMay be coupled to the first error signal line, while the comparison circuit 702₀To 702_MAnd a comparison circuit 704₀To 704_MMay be coupled to the second and third error signal lines, respectively. In yet another embodiment of the present invention, a subset of the compare circuits may be coupled to their own respective error signal lines. For example, comparison circuit 700₀To 700_jComparison circuit 702₀To 702_jAnd a comparison circuit 704₀To 704_jMay be coupled to a first error signal line and the output terminals of the remaining comparison circuits may be coupled to a second error signal line. In yet another embodiment of the present invention, one subset of the compare circuits of each group may be coupled to its own respective error signal line. For example, comparison circuit 700₀To 700_MMay be coupled to the first error signal line, while the comparison circuit 702_M+1To 702_jIs coupled to the second error signal line. Similarly, third, fourth, fifth, and sixth error signal lines may be coupled to the compare circuit 704₀To 704_MComparison circuit 704_M+1To 704_jComparator 706₀To 706_MAnd a comparison circuit 706_M+1To 706_jAn output terminal of (1).

Fig. 8 is a circuit diagram showing the control circuit 200, the pixel array 202, the sampling circuit 212, and the second comparison circuit 214. The sampling circuit 212 acquires a read line 304 from the pixel array 202₀To 304_NAnd operates according to a control signal output from the control circuit 200. Accordingly, the sampling circuit 212 is coupled to receive a control signal from the control circuit 200. The second comparison circuit 214 is coupled to the sampling circuit 212 and the control circuit 200 and is operative to output an error signal when the control signal from the sampling circuit 212 does not correspond to the control signal output from the control circuit 200.

The sampling circuit 212 includes: a control signal adjusting circuit 800, a first control signal line 802, a second control signal line 804, a third control signal line 806, and a plurality of pixel reading circuits 808₀To 808_N。

The control signal adjusting circuit 800 is operated so that the control signal output from the control circuit 200 is adjusted before it is applied to the first control signal line 802, the second control signal line 804, and the third control signal line 806. The control signal conditioning circuit 800 includes: a first input terminal 810, a second input terminal 812, a third input terminal 814, a level shift (level shift) circuit 816, a first buffer circuit 818, a second buffer circuit 820, a third buffer circuit 822, a first output terminal 824, a second output terminal 826, and a third output terminal 828. The first input terminal 810 is coupled to receive an amplifier control signal output from the control circuit 200. Second input terminal 812 is coupled to receive an analog-to-digital converter control signal output from control circuit 200. The third input terminal 814 is coupled to receive a memory circuit control signal output from the control circuit 200. Level shifting circuitry 816 is coupled to the first input terminal 810, the second input terminal 812, and the third input terminal 814 to level shift the control signals applied thereto by the control circuitry 200. The first buffer circuit 818 is operative to buffer the amplifier control signal applied to the first input terminal 810 after a level shifted by the level shift circuit 816. After being buffered by the first buffer circuit 818, the amplifier control signal is applied from the first output terminal 824 to the control signal line 802. The second buffer circuit 820 is operative to buffer the analog-to-digital converter control signal applied to the second input terminal 812 after the level shifted by the level shift circuit 816. After being buffered by the buffer circuit 820, the analog-to-digital converter control signal is applied from the output terminal 826 to the control signal line 804. The third buffer circuit 822 is operative to buffer the storage circuit control signal applied to the third input terminal 814 after a level shifted by the level shifting circuit 816. After being buffered by the buffer circuit 822, the memory circuit control signal is applied to the control signal line 806 from the output terminal 828.

The control signal line 802 includes a first end 830 and a second end 832, the control signal line 804 includes a first end 834 and a second end 836, and the control signal line 806 includes a first end 838 and a second end 840. The control signal line 802 is an amplifier control signal line operated to supply an amplifier control signal to the pixel reading circuit 808₀To 808_N. A first end 830 and a second end 832 of the control signal line 802 are coupled to the output terminal 824 of the control signal conditioning circuit 800 and the second comparison circuit 214, respectively. The control signal line 804 is an analog-to-digital converter control signal line operated to supply an analog-to-digital converter control signal to the pixel reading circuit 808₀To 808_N. The first and second ends 834, 836 of the control signal line 804 are coupled to the output terminal 826 of the control signal conditioning circuit 800 and the second comparison circuit 214, respectively. The control signal line 806 is a memory circuit control signal line operated to supply a memory circuit control signal to the pixel reading circuit 808₀To 808_N. The first end 838 and the second end 840 of the control signal line 806 are coupled to the output terminal 828 of the control signal conditioning circuit 800 and the second comparison circuit 214, respectively.

Pixel reading circuit 808₀To 808_NIs operated to obtain a representation of a corresponding read line 304₀To 304_NDigital data of electrical states of (a). For example, the pixel read circuit 808_N-1Is operated to obtain a representative read line 304_N-1Digital data of electrical states of (a). Pixel reading circuit 808₀To 808_NEach of which comprises: capacitor 842, amplifier 844, analog-to-digital converter 846, and memory circuit 848. Capacitor 842₀To 842_NIncludes a first terminal 850 and a second terminal 852 coupled to a respective read line 304 and amplifier 844, respectively. Amplifier 844₀To 844_NIs operated to amplify the respective second terminal 852₀To 852_NElectrical state of (c). Amplifier 844₀To 844_NIs coupled to the control signal line 802 and operates in accordance with an amplification control signal (e.g., gain control signal) output from the output terminal 824 of the control signal conditioning circuit 800.

Analog-to-digital converter 846₀To 846_NAre coupled to respective amplifiers 844₀To 844_NAnd is operative to digitize the amplified signal output therefrom. For example, an analog-to-digital converter 846_NGenerating a representation from an amplifier 844_NAnd outputting the binary data word (binary data word) of the amplified voltage. Analog-to-digital converter 846₀To 846_NIs coupled to the control signal line 804 and operates in accordance with an analog-to-digital control signal output from the second output terminal 826 of the control signal conditioning circuit 800. Memory circuit 848₀To 848_NAre respectively coupled to analog-to-digital converters 846₀To 846_NAnd is operative to store binary data words generated therefrom. Memory circuit 848₀To 848_NIs coupled to the control signal line 806 and thus operates according to a memory circuit control signal output from the third output terminal 828 of the control signal adjusting circuit 800. Those skilled in the art will appreciate that the read circuit 808 can be used to read data from a memory cell₀To 808_NThe number of data bits acquired, the resolution of the binary data word, will depend on the particular application. Thus, resolution (e.g., 8-bit words) is not an important aspect of the present invention and thus need not be limited to any particular number of data bits or any particular type of analog-to-digital converterA converter (e.g., successive approximation register (SUCCESSITE) or ramp (ramp) analog-to-digital converter).

The second comparison circuit 214 includes: first input terminal 854, second input terminal 856, third input terminal 858, fourth input terminal 860, fifth input terminal 862, and sixth input terminal 864. The first input terminal 854 is coupled to receive the same amplifier control signal provided to the first input terminal 810 of the control signal conditioning circuit. In the embodiment shown, first input terminal 854 of second comparison circuit 214 and first input terminal 810 of control signal adjustment circuit 800 are connected via transmission line 866 and are thus coupled to the same node. The second input terminal 856 is coupled to receive the same analog-to-digital control signal provided from the control circuit 200 to the second input terminal 812 of the control signal conditioning circuit 800. In the illustrated embodiment, the second input terminal 856 of the second comparison circuit 214 and the second input terminal 812 of the control signal adjustment circuit 800 are connected via a transmission line 868 and thus coupled to the same node. The third input terminal 858 is coupled to receive the same memory circuit control signal provided from the control circuit 200 to the third input terminal 814 of the control signal conditioning circuit 800. In an exemplary embodiment, the third input terminal 858 of the second comparison circuit 214 and the third input terminal 814 of the control signal conditioning circuit 800 are connected via a transmission line 870 and are thus coupled to the same node.

The fourth input terminal 860 is coupled to the second end 832 of the control signal line 802. The fifth input terminal 862 is coupled to the second end 836 of the control signal line 804. The sixth input terminal 864 is coupled to the second end 840 of the control signal line 806. During operation, second comparison circuit 214 compares the electrical state of first input terminal 854, second input terminal 856, and third input terminal 858 with the electrical state of fourth input terminal 860, fifth input terminal 862, and sixth input terminal 864, respectively. The comparison circuit outputs an error signal if the electrical state of first input terminal 854, second input terminal 856 and third input terminal 858 does not correspond to the electrical state of the respective fourth input terminal 860, fifth input terminal 862 and sixth input terminal 864.

Fig. 9 is a circuit diagram illustrating additional details of second comparator circuit 214 according to an embodiment of the present invention. The second comparison circuit 214 includes a plurality of logic gates and an error signal output terminal 908. In the illustrated embodiment, the second comparison circuit 214 includes a plurality of XOR gates and OR gates. In other embodiments of the invention, other logic gates may be used, such as XNOR gates or NOR gates. Using an OR gate, the output will be logic high if any of these input terminals is at logic high.

The second comparison circuit 214 includes: a first XOR gate 900, a second XOR gate 902, a third XOR gate 904, an OR gate 906, and an error signal output terminal 908. The first XOR gate 900 includes a first input terminal 910, a second input terminal 912, and an output terminal 914. The first input terminal 910 and the second input terminal 912 of the first XOR gate 900 are coupled to the first input terminal 854 and the fourth input terminal 860, respectively. Thus, when both the first input terminal 910 and the second input terminal 912 are logic high or logic low, the logic state of the output terminal 914 is low, thus representing that the amplifier control signal applied on the control line 802 is properly distributed among all of the amplifiers 844₀To 844_N. If the control signal provided to the first input terminal 810 of the control signal conditioning circuit 800 is improperly distributed across the control lines 802 through the fourth input terminal 860, the input terminal 910 will not have the same logic value as the second input terminal 912, causing the output terminal 914 to have a high logic state.

The second XOR gate 902 includes a first input terminal 916, a second input terminal 918, and an output terminal 920. The first input terminal 916 and the second input terminal 918 of the second XOR gate 902 are coupled to the second input terminal 856 and the fifth input terminal 862, respectively. When both the first input terminal 916 and the second input terminal 918 are logic high or logic low, the logic state of the output terminal 920 is low, thereby indicating that the analog-to-digital converter control signal applied on the control line 804 is properly distributed to all analog-to-digital converters 846₀To 846_N. If the second input terminal of the circuit 800 is adjusted to the control signal812 is not properly distributed across the control line 804 to the fifth input terminal 862, the second input terminal 918 and the first input terminal 916 will not match, causing the output terminal 920 to have a high logic state.

The third XOR gate 904 includes: a first input terminal 922, a second input terminal 924, and an output terminal 926. The first input terminal 922 and the second input terminal 924 of the third XOR gate 904 are coupled to the third input terminal 858 and the sixth input terminal 864, respectively. When first input terminal 922 and second input terminal 924 are matched, the logic state of output terminal 926 is low, thereby indicating that the memory circuit control signals applied on control lines 806 are properly distributed throughout memory circuits 848₀To 848_N. If the control signal provided to the third input terminal 814 of the control signal conditioning circuit 800 is inappropriately distributed across the control lines 806 to the sixth input terminal 864, the second input terminal 924 and the first input terminal 922 will not match, causing the output terminal 926 to have a high logic state.

The OR gate 906 includes: a first input terminal 928, a second input terminal 930, a third input terminal 932, and an output terminal 908. The first input terminal 928, the second input terminal 930, and the third input terminal 932 are respectively coupled to the output terminals 914, 920, 926. When the logic states of output terminals 914, 920, 926 are all low, the logic state of output terminal 908 will be low. If the logic state of one or more of output terminals 914, 920, 926 is high, output terminal 908 will have a high logic state, indicating that some type of fault has occurred in sampling circuit 212.

In the embodiment shown, XOR gates are used. In other embodiments of the invention, other logic gates may be used, such as NAND gates or NOR gates. Using an XOR gate, if the two inputs do not match, a logic high will be output.

Fig. 10 is a circuit diagram of the third comparing circuit 218 (fig. 2) according to an embodiment of the invention. When the image sensor 100 is operating in the test mode, the third comparison circuit 218 will pass through the random bit generator 400 via the random bitThe test signal provided by the machine side supply line 402 (which should also be the test signal provided by the column injection circuit 226)₀To 226_NProvided to the pixel 202 and then sampled from the pixel 202 by the sampling circuit 212) is compared with the digital data actually acquired by the sampling circuit 212. In the case where the acquired data does not match the test data, the third comparison circuit 218 outputs an error signal from the error signal output terminal 1000. In the illustrated embodiment, the third comparison circuit 218 includes: a first checksum (checksum) circuit 1002, a threshold circuit 1004, a second checksum circuit 1006, and a comparator 1008.

The first checksum circuit 1002 includes: a clock input terminal 1010, a data bit input terminal 1012, and an output terminal 1014. The clock input terminal 1010 and the data bit input terminal 1012 are coupled to the buffered clock signal line 408 and the random bit supply line 402, respectively. A buffer 420 is coupled between the control circuit 200 and the buffered clock signal line 408 to buffer and/or amplify the clock signal from the control circuit 200. The clock signal applied on buffered clock signal line 408 causes first checksum circuit 1002 to sequentially read, via input terminal 1012, the randomly generated data bits that are sequentially applied on random bit supply line 402 by random bit generator 400 (see FIG. 4). Since the randomly generated bits are sequentially received by the first checksum circuit 1002, the first checksum circuit 1002 calculates a checksum value that is output to the comparator 1008 through the output terminal 1014.

The threshold circuit 1004 includes: a clock input terminal 1016, a data input terminal 1018, and an output terminal 1020. The clock input terminal 1016 is coupled to a second clock signal line 1022 to receive a clock signal from the control circuit 200. The data input terminal 1018 is coupled to the data line 228 to receive pixel data acquired by the sampling circuit 212. The pixel data is processed and provided from image processor 216 to terminal 1018 via data line 228 as binary data words, each word representing the charge state of a particular pixel. Alternatively, the pixel data may be supplied directly from the sampling circuit 212 to the data input terminal 1018 in the form of a binary data word. A single data bit is output from terminal 1020 each time a data word is downloaded to threshold circuit 1004. The threshold circuit 1004 outputs a binary "0" from the output terminal 1020 if the binary value of the data word received via the data input terminal 1018 is below a predetermined threshold. The threshold circuit 1004 outputs a binary "1" from the output terminal 1020 if the binary value of the data word received via the data input terminal 1018 is greater than or equal to a predetermined threshold value. Thus, each time the clock signal line 1022 is cycled (cycle), the threshold circuit 1004 receives another data word and outputs another data bit corresponding thereto.

The second checksum circuit 1006 includes: a clock input terminal 1026, a data bit input terminal 1028, and an output terminal 1030. The clock input terminal 1026 and the data bit input terminal 1028 of the second checksum circuit 1006 are coupled to the second clock signal line 1022 and the output terminal 1020, respectively, of the threshold circuit 1004. Thus, the second checksum circuit 1006 receives another bit of data output from the threshold circuit 1004 each time the clock signal line 1022 is cycled. Because the randomly generated bits are sequentially received through the input terminal 1028, the first checksum circuit 1006 calculates a checksum value that is output to the comparator 1008 through the output terminal 1030.

The comparator 1008 includes: a first input terminal 1032, a second input terminal 1034, and an output terminal 1036. The first and second input terminals 1032, 1034 are coupled to receive binary checksum values output from the output terminals 1014, 1030, respectively. An output terminal 1036 of the comparator 1008 is coupled to the error signal output terminal 1000. If the checksum value received via second input terminal 1034 is not equal to the checksum value received via first input terminal 1032, output terminal 1036 applies an error signal on error signal output terminal 1000. The checksum may be calculated for each row or for the entire frame, but the verification of each row provides the advantage that a particular faulty row can be identified.

Fig. 11 is an exemplary timing diagram 1100 illustrating the operation of the image sensor 100 in the image capture mode. The following example describes row 222 when image sensor 100 is operating in an image capture mode_iControl and sampling. This is achieved byFurthermore, this example illustrates responding to row 222_iControl of, pixel 220_i,jElectrical states of various components. Although only row 222 is depicted in this example_iBut all rows 222 are controlled and sampled sequentially in the same manner₀To 222_M. The operation of the image sensor 100 will also be described with reference to fig. 2 to 10.

In fetch row 222_i-1After the image data of (2), the line 222 is acquired as follows_iThe image data of (1). First, the control circuit 200 outputs a set of row control instructions (e.g., row address for row i) to the first row controller 206 and the second row controller 208. In response to row control instructions, the row controller 206 applies row select signals 1102 on the row select lines 306_iThereby making the pixel 220_i,0To 220_i,NThe row select transistor 324 operates in an on state. One and for example pixel 220_i,jThe row select transistor 324 is in a conductive state and the associated read line 304 is turned on_jCorresponds to a charge storage (FD) region 314_i,j1106.

In the present exemplary embodiment, voltage supply line 404 provides a reference voltage (Vhi) 1110 in which injection line 302 is maintained when image sensor 100 is operating in an image capture mode₀To 302_NAt a reference voltage. The high voltage state of the charge injection reset signal line 410 causes the switch circuit 502 to switch₀To 502_NEach of (fig. 5) couples the high voltage supply line 404 to a respective one of the charge injection lines 302. Thus, all injection lines 302₀To 302_N(i.e., all injection lines to pixels 220 in row i) is coupled to a high voltage supply line 404.

Upon application of a reset signal 1108 on the charge injection reset signal line 410, a pixel reset signal 1112 is applied on the reset line 308_iThereby driving the pixel 220_i,0To 220_i,NTo each associated reset transistor 318. As previously described, the driving transistor 318 couples the associated charge storage (FD) region 314 with the voltage source terminal 316 (Vdd). Reset signal 1112 remains applied to resetLine 308_iThe last predetermined duration is sufficient to allow any charge previously accumulated in charge storage region 314 to return to a known reset state.

In the self reset line 308_iAfter the reset signal 1112 is removed (e.g., goes low), the sampling circuit 212 simultaneously acquires from the read line 304₀To 304_NVoltage samples of each. SHR1 (Samp 1 e-hall-Reset 1, sample-and-hold Reset 1), indicated by a dashed line, indicates the timing of taking the first voltage sample. Shortly after SHR1, transmission signal 1114 is applied to transmission line 310_iThereby driving the pixel 220_i,0To 220_i,NEach associated pass transistor 320. Driving the transfer transistor 320 causes an electrical coupling and, therefore, a charge to be transferred from the photosensor 312 to the charge storage (FD) region 314. As shown, for example, when a transmission signal 1114 is applied to the transmission line 310_iIn the upper stage, the optical sensor 312_i,jInitial low charge state 1116 and charge storage region 314_i,jRespectively, increases and decreases simultaneously. The transmission signal 1114 remains applied to the transmission line 310_iLast predetermined duration sufficient to allow passage of light through the light sensor 312_i,jAny charge generated is transferred to charge storage region 314_i,j. On the self-transmission line 310_iAfter the transmission signal 114 is removed, the sampling circuit 212 simultaneously acquires the data from the read line 304₀To 304_NThe second voltage sample of each of (1). The timing of the acquisition of the second voltage Sample is indicated by the SHS1 (Sample-hall-Signal 1, Sample-and-hold Signal 1) indicated by the dashed line. Finally, the line 306 is selected by itself_iThe row select signal 1102 is removed and the row 222 is aligned_i+1The above process is repeated.

Fig. 12 is a timing diagram 1200 illustrating an example of the operation of the image sensor 100 in the test mode. In particular, the timing diagram 1200 shows the image capture process (before the SHS 1) followed by the test process (after the SHS 1). The following description explains row 222_iAnd is responsive to row 222 and sampling_iIllustrates the pixel 220_i,jElectrical state of various elements ofState. Although only row 222 is depicted in this example_iAll rows 222 are controlled and sampled sequentially in a similar manner₀To 222_M. The following description is also made with reference to fig. 2 to 10.

In an effort to convey the novel features of the present invention in a simple manner, image sensor 100 is depicted as having only 24 rows of pixels. However, it will be apparent to those skilled in the art that in typical applications, the image sensor 100 will likely have a substantially large number of pixel rows. However, the invention may be practiced with image sensor 100 having any practical number of rows and/or columns of pixels.

First, the control circuit 200 begins to apply a sequence of clock signals 1202 on the clock signal line 408. The number of cycles in the clock signal 1202 is equal to the number of pixel columns 224 of the image sensor 100. Because this particular example depicts the image sensor 100 having 24 pixel columns 224, there are 24 cycles in the portion of the clock signal 1202 shown. At each falling edge of the clock signal 1202, the random bit generator 400 causes a new randomly generated bit to be applied to the random bit line 402. Thus, random bit generator 400 causes a sequence of 24 randomly generated bits to be applied to random bit line 402. Each time a newly randomly generated bit is applied to the random bit line 402, it is previously stored in the storage element 500_j+1Is transmitted to the memory element 500_jAnd a data input terminal 508. Thus, the 24-bit sequence 1204 is shifted to 24 storage elements 500₀To 500₂₃(only two storage elements 500 are shown). Starting with the 1 st and ending with the 24 th bit, the 24 bit sequence 1204 shown in this example is 110100101011000101010111.

The first bit of bit sequence 1204 is shifted to storage element 500_jThereafter, a row selection signal 1102 is applied to the row selection signal line 306_iThereby connecting the pixels 220_i,0To 220_i,23To the corresponding read line 304₀To 304₂₃. At the row select signal 1102 applied to the row select line 306_iShortly after, the reset signal 1108 is applied to the charge injection reset signal line 410 of the test signal injection circuit 204. The logic high voltage state of the charge injection reset signal line 410 causes the first switch circuit 502 to be turned on₀To 502₂₃Each respectively coupled to an output terminal 518₀To 518₂₃And a first input terminal 514₀To 514₂₃. Thus, the charge injection line 302₀To 302₂₃Are coupled to a high voltage supply line 404. While the reset signal 1108 is applied to the charge injection reset signal line 410, the pixel reset signal 1112 is applied to the reset line 308_iThereby causing charge storage region 314 to_i,0To 314_i；23Coupled to at pixel 220_i,0To 220_i,23A voltage source terminal 316 in each of the associated ones. In the charge storage region 314_i,0To 314_i,23After each of the reset charge states returns to a known reset charge state, the reset lines 308_iThe reset signal 1112 is removed (goes low).

In the self reset line 308_iAfter the reset signal 1112 is removed, the sampling circuit 212 simultaneously acquires the data from the read lines 304₀To 304₂₃Voltage samples of each. While in image capture mode, a first voltage sample (reset voltage sample) is taken at SHR 1. Shortly after SHR1, transmission signal 1114 is applied to transmission line 310_iAnd thus respectively from the light sensor 312_i,0To 312_i,23Transferring charge to charge storage region 314_i,0To 314_i,23. Then, self-transmission line 310_iThe (low) transmit signal 1114 is removed and the sampling circuit 212 simultaneously acquires data from the read line 304 at SHS1₀To 304₂₃The second voltage sample (image signal) of each of the first and second pixels. This completes the image capturing process.

Shortly after the SHS1, the reset signal 1112 is again applied to the reset line 308_iUp to thereby reset charge storage region 314_i,0To 314_i,N1106. In the self reset line 308_iSecond time after reset signal 1112 is removed, sampling circuit 212 is simultaneously at SHR2Fetch from read line 304₀To 304₂₃Of each of the first and second voltage samples. After SHR2, the reset signal 1108 is removed from the charge injection reset signal line 410, causing the first switch circuit 502 to operate₀To 502_NRespectively electrically coupled to the second input terminals 516₀To 516_NAnd output terminal 518₀To 518_N. Therefore, are used in the corresponding control terminals 520₀To 520_NThe logic state of any of the valid bit sequences 1204 indicating each of the test signal injection lines 302₀To 302_N1110. For example, when applied to the memory element 500_jData bit input terminal 508_jWhen the bit of the bit sequence 1204 happens to be "0", the column injection circuit 226_jSecond switching circuit 504_jElectrical coupling terminal 526_jAnd 522_j. Coupling terminal 526_jAnd 522_jMake the injection line 302_jIndirectly through the switching circuit 502_jAnd 504_jCoupled to a logic high voltage supply line 404. On the other hand, when applied to the memory element 500_jData bit input terminal 508_jWhen the bit of the bit sequence 1204 happens to be "1", the column injection circuit 226_jSecond switching circuit 504_jCoupling terminal 526_jAnd 524_j. As a coupling terminal 526_jAnd 524_jAs a result of (1), the injection line 302_jIndirectly through the first switching circuit 502_jAnd 504_jCoupled to a logic low voltage line 406. However, in this particular example, the storage is at terminal 508_jThe 24 th bit of the bit sequence 1204 is a "1" to cause the injection line 302 to inject when the reset signal 1108 is removed from the charge injection reset signal line 410_jTo a logic low voltage of the low voltage supply line 406. Of course, if the 24 th bit of the bit sequence 1204 is a "0" instead of a "1," the injection line 302 is at the time the reset signal 1108 is removed from the charge injection reset signal line 410_jWill remain at the level of logic high voltage line 404.

Unlike when the image sensor 100 is operating in an image capture mode, the image sensor 100 is inWhen operating in the test mode, the second transmission signal 1114 is not applied to the transmission line 310 after the SHR2_jThe above. Indeed, not by the intensity of the incident light (i.e., not by the light sensor 312)_i,0To 312_i,NAccumulated photo-generated charge) indicating pixel 220_i,0To 220_i,23The charge state of (c). Instead, through the injection lines 302, respectively₀To 302_jVoltage state indicating pixel 220_i,0To 220_i,23The charge state of (c). Because the injection line 302₀To 302_jMay have only one of two possible voltage states (Vhi or Vlo), so that during SHR2, there is a corresponding read line 304₀To 304_jEach of the acquired voltage samples may have only one of two possible values. In effect, the sampling circuit 212 passes the light from the light sensor 312_i,0To 312_i,NTo the corresponding charge storage region 314_i,0To 314_i,NInstead of (2) injecting randomly generated test signals into charge storage region 314_i,0To 314_i,NTo sample the injection into the pixel 220_i,0To 220_i,NThe analog pixel data of (1).

It is not necessary that each image capture process be followed by a test process. The frequency at which the test procedure (injection signal sampling) is performed depends on how fast sensor faults must be detected. Typically, every N image capture processes may be followed by a test process, where N is an integer greater than 0. Alternatively, only a subset of the rows of pixels 222 may be tested during each frame time (i.e., the time at which the image capture process for each row 222 in pixel array 202 is completed).

Fig. 13 is a circuit diagram of a first comparison circuit 210 according to an alternative embodiment of the present invention. In this particular embodiment, the first comparison circuit 210 (fig. 2) is configured to be selectively enabled and disabled according to a control signal applied on its additional input terminal 1300. One advantage of selectively enabling and disabling the first comparison circuit 210 is that when the first comparison circuit 210 is not in use, the first comparison circuit 210 may be disabled, thereby reducing the overall power consumption of the image sensor 100. In some applications, the comparison process may only need to be performed once every few frames in order to achieve some predetermined image data reliability. In this case, it may be necessary to disable the first comparison circuit 210 during a frame in which the control signal does not need to be applied.

To implement the selective control, the first comparison circuit 210 further includes: multiple transistors 1302₀To 1302_MA plurality of second transistors 1304₀To 1304_MA plurality of third transistors 1306₀To 1306_MAn enable transistor 1308, and an inverter 1310. Transistor 1302₀To 1302_MEach of which comprises: a first terminal 1312, a second terminal 1314, and a third terminal 1316. As shown, a transistor 1302 is used that identifies it as belonging to₀To 1302_MThe subscripts of the associated transistors indicate each of the first terminal 1312, the second terminal 1314, and the third terminal 1316. First terminal 1312₀To 1312_MAre respectively connected to the output terminals 712₀To 712_M. Corresponding transistor 1302₀To 1302_MAll the second terminals 1314₀To 1314_MTo the ground terminal 1318 of the first comparison circuit 210. Corresponding transistor 1302₀To 1302_MAll third terminals 1316₀To 1316_MA common supply line 1320 connected to the first comparison circuit 210.

Second transistor 1304₀To 1304_MEach of which further comprises: a first terminal 1322, a second terminal 1324, and a third terminal 1326. As shown, a second transistor 1304 is also used that identifies it belongs to₀To 1304_MThe subscripts of the associated transistors indicate each of the first terminal 1322, the second terminal 1324, and the third terminal 1326. First terminal 1322₀To 1322_MAre respectively connected to the output terminals 718₀To 718 of_M. Respective second transistors 1304₀To 1304_MAll second terminals 1324 of₀To 1324_MTo the ground terminal 1318 of the first comparison circuit 210. Corresponding second transistor1304₀To 1304_MAll third terminals 1326₀To 1326_MA common supply line 1320 connected to the first comparison circuit 210.

Third transistor 1306₀To 1306_NEach of which further comprises: a first terminal 1328, a second terminal 1330, and a third terminal 1332. As shown, a third transistor 1306 is also used to identify its membership₀To 1306_MThe subscripts of the associated transistors indicate each of the first terminal 1328, the second terminal 1330, and the third terminal 1332. First terminal 1328₀To 1328_MAre respectively connected to the output terminals 724₀To 724_M. Corresponding third transistor 1306₀To 1306_MAll the second terminals 1330₀To 1330_MTo the ground terminal 1318 of the first comparison circuit 210. Corresponding third transistor 1306₀To all third terminals 1332 within 130₀To 1332_MA common supply line 1320 connected to the first comparison circuit 210.

The enable transistor 1308 includes: a first terminal 1334 connected to the input terminal 1300 of the first comparison circuit 210; a second terminal 1336 connected to the common supply line 1320; and a third terminal 1338 connected to the voltage source 1340 of the first comparison circuit 210. The inverter 1310 includes: an input terminal 1342 connected to the common supply line 1320; and an output terminal 1344 connected to the error signal output line 706 of the first comparison circuit 210.

The following example describes the operation of the first comparison circuit 210 according to this alternative embodiment. First, the input terminal 1300 is in a low voltage state, driving the enable transistor 1308. When the enable transistor 1308 is actuated, no voltage drop occurs between the third terminal 1338 and the second terminal 1336, so the voltage state of the node comprising the common supply line 1320 and the input terminal 1342 of the inverter 1310 is equal to the high voltage state of the voltage source 1340. Of course, since the input terminal 1342 of the inverter 1310 is in a high voltage state, the output terminal 1344 is in a low voltage state. To enable the first comparison circuit 210, the enable signal is in the form of a high voltage stateApplied to the input terminal 1300. This causes the enable transistor 1308 to be in a non-conductive state ("off"), thereby disconnecting the common supply line 1320 and the input terminal 1342 of the inverter 1310 from the voltage source 1340. After enabling transistor 1308 is turned off, the voltage state of common supply line 1320 and input terminal 1342 of inverter 1310 remains precharged (precharge) to a high voltage state. If XOR gate 700₀To 700_M、702₀To 702_MAnd/or 704₀To 704_MHas a non-corresponding input terminal, the associated output terminal will have a high voltage state, driving (in a conductive state) the transistor 1302₀To 1302_MA second transistor 1304₀To 1304_MOr a third transistor 1306₀Any of through 130 has a gate connected thereto. Transistor 1302₀To 1302_MA second transistor 1304₀To 1304_MOr a third transistor 1306₀To 1306_MWill couple the common supply line 1320 and the input terminal 1342 of the inverter 1310 to the ground terminal 1318. Thus, the input terminal 1342 of the inverter 1310 causes the output terminal 1344 (and thus the erroneous output signal line 706) to have a high voltage state. Of course, the high voltage state of the error signal line 706 is such that one or more control signals have not been properly distributed to the control signal line 300₀To 300_MIs detected.

Fig. 14 is a circuit diagram of an alternate sampling circuit 1400 and an alternate comparison circuit 1402 in another embodiment in accordance with the invention. It will be appreciated that many features of the sampling circuit 1400 are substantially similar to the sampling circuit 212 and, therefore, are referred to by similar reference numerals. Those substantially similar elements are not described in detail again to avoid repetition.

In this particular embodiment, the sampling circuit 1400 includes a first encoder 1404 and a second encoder 1406. The first encoder 1404 is connected to first ends 830, 834, 838 of the first, second, and third control signal lines 802, 804, 806, respectively, and is operative to encode control signals applied thereto. The first encoder 1404 includes an output terminal 1408 connected to provide the comparison circuit 1402 with encoded data represented by control signals applied to the first ends 830, 834, 838 of the respective first, second and third control signal lines 802, 804, 806. The second encoder 1406 is connected to the second ends 832, 836, 840 of the first control signal line 802, the second control signal line 804, and the third control signal line 806, respectively, and is operative to encode control signals applied thereto. The second encoder 1406 also includes an output terminal 1410 connected to provide the comparison circuit 1402 with encoded data represented by control signals applied to the second ends 832, 836, 840 of the respective first, second and third control signal lines 802, 804, 806.

The comparison circuit 1402 includes: a first input terminal 1412, a second input terminal 1414, and an error signal output terminal 1416. The first input terminal 1412 is connected to receive encoded data from the output terminal 1408 of the first encoder 1404. Second input terminal 1414 is connected to receive encoded data from output terminal 1410 of second encoder 1406.

During operation of the sampling circuit 1400, the first encoder 1404 and the second encoder 1406 encode control signals applied to the first control signal line 802, the second control signal line 804, and the third control signal line 806 simultaneously. More specifically, the first encoder 1404 encodes control signals from the first ends 830, 834, 838, and the second encoder 1406 encodes control signals from the second ends 832, 836, 840. The first encoder 1404 and the second encoder 1406 also output encoded data from the output terminals 1408 and 1410, respectively, simultaneously. The input terminals 1412 and 1414 of the comparator circuit 1402 simultaneously receive the encoded data output from the input terminals 1408 and 1410, respectively. Then, the comparison circuit 1402 determines whether the encoded data received from the input terminal 1412 corresponds to the encoded data received from the input terminal 1414. The comparison circuit if the encoded data received from input terminal 1412 improperly corresponds to the encoded data received from input terminal 1414An error signal is output from the error signal output terminal 1416. The error signal indicates that the control signals applied to the first control signal line 802, the second control signal line 804, and the third control signal line 806 are not properly distributed to all the pixel reading circuits 808₀To 808_N。

The term "connect" as used herein refers to a direct electrical connection between connected elements without any intervening devices. The term "coupled" refers to either a direct electrical connection between the connecting elements or an indirect connection through one or more passive or active intermediary devices. The term "circuit" refers to a single component or a plurality of components, active and/or passive, connected together to provide a desired function. The term "signal" refers to at least one of a current, voltage, charge, data, or other signal.

One or more embodiments include an article of manufacture (e.g., a computer process product) comprising a machine-accessible and/or machine-readable medium. The media may include mechanisms that provide for storage of information, for example, in a form accessible and/or readable by a machine. A machine-accessible and/or machine-readable medium may provide, or have stored thereon, one or more or a sequence of instructions and/or data structures that, if executed via a machine, cause or occur in and/or cause the machine to perform, to implement, one or more or a portion of the operations or methods or techniques illustrated in the figures disclosed herein.

In an embodiment, the machine-readable medium may comprise a tangible, non-transitory machine-readable storage medium. For example, the tangible, non-transitory, machine-readable storage medium may include a floppy disk, an optical storage medium, an optical disk, a CD-ROM, a magnetic disk, a magneto-optical disk, a Read Only Memory (ROM), a Programmable ROM (PROM), an Erasable Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), a Random Access Memory (RAM), a Static RAM (SRAM), a Dynamic RAM (Dynamic RAM, DRAM), a flash Memory, a Phase-Change Memory (Phase-Change) Memory, or a combination thereof. The tangible medium may include one or more solid state or tangible physical materials, such as, for example, semiconductor materials, phase change materials, magnetic materials, and the like. Examples of suitable machines include, but are not limited to, digital cameras, digital video cameras, mobile telephones, computer systems, other electronic devices having arrays of pixels, and other electronic devices capable of capturing images. Such electronic devices typically include one or more processors coupled with one or more other elements, such as one or more storage devices (non-transitory machine-readable storage media). Thus, the memory device of a given electronic device may store code and/or data that is executed on one or more processors of the electronic device. Alternatively, one or more portions of the embodiments may be implemented using different combinations of software, firmware, and/or hardware.

A description of specific embodiments of the present invention is now complete. Many of the described features may be substituted, altered or omitted without departing from the scope of the invention. For example, the inventive features may be applied to various image sensor types (e.g., front-lit sensors, back-lit sensors, etc.). As another example, many circuit elements and structures (e.g., logic gates, transistor types, switches, etc.) may be replaced with alternative circuit elements and structures that perform substantially similar functions. These and other features of the particular embodiments shown will be apparent to those skilled in the art, particularly in light of the foregoing disclosure.

Claims (27)

1. An image capture device comprising:

a plurality of pixels, each pixel comprising a photosensor, a charge storage region selectively coupled to receive a photocurrent from the photosensor, an output coupled to the charge storage region and operative to provide an output signal indicative of an amount of charge stored in the charge storage region, and a test signal input coupled to the charge storage region;

a test signal injection circuit coupled to provide a test signal to the test signal input of the pixel;

a sampling circuit selectively coupled to receive the output signal from the output of the pixel; and

a comparison circuit responsive to the test signal provided to the pixel and the output signal received from the pixel and operative to provide an error signal responsive to the output signal not corresponding to the test signal.

2. The image capture device as in claim 1 wherein the test signal injection circuit is coupled to the comparison circuit to also provide the test signal provided to the pixel to the comparison circuit.

3. The image capturing apparatus according to claim 1, wherein:

the pixels are arranged in a plurality of columns; and

the image capturing device includes a plurality of charge injection lines, each of which connects the test signal input terminals of the pixels of a corresponding one of the columns to the test signal injection circuit.

4. The image capture device as claimed in claim 3, wherein the charge storage region of each pixel is coupled to a respective one of the charge injection lines via a capacitor.

5. The image capture device of claim 4, wherein no switching device is interposed between the charge storage region of the pixel and the charge injection line.

6. The image capture device as in claim 3 wherein the test signal injection circuit is capable of providing different test signals on different of the charge injection lines.

7. The image capturing device of claim 3, wherein the test signal injection circuit is capable of providing different test signals on the same charge injection line at different timings.

8. The image capturing device of claim 3, wherein the test signal injection circuit comprises:

a plurality of test signal storage elements, each selectively coupled to a respective one of the charge injection lines; and

a test signal generator coupled to the test signal storage element and operative to generate a test signal value and store the test signal value in the test signal storage element.

9. The image capture device of claim 8, wherein:

the test signal generator is operative to generate a digital test signal value; and

each of the test signal storage elements is a unit storage element.

10. An image capture device as claimed in claim 9, wherein the test signal generator comprises a random bit generator.

11. The image capture device of claim 10, wherein:

the test signal storage elements are coupled together in series; and

bits from the random bit generator are shifted into the test signal storage elements.

12. The image capturing apparatus according to claim 3, wherein:

the charge storage region of each of said pixels being selectively coupled to the photosensor of each of said pixels by the switching device of each of said pixels;

the image capture device further includes a controller coupled to provide a transmit signal to the switching device of the pixel;

the switching device, in response to a first value of the transmission signal, conducts a photocurrent between the photosensor and the charge storage region to facilitate image capture; and

the switching device, in response to a second value of the transmission signal, blocks photocurrent between the photosensor and the charge storage region to facilitate test signal injection.

13. The image capture device of claim 12, wherein:

the image capture device performing a repetitive image capture process over successive frame times to capture frames of image data;

the controller applies the second value of the transmit signal for a duration of an image capture process to facilitate test signal injection every N frame times, where N is an integer greater than 1.

14. The image capture device of claim 1, further comprising:

a controller operative to provide a control signal;

a driver responsive to the control signal and operative to generate a drive signal based on the control signal and to apply the drive signal on a control line of the image capture device; and

a comparator responsive to a first input based on the control signal and a second input based on the drive signal, the comparator being operative to generate an error signal if the control signal does not correspond in a predetermined manner to the applied drive signal.

15. The image capturing device of claim 14, wherein the comparator directly compares the control signal with the driving signal to determine whether the driving signal corresponds to the control signal.

16. The image capture device of claim 14, wherein:

the image capture device further includes an image light sensor array; and

the driver controls the driver for the rows of the image light sensor array.

17. The image capture device of claim 14, wherein:

the image capture device further includes an image light sensor array;

the image capture device further includes an image data sampling circuit coupled to receive rows of data from the image photosensor array; and

the driver is an element of the image data sampling circuit.

18. The image capture device of claim 14, wherein:

the image capture device further includes a second driver coupled to receive the control signal and operative to generate a second drive signal based on the control signal; and

the comparator is operated to compare the second driving signal with the driving signal.

19. The image capture device of claim 14, further comprising:

a plurality of the control lines;

a first encoder coupled to the control line at a first point and operative to generate a first encoded value based on a drive signal detected on the control line; and

a second encoder coupled to the control line at a second point at a distance from the first point, the second encoder being operative to generate a second encoded value based on the drive signal detected on the control line,

wherein the comparator is operative to compare the first encoded value with the second encoded value.

20. A method for detecting a fault in an image capture device, the method comprising:

providing the image capture device comprising an array of light sensors;

focusing an image on the photosensor array;

repeatedly capturing a frame of image data using the photosensor array, the image data representing the image focused on the photosensor array;

periodically injecting test data into the photosensor array between the repeated captures of the image data;

reading the test data from the image capture device;

comparing the read test data with the injected test data; and

if the read test data does not correspond to the injected test data, an error signal is generated.

21. The method of claim 20, further comprising:

receiving a control signal;

generating a driving signal based on the control signal;

applying the driving signal to a control line of the image capturing apparatus;

comparing the applied drive signal with the control signal; and

an error signal is generated if the control signal does not correspond in a predetermined manner to the applied drive signal.

22. The method of claim 21, wherein the step of applying the driving signal on the control line of the image capturing device comprises: the drive signals are applied to row control lines of the image photosensor array.

23. The method of claim 21, wherein the step of applying the driving signal on the control line of the image capturing device comprises: the driving signal is applied to a control line of the image data sampling circuit.

24. The method of claim 21, wherein the step of comparing the applied drive signal to the control signal comprises:

generating a second drive signal based on the control signal; and

the second driving signal is compared with the driving signal.

25. The method of claim 21, wherein the step of comparing the applied drive signal to the control signal comprises:

generating a first encoded value based on a drive signal applied at a first point on a plurality of control lines;

generating a second encoded value based on the drive signal applied at a second point on the control line; and

the first encoded value is compared with the second encoded value.

26. An image capture device comprising:

a plurality of pixels, each of the pixels comprising a photosensor, a charge storage region selectively coupled to receive a photocurrent from the photosensor, an output coupled to the charge storage region and operative to provide an output signal indicative of an amount of charge stored in the charge storage region, and a test signal input coupled to the charge storage region;

a test signal injection circuit coupled to provide a test signal to the test signal input of the pixel;

a sampling circuit selectively coupled to receive the output signal from the output of the pixel; and

means for comparing the test signal provided to the pixel with the output signal received from the pixel and for providing an error signal in response to the output signal not corresponding to the test signal.

27. The image capture device of claim 26, further comprising:

a controller operative to provide a control signal;

a driver responsive to the control signal and operative to generate a drive signal based on the control signal and to apply the drive signal on a control line of the image capture device; and

means for comparing a first input based on the control signal with a second input based on the drive signal and for generating an error signal if the control signal does not correspond in a predetermined manner to the applied drive signal.