HK1196464B - Semiconductor device - Google Patents

Description

Semiconductor device with a plurality of transistors

Technical Field

The present invention relates to a semiconductor device, and more particularly, to an effective technique suitable for a power semiconductor device used in, for example, an inverter of an air conditioner, a DC/DC converter of a computer power supply, an inverter module of a hybrid vehicle or an electric vehicle, and the like.

Background

Japanese patent application laid-open No. 2000-506313 (patent document 1) describes a technique for providing a switching element that achieves both low on-resistance and high breakdown voltage. Specifically, patent document 1 describes a structure in which a Junction Field Effect Transistor (Junction Field Effect Transistor) using silicon carbide (SiC) as a material and a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) using silicon (Si) as a material are cascade-connected (cascode).

Japanese patent application laid-open No. 2008-198735 (patent document 2) describes the following structure: in order to provide an element having a low on-voltage and a high withstand voltage, an FET made of SiC and a diode made of Si are connected in series.

Japanese patent laid-open publication No. 2002-208673 (patent document 3) describes the following structure: in order to reduce the area of the power module, the switching element and the diode are stacked with the flat connection terminal interposed therebetween.

Jp 2010-206100 a (patent document 4) describes a technique of preventing erroneous arcing by increasing the threshold voltage of a normally-closed junction FET made of SiC. Specifically, a junction FET and a MOSFET are arranged on a SiC substrate, and the MOSFET is diode-connected to a gate electrode of the junction FET.

Documents of the prior art

Patent document

Patent document 1: japanese Kohyo publication No. 2000-506313

Patent document 2: japanese laid-open patent publication No. 2008-198735

Patent document 3: japanese laid-open patent publication No. 2002-208673

Patent document 4: japanese patent application laid-open No. 2010-206100

Disclosure of Invention

As a switching element that achieves both an improvement in withstand voltage and a reduction in on-resistance, there is a switching element using a cascade connection method. The switching element using the cascade connection method is, for example, a structure in which a normally-open junction fet (junction Field Effect transistor) using a material having a larger band gap (band gap) than silicon (Si) and a normally-closed mosfet (metal Oxide Semiconductor Field Effect transistor) using silicon (Si) are connected in series. According to the switching element of the cascade connection type, the withstand voltage can be secured by the junction FET having a large withstand voltage, and the on-resistance can be reduced by the normally-open junction FET and the on-resistance can be reduced by the MOSFET having a low withstand voltage, whereby the switching element having both the improvement of the withstand voltage and the reduction of the on-resistance can be obtained.

In the mounting structure of the switching element formed by the cascade connection, a structure is adopted in which a semiconductor chip on which a junction FET is formed and a semiconductor chip on which a MOSFET is formed are connected by a bonding wire. The present inventors have newly found that, in the case of this structure, a voltage having a magnitude equal to or higher than a designed breakdown voltage is applied between the source and the drain of the low-breakdown-voltage MOSFET during switching due to the influence of parasitic inductance existing in the bonding wire and the influence of leakage current of the junction FET. As such, when a voltage higher than a designed withstand voltage is applied to a MOSFET having a low withstand voltage, the MOSFET may be broken down, resulting in a decrease in reliability of the semiconductor device.

The invention aims to provide a technology capable of improving the reliability of a semiconductor device.

The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

A summary of representative embodiments of the invention disclosed in the present application is described below.

A semiconductor device according to one embodiment is characterized in that a gate pad of a semiconductor chip in which a junction FET is formed is arranged closer to a source lead than to other leads (a gate lead and a drain lead).

Effects of the invention

The effects obtained by the typical embodiments of the invention disclosed in the present application will be briefly described as follows.

According to one embodiment, reliability of a semiconductor device can be improved. In addition, the electrical characteristics of the semiconductor device can be improved.

Drawings

Fig. 1 is a circuit configuration diagram showing a switching element using a cascade connection method.

Fig. 2 (a) is a circuit diagram showing an inverter using a junction FET and a MOSFET connected in cascade as switching elements. Fig. 2 (b) is a diagram showing a waveform when the switching element constituting the upper arm is turned on, and fig. 2 (c) is a diagram showing a waveform when the switching element constituting the upper arm is turned off.

Fig. 3 is a mounting structure diagram showing a semiconductor device according to embodiment 1 of the present invention.

Fig. 4 is a mounting configuration diagram showing another semiconductor device according to embodiment 1.

Fig. 5 is a mounting configuration diagram showing a semiconductor device according to modification 1.

Fig. 6 is a mounting configuration diagram showing another semiconductor device according to modification 1.

Fig. 7 is a mounting configuration diagram showing another semiconductor device according to modification 1.

Fig. 8 is a sectional view showing a section of fig. 7.

Fig. 9 is a mounting configuration diagram showing another semiconductor device according to modification 1.

Fig. 10 is a sectional view showing a section of fig. 9.

Fig. 11 is a mounting configuration diagram showing another semiconductor device according to modification 1.

Fig. 12 (a) is a circuit diagram showing the positions of the switching elements and parasitic inductances according to the prior art, and fig. 12 (b) is a circuit diagram showing the positions of the switching elements and parasitic inductances according to embodiment 1. Fig. 12 (c) is a circuit diagram showing the positions of the switching elements and the parasitic inductances in modification 1.

Fig. 13 is a mounting structure diagram showing a semiconductor device according to modification 2.

Fig. 14 is a sectional view showing one section of fig. 13.

Fig. 15 is a mounting structure diagram showing another semiconductor device according to modification 2.

Fig. 16 is a sectional view showing a section of fig. 15.

Fig. 17 is a mounting structure diagram showing a semiconductor device according to modification 3.

Fig. 18 is a sectional view showing a section of fig. 17.

Fig. 19 is a mounting configuration diagram showing another semiconductor device according to modification 3.

Fig. 20 is a sectional view showing a section of fig. 19.

Fig. 21 is a mounting structure diagram showing a semiconductor device according to modification 4.

Fig. 22 is a sectional view showing a section of fig. 21.

Fig. 23 is a mounting configuration diagram showing another semiconductor device according to modification 4.

Fig. 24 is a sectional view showing a section of fig. 23.

Fig. 25 is a structural diagram showing a stacked semiconductor chip of embodiment 2.

Fig. 26 is a diagram showing another structure of the stacked semiconductor chip according to embodiment 2.

Fig. 27 is a sectional view taken along line a-a of fig. 25 and 26.

Fig. 28 is a structural diagram showing a laminated semiconductor chip according to a modification.

Fig. 29 is a diagram showing another structure of a laminated semiconductor chip according to a modification.

Fig. 30 is a sectional view taken along line a-a of fig. 28 and 29.

Fig. 31 is a cross-sectional view showing a device structure of a MOSFET of embodiment 2.

Fig. 32 is a diagram showing current paths in switching elements connected in cascade. Fig. 32 (a) is a diagram showing a current path at the time of on-state, and fig. 32 (b) is a diagram showing a current path of a leakage current flowing at the time of off-state.

Fig. 33 is a cross-sectional view showing the device structure of the junction FET in embodiment 2.

Fig. 34 is a cross-sectional view showing another device structure of the junction FET in embodiment 2.

Detailed Description

In the following embodiments, the description will be given in terms of a plurality of parts or embodiments as necessary for the sake of convenience, but unless otherwise stated, there is no relationship between them, and some or all of the modifications, details, supplementary descriptions, and the like, in which one is the other, are described.

In the following embodiments, when the number of elements or the like (including the number, numerical value, amount, range, and the like) is referred to, the number is not limited to the specific number, and may be equal to or greater than the specific number or equal to or less than the specific number, unless otherwise explicitly stated or clearly limited to the specific number in principle.

In the following embodiments, it goes without saying that the constituent elements (including element steps) are not necessarily essential unless explicitly stated otherwise or if they are considered to be clearly essential in principle.

Similarly, in the following embodiments, the shapes, positional relationships, and the like of the components and the like include those substantially similar to or similar to the shapes and the like thereof, unless otherwise stated or assumed to be clearly not satisfied in principle. In this regard, the same applies to the above-mentioned numerical values and ranges.

In all the drawings for describing the embodiments, the same components are denoted by the same reference numerals in principle, and redundant description thereof will be omitted. In addition, hatching is also marked in the top view for ease of understanding of the drawings.

(embodiment mode 1)

< details of the technical problem found by the present inventors >

In a large social trend of protecting the global environment, electronic industry for reducing the environmental load is increasingly important. Among them, power devices (power semiconductor devices) are used for power sources of railway vehicles, hybrid cars, inverters of electric cars or inverters of air conditioners, computers, and other consumer appliances, and performance improvement of power devices is greatly helpful for improvement of electric power efficiency of basic systems and consumer appliances. The improvement of the power efficiency means that energy resources required for the system operation, in other words, the emission amount of carbon dioxide can be reduced, that is, the environmental load can be reduced. Therefore, research and development for improving the performance of power devices are prevalent in various companies.

In general, a power device is made of silicon as in a large Scale integration (lsi), but in recent years, silicon carbide (SiC) having a larger band gap than silicon has attracted attention, and since SiC has a larger band gap, the breakdown voltage is about 10 times that of silicon²) It is possible to greatly contribute to improvement of power efficiency. In view of such characteristics, development of MOSFETs, schottky diodes, and junction FETs using SiC is progressing at home and abroad.

In particular, junction fets (jfets) made of SiC have been rapidly produced in the field of switching devices. In this junction FET, compared with a MOSFET using SiC as a material, for example, a gate insulating film made of a silicon oxide film is not required, and therefore defects at the interface between the silicon oxide film and SiC and the deterioration of device characteristics due to the defects can be avoided. In addition, since this junction FET can control the on/off of the channel by controlling the growth of the depletion layer of the pn junction, it is possible to easily separately fabricate a normally-off junction FET and a normally-on junction FET. As described above, the junction FET using SiC as a material is superior to the MOSFET using SiC as a material in terms of long-term reliability, and has a feature that the device is easily manufactured.

In a junction FET using SiC as a material, a normally-open junction FET normally turns on a channel to flow a current, and when it is necessary to turn off the channel, a negative voltage is applied to a gate electrode to grow a depletion layer from a pn junction to turn off the channel. Thus, in the case where the junction FET is destroyed for some reason, the channel is in the on state and current continues to flow. In general, from the viewpoint of safety (fail safe), it is desirable not to flow a current when a junction FET is destroyed, but in a normally-open junction FET, a current continues to flow even when the junction FET is destroyed, and thus the application is limited. Therefore, from the viewpoint of fault protection, a normally-off junction FET is desired.

However, the normally-off junction FET has the following technical problem. That is, since the gate electrode and the source region of the junction FET have a pn junction diode structure including a p-type semiconductor region (gate electrode) and an n-type semiconductor region (source region), respectively, when the voltage between the gate electrode and the source region is about 3V, the parasitic diode between the gate electrode and the source region is turned on. As a result, a large current may flow between the gate electrode and the source region, which may cause the junction FET to generate heat excessively and break down. From this, it is found that in order to use the junction FET as a normally-off switching element, it is desirable to limit the gate voltage to a low voltage of about 2.5V and use the junction FET in a state where a parasitic diode is not turned on or in a state where a diode current between the gate electrode and the source region is sufficiently small. In addition, in a general MOSFET using Si as a material, a gate voltage of about 0 to 15V or 20V is applied. Therefore, in order to use the normally-off junction FET, it is necessary to add a step-down circuit (DC/DC converter) that generates a voltage of about 2.5V, a level conversion circuit, and the like to the gate driver circuit of the conventional MOSFET. This design change, i.e., addition of components, leads to an increase in the cost of the entire system. As described above, although the junction FET is excellent in long-term reliability and is easy to manufacture, since the gate voltage for driving is significantly different from that of a general MOSFET, when the junction FET is newly used, a large design change including a driving circuit and the like is required, and thus there is a technical problem in that the cost of the entire system increases.

As a method for solving the technical problem, there is a cascade connection system. The cascade connection system is a system in which a normally-open junction FET made of SiC and a low-voltage MOSFET made of Si are connected in series. When such a connection method is adopted, the gate drive circuit drives the low withstand voltage MOSFET, and therefore, the gate drive circuit does not need to be changed. On the other hand, the withstand voltage between the drain and the source can be determined by the characteristics of the junction FET having a high withstand voltage. In addition, when the cascade connection is performed, since the low on-resistance of the junction FET and the low on-resistance of the low-voltage MOSFET are connected in series, the on-resistance of the switching element formed by the cascade connection can be suppressed to be small. As described above, the cascade connection method has a possibility of solving the problem of the normally-off junction FET.

Fig. 1 is a circuit configuration diagram showing a switching element using a cascade connection method. As shown in fig. 1, the switching element using the cascade connection method has a structure in which a normally-open junction fet q1 and a normally-closed mosfet q2 are connected in series between a source S and a drain D. Specifically, a junction fet q1 is disposed on the drain D side, and a mosfet q2 is disposed on the source S side. That is, the source Sj of the junction fet q1 is connected to the drain Dm of the mosfet q2, and the source Sm of the mosfet q2 is connected to the source S of the switching element. The gate electrode Gj of the junction fet q1 is connected to the source S of the switching element, and the gate electrode Gm of the mosfet q2 is connected to a gate driver circuit (not shown).

As shown in fig. 1, a freewheeling diode is connected in anti-parallel with the mosfet q 2. The free wheel diode has a function of circulating a reverse current and discharging energy stored in the inductor. That is, when the switching element shown in fig. 1 is connected to a load including an inductor, when the switching element is turned off, a reverse current in a direction opposite to a current flowing direction of the mosfet q2 is generated due to the inductor included in the load. As can be seen from this, by providing a freewheeling diode in anti-parallel with the mosfet q2, the energy stored in the inductor is released by circulating the reverse current.

Such a connection method is a cascade connection method, and since the gate driving circuit (not shown) first drives the gate electrode Gm of the mosfet q2 according to the switching element using the cascade connection method, there are the following advantages: there is no need to change the gate drive circuit based on the use of the MOSFET cells as the switching elements.

Further, since the junction type fet q1 uses a material typified by silicon carbide (SiC) having a larger band gap than silicon (Si), the junction type fet q1 has a larger dielectric breakdown voltage. From this, it is understood that the breakdown voltage of the switching element formed by cascade connection is mainly determined by the characteristics of the junction type fet q 1. Therefore, the insulation withstand voltage required for the MOSFET q2 connected in series to the junction fet q1 can be made lower than that of a switching element using a MOSFET alone. That is, even when an insulation breakdown voltage is required as a switching element, a MOSFET having a low breakdown voltage (for example, about several tens of V) can be used as the MOSFET q 2. Therefore, the on-resistance of the mosfet q2 can be reduced. Further, since the junction FET q1 is formed of a normally-open junction FET, the on-resistance of the junction FET q1 can be reduced. As a result, the switching element formed by cascade bonding has an advantage that a design change of the gate driver circuit is not required, and the insulation resistance can be ensured and the on-resistance can be reduced at the same time, whereby the electrical characteristics of the semiconductor element (switching element) can be improved.

As shown in fig. 1, the junction fet q1 connected in cascade is a normally-open junction fet q1, and the gate electrode Gj of the junction fet q1 is electrically connected to the source S of the switching element. As a result, the voltage between the gate electrode Gj and the source S of the junction fet q1 is not forward biased even at the time of switching (at the time of conduction). As a result, since a large current does not flow through the parasitic diode of the junction fet q1 in the cascade connection, it is possible to suppress the switching element from breaking down due to excessive heat generation. That is, in the normally-off junction FET, a positive voltage is applied to the gate electrode Gj with respect to the source S at the time of switching (on). At this time, since the source region of the junction type fet q1 is formed of an n-type semiconductor region and the gate electrode Gj is formed of a p-type semiconductor region, applying a positive voltage to the gate electrode Gj with respect to the source S means applying a forward voltage (forward bias) between the source region and the gate electrode Gj. Therefore, in the normally-off junction FET, if the forward voltage is excessively increased, a parasitic diode including the source region and the gate electrode Gj is turned on. As a result, a large current may flow between the gate electrode Gj and the source region, and the junction FET may generate heat excessively and break. In contrast, in the switching element formed by cascade connection, a normally-open junction fet q1 is used, and the gate electrode Gj is electrically connected to the source S of the switching element. From this, it is understood that the voltage between the gate electrode Gj and the source S of the junction fet q1 is not forward biased even at the time of switching (at the time of conduction). Therefore, since a large current does not flow through the parasitic diode of the junction type fet q1 in the cascade connection, it is possible to suppress the switching element from breaking down due to excessive heat generation.

As described above, the switching elements formed by cascade connection have the above-described various advantages, but as a result of the study by the present inventors, the following technical problems have been newly found. That is, in order to realize the cascade connection, it is necessary to connect the semiconductor chip on which the junction type fet q1 is formed and the semiconductor chip on which the low withstand voltage mosfet q2 is formed with bonding wires. Thus, for example, the drain Dm of the low voltage mosfet q2 and the source Sj of the junction fet q1 are connected via a bonding wire. In this case, the present inventors newly found that parasitic inductance due to the bonding wire is added to the source Sj of the junction fet q 1. When such a parasitic inductance is added, a large surge voltage is generated at the time of switching, and thus a voltage equal to or higher than the withstand voltage is applied to the low-withstand-voltage mosfet q 2. As a result, the low-withstand-voltage mosfet q2 operates in an avalanche mode, and a large current that cannot be controlled by the gate electrode Gm flows through the low-withstand-voltage mosfet q2, which may cause element breakdown. The mechanism is explained in detail below.

< mechanism for generating technical problem >

Fig. 2 (a) is a circuit diagram showing an inverter using a junction FET and a MOSFET connected in cascade as switching elements. The inverter shown in fig. 2 (a) has an upper arm and a lower arm connected in series to a power source VCC. The upper branch is constituted by a switching element connected between the drain D1 and the source S1. The switching element constituting the upper arm is constituted by a junction type fet q1a and a mosfet q2a connected in cascade. Specifically, the drain Dj1 of the junction type fet q1a is connected to the drain D1 of the switching element, and the source Sj1 of the junction type fet q1a is connected to the drain Dm1 of the mosfet q2 a. The source Sm1 of the mosfet q2a is connected to the source S1 of the switching element. The gate electrode Gj1 of the junction fet q1a is connected to the source S1 of the switching element, and a gate driver circuit (G/D) is connected between the gate electrode Gm1 of the mosfet q2a and the source S1 of the switching element.

Here, a parasitic inductance Lse1 by a bonding wire exists between the source Sj1 of the junction type fet q1a and the drain Dm1 of the mosfet q2a, and a parasitic inductance Lgi1 by a bonding wire exists between the gate electrode Gj1 of the junction type fet q1a and the source S1 of the switching element. In fig. 2 (a), a voltage between the source S1 of the switching element and the drain D1 of the switching element is defined as a voltage Vdsu, and a voltage between the source S1 of the switching element and the drain Dm1 of the mosfet q2a is defined as a voltage Vdsmu.

Similarly, as shown in fig. 2 (a), the lower branch is formed of a switching element connected between the drain D2 and the source S2. The switching element constituting the lower arm is composed of a junction type fet q1b and a mosfet q2b connected in cascade. Specifically, the drain Dj2 of the junction type fet q1b is connected to the drain D2 of the switching element, and the source Sj2 of the junction type fet q1b is connected to the drain Dm2 of the mosfet q2 b. The source Sm2 of the mosfet q2b is connected to the source S2 of the switching element. The gate electrode Gj2 of the junction fet q1b is connected to the source S2 of the switching element, and a gate driver circuit (G/D) is connected between the gate electrode Gm2 of the mosfet q2b and the source S2 of the switching element. A load inductor LL is connected between the source S2 of the switching element and the drain D2 of the switching element.

Here, a parasitic inductance Lse2 by a bonding wire exists between the source Sj2 of the junction type fet q1b and the drain Dm2 of the mosfet q2b, and a parasitic inductance Lgi2 by a bonding wire exists between the gate electrode Gj2 of the junction type fet q1b and the source S2 of the switching element. In fig. 2 (a), a voltage between the source S2 of the switching element and the drain D2 of the switching element is defined as a voltage Vak, and a voltage between the source S2 of the switching element and the drain Dm2 of the mosfet q2b is defined as a voltage Vdsmd.

The inverter using the switching elements connected in cascade is configured as described above, and the mechanism of occurrence of the technical problem will be described below while describing the operation of the inverter. First, a case where the switching element constituting the upper arm is turned on will be described. That is, a case will be described in which the power supply voltage is applied to the load (including the load inductance) by turning on the switching element constituting the upper arm and turning off the switching element constituting the lower arm.

Fig. 2 (b) shows waveforms in the case where the switching element constituting the upper arm is turned on. Specifically, when the switching element constituting the upper arm is turned on, the junction type fet q1a and mosfet q2a constituting the upper arm are turned on, and therefore, a return current flows through a path from the drain Dj1 of the junction type fet q1a, through the drain Dm1 and the source Sm1 of the mosfet q2a, and back to the power supply VCC via the load inductor LL. At this time, as shown in fig. 2 (b), the voltage Vdsmu changes from a predetermined voltage to about 0V, while the voltage Vak increases from 0V at the time of turning off the switching element of the upper arm to a voltage about the power supply voltage. As a result, the voltage Vdsmd, which is the drain voltage of the mosfet q2b in the lower arm, rises to a voltage that turns off the junction fet q1b in the lower arm, and maintains a constant voltage after the junction fet q1b in the lower arm turns off. The variation in the voltage Vdsmd is a variation in an ideal state in which the parasitic inductance can be ignored, as shown by the broken line in fig. 2 (b). However, when the parasitic inductance Lse2 or the parasitic inductance Lgi2 increases, the voltage Vdsmd sharply and significantly rises when the switching element of the upper arm is turned on, as shown by the solid line in fig. 2 (b).

On the other hand, fig. 2 (c) shows waveforms in the case where the switching element constituting the upper arm is turned off. Specifically, when the switching element constituting the upper arm is turned off, as shown in fig. 2 (c), the voltage Vdsmd changes from a predetermined voltage to about 0V, while the voltage Vdsu increases from 0V at the time of turning on the switching element of the upper arm to a voltage about the power supply voltage. As a result, the voltage Vdsmu, which is the drain voltage of the mosfet q2a in the upper arm, rises to a voltage that turns off the junction fet q1a in the upper arm, and maintains a constant voltage after the junction fet q1a in the upper arm turns off. The variation in the voltage Vdsmu is a variation in an ideal state in which the parasitic inductance can be ignored, as shown by a broken line in fig. 2 (c). However, when the parasitic inductance Lse1 or the parasitic inductance Lgi1 increases, the voltage Vdsmu sharply and significantly rises when the switching element of the upper arm is turned off, as shown by the solid line in fig. 2 (c).

As described above, it is understood that when the switching element of the upper arm is turned on, a phenomenon occurs in which the voltage Vdsmd, which is the drain voltage of the mosfet q2b of the lower arm that is turned off, sharply increases, and when the switching element of the upper arm is turned off, a phenomenon occurs in which the voltage Vdsmu, which is the drain voltage of the mosfet q2a of the upper arm that is turned off, sharply increases. Since these phenomena occur in the same mechanism, the mechanism of occurrence of the phenomenon in which the voltage Vdsmd, which is the drain voltage of the mosfet q2b in the lower arm that is turned off, rises sharply will be described below focusing on the case where the switching element in the upper arm is turned on. As the mechanism of occurrence of this phenomenon, three mechanisms shown below are considered.

The 1 st mechanism is that this phenomenon is caused by the parasitic inductance Lse2 existing between the source Sj2 of the junction type fet q1b constituting the lower arm and the drain Dm2 of the mosfet q2b constituting the lower arm. Specifically, when the switching element of the upper arm is turned on, the mosfet q2b of the lower arm is turned off. At this time, the voltage Vak starts to increase from about 0V, and the voltage Vdsmd, which is the drain voltage of the mosfet q2b in the lower arm, starts to increase as the voltage Vak increases. However, in the initial stage of the increase of the voltage Vdsmd, the voltage Vdsmd is not greater than the gate voltage applied to the gate electrode Gj2 of the junction type fet q1b by a predetermined value or more, and therefore the junction type fet q1b is not turned off, and a current flows from the drain Dj2 to the source Sj2 of the junction type fet q1 b. As a result, a current flows into the drain Dm2 of the mosfet q2b, and electric charges are accumulated. From this, it is understood that the voltage Vdsmd, which is the drain voltage of the mosfet q2b, rises. When the voltage Vdsmd continues to rise and becomes greater than the gate voltage of junction fet q1b by a predetermined value or more, junction fet q1b is turned off and no further current flows. That is, in the initial stage of the increase of the voltage Vdsmd, a current flows between the drain Dj2 and the source Sj2 of the junction type fet q1b, and charges are accumulated in the drain Dm2 of the mosfet q2b, so that the voltage Vdsmd increases. Then, as the voltage Vdsmd increases, the voltage Vdsmd approaches a state where the voltage Vdsmd is larger than the gate voltage of the junction type fet q1b by a predetermined value or more, and thus the current flowing through the drain Dj2 and the source Sj2 of the junction type fet q1b gradually decreases. Finally, voltage Vdsmd is greater than the gate voltage of junction fet q1b by a predetermined value or more, and junction fet q1b is turned off. After the junction fet q1b turns off, no charge flows into the drain Dm2 of mosfet q2b and the voltage Vdsmd is substantially constant.

In this way, when the switching element of the upper arm is turned on, mosfet q2b of the lower arm is turned off, but at this stage, junction type fet q1b of the lower arm is not immediately turned off, and a current flows from drain Dj2 to source Sj2 of junction type fet q1 b. The current flowing into the source Sj2 of the junction fet q1b flows into the drain Dm2 of the mosfet q2b via the parasitic inductor Lse 2. At this time, the point is that the current flowing from the drain Dj2 of the junction type fet q1b of the lower arm to the source Sj2 decreases. Which means that the current flowing to the parasitic inductance Lse2 also decreases with time. As a result, an electromotive force that cancels the current reduction is generated in the parasitic inductance Lse 2. That is, the parasitic inductance Lse2 functions to increase the current flowing from the drain Dj2 to the source Sj2 of the junction type fet q1 b. Therefore, when the parasitic inductance Lse2 increases, a large current transiently flows from the drain Dj2 to the source Sj2 of the junction fet q1 b. As a result, the charge flowing into the drain Dm2 of the mosfet q2b increases rapidly, and the voltage Vdsmd increases rapidly. Which is the 1 st mechanism.

Next, the 2 nd mechanism is that this phenomenon is caused by a parasitic inductance Lgi2 existing between the gate electrode Gj2 of the junction type fet q1b constituting the lower arm and the source S2 of the lower arm. Specifically, when the switching element of the upper arm is turned on, the mosfet q2b of the lower arm is turned off. At this time, the voltage Vak increases from about 0V, but, for example, as shown in fig. 2 (b), the voltage Vak oscillates in a range exceeding the power supply voltage at the initial stage of turning on the switching element of the upper arm. Based on the back emf caused by the load inductance LL comprised by the load connected to the inverter. Therefore, the voltage Vak fluctuates in an initial stage when the upper arm is turned on. Here, focusing on the junction type fet q1b, a parasitic capacitance is formed between the drain Dj2 and the gate electrode Gj2 of the junction type fet q1b, and when the voltage Vak fluctuates, the voltage applied to the parasitic capacitance also fluctuates. Further, since the capacitance value of the parasitic capacitance is relatively large, the charge/discharge current generated in accordance with the voltage variation applied to the parasitic capacitance also increases. The charge/discharge current flows between the gate electrode Gj2 of the junction type fet q1b and the source S2 of the lower arm. At this time, the charge/discharge current is a time-varying current. Therefore, for example, when there is a parasitic inductance Lgi2 between the gate electrode Gj2 of the junction type fet q1b and the source S2 of the lower arm, since a charge/discharge current that changes with time flows through the parasitic inductance Lgi2, a resistance component proportional to the product of the magnitude of the parasitic inductance Lgi2 and the time differential of the charge/discharge current is generated between the gate electrode Gj2 of the junction type fet q1b and the source S2 of the lower arm. As a result, the gate electrode Gj2 of the junction type fet q1b and the source S2 of the lower arm are not at the same potential, and a pattern occurs in which the gate electrode Gj2 of the junction type fet q1b rises in the positive voltage direction with respect to the source S2 of the lower arm. In this case, since the gate electrode Gj2 of the junction type fet q1b becomes a positive voltage, a depletion layer grown from the gate electrode Gj2 of the junction type fet q1b is suppressed, and the width of the channel region increases. Therefore, the current flowing from the drain Dj2 to the source Sj2 of the junction type fet q1b transiently increases. As a result, the charge flowing into the drain Dm2 of the mosfet q2b increases rapidly, and the voltage Vdsmd increases rapidly. Which is the 2 nd mechanism. In the 2 nd mechanism, a positive voltage is applied to the gate electrode Gj2 of the junction type fet q1b, and therefore, in order to turn off the junction type fet q1b, a voltage larger than that in the case where 0V is applied to the source Sj2 of the junction type fet q1b must be applied to the gate electrode Gj 2. From this point of view, the voltage Vdsmd that rises before the junction type fet q1b turns off also increases.

The 3 rd mechanism is that this phenomenon is caused by parasitic resistance existing between the gate electrode Gj2 of the junction type fet q1b constituting the lower arm and the source S2 of the lower arm. As described in the mechanism 2, a charge/discharge current flows between the gate electrode Gj2 of the junction type fet q1b and the source S2 of the lower arm. From this, it is found that, when a parasitic resistance exists between the gate electrode Gj2 of the junction type fet q1b and the source S2 of the lower arm, a charge/discharge current flows through the parasitic resistance, and a voltage drop occurs. As a result, the gate electrode Gj2 of the junction type fet q1b and the source S2 of the lower arm are not at the same potential, and a pattern occurs in which the gate electrode Gj2 of the junction type fet q1b rises in the positive voltage direction with respect to the source S2 of the lower arm. Thus, in the 3 rd mechanism, as in the 2 nd mechanism, the gate electrode Gj2 of the junction type fet q1b becomes a positive voltage, and therefore, a depletion layer growing from the gate electrode Gj2 of the junction type fet q1b is also suppressed, and the width of the channel region increases. Therefore, the current flowing from the drain Dj2 to the source Sj2 of the junction type fet q1b transiently increases. As a result, the charge flowing into the drain Dm2 of the mosfet q2b increases rapidly, and the voltage Vdsmd increases rapidly.

As described above, the voltage Vdsmd is found to increase rapidly by the 1 st to 3 rd mechanisms relating to the parasitic inductance Lse2, the parasitic inductance Lgi2, and the parasitic resistance. As described above, when the parasitic inductance Lse2, the parasitic inductance Lgi2, and the parasitic resistance increase, the voltage Vdsmd, which is the drain voltage of the mosfet q2b of the lower arm, increases to a voltage equal to or higher than the withstand voltage of the mosfet q2b, whereby the mosfet q2b of the lower arm performs an avalanche operation, and eventually, the mosfet q2b of the lower arm may break down.

Specifically, when a voltage equal to or higher than a withstand voltage is applied to the mosfet q2b, a region where an electric field is concentrated is locally generated in the mosfet q2b, and a large number of hole-electron pairs are generated in the region by impact ionization. The parasitic npn bipolar transistor formed by the source region (n-type semiconductor region), the channel formation region (p-type semiconductor region), and the drift region (n-type semiconductor region) is turned on by the pair of holes and electrons generated in large quantities. In the cell (mosfet q2 b) in which the parasitic npn bipolar transistor is on, heat is generated by a large current that cannot be controlled by the gate electrode Gm2 of the mosfet q2 b. At this time, the temperature rises due to heat generation, and the resistance of the semiconductor region decreases, thereby causing positive feedback in which a larger current flows. As a result, a large current flows locally, and the mosfet q2b breaks down. This phenomenon is avalanche breakdown. When such avalanche breakdown occurs, reliability of the semiconductor device is lowered.

Therefore, in embodiment 1, in order to suppress application of a voltage higher than or equal to the dielectric breakdown voltage, which causes avalanche breakdown, to the MOSFET, studies have been made to reduce parasitic inductance and parasitic resistance. The technical idea of embodiment 1 for carrying out this study will be described below. In embodiment 1, the mounting structure of a semiconductor device is considered to have a characteristic feature, and the mounting structure of a semiconductor device including the characteristic feature will be described.

< mounting structure of semiconductor device in embodiment 1 >

Fig. 3 is a mounting configuration diagram showing a package (semiconductor device) PKG1 according to embodiment 1. As shown in fig. 3, the package PKG1 of embodiment 1 includes two chip mounting portions PLT1 and PLT2 electrically insulated from each other. In fig. 3, the metal plate disposed on the right side constitutes a chip mounting portion PLT1, and the metal plate disposed on the left side constitutes a chip mounting portion PLT 2. The chip mounting portion PLT1 is integrally formed so as to be connected to the drain lead DL, and the chip mounting portion PLT1 and the drain lead DL are electrically connected. Further, a source lead SL and a gate lead GL are disposed so as to be separated from each other with the drain lead DL interposed therebetween. Specifically, as shown in fig. 3, a source lead SL is disposed on the right side of a drain lead DL, and a gate lead GL is disposed on the left side of the drain lead DL. These drain lead DL, source lead SL, and gate lead GL are electrically insulated from each other. Further, a source lead post SPST formed of a wide region is formed at the distal end of the source lead SL, and a gate lead post GPST formed of a wide region is formed at the distal end of the gate lead GL.

Next, the semiconductor chip CHP1 is mounted on the chip mounting portion PLT1 via a conductive adhesive material made of, for example, silver solder or solder. A junction FET made of SiC, for example, is formed on the semiconductor chip CHP 1. The back surface of the semiconductor chip CHP1 serves as a drain electrode, and a source pad SPj and a gate pad GPj are formed on the front surface (main surface) of the semiconductor chip CHP 1. That is, a junction FET constituting a part of the switching elements connected in cascade is formed on the semiconductor chip CHP1, a drain electrode electrically connected to the drain of the junction FET is formed on the back surface of the semiconductor chip CHP1, and a source pad SPj electrically connected to the source of the junction FET and a gate pad GPj electrically connected to the gate electrode of the junction FET are formed on the front surface of the semiconductor chip CHP 1.

Next, the semiconductor chip CHP2 is mounted on the chip mounting portion PLT2 via a conductive adhesive material made of, for example, silver solder or solder. A MOSFET made of Si, for example, is formed on the semiconductor chip CHP 2. At this time, the back surface of the semiconductor chip CHP2 serves as a drain electrode, and the source pad SPm and the gate pad GPm are formed on the front surface (main surface) of the semiconductor chip CHP 2. That is, a MOSFET constituting a part of the switching elements connected in cascade connection is formed on the semiconductor chip CHP2, a drain electrode electrically connected to the drain of the MOSFET is formed on the rear surface of the semiconductor chip CHP2, and a source pad SPm electrically connected to the source of the MOSFET and a gate pad GPm electrically connected to the gate electrode of the MOSFET are formed on the front surface of the semiconductor chip CHP 2.

The semiconductor chip CHP1 mounted on the chip mounting portion PLT1 and the semiconductor chip CHP2 mounted on the chip mounting portion PLT2 are connected by a bonding wire, whereby a switching element connected in cascade can be configured. Specifically, as shown in fig. 3, the gate pad GPj formed on the surface of the semiconductor chip CHP1 and the source lead post SPST formed at the tip of the source lead SL are electrically connected to each other by a wire Wgj. The source pad SPj formed on the surface of the semiconductor chip CHP1 and the chip mounting portion PLT2 are electrically connected by a wire Wds. The source pad SPm formed on the surface of the semiconductor chip CHP2 and the source lead post SPST formed at the tip of the source lead SL are electrically connected to each other by the wire Wsm. The gate pad GPm formed on the surface of the semiconductor chip CHP2 and the gate lead post GPST formed at the distal end of the gate lead GL are electrically connected to each other by a wire Wgm. Here, the region of source pin portion SPST to which lead Wgj and lead Wsm are connected and the region of gate pin portion GPST to which lead Wgm is connected are located higher than the upper surface of chip mounting portion PLT1 and the upper surface of chip mounting portion PLT 2.

Since the semiconductor chip CHP1 is mounted on the chip mounting portion PLT1 via a conductive adhesive, the drain electrode formed on the back surface of the semiconductor chip CHP1 is electrically connected to the chip mounting portion PLT 1. Since the semiconductor chip CHP2 is mounted on the chip mounting portion PLT2 via a conductive adhesive, the drain electrode formed on the back surface of the semiconductor chip CHP2 is electrically connected to the chip mounting portion PLT 2.

In the package PKG1 configured as described above, at least the semiconductor chip CHP1, the semiconductor chip CHP2, a part of the chip mounting portion PLT1, a part of the chip mounting portion PLT2, a part of the drain lead DL, a part of the source lead SL, a part of the gate lead GL, and the wires Wgj, Wds, Wgm, Wsm are sealed by a sealing material. Therefore, a part of the solid sealing body is disposed between the chip mounting portion PLT1 and the chip mounting portion PLT2, and thus the chip mounting portion PLT1 and the chip mounting portion PLT2 are electrically insulated by the solid sealing body. The lower surface of chip mounting portion PLT1 and the lower surface of chip mounting portion PLT2 may be exposed from the sealing body. In this case, the heat generated by the semiconductor chip CHP1 and the semiconductor chip CHP2 can be efficiently dissipated from the lower surface of the chip mounting portion PLT1 and the lower surface of the chip mounting portion PLT 2.

The sealing member has, for example, a rectangular parallelepiped shape and has a 1 st side surface and a 2 nd side surface opposite to the 1 st side surface. In this case, for example, a part of the drain lead DL, a part of the source lead SL, and a part of the gate lead GL protrude from the 1 st side surface of the solid sealing body. These protruding drain lead DL, source lead SL, and gate lead GL function as external connection terminals.

Here, in the switching element formed by cascade connection, two semiconductor chips, i.e., the semiconductor chip CHP1 and the semiconductor chip CHP2, are mounted, and therefore, it is not possible to directly use a conventional general-purpose package having only one chip mounting portion in the package. For example, it is also considered that the junction FET formed on the semiconductor chip CHP1 and the MOSFET formed on the semiconductor chip CHP2 are used at a large rated current of several a or more, and have a so-called vertical structure having a drain electrode on the back surface of the semiconductor chip. In this case, in the switching element of the cascade connection method, the drain electrode formed on the back surface of the semiconductor chip CHP1 and the drain electrode formed on the back surface of the semiconductor chip CHP2 cannot be electrically connected. As described above, in the conventional general-purpose package having only one chip mounting portion in the package, when the semiconductor chip CHP1 and the semiconductor chip CHP2 are disposed on the one chip mounting portion, the drain electrode formed on the back surface of the semiconductor chip CHP1 and the drain electrode formed on the back surface of the semiconductor chip CHP2 are electrically connected to each other, and thus the cascade connection method cannot be realized.

Therefore, in embodiment 1, as shown in fig. 3, the package PKG1 is configured such that two chip mounting portions PLT1 and PLT2 that are electrically insulated from each other are provided inside the package, on the premise that the external shape is the same as that of a general-purpose package. Then, the package PKG1 is configured such that the semiconductor chip CHP1 is mounted on the chip mounting portion PLT1 and the semiconductor chip CHP2 is mounted on the chip mounting portion PLT 2. That is, two electrically insulated chip mounting portions PLT1 and PLT2 are provided in the package PKG1, the semiconductor chip CHP1 and the semiconductor chip CHP2 are arranged in a planar manner, and the semiconductor chip CHP1 and the semiconductor chip CHP2 arranged in a planar manner are connected by a wire, whereby cascade connection is realized.

Therefore, according to the package PKG1 of embodiment 1, for example, an existing general-purpose package mounted with a switching element used in a power supply circuit or the like can be replaced with the package PKG1 of embodiment 1 having the same outer dimensions. In particular, according to the package PKG1 of embodiment 1, since the arrangement of the drain lead DL, the source lead SL, and the gate lead GL is the same as that of a general-purpose package, the general-purpose package can be replaced with the package PKG1 of embodiment 1, and it is not necessary to change the design of other driver circuits, wirings of a printed circuit board, and the like. Therefore, according to embodiment 1, it is easy to change from a switching element using a general-purpose package to a switching element using a high-performance cascade connection method of the package PKG1 of embodiment 1, and there is an advantage that a high-performance power supply system can be provided without a significant change in design.

Hereinafter, the feature of the encapsulation PKG1 according to embodiment 1 will be described. First, a first characteristic point of embodiment 1 is that, as shown in fig. 3, a gate pad GPj provided on a surface of a semiconductor chip CHP1 on which a junction FET is formed and a source lead SL are arranged as close as possible. Specifically, in embodiment 1, the chip mounting portion PLT1 on which the semiconductor chip CHP1 is mounted is disposed on the same side as the source lead SL with respect to the drain lead DL. This allows chip mounting portion PLT1 to approach source lead SL. This means that the semiconductor chip CHP1 mounted on the chip mounting portion PLT1 can be disposed close to the source lead SL. In embodiment 1, the semiconductor chip CHP1 mounted on the chip mounting portion PLT1 is not disposed at the center of the chip mounting portion PLT1, but the semiconductor chip CHP1 is disposed so as to be close to the side of the chip mounting portion PLT1 closest to the source lead SL. Thus, the semiconductor chip CHP1 can be disposed closest to the source lead SL. In embodiment 1, the semiconductor chip CHP1 is disposed as close as possible to the source lead SL, and the gate pad GPj formed on the surface of the semiconductor chip CHP1 is disposed close to the source lead SL. As described above, in embodiment 1, first, the chip mounting portion PLT1 mounted on the semiconductor chip CHP1 having the junction FET formed thereon is disposed at a position close to the source lead SL, and then the semiconductor chip CHP1 is mounted on a region close to the source lead SL in the internal region of the chip mounting portion PLT 1. In addition, in embodiment 1, the gate pad GPj formed on the surface of the semiconductor chip CHP1 is disposed so as to be close to the source lead SL. Thus, the gate pad GPj and the source lead SL formed on the surface of the semiconductor chip CHP1 are close to each other. In other words, in embodiment 1, the gate pad GPj formed on the surface of the semiconductor chip CHP1 is arranged closer to the source lead SL than the other leads (the drain lead DL and the gate lead GL). As a result, according to embodiment 1, the distance between gate pad GPj and source lead SL can be shortened, and therefore the length of wire Wgj connecting gate pad GPj and source lead SL can be shortened. In particular, in embodiment 1, since the lead Wgj is connected to the wide source post SPST that is present at the tip of the source lead SL near the gate pad GPj, the length of the lead Wgj can be further reduced. Being able to shorten the length of the wire Wgj means that the parasitic inductance (Lgi 1 and Lgi2 of fig. 2) present at the wire Wgj can be reduced. That is, according to embodiment 1, the parasitic inductance existing in the lead Wgj can be sufficiently reduced. It is understood that the application of a voltage of a withstand voltage or higher to the MOSFET according to the above-described mechanism 2 can be suppressed, and thus the avalanche breakdown of the MOSFET connected in cascade can be effectively suppressed. As a result, according to embodiment 1, the reliability of the semiconductor device can be improved.

Next, the 2 nd characteristic point of embodiment 1 will be described. A 2 nd feature of embodiment 1 is that, as shown in fig. 3, the gate pad GPm provided on the surface of the semiconductor chip CHP2 on which the MOSFET is formed and the gate lead GL are arranged as close as possible. Specifically, in embodiment 1, the chip mounting portion PLT2 on which the semiconductor chip CHP2 is mounted is disposed on the same side as the drain lead DL on the side where the gate lead GL is disposed. This allows chip mounting portion PLT2 to approach gate lead GL. This means that the semiconductor chip CHP2 mounted on the chip mounting portion PLT2 can be disposed close to the gate lead GL. In embodiment 1, the semiconductor chip CHP2 mounted on the chip mounting portion PLT2 is not disposed at the center of the chip mounting portion PLT2, but the semiconductor chip CHP2 is disposed so as to be close to the side of the chip mounting portion PLT2 closest to the gate lead GL. Thus, the semiconductor chip CHP2 can be disposed closest to the gate lead GL. In embodiment 1, the semiconductor chip CHP2 is disposed as close as possible to the gate lead GL, and the gate pad GPm formed on the surface of the semiconductor chip CHP2 is disposed close to the gate lead GL. As described above, in embodiment 1, first, the chip mounting portion PLT2 mounted on the semiconductor chip CHP2 having the MOSFET formed thereon is disposed at a position close to the gate lead GL, and then the semiconductor chip CHP2 is mounted on a region close to the gate lead GL in the internal region of the chip mounting portion PLT 2. In addition, in embodiment 1, the gate pad GPm formed on the surface of the semiconductor chip CHP2 is disposed so as to be close to the gate lead GL. Thereby, the gate pad GPm and the gate lead GL formed on the surface of the semiconductor chip CHP2 are close to each other. In other words, in embodiment 1, the gate pad GPm formed on the surface of the semiconductor chip CHP2 is arranged closer to the gate lead GL than the other leads (the drain lead DL and the source lead SL). As a result, according to embodiment 1, the distance between the gate pad GPm and the gate lead GL can be shortened, and therefore, the length of the lead Wgm connecting the gate pad GPm and the gate lead GL can be shortened. In particular, in embodiment 1, since the lead Wgm is connected to the wide gate lead post GPST located at the tip of the gate lead GL near the gate pad GPm, the length of the lead Wgm can be further reduced. Thus, according to embodiment 1, parasitic inductance of lead Wgm can be reduced. The parasitic inductance of the lead Wgm can be reduced, which contributes to improvement of the electrical characteristics of the switching element formed by cascade connection, but is not directly related to suppression of application of a voltage equal to or higher than the dielectric strength to the MOSFET. According to the configuration of characteristic point 2 of embodiment 1, it is possible to suppress the application of a voltage equal to or higher than the dielectric breakdown voltage to the MOSFET not directly but indirectly.

This aspect is explained below. As shown in fig. 3, a second characteristic point of embodiment 1 is that the semiconductor chip CHP2 on which the MOSFET is formed is disposed as close as possible to the gate lead GL. This means that, as shown in fig. 3, the semiconductor chip CHP2 is disposed to be offset to the front side of the chip mounting portion PLT2, in other words, a large space in which the semiconductor chip CHP2 is not mounted can be formed inside the chip mounting portion PLT 2. As described above, embodiment 1 has an indirect feature in that a large space for mounting the semiconductor chip CHP2 can be secured in the chip mounting portion PLT 2. Specifically, according to this feature, as shown in fig. 3, it is possible to sufficiently secure a wire connection region for electrically connecting the source pad SPj formed on the surface of the semiconductor chip CHP1 mounted on the chip mounting portion PLT1 and the chip mounting portion PLT 2. As a result, as shown in fig. 3, the source pad SPj and the chip mounting portion PLT2 can be connected by the plurality of wires Wds. Here, since the chip mounting portion PLT2 is electrically connected to the drain electrode formed on the back surface of the mounted semiconductor chip CHP2, the drain of the MOSFET and the source of the junction FET can be connected by the plurality of wires Wds according to embodiment 1. This means that the parasitic inductance of the wire Wds connecting the drain of the MOSFET and the source of the junction FET (Lse 1, Lse2 of fig. 2) can be reduced. That is, according to embodiment 1, by using the plurality of wires Wds, parasitic inductance between the drain of the MOSFET and the source of the junction FET can be sufficiently reduced.

Further, as shown in fig. 3, it is desirable that the formation position of the source pad SPj formed on the surface of the semiconductor chip CHP1 is arranged as close as possible to the chip mounting portion PLT 2. This is because the length of the lead wire Wds connecting the source pad SPj and the chip mounted part PLT2 can be shortened as much as possible by disposing the source pad SPj in this manner. This also reduces parasitic inductance of the wire Wds (Lse 1 and Lse2 in fig. 2) connecting the drain of the MOSFET and the source of the junction FET.

As is apparent from the above description, according to the 2 nd feature of embodiment 1, it is possible to suppress application of a voltage equal to or higher than the dielectric breakdown voltage to the MOSFET by the 1 st mechanism, thereby effectively suppressing the avalanche breakdown of the MOSFET connected in cascade. As a result, according to embodiment 1, the reliability of the semiconductor device can be improved.

In embodiment 1, as shown in fig. 3, the gate pad GPj is electrically connected to the source lead SL by a lead Wgj, and the gate pad GPm is electrically connected to the gate lead GL by a lead Wgm. At this time, the thickness (width) of the conductive wire Wgj is desirably made thicker than the thickness (width) of the conductive wire Wgm. This is because, when the parasitic resistance existing in the wire Wgj increases, a voltage equal to or higher than the dielectric breakdown voltage is applied to the MOSFET according to the 3 rd mechanism. Therefore, from the viewpoint of reducing the parasitic resistance existing in the lead wire Wgj, it is desirable to adopt a structure in which the thickness of the lead wire Wgj is thicker than the other lead wires. Accordingly, since the parasitic resistance between the gate electrode of the junction FET and the source of the switching element (which may also be referred to as the source of the MOSFET) can be reduced, the application of a voltage higher than the dielectric breakdown voltage to the MOSFET according to the above-described mechanism 3 can be suppressed, and thus the avalanche breakdown of the MOSFET connected in cascade can be effectively suppressed. As a result, according to embodiment 1, the reliability of the semiconductor device can be improved.

Next, the 3 rd characteristic point of embodiment 1 will be explained. A 3 rd characteristic point of embodiment 1 is that, as shown in fig. 3, a source pad SPm provided on the surface of a semiconductor chip CHP2 on which a MOSFET is formed and a source lead SL (source lead post portion SPST) are connected to each other by a plurality of wires Wsm. This can reduce parasitic resistance and parasitic inductance between the source of the MOSFET and the source lead SL. As a result, the potential of the source of the MOSFET can be suppressed from varying from the GND potential (reference potential) supplied from the source lead SL, and the source of the MOSFET can be reliably fixed at the GND potential. In addition, since the parasitic resistance between the source of the MOSFET and the source lead SL is reduced, the on-resistance of the switching element formed by cascade connection can also be reduced. As described above, according to the 3 rd feature of embodiment 1, the electrical characteristics of the switching element formed by cascade connection in the package PKG1 can be improved.

As described above, according to the package PKG1 (semiconductor device) of embodiment 1, since the package PKG1 has the above-described 1 st and 2 nd characteristic points, it is possible to suppress application of a voltage equal to or higher than the dielectric breakdown voltage to the MOSFET, and thereby it is possible to effectively suppress avalanche breakdown of the MOSFET connected in cascade. As a result, the reliability of the semiconductor device can be improved. Further, since the package PKG1 (semiconductor device) according to embodiment 1 has the above-described feature point 3, parasitic resistance and parasitic inductance can be reduced, and thus, electrical characteristics of the semiconductor device can be improved.

As a specific effect of the package PKG1 according to embodiment 1, the package PKG1 according to embodiment 1 has a structure in which the semiconductor chip CHP1 on which the junction FET is formed and the semiconductor chip CHP2 on which the MOSFET is formed are arranged in a planar manner, so that the chip areas of the semiconductor chip CHP1 and the semiconductor chip CHP2 can be freely designed. It is thus understood that the design of low on-resistance and the design of on-current density are also facilitated, and switching elements of various specifications can be realized.

Next, an example of another mounting method of the switching element according to embodiment 1 will be described. Fig. 4 is a diagram showing an installation configuration of the package PKG2 according to embodiment 1. The package PKG2 shown in fig. 4 is different from the package PKG1 shown in fig. 3 in that the formation positions of the source lead SL and the drain lead DL are different. Specifically, in the package PKG1 shown in fig. 3, the gate lead GL is disposed on the leftmost side, the drain lead DL is disposed in the middle, and the source lead SL is disposed on the rightmost side. In contrast, in the package PKG2 shown in fig. 4, the gate lead GL is disposed on the leftmost side, the source lead SL is disposed at the center, and the drain lead DL is disposed on the rightmost side. In this case, as shown in fig. 4, as the position of the source lead SL is changed, the position of the gate pad GPj formed on the surface of the semiconductor chip CHP1 is also changed so as to be closer to the source lead SL than the other leads. As a result, in the package PKG2 shown in fig. 4, the distance between the gate pad GPj and the source lead SL can be shortened. Therefore, the length of the wire Wgj connecting the gate pad GPj and the source lead SL can be shortened. That is, in the package PKG2 shown in fig. 4, the parasitic inductance existing in the wire Wgj can be sufficiently reduced. It is understood that the application of a voltage of a withstand voltage or higher to the MOSFET according to the above-described mechanism 2 can be suppressed, and thus the avalanche breakdown of the MOSFET connected in cascade can be effectively suppressed. As a result, the package PKG2 shown in fig. 4 can also improve the reliability of the semiconductor device.

Further, as a characteristic point peculiar to the package PKG2 shown in fig. 4, the length of the wire Wsm electrically connecting the source pad SPm formed on the surface of the semiconductor chip CHP2 and the source lead SL can be sufficiently shortened as compared with the package PKG1 shown in fig. 3. Therefore, according to the package PKG2 shown in fig. 4, the parasitic resistance and parasitic inductance of the wire Wsm can be reduced, and therefore, the electrical characteristics of the switching element of embodiment 1 can be improved. In particular, the effect obtained by shortening the length of the conductive wire Wsm is remarkable in reducing the on-resistance of the switching element in embodiment 1.

< modification 1 >

Next, a mounting structure of the package PKG3 of modification example 1 will be described. In modification 1, a structure in which a semiconductor chip on which a junction FET is formed and a semiconductor chip on which a MOSFET is formed are stacked will be described.

Fig. 5 is a view showing an installation configuration of the package PKG3 according to modification 1. In fig. 5, the package PKG3 of modification example 1 includes a chip mounting portion PLT formed of a metal plate having a rectangular shape, for example. The chip mounting portion PLT is integrally formed to be connected to the drain lead DL, and the chip mounting portion PLT and the drain lead DL are electrically connected. Further, a source lead SL and a gate lead GL are disposed so as to be separated from each other with the drain lead DL interposed therebetween. Specifically, as shown in fig. 5, a source lead SL is disposed on the right side of a drain lead DL, and a gate lead GL is disposed on the left side of the drain lead DL. These drain lead DL, source lead SL, and gate lead GL are electrically insulated from each other. A source lead post SPST formed of a wide region is formed at the distal end of the source lead SL, and a gate lead post GPST formed of a wide region is formed at the distal end of the gate lead GL.

Next, the semiconductor chip CHP1 is mounted on the chip mounting portion PLT via a conductive adhesive material made of, for example, silver solder or solder. A junction FET made of SiC, for example, is formed on the semiconductor chip CHP 1. The back surface of the semiconductor chip CHP1 serves as a drain electrode, and a source pad SPj and a gate pad GPj are formed on the front surface (main surface) of the semiconductor chip CHP 1. That is, a junction FET constituting a part of the switching elements connected in cascade is formed on the semiconductor chip CHP1, a drain electrode electrically connected to the drain of the junction FET is formed on the back surface of the semiconductor chip CHP1, and a source pad SPj electrically connected to the source of the junction FET and a gate pad GPj electrically connected to the gate electrode of the junction FET are formed on the front surface of the semiconductor chip CHP 1.

Next, the semiconductor chip CHP2 is mounted on the semiconductor chip CHP1 via a conductive adhesive material made of, for example, silver solder or solder. A MOSFET made of Si, for example, is formed on the semiconductor chip CHP 2. At this time, the back surface of the semiconductor chip CHP2 serves as a drain electrode, and the source pad SPm and the gate pad GPm are formed on the front surface (main surface) of the semiconductor chip CHP 1. That is, a MOSFET constituting a part of the switching elements connected in cascade connection is formed on the semiconductor chip CHP2, a drain electrode electrically connected to the drain of the MOSFET is formed on the back surface of the semiconductor chip CHP2, and a source pad SPm electrically connected to the source of the MOSFET and a gate pad GPm electrically connected to the gate electrode of the MOSFET are formed on the front surface of the semiconductor chip CHP 2.

As described above, in modification 1, the semiconductor chip CHP2 is mounted on the semiconductor chip CHP1, and particularly, the semiconductor chip CHP2 is mounted on the source pad SPj formed on the surface of the semiconductor chip CHP 1. Thus, the drain electrode formed on the back surface of the semiconductor chip CHP2 and the source pad SPj formed on the front surface of the semiconductor chip CHP1 are electrically connected. As a result, the source of the junction FET formed on the semiconductor chip CHP1 and the drain of the MOSFET formed on the semiconductor chip CHP2 are electrically connected. As can be seen from this, the semiconductor chip CHP2 needs to be formed so as to be surrounded by the source pad SPj formed on the front surface of the semiconductor chip CHP1 in a plan view. That is, in modification 1, the size of the semiconductor chip CHP2 needs to be smaller than the size of the semiconductor chip CHP1, and the size of the semiconductor chip CHP2 needs to be smaller than the size of the source pad SPj.

Next, as shown in fig. 5, the gate pad GPj formed on the surface of the semiconductor chip CHP1 and the source lead post SPST formed at the tip of the source lead SL are electrically connected to each other by a wire Wgj. The source pad SPm formed on the surface of the semiconductor chip CHP2 and the source lead post SPST formed at the tip of the source lead SL are electrically connected to each other by the wire Wsm. The gate pad GPm formed on the surface of the semiconductor chip CHP2 and the gate lead post GPST formed at the distal end of the gate lead GL are electrically connected to each other by a wire Wgm. Here, the region of source pin portion SPST to which lead Wgj and lead Wsm are connected and the region of gate pin portion GPST to which lead Wgm is connected are located higher than the upper surface of chip mounting portion PLT1 and the upper surface of chip mounting portion PLT 2.

In the package PKG3 configured as described above, at least the semiconductor chip CHP1, the semiconductor chip CHP2, a part of the chip mounting portion PLT, a part of the drain lead DL, a part of the source lead SL, a part of the gate lead GL, and the conductive lines Wgj, Wgm, and Wsm are sealed by a sealing material. Further, the lower surface of the chip mounting portion PLT may be exposed from the sealing body. In this case, the heat generated by the semiconductor chip CHP1 and the semiconductor chip CHP2 can be efficiently dissipated from the lower surface of the chip mounting portion PLT.

The sealing member has, for example, a rectangular parallelepiped shape and has a 1 st side surface and a 2 nd side surface opposite to the 1 st side surface. In this case, for example, a part of the drain lead DL, a part of the source lead SL, and a part of the gate lead GL protrude from the 1 st side surface of the solid sealing body. These protruding drain lead DL, source lead SL, and gate lead GL function as external connection terminals.

The package PKG3 of modification 1 is configured as described above, and features of the package PKG3 of modification 1 will be described below. First, as shown in fig. 5, the feature of modification 1 is that the gate pad GPj provided on the surface of the semiconductor chip CHP1 on which the junction FET is formed and the source lead SL are arranged as close as possible. Specifically, in modification 1, the semiconductor chip CHP1 is disposed on the same side as the source lead SL with respect to the drain lead DL. That is, the semiconductor chip CHP1 is disposed offset to the right with respect to the center line a-a' shown in fig. 5. This enables the semiconductor chip CHP1 to approach the source lead SL. In modification 1, the semiconductor chip CHP1 is not disposed in the center of the chip mounting portion PLT, but the semiconductor chip CHP1 is disposed close to the side of the chip mounting portion PLT closest to the source lead SL. That is, the semiconductor chip CHP1 is arranged closer to the front side (lower side) than the center line b-b' shown in fig. 5. Thus, the semiconductor chip CHP1 can be disposed closest to the source lead SL. In other words, in modification 1, the gate pad GPj formed on the surface of the semiconductor chip CHP1 is arranged closer to the source lead SL than the other leads (the drain lead DL and the gate lead GL). As a result, according to modification 1, since the distance between gate pad GPj and source lead SL can be shortened, the length of wire Wgj connecting gate pad GPj and source lead SL can be shortened. In particular, in modification 1, since the lead Wgj is connected to the wide source post SPST that is present at the tip of the source lead SL near the gate pad GPj, the length of the lead Wgj can be further reduced. Being able to shorten the length of the wire Wgj means that the parasitic inductance (Lgi 1 and Lgi2 of fig. 2) present at the wire Wgj can be reduced. That is, according to modification 1, the parasitic inductance existing in lead Wgj can be sufficiently reduced. It is understood that the application of a voltage of a withstand voltage or higher to the MOSFET according to the above-described mechanism 2 can be suppressed, and thus the avalanche breakdown of the MOSFET connected in cascade can be effectively suppressed. As a result, according to modification 1, the reliability of the semiconductor device can be improved.

Here, from the viewpoint of shortening the length of the wire Wgj connecting the gate pad GPj and the source lead SL, it is considered to dispose the gate pad GPj offset to the side closest to the source lead SL of the semiconductor chip CHP 1. However, in modification 1, as shown in fig. 5, the gate pad GPj is arranged along the right side of the semiconductor chip CHP1 and symmetrically with respect to the right center portion. This is for the following reasons. That is, the gate pad GPj is connected to the gate electrodes of the plurality of junction FETs formed inside the semiconductor chip CHP1 by gate wirings. As can be seen from this, for example, by arranging the gate pads GPj symmetrically with respect to the right center portion, it is possible to suppress variations in the distance between the gate lines connecting the gate electrodes of the plurality of junction FETs and the gate pads GPj. This means that the characteristics of the plurality of junction FETs formed in the semiconductor chip CHP1 can be uniformly utilized. For this reason, in modification 1, the gate pad GPj is arranged symmetrically with respect to the right center portion of the semiconductor chip CHP 1.

In modification 1, as shown in fig. 5, the gate pad GPj is electrically connected to the source lead SL by a lead Wgj, and the gate pad GPm is electrically connected to the gate lead GL by a lead Wgm. At this time, the thickness (width) of the conductive wire Wgj is desirably made thicker than the thickness (width) of the conductive wire Wgm. This is because, if the parasitic resistance existing in the wire Wgj increases, a voltage equal to or higher than the dielectric breakdown voltage is applied to the MOSFET according to the 3 rd mechanism. Therefore, from the viewpoint of reducing the parasitic resistance existing in the lead wire Wgj, it is desirable to make the thickness of the lead wire Wgj thicker than the other lead wires. Accordingly, since the parasitic resistance between the gate electrode of the junction FET and the source of the switching element (which may also be referred to as the source of the MOSFET) can be reduced, the application of a voltage higher than the dielectric breakdown voltage to the MOSFET according to the above-described mechanism 3 can be suppressed, and thus the avalanche breakdown of the MOSFET connected in cascade can be effectively suppressed. As a result, according to modification 1, the reliability of the semiconductor device can be improved.

Next, further characteristic points of modification 1 will be described. As shown in fig. 5, a further characteristic of modification 1 is that the source pad SPm provided on the surface of the semiconductor chip CHP2 on which the MOSFET is formed and the source lead SL (source lead post part SPST) are connected to each other by a plurality of wires Wsm. This can reduce parasitic resistance and parasitic inductance between the source of the MOSFET and the source lead SL. As a result, the potential of the source of the MOSFET can be suppressed from varying from the GND potential (reference potential) supplied from the source lead SL, and the source of the MOSFET can be reliably fixed at the GND potential. In addition, since the parasitic resistance between the source of the MOSFET and the source lead SL is reduced, the on-resistance of the switching element formed by cascade connection can also be reduced. As described above, according to a further characteristic point of the present modification 1, it is possible to improve the electrical characteristics of the switching element formed by cascade connection in the package PKG 3.

Next, characteristic points unique to modification 1 will be described. As shown in fig. 5, a characteristic feature unique to modification 1 is that a semiconductor chip CHP2 having a MOSFET formed thereon is mounted on the semiconductor chip CHP1 having a junction FET formed thereon. This allows the source pad SPj formed on the front surface of the semiconductor chip CHP1 and the drain electrode formed on the back surface of the semiconductor chip CHP2 to be directly connected to each other. That is, according to modification 1, the source of the junction FET and the drain of the MOSFET can be directly connected without using a wire. This means that the parasitic inductance interposed between the source of the junction FET and the drain of the MOSFET can be almost completely removed. That is, the characteristic feature unique to modification 1 is that the semiconductor chip CHP2 is directly mounted on the semiconductor chip CHP1, and according to this configuration, a wire for connecting the source of the junction FET and the drain of the MOSFET is not required. In the case of using a wire, the parasitic inductance existing in the wire becomes a problem, but according to modification 1, the source of the junction FET and the drain of the MOSFET can be directly connected without using a wire, so that the parasitic inductance between the drain of the MOSFET and the source of the junction FET can be almost completely removed (Lse 1, Lse2 in fig. 2). As is clear from the above, according to the characteristic points unique to modification 1, it is possible to suppress the application of a voltage equal to or higher than the dielectric breakdown voltage to the MOSFET by the above-described mechanism 1, and thereby it is possible to effectively suppress the avalanche breakdown of the MOSFETs connected in cascade. As a result, according to modification 1, the reliability of the semiconductor device can be improved.

According to the package PKG3 of modification 1, the semiconductor chip CHP1 and the semiconductor chip CHP2 are stacked on the chip mounting portion PLT. As described above, in the package PKG3 of modification 1, since the package can have a structure in which one chip mounting unit PLT is provided, it is possible to directly use a conventional general-purpose package having only one chip mounting unit in the package. That is, according to the package PKG3 of modification 1, a so-called inexpensive general-purpose package can be directly used, and thus a high-performance switching element connected in cascade can be provided at low cost. In other words, according to modification 1, the cost of the package PKG3 in which the high-performance switching elements are formed by cascade connection can be reduced.

Further, according to modification 1, since the semiconductor chip CHP1 on which the junction FET is formed and the semiconductor chip CHP2 on which the MOSFET is formed are stacked, there is also obtained an advantage that the mounting area of the semiconductor chip can be reduced. In particular, in this case, as shown in fig. 5, since a large space can be secured in the chip mounting portion PLT, the heat generated by the semiconductor chip CHP1 and the semiconductor chip CHP2 can be efficiently dissipated. Further, according to modification 1, since the mounting area of the switching element can be reduced, there is also obtained an advantage that the flywheel diode (free wheeling diode) conventionally disposed on the printed board outside the package can be mounted on the same package as the switching element. As a result, according to modification 1, the reduction of the mounting area of the printed circuit board can be facilitated, and thus the cost of the entire system including the power supply system can be reduced.

Next, an example of another mounting method of the switching element of modification 1 will be described. Fig. 6 is a view showing an installation configuration of the package PKG4 according to modification 1. The package PKG4 shown in fig. 6 is different from the package PKG3 shown in fig. 5 in the arrangement position of the gate pad GPj formed on the surface of the semiconductor chip CHP 1. Specifically, in the package PKG3 shown in fig. 5, the gate pads GPj are arranged along the right side of the semiconductor chip CHP1 and symmetrically with respect to the right center portion. In contrast, in the package PKG4 shown in fig. 6, the gate pad GPj is arranged to be offset to the side of the semiconductor chip CHP1 closest to the source lead SL. In this case, the distance from gate pad GPj to source lead SL can be minimized. Therefore, according to the package PKG4 shown in fig. 6, the length of the wire Wgj connecting the gate pad GPj and the source lead SL can be minimized, and thus, the parasitic inductance existing in the wire Wgj can be minimized. It is understood that the application of a voltage of a withstand voltage or higher to the MOSFET according to the above-described mechanism 2 can be suppressed, and thus the avalanche breakdown of the MOSFET connected in cascade can be effectively suppressed. As a result, in the package PKG4 shown in fig. 6, the reliability of the semiconductor device can be improved.

Another example of the mounting method of the switching element according to modification 1 will be described. Fig. 7 is a view showing an installation configuration of the package PKG5 according to modification 1. In the package PKG5 shown in fig. 7, for example, a clip CLP made of a copper plate (metal plate) is used for connection between the gate pad GPj and the source lead SL and for connection between the source pad SPm and the source lead SL. By using the copper plate in this manner, the conductor resistance is reduced compared to that of the lead wire, and thus the parasitic inductance can be reduced. That is, by using the clip CLP configured by a metal plate, parasitic inductance existing between the gate pad GPj and the source lead SL and parasitic inductance existing between the source pad SPm and the source lead SL can be reduced.

In particular, according to the package PKG5 shown in fig. 7, since the parasitic inductance existing between the gate pad GPj and the source lead SL can be reduced, the application of a voltage equal to or higher than the dielectric breakdown voltage to the MOSFET by the above-described mechanism 2 can be suppressed, and thus, the avalanche breakdown of the MOSFET connected in cascade can be effectively suppressed. As a result, the package PKG5 shown in fig. 7 can improve the reliability of the semiconductor device. Further, according to the package PKG5 shown in fig. 7, since the parasitic inductance existing between the source pad SPm and the source lead SL can also be reduced, the electrical characteristics of the semiconductor device can also be improved.

Fig. 8 is a view showing a cross section of the package PKG5 according to modification 1. As shown in fig. 8, a semiconductor chip CHP1 is mounted on the chip mounting portion PLT via a conductive adhesive PST, and a semiconductor chip CHP2 is mounted on the semiconductor chip CHP1 via a conductive adhesive (not shown). Further, the semiconductor chip CHP1 (gate pad) and the source lead SL, and the semiconductor chip CHP2 (source pad) and the source lead SL are electrically connected by a clip CLP. In addition, the dotted line indicates a portion covered with a sealing material.

Next, an example of another mounting method of the switching element of modification 1 will be described. Fig. 9 is a view showing an installation configuration of the package PKG6 according to modification 1. The package PKG6 shown in fig. 9 is different from the package PKG3 shown in fig. 5 in that the formation positions of the source lead SL and the drain lead DL are different. Specifically, in the package PKG3 shown in fig. 5, the gate lead GL is disposed on the leftmost side, the drain lead DL is disposed in the middle, and the source lead SL is disposed on the rightmost side. In contrast, in the package PKG6 shown in fig. 9, the gate lead GL is disposed on the leftmost side, the source lead SL is disposed at the center, and the drain lead DL is disposed on the rightmost side. In this case, as shown in fig. 9, the mounting position of the semiconductor chip CHP1 mounted on the chip mounting portion PLT is changed in accordance with the change in the position of the source lead SL. That is, the arrangement position of the semiconductor chip CHP1 is changed so as to be closer to the source lead SL than the other leads. Specifically, the semiconductor chip CHP1 is disposed symmetrically with respect to the center line a-a 'shown in fig. 9, and is disposed at a position closer to the front side (lower side) than the center line b-b'. As a result, in the package PKG6 shown in fig. 9, the distance between the gate pad GPj and the source lead SL can be shortened. Therefore, the length of the wire Wgj connecting the gate pad GPj and the source lead SL can be shortened. That is, in the package PKG6 shown in fig. 9, the parasitic inductance existing in the wire Wgj can be sufficiently reduced. It is understood that the application of a voltage of a withstand voltage or higher to the MOSFET according to the above-described mechanism 2 can be suppressed, and thus the avalanche breakdown of the MOSFET connected in cascade can be effectively suppressed. As a result, in the package PKG6 shown in fig. 9, the reliability of the semiconductor device can be improved.

Further, as a characteristic point peculiar to the package PKG6 shown in fig. 9, the length of the wire Wgm electrically connecting the gate pad GPm formed on the surface of the semiconductor chip CHP2 and the gate lead GL can be sufficiently shortened as compared with the package PKG3 shown in fig. 5. Therefore, according to the package PKG6 shown in fig. 9, since the parasitic resistance and parasitic inductance of the wire Wgm can be reduced, the electrical characteristics of the switching element of modification 1 can be improved.

Fig. 10 is a view showing a cross section of the package PKG6 according to modification 1. As shown in fig. 10, a semiconductor chip CHP1 is mounted on the chip mounting portion PLT via a conductive adhesive PST, and a semiconductor chip CHP2 is mounted on the semiconductor chip CHP1 via a conductive adhesive (not shown). Further, the semiconductor chip CHP2 (source pad) and the source lead SL are electrically connected by a wire Wsm. In addition, the dotted line indicates a portion covered with a sealing material.

Next, an example of another mounting method of the switching element of modification 1 will be described. Fig. 11 is a view showing an installation configuration of the package PKG7 according to modification 1. The package PKG7 shown in fig. 11 is different from the package PKG6 shown in fig. 9 in the arrangement position of the gate pad GPj formed on the surface of the semiconductor chip CHP 1. Specifically, in the package PKG6 shown in fig. 9, the gate pads GPj are arranged along the right side of the semiconductor chip CHP1 and symmetrically with respect to the right center portion. In contrast, in the package PKG7 shown in fig. 11, the gate pad GPj is arranged to be offset to the side of the semiconductor chip CHP1 closest to the source lead SL. In this case, the distance from gate pad GPj to source lead SL can be minimized. Therefore, according to the package PKG7 shown in fig. 11, the length of the wire Wgj connecting the gate pad GPj and the source lead SL can be made shortest, and thereby the parasitic inductance existing in the wire Wgj can be minimized. It is understood that the application of a voltage of a withstand voltage or higher to the MOSFET according to the above-described mechanism 2 can be suppressed, and thus the avalanche breakdown of the MOSFET connected in cascade can be effectively suppressed. As a result, in the package PKG7 shown in fig. 11, the reliability of the semiconductor device can be improved.

Next, parasitic inductances of the switching element according to embodiment 1 and the switching element according to the present modification are described in comparison with parasitic inductances of the switching elements according to the related art. Fig. 12 is a circuit diagram showing switching elements connected in cascade and a diagram showing parasitic inductance. Specifically, (a) of fig. 12 is a circuit diagram showing the positions of the switching elements and the parasitic inductances according to the prior art, and (b) of fig. 12 is a circuit diagram showing the positions of the switching elements and the parasitic inductances according to embodiment 1. Fig. 12 (c) is a circuit diagram showing the positions of the switching elements and the parasitic inductances in modification 1.

First, as is clear from fig. 12 (a), in the switching element formed by the cascade connection in the related art, a parasitic inductance Lse exists at an intermediate node Se connecting the source of the junction type fet q1 and the drain of the mosfet q2, and a parasitic inductance Ls exists between the source of the mosfet q2 and the source S of the switching element. Further, a parasitic inductance Lgi exists between the gate electrode of the junction FET and the source S of the switching element, and a parasitic inductance exists in the gate electrode Gm of the MOSFET.

In contrast, as shown in fig. 12 (b), in the switching element formed by cascade connection according to embodiment 1, the parasitic inductance Lse, the parasitic inductance Ls, and the parasitic inductance Lgi are reduced as compared with the switching element formed by cascade connection according to the related art shown in fig. 12 (a). It is realized based on the following aspects: for example, as shown in fig. 3, in embodiment 1, the arrangement position of the chip mounting portion PLT1, the arrangement position of the semiconductor chip CHP1, and the arrangement position of the gate pad GPj are examined, and the lead Wgj connecting the gate pad GPj and the source lead SL is shortened; and a lead Wds connecting the source pad SPj and the chip mounting portion PLT2 is constituted by a plurality of wires. Thus, according to embodiment 1, it is possible to suppress application of a voltage equal to or higher than the dielectric breakdown voltage to the MOSFET, thereby effectively suppressing avalanche breakdown of the MOSFETs connected in cascade. As a result, according to embodiment 1, the reliability of the semiconductor device can be improved.

As shown in fig. 12 (c), in the switching element formed by cascade connection in modification 1, as in embodiment 1, parasitic inductance Ls and parasitic inductance Lgi can be reduced compared to the switching element formed by cascade connection in the related art shown in fig. 12 (a). In addition, in modification 1, parasitic inductance Lse existing at intermediate node Se connecting the source of junction type fet q1 and the drain of mosfet q2 can be almost completely removed. This is because, for example, as shown in fig. 5, a semiconductor chip CHP2 in which a MOSFET is formed is mounted on the semiconductor chip CHP1 in which the junction FET is formed. This allows the source pad SPj formed on the front surface of the semiconductor chip CHP1 and the drain electrode formed on the back surface of the semiconductor chip CHP2 to be directly connected to each other. That is, according to modification 1, the source of the junction FET and the drain of the MOSFET can be directly connected without using a wire. Therefore, according to modification 1, the parasitic inductance interposed between the source of the junction FET and the drain of the MOSFET can be almost completely removed. Thus, according to modification 1, it is possible to suppress application of a voltage equal to or higher than the dielectric breakdown voltage to the MOSFET, thereby effectively suppressing the avalanche breakdown of the MOSFET connected in cascade. As a result, according to modification 1, the reliability of the semiconductor device can be improved.

< modification 2 >

Next, a mounting structure of the package PKG8 of modification example 2 will be described. Fig. 13 is a view showing an installation configuration of the package PKG8 according to modification 2. The structure of the encapsulating PKG8 shown in fig. 13 is substantially the same as the structure of the encapsulating PKG1 shown in fig. 3. The difference is in the shape of the package. As described above, the technical idea of the present invention can be applied not only to the encapsulation PKG1 shown in fig. 3 but also to the encapsulation PKG8 shown in fig. 13. That is, various general packages exist in a package in which a switching element is mounted, and the technical idea of the present invention can be realized by, for example, improving various general packages represented by a package PKG1 shown in fig. 3 and a package PKG8 shown in fig. 13. Specifically, in the package PKG8 shown in fig. 13, for example, the distance between the gate pad GPj and the source lead SL can be shortened, and therefore the length of the wire Wgj connecting the gate pad GPj and the source lead SL can be shortened. As a result, it is found that the parasitic inductance existing in the wire Wgj can be sufficiently reduced in the package PKG8 shown in fig. 13. It is thus understood that the application of a voltage equal to or higher than the dielectric breakdown voltage to the MOSFET can be suppressed, and thus the avalanche breakdown of the MOSFET connected in cascade can be effectively suppressed. As a result, in the package PKG8 shown in fig. 13, the reliability of the semiconductor device can be improved.

Fig. 14 is a view showing a cross section of the package PKG8 according to modification 2. As shown in fig. 14, a semiconductor chip CHP2 is mounted on the chip mounting portion PLT2 via a conductive adhesive PST. Further, for example, the semiconductor chip CHP2 (gate pad) and the gate lead GL (gate lead pillar portion GPST) are electrically connected via a wire Wgm. In addition, the dotted line indicates a portion covered with a sealing material.

Next, an example of another mounting method of the switching element of modification 2 will be described. Fig. 15 is a view showing an installation configuration of the package PKG9 according to modification example 2. The structure of the encapsulating PKG9 shown in fig. 15 is substantially the same as the structure of the encapsulating PKG3 shown in fig. 5. The difference is in the shape of the package. As described above, the technical idea of the present invention can be applied not only to the encapsulation PKG3 shown in fig. 5 but also to the encapsulation PKG9 shown in fig. 15. That is, various general packages exist in a package in which a switching element is mounted, and the technical idea of the present invention can be applied to various general packages represented by, for example, a package PKG3 shown in fig. 5 and a package PKG9 shown in fig. 15. Specifically, according to the package PKG9 shown in fig. 15, since the semiconductor chip CHP2 having the MOSFET formed thereon is also mounted on the semiconductor chip CHP1 having the junction FET formed thereon, the source pad SPj and the drain electrode formed on the back surface of the semiconductor chip CHP2 can be directly connected to each other. As described above, according to the package PKG9 shown in fig. 15, since the source of the junction FET and the drain of the MOSFET can be directly connected without using a wire, the parasitic inductance between the drain of the MOSFET and the source of the junction FET can be almost completely removed (Lse 1 and Lse2 in fig. 2). Therefore, according to the package PKG9 shown in fig. 15, the application of a voltage higher than the dielectric breakdown voltage to the MOSFET can be suppressed, and thus the avalanche breakdown of the MOSFET connected in cascade can be effectively suppressed. As a result, according to modification 2, the reliability of the semiconductor device can be improved.

Fig. 16 is a view showing a cross section of the package PKG9 according to modification 2. As shown in fig. 16, a semiconductor chip CHP1 is mounted on the chip mounting portion PLT via a conductive adhesive PST, and a semiconductor chip CHP2 is mounted on the semiconductor chip CHP1 via a conductive adhesive (not shown). Further, for example, the semiconductor chip CHP2 (gate pad) and the gate lead GL (gate lead pillar portion GPST) are electrically connected by a wire Wgm. In addition, the dotted line indicates a portion covered with a sealing material.

< modification 3 >

Next, a mounting structure of the package PKG10 of modification example 3 will be described. Fig. 17 is a view showing an installation configuration of the package PKG10 according to modification 3. The structure of the encapsulating PKG10 shown in fig. 17 is substantially the same as the structure of the encapsulating PKG1 shown in fig. 3. The difference is in the shape of the package. As described above, the technical idea of the present invention can be applied not only to the encapsulation PKG1 shown in fig. 3 but also to the encapsulation PKG10 shown in fig. 17. That is, various general packages exist in a package in which a switching element is mounted, and the technical idea of the present invention can be realized by modifying various general packages represented by, for example, a package PKG1 shown in fig. 3 and a package PKG10 shown in fig. 17. Specifically, in the package PKG10 shown in fig. 17, for example, the distance between the gate pad GPj and the source lead SL can be shortened, and therefore the length of the wire Wgj connecting the gate pad GPj and the source lead SL can be shortened. As a result, it is found that the parasitic inductance existing in the wire Wgj can be sufficiently reduced in the package PKG10 shown in fig. 17. It is thus understood that the application of a voltage equal to or higher than the dielectric breakdown voltage to the MOSFET can be suppressed, and thus the avalanche breakdown of the MOSFET connected in cascade can be effectively suppressed. As a result, in the package PKG10 shown in fig. 17, the reliability of the semiconductor device can be improved.

Fig. 18 is a view showing a cross section of the package PKG10 according to modification 3. As shown in fig. 18, a semiconductor chip CHP1 is mounted on the chip mounting portion PLT1 via a conductive adhesive PST. Further, for example, the semiconductor chip CHP1 (gate pad GPj) and the source lead SL (source lead post SPST) are electrically connected by a wire Wgj. In addition, the dotted line indicates a portion covered with a sealing material.

Next, an example of another mounting method of the switching element of modification 3 will be described. Fig. 19 is a mounting configuration diagram showing a package PKG11 according to modification 3. The structure of the encapsulating PKG11 shown in fig. 19 is substantially the same as the structure of the encapsulating PKG3 shown in fig. 5. The difference is in the shape of the package. As described above, the technical idea of the present invention can be applied not only to the encapsulation PKG3 shown in fig. 5 but also to the encapsulation PKG11 shown in fig. 19. That is, various general packages exist in a package in which a switching element is mounted, and the technical idea of the present invention can be applied to various general packages represented by, for example, a package PKG3 shown in fig. 5 and a package PKG11 shown in fig. 19. Specifically, according to the package PKG11 shown in fig. 19, since the semiconductor chip CHP2 having the MOSFET formed thereon is also mounted on the semiconductor chip CHP1 having the junction FET formed thereon, the source pad SPj and the drain electrode formed on the back surface of the semiconductor chip CHP2 can be directly connected to each other. As described above, according to the package PKG11 shown in fig. 19, since the source of the junction FET and the drain of the MOSFET can be directly connected without using a wire, the parasitic inductance between the drain of the MOSFET and the source of the junction FET can be almost completely removed (Lse 1 and Lse2 in fig. 2). Therefore, according to the package PKG11 shown in fig. 19, the application of a voltage higher than the dielectric breakdown voltage to the MOSFET can be suppressed, and thus the avalanche breakdown of the MOSFET connected in cascade can be effectively suppressed. As a result, according to modification 3, the reliability of the semiconductor device can be improved.

Fig. 20 is a view showing a cross section of the package PKG11 according to modification 3. As shown in fig. 20, a semiconductor chip CHP1 is mounted on the chip mounting portion PLT via a conductive adhesive PST, and a semiconductor chip CHP2 is mounted on the semiconductor chip CHP1 via a conductive adhesive (not shown). Further, for example, the semiconductor chip CHP2 (gate pad) and the gate lead GL (gate lead pillar portion GPST) are electrically connected by a wire Wsm. In addition, the dotted line indicates a portion covered with a sealing material.

< modification 4 >

Next, a mounting structure of the package PKG12 of modification example 4 will be described. Fig. 21 is a view showing an installation configuration of the package PKG12 according to modification example 4. The structure of the encapsulating PKG12 shown in fig. 21 is substantially the same as the structure of the encapsulating PKG1 shown in fig. 3. The difference is in the shape of the package. Specifically, the Package PKG12 of modification example 4 is packaged in a SOP (small outline Package). As described above, the technical idea of the present invention can be applied not only to the encapsulation PKG1 shown in fig. 3 but also to the encapsulation PKG12 shown in fig. 21. That is, various general packages exist in a package in which a switching element is mounted, and the technical idea of the present invention can be realized by, for example, improving various general packages represented by a package PKG1 shown in fig. 3 and a package PKG12 shown in fig. 21. Specifically, in the package PKG12 shown in fig. 21, for example, the distance between the gate pad GPj and the source lead SL can be shortened, and therefore the length of the wire Wgj connecting the gate pad GPj and the source lead SL can be shortened. As a result, it is found that the parasitic inductance existing in the wire Wgj can be sufficiently reduced in the package PKG12 shown in fig. 21. It is thus understood that the application of a voltage equal to or higher than the dielectric breakdown voltage to the MOSFET can be suppressed, and thus the avalanche breakdown of the MOSFET connected in cascade can be effectively suppressed. As a result, in the package PKG12 shown in fig. 21, the reliability of the semiconductor device can be improved.

Fig. 22 is a diagram showing a cross section of the package PKG12 according to modification 4. As shown in fig. 22, a semiconductor chip CHP1 is mounted on the chip mounting portion PLT1 via a conductive adhesive (not shown). Further, for example, the semiconductor chip CHP1 (gate pad GPj) and the source lead SL (source lead post SPST) are electrically connected by a wire Wgj. In modification 4, for example, as shown in fig. 22, the chip mounting portion PLT1, the semiconductor chip CHP1, the lead Wgj, and a part of the lead are sealed with a sealing member MR made of a resin. In this case, as can be analogized from fig. 21 and 22, in the package PKG12 (SOP package), the sealing body MR has a substantially rectangular parallelepiped shape and has a 1 st side surface and a 2 nd side surface opposite to the 1 st side surface. The gate lead GL and the source lead SL protrude from the 1 st side surface of the sealing body MR, and the drain lead DL protrudes from the 2 nd side surface of the sealing body MR.

Next, an example of another mounting method of the switching element of modification 4 will be described. Fig. 23 is a view showing an installation configuration of the package PKG13 according to modification 4. The structure of the encapsulating PKG13 shown in fig. 23 is substantially the same as the structure of the encapsulating PKG3 shown in fig. 5. The difference is in the shape of the package. Specifically, the packaging method of the packaging PKG13 of modification example 4 is sop (small Outline package). As described above, the technical idea of the present invention can be applied not only to the encapsulation PKG3 shown in fig. 5 but also to the encapsulation PKG13 shown in fig. 23. That is, various general packages exist in a package in which a switching element is mounted, and the technical idea of the present invention can be applied to various general packages represented by, for example, a package PKG3 shown in fig. 5 and a package PKG13 shown in fig. 23. Specifically, according to the package PKG13 shown in fig. 23, since the semiconductor chip CHP2 having the MOSFET formed thereon is also mounted on the semiconductor chip CHP1 having the junction FET formed thereon, the source pad SPj and the drain electrode formed on the back surface of the semiconductor chip CHP2 can be directly connected to each other. As described above, according to the package PKG13 shown in fig. 23, since the source of the junction FET and the drain of the MOSFET can be directly connected without using a wire, the parasitic inductance between the drain of the MOSFET and the source of the junction FET can be almost completely removed (Lse 1 and Lse2 in fig. 2). Therefore, according to the package PKG13 shown in fig. 23, the application of a voltage higher than the dielectric breakdown voltage to the MOSFET can be suppressed, and thus the avalanche breakdown of the MOSFET connected in cascade can be effectively suppressed. As a result, according to modification 4, the reliability of the semiconductor device can be improved.

Fig. 24 is a view showing a cross section of the package PKG13 according to modification 4. As shown in fig. 24, a semiconductor chip CHP1 is mounted on the chip mounting portion PLT via a conductive adhesive (not shown), and a semiconductor chip CHP2 is mounted on the semiconductor chip CHP1 via a conductive adhesive (not shown). Further, for example, the semiconductor chip CHP1 (gate pad GPj) and the source lead SL (source lead post SPST) are electrically connected by a wire Wgj. In modification 4, for example, as shown in fig. 24, the chip mounting portion PLT, the semiconductor chip CHP1, the semiconductor chip CHP2, the lead Wgj, and a part of the lead are sealed with a sealing body MR made of resin. At this time, a part of the lead wire protrudes from the side surfaces on both sides of the sealing body MR.

(embodiment mode 2)

In embodiment 1 described above, the point of investigation concerning the package structure is described, but in embodiment 2, the point of investigation concerning the device structure is described.

< layout Structure of stacked semiconductor chips >

Fig. 25 is a layout configuration diagram showing a semiconductor chip according to embodiment 2. The layout structure of the semiconductor chip shown below shows an example in which a semiconductor chip CHP2 formed with a MOSFET using silicon (Si) as a material is stacked on a semiconductor chip CHP1 formed with a junction FET using a material, such as silicon carbide (Si), having a larger band gap than silicon (Si). In fig. 25, the semiconductor chip CHP1 has a rectangular shape, and a termination region TMj is formed in the outer peripheral region of the rectangular semiconductor chip CHP 1. The termination region TMj is provided to ensure withstand voltage. The inner region of the termination region TMj is an active (active) region ACTj. A plurality of junction FETs are formed in the active region ACTj.

The termination region TMj is provided in the outer peripheral region of the semiconductor chip CHP1, but a part of the termination region TMj enters inside, and a gate pad GPj is formed in this region. The gate pad GPj is connected to the gate electrodes of the junction FETs formed in the active region ACTj via gate wirings. Here, in fig. 25, the gate pad GPj is arranged in the right center portion of the semiconductor chip CHP 1. In other words, the gate pad GPj is arranged offset to the right and is arranged symmetrically with respect to a center line extending in the left and right direction. This can suppress variations in the distance between the gate lines connecting the gate electrodes of the junction FETs and the gate pad GPj. Therefore, according to the layout structure shown in fig. 25, there is obtained an advantage that the characteristics of the plurality of junction FETs formed in the semiconductor chip CHP1 can be uniformly utilized.

An active electrode pad SPj is formed on the active region ACTj of the semiconductor chip CHP 1. The source pad SPj is electrically connected to the source region of the junction FET formed in the active region ACTj. A semiconductor chip CHP2 having a rectangular shape is mounted on the source pad SPj. A plurality of MOSFETs are formed on the semiconductor chip CHP2, and a source pad SPm and a gate pad GPm are formed on the main surface of the semiconductor chip CHP 2. The source pad SPm is electrically connected to the source region of the MOSFET, and the gate pad GPj is electrically connected to the gate electrode of the MOSFET.

Fig. 26 is a diagram showing another layout structure of the stacked semiconductor chips according to embodiment 2. The layout structure shown in fig. 26 is substantially the same as the layout structure shown in fig. 25. Fig. 26 is different from fig. 25 in that the gate pad GPj is arranged at the right center portion in the layout structure shown in fig. 25, and the gate pad GPj is arranged offset to the lower right corner portion of the semiconductor chip CHP1 in the layout structure shown in fig. 26. As described above, by being disposed at the lower right corner of the semiconductor chip CHP1 in fig. 26, for example, as shown in fig. 6, the distance from the gate pad GPj to the source lead SL can be minimized. That is, by adopting the layout structure shown in fig. 26, the length of the wire Wgj connecting the gate pad GPj and the source lead SL can be made the shortest, and thereby the parasitic inductance existing in the wire Wgj can be minimized.

Next, fig. 27 is a cross-sectional view taken along line a-a of fig. 25 and 26. As shown in fig. 27, a drain electrode DEj is formed on the back surface of the semiconductor substrate SUBj, and a drift layer DFTj is formed on the main surface (front surface) of the semiconductor substrate SUBj. An active region ACTj is formed in the drift layer DFTj, and a gate electrode and a source region of the junction FET are formed in the active region ACTj. A termination region TMj for ensuring withstand voltage is formed at an end of the active region ACTj, and an active electrode pad SPj is formed on the active region ACTj. An insulating film IL1 made of, for example, a silicon oxide film is formed so as to cover the end of the source pad SPj. The structure described above is a structure in which a semiconductor chip CHP1 having a junction FET is formed, and a semiconductor chip CHP2 having a MOSFET formed thereon is mounted on the semiconductor chip CHP1 having a junction FET formed thereon.

Specifically, the exposed source pad SPj is in contact with the drain electrode DEm via a conductive adhesive (not shown), for example. The drain electrode DEm is formed on the back surface of the semiconductor substrate SUBm, and a drift layer DFTm is formed on the main surface (front surface) of the semiconductor substrate SUBm on the opposite side to the back surface. An active region ACTm is formed in the drift layer DFTm, and termination regions TMm for ensuring breakdown voltage are formed at both ends of the active region ACTm. In the active region ACTm, a gate electrode and a source region of the MOSFET are formed. The active electrode pad SPm is formed so as to straddle the active region ACTm and the termination region TMm. Although the insulating film IL2 is formed so as to cover the end of the source pad SPm, most of the surface area of the source pad SPm is exposed from the insulating film IL 2. Thus, the semiconductor chip CHP2 formed with the MOSFET is mounted on the semiconductor chip CHP1 formed with the junction FET.

As shown in fig. 27, the semiconductor chip CHP2 is mounted on the semiconductor chip CHP1 so as to be surrounded by the source pad SPj. Therefore, the drain electrode DEm formed on the back surface of the semiconductor chip CHP2 and the source pad SPj formed on the front surface of the semiconductor chip CHP1 are in direct contact with each other through a conductive adhesive material (not shown) without a wire. This means that the parasitic inductance sandwiched between the source of the junction FET and the drain of the MOSFET can be almost completely removed. That is, as shown in fig. 27, by mounting the semiconductor chip CHP2 directly on the semiconductor chip CHP1, a wire for connecting the source of the junction FET and the drain of the MOSFET is not required. In the case of using a wire, the parasitic inductance existing in the wire becomes a problem, but according to the layout structure of embodiment 2, the source of the junction FET and the drain of the MOSFET can be directly connected without using a wire. This shows that the parasitic inductance between the drain of the MOSFET and the source of the junction FET (Lse 1 and Lse2 in fig. 2) can be almost completely removed. As is clear from the above, according to embodiment 2, it is possible to suppress application of a voltage equal to or higher than the dielectric breakdown voltage to the MOSFET, thereby effectively suppressing avalanche breakdown of the MOSFET connected in cascade. As a result, according to embodiment 2, the reliability of the semiconductor device can be improved.

As shown in fig. 27, according to the layout structure of embodiment 2, since source pad SPj is disposed in active region ACTj, the current flowing through the junction FET can be increased. In this case, since the source pad SPj can be made larger in area, the area of the semiconductor chip CHP2 mounted on the source pad SPj can be increased. That is, the ability to increase the area of the semiconductor chip CHP2 means that the number of MOSFETs formed in the semiconductor chip CHP2 can be increased, and as a result, the current flowing through the entire plurality of MOSFETs can be increased. As described above, according to the layout structure of embodiment 2, the current flowing through the entire plurality of junction FETs and the current flowing through the entire plurality of MOSFETs can be increased, and thus, a large current can be easily obtained in the switching element in which the junction FETs and the MOSFETs are cascade-connected. Further, according to embodiment 2, since the junction FET using silicon carbide which can achieve a higher withstand voltage and a lower on-resistance in principle is used as compared with silicon, a switching element which can achieve a larger current, a higher withstand voltage, and a lower on-resistance at the same time can be provided.

< modification of layout Structure >

Next, another layout structure of the stacked semiconductor chip of embodiment 2 will be described. Fig. 28 is a layout configuration diagram showing a stacked semiconductor chip according to this modification. As shown in fig. 28, the semiconductor chip CHP1 has a rectangular shape, and a termination region TMj is formed in the outer peripheral region of the rectangular semiconductor chip CHP 1. In addition, an active region ACTj, a gate pad GPj, and a source pad SPj are formed in an inner region of the termination region TMj. Here, the present modification is characterized in that the active region ACTj, the gate pad GPj, and the source pad SPj are arranged so as not to overlap each other in a planar manner. That is, as shown in fig. 28, the active region ACTj in which the junction FET is formed is disposed so as to avoid the gate pad GPj and the source pad SPj. Further, a semiconductor chip CHP2 is mounted on the source pad SPj.

Fig. 29 is a diagram showing another layout structure of the stacked semiconductor chip according to the present modification. The layout structure shown in fig. 29 is substantially the same as the layout structure shown in fig. 28. Fig. 29 differs from fig. 28 in that the gate pad GPj is arranged at the right center portion in the layout structure shown in fig. 28, whereas the gate pad GPj is arranged offset to the lower right corner portion of the semiconductor chip CHP1 in the layout structure shown in fig. 29.

Next, fig. 30 is a cross-sectional view taken along line a-a of fig. 28 and 29. As shown in fig. 30, a drain electrode DEj is formed on the back surface of the semiconductor substrate SUBj, and a drift layer DFTj is formed on the main surface (front surface) of the semiconductor substrate SUBj. An active region ACTj is formed in the drift layer DFTj, and a termination region TMj is formed in a region outside the active region ACTj. A gate electrode GE and a source region SR of the junction FET are formed in the active region ACTj. An insulating film IL1 is formed on the active region ACTj and on the terminal region TMj, and a source pad SPj is formed on the insulating film IL 1. Here, in the present modification, the important point is that the source pad SPj is not formed in the active region ACTj, but is formed on the termination region TMj. That is, in the present modification, in a plan view, the active region ACTj and the source pad SPj are arranged so as not to overlap each other, and the source pad SPj is arranged on the termination region TMj. In fig. 30, the semiconductor chip CHP2 disposed on the source pad SPj is not shown. That is, in fig. 30, the semiconductor chip CHP2 is mounted on the source pad SPj, as in fig. 27, and since the structure is the same, the semiconductor chip CHP2 disposed on the source pad SPj is not shown in fig. 30.

According to the present modification configured as described above, the following effects can be obtained. That is, the semiconductor chip CHP2 is mounted on the source pad SPj. In this case, stress acts on the source pad SPj. However, in the present modification, the active region ACTj in which the junction FET is formed is not formed in the region directly below the source pad SPj, and therefore, stress can be prevented from being applied to the active region ACTj. That is, according to this modification, since unnecessary stress can be prevented from being applied to the active region ACTj, mechanical breakdown of the junction FET formed in the active region ACTj can be prevented.

Further, a gate pad GPm and a source pad SPm are formed on the surface of the semiconductor chip CHP2 mounted on the source pad SPj, and a lead wire is connected to these pads by wire bonding. Although stress is generated in this wire bonding step, in this modification, since the semiconductor chip CHP2 and the active region ACTj are arranged so as not to overlap each other in a planar manner, the stress generated in the wire bonding step can be prevented from being directly transmitted to the active region ACTj. As a result, according to the layout structure of the stacked semiconductor chip of the present modification, it is possible to suppress the influence of the stress generated at the time of mounting the semiconductor chip CHP2 or at the time of wire bonding on the characteristics of the junction FET formed in the active region ACTj of the semiconductor chip CHP 1. That is, according to the present modification, a semiconductor device with high assembly yield and high reliability can be provided.

< device architecture of MOSFET >

Next, an example of the device structure of the MOSFET formed on the semiconductor chip CHP2 will be described. Fig. 31 is a cross-sectional view showing an example of the device structure of the MOSFET of embodiment 2. As shown in fig. 31, for example, a drain electrode DEm formed of, for example, a gold film is formed on the back surface of a semiconductor substrate SUBm made of silicon into which an n-type impurity is introduced, and a drift layer DFTm formed of an n-type semiconductor region is formed on the main surface side of the semiconductor substrate SUBm. A body region PR made of a p-type semiconductor region is formed in the drift layer DFTm, and a source region SR made of an n-type semiconductor region is formed so as to be surrounded by the body region PR. The surface region of the body region PR sandwiched between the source region SR and the drift layer DFTm functions as a channel formation region. The active electrode SE is formed to be electrically connected to both the source region SR and the body region PR. Further, a gate insulating film GOX made of, for example, a silicon oxide film is formed on the surface of the drift layer DFTm including the channel formation region, and a gate electrode G is formed on the gate insulating film GOX.

In the MOSFET having such a structure, for example, electrons flow from the source region SR through the channel formation region formed on the front surface of the body region PR, and flow from the drift layer DFTm to the drain electrode DEm formed on the rear surface of the semiconductor substrate SUBm, which is a so-called vertical MOSFET. The vertical MOSFET has an advantage that it can be formed on the semiconductor chip CHP2 at high density, and thus has a high current density. Therefore, by using a vertical MOSFET as the switching element of the present invention, a switching element having a high current density can be realized.

For example, in the case of the layout structures shown in fig. 28 and 29, while characteristic degradation due to stress to the junction FET formed in the active region ACTj can be effectively prevented, the area of the source pad SPj is small. In this case, the area of the MOSFET-formed semiconductor chip CHP2 disposed on the source pad SPj is also small, but a MOSFET with a large current density can be realized even with a small chip area by using a vertical MOSFET shown in fig. 31 as the MOSFET formed in the semiconductor chip CHP 2. As a result, the current density of the entire switching element formed by cascade connection can be increased. That is, by adopting the layout structure shown in fig. 28 or 29 in particular, it is possible to provide a high-performance switching element capable of securing a large current while effectively preventing characteristic deterioration due to stress to the junction FET formed in the active region ACTj by using the vertical MOSFET shown in fig. 31 even when the area of the semiconductor chip CHP2 on which the MOSFET is formed is small.

< technical problem found by the present inventors >

Next, a new technical problem found by the present inventors will be described. Fig. 32 is a diagram showing current paths in switching elements connected in cascade. Fig. 32 (a) is a diagram showing a current path at the time of on-state, and fig. 32 (b) is a diagram showing a current path of a leakage current flowing at the time of off-state. As shown in fig. 32 (a), when turned on, the rated current Id flows from the drain of the junction type fet q1 to the source of the mosfet q 2. That is, the rated current Id flows from the drain D to the source S of the switching element connected in cascade. At this time, the drain voltage of the mosfet q2 (the voltage of the intermediate node Se) before the mosfet q2 is turned off can be obtained from the product of the on-resistance of the mosfet q2 and the rated current Id. For example, if the on-resistance is 10m Ω and the rated current Id is 40A, the voltage of the intermediate node Se is 0.4V. Since the voltage of the intermediate node Se is the drain voltage of the mosfet q2 and the source voltage of the junction type fet q1, the gate voltage of the junction type fet q1, i.e., the voltage Vgs, based on the source voltage of the junction type fet q1 is-0.4V.

When the switching elements connected in cascade are changed from the on state to the off state, as shown in fig. 32 (a), from the state where 15V is applied to the gate electrode Gm of the mosfet q2, 0V is applied to the gate electrode Gm of the mosfet q2 as shown in fig. 32 (b). The MOSFET q2 is a normally-off MOSFET, and therefore is turned off when 0V is applied to the gate electrode Gm.

In turning off the mosfet q2, the channel gradually disappears in the initial stage, and thus the on-resistance between the drain and source of the mosfet q2 gradually rises. The junction type fet q1 used in the switching element formed by cascade connection is a normally-open type, and at the initial stage of turning off the mosfet q2, the voltage Vgs of the junction type fet q1 is-0.4V, so the junction type fet q1 maintains the on state. Thus, current flows from the drain of junction fet q1 (e.g., about 300V for a supply voltage of 300V) to the source of junction fet q 1. Therefore, the drain voltage of the mosfet q2 (the voltage of the intermediate node Se) is a product of the on-resistance that increases with the disappearance of the channel and the drain current that flows from the drain of the junction type fet q1, and therefore the drain voltage of the mosfet q2 (the voltage of the intermediate node Se) gradually increases from 0.4V.

When the channel of mosfet q2 completely disappears and mosfet q2 completely turns off, the charge is accumulated at intermediate node Se by the current flowing from junction type fet q1, and therefore the drain voltage of mosfet q2 (the voltage of intermediate node Se) further rises to the off-voltage of junction type fet q1 (for example, about 5V to 15V). When this state is achieved, the junction type fet q1 is off, and the drain current of the junction type fet q1 does not flow. That is, the drain voltage of the mosfet q2 (the voltage of the intermediate node Se) stops rising, and this state is maintained.

However, the present inventors have found that in a switching element formed by cascade connection, even when the voltage Vgs of the junction type fet q1 is about-5V to-15V, the drain current Idl may flow between the drain and the source of the junction type fet q 1. When the drain current Idl flows, electric charge is accumulated in the intermediate node Se, and therefore, the drain voltage of the mosfet q2 (the voltage of the intermediate node Se) rises. From this, it is found that when the drain current Idl increases, the drain voltage of the mosfet q2 (the voltage of the intermediate node Se) may become a voltage equal to or higher than the withstand voltage of the mosfet q2 (for example, equal to or higher than 30V). As a result, mosfet q2 avalanche action occurs, which may eventually result in mosfet q2 breakdown. As a countermeasure against this, it is possible to prevent the possibility of avalanche breakdown of the MOSFET from increasing if a high-voltage MOSFET having a high withstand voltage is used, but in the case of using a high-voltage MOSFET, the drift layer needs to be designed to be thick in order to ensure the withstand voltage. As described above, when the thickness of the low-concentration drift layer is increased, the on-resistance of the MOSFET increases, and thus, there is a problem that the conduction loss at the time of turning on the switching element connected in cascade increases. That is, in order to ensure high performance of the switching element formed by cascade connection and prevent avalanche breakdown of the MOSFET, it is necessary to conduct research in other aspects than the structure in which the low-concentration drift layer is thickened. Therefore, in embodiment 2, in order to prevent the avalanche breakdown of the MOSFET while ensuring high performance of the switching element formed by cascade connection, the device structure of the junction FET is studied. The device structure of the junction FET of embodiment 2 obtained by this study will be described below.

Device structure of junction FET

Fig. 33 is a cross-sectional view showing the device structure of the junction FET in embodiment 2. As shown in fig. 33, the junction FET of embodiment 2 includes a semiconductor substrate SUBj, and a drain electrode DEj is formed on the back surface of the semiconductor substrate SUBj. On the other hand, a drift layer DFTj is formed on the main surface side of the semiconductor substrate SUBj opposite to the back surface, and a plurality of trenches (trenches) TR are formed in the drift layer DFTj. Further, gate electrodes GE (also referred to as gate regions) are formed on the side surfaces and the bottom surfaces of the plurality of trenches TR, and a channel formation region is formed so as to be sandwiched between the gate electrodes GE formed on the side surfaces and the bottom surfaces of the adjacent trenches TR. A source region SR is formed above the channel formation region. In the junction FET thus configured, the growth of the depletion layer from the gate electrode GE is controlled by suppressing the voltage applied to the gate electrode GE. Thus, when the depletion layers grown from the gate electrodes GE adjacent to each other are connected, the channel formation region disappears and the off state is realized, and on the other hand, when the depletion layers grown from the gate electrodes GE adjacent to each other are not connected, the channel formation region is formed and the on state is realized.

Here, the junction FET of embodiment 2 is characterized in that the channel length CL of the channel formation region is 1 μm or more. In other words, embodiment 2 is characterized in that the distance between the bottom of source region SR and the bottom of gate electrode GE is 1 μm or more. This can increase the channel length of the channel formation region, and therefore can increase the electrostatic potential in the channel formation region when the junction FET is on. As described above, according to embodiment 2, the leakage current flowing between the drain and the source of the junction FET can be suppressed to be smaller than the case of using a device structure having a channel length of about 0.5 μm. In this manner, the advantage of making the channel length CL 1 μm or more is that the electrostatic potential in the channel formation region at the time of off can be increased to reduce the leakage current, but it is considered that the extension of the channel length CL itself contributes to the reduction of the leakage current.

In the device structure of the junction FET shown in fig. 33, the distance between the semiconductor substrate SUBj serving as the drain and the gate electrode GE is smaller than the distance between the semiconductor substrate SUBj and the source region SR. In a state where the junction FET is off, a reverse voltage (reverse bias) is applied to the gate electrode GE and the drift layer DFTj. As a result, it is considered that the leakage current flowing through the junction FET at the off time flows mainly as a reverse current (leakage current) between the semiconductor substrate SUBj and the gate electrode GE, which are short in distance, compared to the leakage current flowing between the semiconductor substrate SUBj and the source region SR. Therefore, according to embodiment 2, after the junction FET is turned off, the leakage current flowing between the drain and the source of the junction FET can be significantly reduced. As described above, according to embodiment 2, it is possible to suppress the increase of the drain voltage of the MOSFET to a voltage equal to or higher than the withstand voltage due to the leakage current flowing between the drain and the source of the junction FET at the time of off-state, thereby effectively preventing the MOSFET from avalanche operation and eventually causing the MOSFET to break down. Further, according to the junction FET having the trench structure shown in fig. 33, since the junction FET can be formed at high density, it is needless to say that a switching element having high current density can be realized.

Next, fig. 34 is a cross-sectional view showing another device structure of the junction FET in embodiment 2. As shown in fig. 34, the other junction FET in embodiment 2 includes a semiconductor substrate SUBj, and a drain electrode DEj is formed on the back surface of the semiconductor substrate SUBj. On the other hand, a drift layer DFTj is formed on the main surface side of the semiconductor substrate SUBj opposite to the back surface, and a plurality of gate electrodes GE are formed on the drift layer DFTj so as to be separated and embedded therein. Further, a source region SR is formed on the surface of the drift layer DFTj between the adjacent gate electrodes GE. The junction FET shown in fig. 34 configured as described above is a so-called vertical junction FET having no trench structure.

In the junction FET having such a structure, the channel length CL of the channel formation region is 1 μm or more. In other words, the distance (channel length CL) between the bottom of the source region SR and the bottom of the gate electrode GE is 1 μm or more. Thus, since the channel length of the channel formation region can be increased, the electrostatic potential in the channel formation region at the time of off-state can be increased even in the junction FET shown in fig. 34. As a result, it is understood that the junction FET shown in fig. 34 can suppress the leakage current flowing between the drain and the source of the junction FET to be smaller than the case of using a device structure having a channel length of about 0.5 μm. In this manner, the advantage of making the channel length CL 1 μm or more is that the electrostatic potential in the channel formation region at the time of off-state can be increased to reduce the leakage current, and it is considered that the extension of the channel length CL itself contributes to the reduction of the leakage current.

The junction FET shown in fig. 34 has an advantage in that the device configuration is simple and the manufacturing cost can be reduced. In addition, in the junction FET shown in fig. 33, it is necessary to form a conductive type impurity (p-type impurity) on the side surface of the channel TR by a highly difficult oblique ion implantation technique or the like, whereas in the junction FET shown in fig. 34, it is not necessary to use a highly difficult oblique ion implantation technique for forming the gate electrode GE, and there is an advantage that the impurity profile introduced into the gate electrode GE is highly accurate. That is, the junction FET shown in fig. 34 has an advantage that a junction FET having uniform characteristics can be easily formed.

The invention made by the present inventors has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and it is needless to say that various modifications can be made within a range not departing from the gist thereof.

For example, in the above-described embodiment, the gate electrode of the MOSFET is driven by the gate driver circuit (gate driver), but the gate electrode of the junction FET may be driven simultaneously by the gate driver circuit. In this case, the gate electrode of the junction FET is controlled by the gate drive circuit, whereby the source electrode of the junction FET can be controlled to a desired level. In the case of this structure, although the number of terminals is increased, an advantage of a switching element capable of providing lower loss is obtained.

In the package described in embodiment 1, the lead arrangement is not limited to this. That is, the arrangement positions of the gate lead, the drain lead, and the source lead can be variously changed. For example, when the package is mounted on the mounting substrate, the lead arrangement of the package can be determined so that the conventional lead arrangement can be used. In this case, it is not necessary to change the mounting substrate, and an increase in cost due to a change in design can be suppressed.

The layout structure of the stacked semiconductor chips is not limited to the layout structure described in the specification, and the shape of each semiconductor chip, the shape of the pad, the shape of the termination region, and the like are not particularly limited. The structures of the junction FET and the MOSFET are not limited, and various conventional structures can be applied. Furthermore, the impurity distribution of the device can be freely changed. For example, in the MOSFET, the impurity concentration at the surface may be made small to avoid punch-through, and the impurity may be implanted so that the impurity concentration gradually increases in the depth direction.

The MOSFET is not limited to the case where the gate insulating film is formed of an oxide film, and a MISFET (Metal Insulator Semiconductor Field effect transistor) in which the gate insulating film is formed of an insulating film by enlarging the gate insulating film is assumed to be included. That is, in the present specification, the term of the MOSFET is used for convenience of description, but the MOSFET is used in the present specification as a term intended to include the MISFET.

As the metal material of each of the above-mentioned leads, gold (Au), gold alloy, copper (Cu), copper alloy, aluminum (Al), aluminum alloy, or the like can be used.

The switching element of the present invention can be applied to, for example, a power supply circuit, but is not limited to this, and can also be applied to various devices such as an inverter for air conditioning, a power conditioner for a solar power generation system, an inverter for a hybrid vehicle or an electric vehicle, a power module for a computer, and an inverter for a white LED.

Industrial applicability

The present invention can be widely applied to the manufacturing industry of manufacturing semiconductor devices.

Description of the reference numerals

ACTj active area

ACTm active area

CHP1 semiconductor chip

CHP2 semiconductor chip

Length of CL channel

CLP clip

D drain electrode

D1 drain electrode

D2 drain electrode

DEj drain electrode

DEm drain electrode

DFTj drift layer

DFTm drift layer

Dj1 drain electrode

Dj2 drain electrode

DL drain lead

Dm drain

Dm1 drain

Dm2 drain

G gate electrode

GE gate electrode

Gj gate electrode

Gj1 gate electrode

Gj2 gate electrode

GL gate lead

Gm gate electrode

Gm1 gate electrode

Gm2 gate electrode

GOX gate insulating film

GPj gate pad

GPm grid electrode bonding pad

GPST grid pin part

Id rated current

Idl leakage current

IL1 insulating film

IL2 insulating film

Lgi1 parasitic inductance

Lgi2 parasitic inductance

LL load inductance

Ls parasitic inductance

Lse1 parasitic inductance

Lse2 parasitic inductance

MR seal

PKG1 packaging

PKG2 packaging

PKG3 packaging

PKG4 packaging

PKG5 packaging

PKG6 packaging

PKG7 packaging

PKG8 packaging

PKG9 packaging

PKG10 packaging

PKG11 packaging

PKG12 packaging

PKG13 packaging

PLT chip mounting part

PLT1 chip mounting part

PLT2 chip mounting part

PR body region

Q1 junction FET

Q1a junction FET

Q1b junction FET

Q2 MOSFET

Q2a MOSFET

Q2b MOSFET

S source electrode

S1 Source

S2 Source

SE source electrode

Intermediate node of Se

Sj source electrode

Sj1 source

Sj2 source

SL source lead

Sm source electrode

Sm1 source

Sm2 source

SPj source pad

SPm source pad

SPST source pin part

SR source region

SUBj semiconductor substrate

SUBm semiconductor substrate

TMj terminating area

TMm terminating area

TR groove

Vak voltage

Vdsu voltage

Vdsmu voltage

Vdsmd voltage

Wds conducting wire

Wgj conducting wire

Wgm conducting wire

Wsm conductor

Claims (26)

1. A semiconductor device, comprising:

a normally-open junction FET which is made of a material having a larger band gap than silicon, and which has a 1 st gate electrode, a 1 st source electrode, and a 1 st drain electrode; and

a normally-off MOSFET, which is made of silicon and has a 2 nd gate electrode, a 2 nd source and a 2 nd drain,

the 1 st source of the junction FET and the 2 nd drain of the MOSFET are electrically connected, and the 1 st gate electrode of the junction FET and the 2 nd source of the MOSFET are electrically connected, thereby forming a cascade connection,

the semiconductor device is characterized by comprising:

(a) a 1 st semiconductor chip having a 1 st surface and a 1 st back surface opposite to the 1 st surface, wherein a 1 st source pad electrically connected to the 1 st source of the junction FET and a 1 st gate pad electrically connected to the 1 st gate electrode of the junction FET are formed on the 1 st surface, and the 1 st back surface is electrically connected to the 1 st drain of the junction FET;

(b) a 2 nd semiconductor chip having a 2 nd surface and a 2 nd backside opposite to the 2 nd surface, wherein a 2 nd source pad electrically connected to the 2 nd source of the MOSFET and a 2 nd gate pad electrically connected to the 2 nd gate electrode of the MOSFET are formed on the 2 nd surface, and the 2 nd backside is electrically connected to the 2 nd drain of the MOSFET;

(c) a 1 st chip mounting portion having a 1 st upper surface on which the 1 st semiconductor chip is mounted via a 1 st conductive adhesive material;

(d) a drain lead connected to the 1 st chip mounting portion;

(e) a source lead electrically insulated from the drain lead;

(f) a gate lead electrically insulated from the drain lead and the source lead;

(g) a 1 st metal conductor electrically connecting the 1 st gate pad and the source lead of the 1 st semiconductor chip; and

(h) a sealing body sealing the 1 st semiconductor chip, the 2 nd semiconductor chip, a part of the 1 st chip mounting portion, a part of the drain lead, a part of the source lead, a part of the gate lead, and the 1 st metal conductor,

the 1 st source pad of the 1 st semiconductor chip and the 2 nd back surface of the 2 nd semiconductor chip are electrically connected,

the 2 nd gate pad of the 2 nd semiconductor chip and the gate lead are electrically connected,

the 2 nd source pad of the 2 nd semiconductor chip and the source lead are electrically connected,

the 1 st gate pad of the 1 st semiconductor chip is disposed closer to the source lead than the other leads.

2. The semiconductor device according to claim 1,

the 2 nd gate pad and the gate lead of the 2 nd semiconductor chip are electrically connected by a 2 nd metal conductor,

the 2 nd gate pad of the 2 nd semiconductor chip is disposed closer to the gate lead than the 2 nd source pad.

3. The semiconductor device according to claim 2,

the conductor width of the 1 st metal conductor is larger than that of the 2 nd metal conductor.

4. The semiconductor device according to claim 2,

the 2 nd semiconductor chip is mounted on the 1 st source pad of the 1 st semiconductor chip via a 2 nd conductive adhesive material so that the 2 nd back surface of the 2 nd semiconductor chip and the 1 st source pad of the 1 st semiconductor chip are opposed to each other.

5. The semiconductor device according to claim 4,

the 1 st semiconductor chip is disposed on the 1 st chip mounting portion so as to be closer to the source lead than the other leads.

6. The semiconductor device according to claim 4,

the 2 nd source pad and the source lead of the 2 nd semiconductor chip are electrically connected by a 3 rd metal conductor.

7. The semiconductor device according to claim 6,

the 1 st metal conductor, the 2 nd metal conductor and the 3 rd metal conductor are respectively welding wires.

8. The semiconductor device according to claim 7,

there are a plurality of said 3 rd metal conductors for the bonding wires.

9. The semiconductor device according to claim 4,

the 1 st conductive adhesive material and the 2 nd conductive adhesive material are any one of silver solder and solder.

10. The semiconductor device according to claim 6,

the source lead has a source lead post portion,

the gate lead has a gate lead post portion,

the 1 st metal conductor and the 3 rd metal conductor are connected with the source lead post portion,

the 2 nd metal conductor is connected with the gate lead post portion.

11. The semiconductor device according to claim 10,

the region of the source terminal portion to which the 1 st metal conductor and the 3 rd metal conductor are connected and the region of the gate terminal portion to which the 2 nd metal conductor are connected are located higher than the 1 st upper surface of the 1 st chip mounting portion.

12. The semiconductor device according to claim 1,

the solid sealing body is provided with a 1 st side and a 2 nd side opposite to the 1 st side,

the drain lead, the gate lead, and the source lead protrude from the 1 st side of the encapsulation body.

13. The semiconductor device according to claim 12,

the drain lead is disposed between the gate lead and the source lead.

14. The semiconductor device according to claim 1,

further comprising a 2 nd chip mounting part having a 2 nd upper surface on which the 2 nd semiconductor chip is mounted and electrically insulated from the 1 st chip mounting part,

the 2 nd back surface of the 2 nd semiconductor chip and the 2 nd upper surface of the 2 nd chip mounting portion are electrically connected via a 3 rd conductive adhesive material,

the 1 st source pad of the 1 st semiconductor chip and the 2 nd upper surface of the 2 nd chip mounting portion are electrically connected by a 4 th metal conductor.

15. The semiconductor device according to claim 14,

the 4 th metal conductor is a welding wire.

16. The semiconductor device according to claim 14,

a part of the solid sealing body is disposed between the 1 st chip mounting portion and the 2 nd chip mounting portion.

17. The semiconductor device according to claim 1,

the 1 st chip mounting part further has a 1 st lower surface opposite to the 1 st upper surface,

the 1 st lower surface of the 1 st chip mounting portion is exposed from the sealing body.

18. The semiconductor device according to claim 1,

the solid sealing body is provided with a 1 st side and a 2 nd side opposite to the 1 st side,

the gate lead and the source lead protrude from the 1 st side of the encapsulation body,

the drain lead protrudes from the No. 2 side of the encapsulant.

19. The semiconductor device according to claim 1,

the 1 st metal conductor is also electrically connected to the 2 nd source pad of the 2 nd semiconductor chip,

the 1 st metal conductor is a metal plate.

20. The semiconductor device according to claim 19,

the metal plate is made of a copper material.

21. The semiconductor device according to claim 1,

the junction FET is made of silicon carbide.

22. The semiconductor device according to claim 1,

the junction FET has:

a semiconductor substrate to be the 1 st drain;

a drift layer formed on a main surface of the semiconductor substrate;

a plurality of trenches formed in the drift layer;

the 1 st gate electrode formed on a side surface and a bottom surface of each of the plurality of trenches;

a channel forming region sandwiched between the gate electrodes formed on the side surfaces and the bottom surface of the adjacent trenches; and

the 1 st source electrode formed on the channel formation region,

the length of the channel forming region is 1 [ mu ] m or more.

23. The semiconductor device according to claim 1,

the junction FET has:

a semiconductor substrate to be the 1 st drain;

a drift layer formed on a main surface of the semiconductor substrate;

a plurality of trenches formed in the drift layer;

the 1 st gate electrode formed on a side surface and a bottom surface of each of the plurality of trenches;

a channel forming region sandwiched between the gate electrodes formed on the side surfaces and the bottom surface of the adjacent trenches; and

the 1 st source electrode formed on the channel formation region,

the distance between the bottom of the 1 st source and the bottom of the 1 st gate electrode is 1 [ mu ] m or more.

24. The semiconductor device according to claim 1,

the junction FET has:

a semiconductor substrate to be the 1 st drain;

a drift layer formed on a main surface of the semiconductor substrate;

a plurality of the 1 st gate electrodes formed on the drift layer separately from each other; and

the 1 st source electrode formed on the surface of the drift layer between the separately formed 1 st gate electrodes,

the distance between the bottom of the 1 st source and the bottom of the 1 st gate electrode is 1 [ mu ] m or more.

25. A semiconductor device, comprising:

a normally-open junction FET which is made of a material having a larger band gap than silicon, and which has a 1 st gate electrode, a 1 st source electrode, and a 1 st drain electrode; and

a normally-off MOSFET, which is made of silicon and has a 2 nd gate electrode, a 2 nd source and a 2 nd drain,

the 1 st source of the junction FET and the 2 nd drain of the MOSFET are electrically connected, and the 1 st gate electrode of the junction FET and the 2 nd source of the MOSFET are electrically connected, thereby forming a cascade connection,

the semiconductor device is characterized by comprising:

(a) a 1 st semiconductor chip having a 1 st surface and a 1 st back surface opposite to the 1 st surface, wherein a 1 st source pad electrically connected to the 1 st source of the junction FET and a 1 st gate pad electrically connected to the 1 st gate electrode of the junction FET are formed on the 1 st surface, and the 1 st back surface is electrically connected to the 1 st drain of the junction FET;

(b) a 2 nd semiconductor chip having a 2 nd surface and a 2 nd backside opposite to the 2 nd surface, wherein a 2 nd source pad electrically connected to the 2 nd source of the MOSFET and a 2 nd gate pad electrically connected to the 2 nd gate electrode of the MOSFET are formed on the 2 nd surface, and the 2 nd backside is electrically connected to the 2 nd drain of the MOSFET;

(c) a 1 st chip mounting portion having a 1 st upper surface on which the 1 st semiconductor chip is mounted via a 1 st conductive adhesive material;

(d) a drain lead connected to the 1 st chip mounting portion;

(e) a source lead electrically insulated from the drain lead;

(f) a gate lead electrically insulated from the drain lead and the source lead;

(g) a 1 st metal conductor electrically connecting the 1 st gate pad and the source lead of the 1 st semiconductor chip;

(h) a 2 nd metal conductor electrically connecting the 2 nd gate pad and the gate lead of the 2 nd semiconductor chip,

(i) a 3 rd metal conductor electrically connecting the 2 nd source pad of the 2 nd semiconductor chip and the source lead; and

(j) a sealing body sealing the 1 st semiconductor chip, the 2 nd semiconductor chip, a part of the 1 st chip mounting portion, a part of the drain lead, a part of the source lead, a part of the gate lead, the 1 st metal conductor, the 2 nd metal conductor, and the 3 rd metal conductor,

mounting the 2 nd semiconductor chip on the 1 st source pad of the 1 st semiconductor chip via a 2 nd conductive adhesive so that the 2 nd back surface of the 2 nd semiconductor chip and the 1 st source pad of the 1 st semiconductor chip are opposed to each other,

the 1 st gate pad of the 1 st semiconductor chip is disposed closer to the source lead than the other leads.

26. A semiconductor device, comprising:

a normally-open junction FET which is made of a material having a larger band gap than silicon, and which has a 1 st gate electrode, a 1 st source electrode, and a 1 st drain electrode; and

a normally-off MOSFET, which is made of silicon and has a 2 nd gate electrode, a 2 nd source and a 2 nd drain,

the 1 st source of the junction FET and the 2 nd drain of the MOSFET are electrically connected, and the 1 st gate electrode of the junction FET and the 2 nd source of the MOSFET are electrically connected, thereby forming a cascade connection,

the semiconductor device is characterized by comprising:

(a) a 1 st semiconductor chip having a 1 st surface and a 1 st back surface opposite to the 1 st surface, wherein a 1 st source pad electrically connected to the 1 st source of the junction FET and a 1 st gate pad electrically connected to the 1 st gate electrode of the junction FET are formed on the 1 st surface, and the 1 st back surface is electrically connected to the 1 st drain of the junction FET;

(b) a 2 nd semiconductor chip having a 2 nd surface and a 2 nd backside surface opposite to the 2 nd surface, wherein a 2 nd source pad electrically connected to the 2 nd source of the MOSFET and a 2 nd gate pad electrically connected to the 2 nd gate electrode of the MOSFET are formed on the 2 nd surface, and the 2 nd backside surface is electrically connected to the 2 nd drain of the MOSFET;

(c) a 1 st chip mounting portion having a 1 st upper surface on which the 1 st semiconductor chip is mounted via a 1 st conductive adhesive material;

(d) a 2 nd chip mounting portion having a 2 nd upper surface on which the 2 nd semiconductor chip is mounted via a 2 nd conductive adhesive material, and electrically insulated from the 1 st chip mounting portion;

(e) a drain lead connected to the 1 st chip mounting portion;

(f) a source lead electrically insulated from the drain lead;

(g) a gate lead electrically insulated from the drain lead and the source lead;

(h) a 1 st metal conductor electrically connecting the 1 st gate pad and the source lead of the 1 st semiconductor chip;

(i) a 2 nd metal conductor electrically connecting the 2 nd gate pad and the gate lead of the 2 nd semiconductor chip;

(j) a 3 rd metal conductor electrically connecting the 2 nd source pad of the 2 nd semiconductor chip and the source lead;

(k) a 4 th metal conductor electrically connecting the 1 st source pad of the 1 st semiconductor chip and the 2 nd upper surface of the 2 nd chip mounting portion; and

(l) A sealing body sealing the 1 st semiconductor chip, the 2 nd semiconductor chip, a part of the 1 st chip mounting portion, a part of the 2 nd chip mounting portion, a part of the drain lead, a part of the source lead, a part of the gate lead, the 1 st metal conductor, the 2 nd metal conductor, the 3 rd metal conductor, and the 4 th metal conductor,

the 1 st gate pad of the 1 st semiconductor chip is disposed closer to the source lead than the other leads.