HK1195397B - Method of manufacturing semiconductor device - Google Patents

Description

Method for manufacturing semiconductor device

Cross reference to related applications

The disclosure of japanese patent application No.2012-212494, filed on 9/26/2012, including the specification, drawings and abstract, is incorporated herein by reference in its entirety.

Technical Field

The present invention relates to a technique for manufacturing a semiconductor device, and to a technique that can be effectively applied to a technique for manufacturing a semiconductor device sealed with, for example, resin.

Background

Japanese patent laid-open No.2001-257291 describes a technique in which a solder material (e.g., solder) is used for coupling between one conductive via and one circuit element, whereas a conductive paste (e.g., Ag paste) is used for coupling between another conductive via and another circuit element.

In japanese patent laid-open No.2010-114454, one semiconductor chip is mounted over a wiring substrate, and the wiring substrate and the one semiconductor chip are coupled to each other using a first solder. The first solder is formed of a high melting point solder (e.g., Pb (lead) -Sn (tin) solder containing Pb (lead)) that is in a liquid state at a temperature equal to or greater than, for example, 280 ℃. Further, the other semiconductor chip is also mounted over the wiring substrate, and the wiring substrate and the other semiconductor chip are coupled to each other using a second solder. The second solder is formed of, for example, a lead-free solder (e.g., tin (Sn) -silver (Ag) -copper (Cu) solder) that does not contain Pb (lead) that is in a liquid state at a temperature equal to or greater than 200 ℃.

Japanese patent laid-open No.2008-53748 describes a technique in which a control power MOSFET chip and a synchronous power MOSFET chip are provided. Then, drain terminals on the rear surfaces of the control power MOSFET chip and the synchronous power MOSFET chip, respectively, are bonded to the plate-like lead portion on the input side and the plate-like lead portion on the output side via, for example, a die bonding material (e.g., silver paste).

Disclosure of Invention

The semiconductor device is formed of, for example, a semiconductor chip having a semiconductor element (e.g., MOSFET (metal-oxide-semiconductor field effect transistor)) formed therein, and a package formed to cover the semiconductor chip. The package structure of such a semiconductor device includes various types, for example, BGA (ball grid array) packages, QFP (quad flat package) packages, and QFN (quad flat non-lead package) packages.

Here, QFN packages, for example, are of primary interest. In the technique of manufacturing the QFN package using the MAP molding technique, a technique of suppressing leakage of resin into the rear surface terminals by applying a tape to the rear surface of the substrate is employed.

Here, for example, there may be a case where there is a step of heating an adhesive for bonding a semiconductor chip to a chip mounting portion formed on a substrate at a first temperature. In this case, if the tape is applied to the rear surface of the substrate in advance before the heating step, the tape may not withstand the heat treatment at the first temperature when the first temperature is higher than the heat-resistant temperature of the tape.

Therefore, it can be considered that: the tape should be applied to the rear surface of the substrate after the heating step described above is performed. However, in this case, the semiconductor chip has already been mounted on the upper surface side of the substrate, and thus it may be difficult to stably apply the tape to the rear surface of the substrate while supporting the upper surface side of the substrate.

Other objects and novel features of the present invention will become apparent from the description of the specification and drawings.

According to an embodiment, after the heating step of heating the first conductive adhesive and the second conductive adhesive at the first temperature is performed, a tape applying step for applying a tape on a face of the first lead frame opposite to a face on which the first semiconductor chip is mounted is performed. Here, the tape applying step applies the tape to the first lead frame while supporting the first metal plate.

Further, according to an embodiment, after the heating step of heating the first conductive adhesive and the second conductive adhesive at the first temperature is performed, the tape applying step of applying the tape on the face of the first lead frame opposite to the face on which the first semiconductor chip is mounted is performed. Subsequently, after the second semiconductor chip is mounted on the second chip mounting portion via the third conductive adhesive, the second conductive adhesive is heated at a second temperature. Here, the second temperature is lower than the first temperature.

According to an embodiment, the reliability of applying the tape to the rear surface of the substrate may be improved while ensuring heat resistance of the tape applied to the rear surface of the substrate.

Drawings

Fig. 1 is a view showing a circuit configuration of a step-down DC/DC converter;

fig. 2 is a view showing a package configuration of a semiconductor device in the first embodiment;

fig. 3 is a plan view seen from the lower surface (rear surface) of the semiconductor device in the first embodiment;

fig. 4 is a view showing an internal configuration of a semiconductor device in the first embodiment;

fig. 5 is a sectional view showing an example of a resin sealing step in the case of forming a general QFN package using an individual molding technique;

fig. 6 is a sectional view showing an example of a resin sealing step in the case of forming a general QFN package using the MAP molding technique;

fig. 7 is a sectional view showing a configuration in which a tape is previously applied to the rear surface of the lead frame;

fig. 8 is a sectional view showing a configuration in which a semiconductor chip is mounted over a chip mounting portion in a state where a tape is applied to a rear surface of a lead frame;

fig. 9 is a sectional view showing a configuration in which a semiconductor chip is mounted over a chip mounting portion via a high melting point solder without applying a tape to the rear surface of a lead frame prepared in advance;

fig. 10 is a sectional view showing a configuration in which a tape is applied to the rear surface of a lead frame in a state in which a semiconductor chip is mounted on a chip mounting portion via a high-melting-point solder;

fig. 11 is a flowchart showing a manufacturing flow of a semiconductor device in the first embodiment;

fig. 12 is a flowchart showing a manufacturing flow of the semiconductor device in the first embodiment;

fig. 13 is a flowchart showing a manufacturing flow of the semiconductor device in the first embodiment;

fig. 14A is a view showing a schematic overall configuration of a lead frame, fig. 14B is an enlarged view showing a part of the lead frame shown in fig. 14A, and fig. 14C is a further enlarged view showing the part of the lead frame shown in fig. 14B;

fig. 15A is a view showing a schematic overall configuration of a clip sub-assembly, and fig. 15B is an enlarged view showing a part of the clip sub-assembly;

fig. 16 is a plan view showing a manufacturing process of the semiconductor device in the first embodiment;

fig. 17 is a plan view showing the manufacturing process of the semiconductor device after fig. 16;

fig. 18 is a plan view showing the manufacturing process of the semiconductor device after fig. 17;

fig. 19 is a plan view showing the manufacturing process of the semiconductor device after fig. 18;

fig. 20A and 20B show a manufacturing process of the semiconductor device after fig. 19, fig. 20A is a plan view showing the process, and fig. 20B is a sectional view showing the process;

fig. 21A and 21B illustrate a manufacturing process of the semiconductor device subsequent to fig. 20A and 20B, fig. 21A being a plan view illustrating the process, and fig. 21B being an enlarged plan view illustrating a partial region of fig. 21A;

fig. 22 is a view showing a manufacturing process of the semiconductor device after fig. 21A and 21B;

fig. 23 is a plan view as seen from the rear surface of fig. 22;

fig. 24A and 24B show a manufacturing process of the semiconductor device subsequent to fig. 22 and 23, fig. 24A being a plan view showing the process, and fig. 24B being a side view showing the process;

fig. 25A to 25C show a manufacturing process of the semiconductor device subsequent to fig. 24A and 24B, fig. 25A is a plan view showing the process, fig. 25B is a side view showing the process, and fig. 25C is a plan view showing the semiconductor device which has been singulated in this step;

fig. 26A is a view showing a configuration of a lead frame immediately before tape is applied to a rear surface of the lead frame, and fig. 26B is an enlarged view showing a part of fig. 26A;

fig. 27A is a plan view showing a schematic overall configuration of a support member used in the first embodiment, and fig. 27B is an enlarged view showing a part of fig. 27A;

fig. 28 is a sectional view showing how a tape is applied to the rear surface of the lead frame in a state where the upper surface side of the lead frame is supported by a support member;

fig. 29 is a sectional view showing how a tape is applied to the rear surface of a lead frame in a state where the upper surface side of the lead frame is supported by a support member in modification 1 of the first embodiment;

fig. 30 is a sectional view showing how a tape is applied to the rear surface of a lead frame in a state where the upper surface side of the lead frame is supported by a support member in modification 2 of the first embodiment;

FIG. 31 is a graph showing the longitudinal modulus of elasticity, Shore A hardness (Shore A hardness), and Vickers hardness (Vickers hardness) of various materials;

fig. 32 is a view showing a package configuration of a semiconductor device in the second embodiment;

fig. 33 is a plan view seen from the lower surface (rear surface) of the semiconductor device in the second embodiment;

fig. 34 is a view showing an internal configuration of a semiconductor device in the second embodiment;

fig. 35 is a flowchart showing a manufacturing flow of the semiconductor device in the second embodiment;

fig. 36 is a flowchart showing a manufacturing flow of the semiconductor device in the second embodiment;

fig. 37 is a flowchart showing a manufacturing flow of a semiconductor device in the second embodiment;

fig. 38A is a view showing a schematic overall configuration of a clip frame (clip frame), and fig. 38B is an enlarged view showing a part of the clip frame;

fig. 39 is a plan view showing a manufacturing process of the semiconductor device in the second embodiment;

fig. 40A and 40B show a manufacturing process of the semiconductor device after fig. 39, fig. 40A is a plan view showing the process, and fig. 40B is a sectional view showing the process;

fig. 41A and 41B show a manufacturing process of the semiconductor device subsequent to fig. 40A and 40B, fig. 41A is a plan view showing the process, and fig. 41B is an enlarged view showing a partial region of fig. 41A;

fig. 42A is a view showing a configuration of a lead frame immediately before a tape is applied to a rear surface of the lead frame, and fig. 42B is an enlarged view showing a part of fig. 42A;

fig. 43A is a plan view showing a schematic overall configuration of a support member used in the second embodiment, and fig. 43B is an enlarged view showing a part of fig. 43A;

fig. 44 is a sectional view showing how a tape is applied to the rear surface of the lead frame in a state where the upper surface side of the lead frame is supported by a support member;

fig. 45 is a sectional view showing how a tape is applied to the rear surface of a lead frame in a state where the upper surface side of the lead frame is supported by a support member in modification 1 of the second embodiment;

fig. 46 is a sectional view showing how a tape is applied to the rear surface of a lead frame in a state where the upper surface side of the lead frame is supported by a support member in modification 2 of the second embodiment;

fig. 47 is a view showing an internal configuration of a semiconductor device in the third embodiment;

fig. 48 is a flowchart showing a manufacturing flow of the semiconductor device in the third embodiment;

fig. 49 is a flowchart showing a manufacturing flow of the semiconductor device in the third embodiment;

fig. 50 is a flowchart showing a manufacturing flow of the semiconductor device in the third embodiment;

fig. 51 is a plan view showing a manufacturing process of the semiconductor device in the third embodiment;

fig. 52 is a plan view showing the manufacturing process of the semiconductor device after fig. 51;

fig. 53 is a plan view showing the manufacturing process of the semiconductor device after fig. 52;

fig. 54 is a plan view showing the manufacturing process of the semiconductor device after fig. 53;

fig. 55A and 55B show a manufacturing process of the semiconductor device subsequent to fig. 54, fig. 55A being a plan view showing the process, and fig. 55B being a sectional view showing the process;

fig. 56 is a plan view showing the manufacturing process of the semiconductor device after fig. 55A and 55B;

fig. 57 is a plan view showing the manufacturing process of the semiconductor device after fig. 56;

fig. 58A is a view showing a configuration of a lead frame immediately before tape is applied to a rear surface of the lead frame, and fig. 58B is an enlarged view showing a part of fig. 58A;

fig. 59A is a plan view showing a schematic overall configuration of a support member used in the third embodiment, and fig. 59B is an enlarged view showing a part of fig. 59A;

fig. 60 is a sectional view showing how a tape is applied to the rear surface of the lead frame in a state where the upper surface side of the lead frame is supported by a support member;

fig. 61 is a sectional view showing how a tape is applied to the rear surface of a lead frame in a state where the upper surface side of the lead frame is supported by a support member in a modification of the third embodiment;

fig. 62 is a view showing a configuration of a lead frame immediately before tape is applied to a rear surface of the lead frame in the fourth embodiment;

fig. 63 is a view showing a state in which a tape is applied to the rear surface of the lead frame in the fourth embodiment;

fig. 64 is a plan view showing a schematic overall configuration of a support member used in the fourth embodiment;

fig. 65 is a sectional view showing how a tape is applied to the rear surface of a lead frame in a state where the upper surface side of the lead frame is supported by a support member in a modification of the fourth embodiment;

fig. 66 is a view showing a wire bonding step in the fourth embodiment;

fig. 67 is a view showing the configuration of a lead frame immediately before tape is applied to the rear surface thereof in modification 1 of the fourth embodiment;

fig. 68 is a view showing a state in which a tape is applied to the rear surface of the lead frame in modification 1;

fig. 69 is a sectional view showing how a tape is applied to the rear surface of a lead frame in a state where the upper surface side of the lead frame is supported by a supporting member in modification 1;

fig. 70 is a view showing how a high MOS chip is mounted in modification 1;

fig. 71 is a view showing a wire bonding step in modification 1;

fig. 72 is a view showing the configuration of a lead frame immediately before tape is applied to the rear surface thereof in modification 2 of the fourth embodiment;

fig. 73 is a view showing a state in which a tape is applied to the rear surface of the lead frame in modification 2;

fig. 74 is a sectional view showing how a tape is applied to the rear surface of the lead frame in a state where the upper surface side of the lead frame is supported by a support member in modification 2; and

fig. 75 is a view showing a wire bonding step in modification 2.

Detailed Description

The following embodiments will be explained, which can be divided into a plurality of sections or embodiments if necessary for convenience. They are not independent of one another except where expressly indicated, but have, for example, the following relationships: one is a part of the other or a variation, detail and supplementary description of the whole.

In the following embodiments, when referring to the number of elements and the like (including numbers, numerical values, amounts, ranges, and the like), they may not be limited to a specific number, but may be larger or smaller than the specific number, except for the case where they are clearly specified in particular and the case where they are clearly limited to the specific number in theory.

Further, needless to say, in the following embodiments, an element (including a basic step and the like) is not necessarily indispensable except for the case where it is specifically and clearly indicated and the case where it is considered to be obviously indispensable from a theoretical point of view, and the like.

Similarly, in the following embodiments, when referring to the shape, positional relationship, and the like of an element or the like, a shape similar or analogous to the shape will be basically included except for the case where it is specifically and explicitly specified and the case where it is considered to be apparently incorrect from a theoretical point of view. The same applies to the values and ranges described above.

In all the drawings for explaining the embodiments, the same symbols are attached to the same components in principle, and repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(first embodiment)

< Circuit configuration and operation of DC/DC converter >

Fig. 1 is a view showing a circuit configuration of a step-down DC/DC converter. As shown in fig. 1, in the step-down DC/DC converter, the high MOS transistor QH and the low MOS transistor QL are coupled in series between the input terminal TE1 and the ground GND. Then, the inductor L and the load RL are coupled in series between the node NA between the high MOS transistor QH and the low MOS transistor QL and the ground GND, and the capacitor C is coupled in parallel with the load RL.

Further, the gate electrode of the high MOS transistor QH and the gate electrode of the low MOS transistor QL are coupled to the control circuit CC, and on/off of the high MOS transistor QH and on/off of the low MOS transistor QL are controlled by the control circuit CC. Specifically, the control circuit CC controls to turn off the low MOS transistor QL when the high MOS transistor QH is turned on and to turn on the low MOS transistor QL when the high MOS transistor QH is turned off.

Here, for example, when the high MOS transistor QH is turned on and the low MOS transistor QL is turned off, a current flows from the input terminal TE1 into the load RL via the high MOS transistor QH and the inductor L. Subsequently, if the high MOS transistor QH is turned off and the low MOS transistor QL is turned on, first, since the high MOS transistor QH is turned off, the current flowing from the input terminal TE1 to the load RL through the high MOS transistor QH and the inductor L is cut off. That is, the current flowing into the inductor L is cut off. However, if the current is reduced (switched off), the inductor L will try to maintain the current flowing through it. Then, since the low MOS transistor QL is on, a current will then flow from the ground GND to the load RL through the low MOS transistor QL and the inductor L. Subsequently, again, the high MOS transistor QH is turned on and the low MOS transistor QL is turned off. In the step-down DC/DC converter shown in fig. 1, when the input voltage Vin is input to the input terminal TE1, the output voltage Vout lower than the input voltage Vin will be output across the load RL by repeating such operations.

In the following, the reason why the output voltage Vout lower than the input voltage Vin is output across the load RL by repeating the above-described switching operation when the input voltage Vin is input to the input terminal TE1 will be briefly described. Note that, in the following, it is assumed that the current flowing through the inductor L is not intermittent.

First, it is assumed that the high MOS transistor QH is in the ON (ON) period T under the control of the control circuit CC_ONAnd an OFF period T_OFFThe switching operation is internally performed. The switching frequency is in this case f = 1/(T)_ON+T_OFF)。

Here, for example, in fig. 1, the capacitor C inserted in parallel with the load RL has the output voltage V that is not allowed_OUTA function that changes significantly in a short period of time. That is, in the step-down DC/DC converter shown in fig. 1, since the capacitor C having a relatively large capacitance value is inserted in parallel with the load RL, in a steady state, a ripple voltage contained within the output voltage Vout has a small value as compared with the output voltage Vout. Therefore, it is assumed that the output voltage Vout is a wave in a period of one switching operationKinetic energy can be neglected.

First, consider a case in which the high MOS transistor QH is on. Since it is assumed that the output voltage Vout does not fluctuate within one cycle, the voltage applied to the inductor L is (Vin-Vout) and can be considered constant. As a result, if the inductance of the inductor L is represented by L1, the on period T is_ONInternal current delta Δ I_ONGiven by equation (1).

ΔI_ON=(Vin–Vout)/L1×T_ON（1）

Then, a case where the high MOS transistor QH is off is considered. In this case, since the low MOS transistor QL is on, the voltage applied to the inductor L is 0-Vout = -Vout. Thus, during the off-period T_OFFInternal current delta Δ I_OFFGiven by equation (2).

ΔI_OFF=–Vout/L1×T_OFF（2）

Then, in the steady state, the current flowing through the inductor L will neither increase nor decrease within one cycle of the switching operation. In other words, when the current flowing through the inductor L increases or decreases within one cycle, this means that the state has not yet reached the steady state. Therefore, in the steady state, the formula (3) is satisfied.

ΔI_ON+ΔI_OFF=0 （3）

If the relationship of formula (1) and the relationship of formula (2) are substituted into this formula (3), formula (4) shown below can be obtained.

Vout=Vin×T_ON/(T_ON+T_OFF) （4）

In this formula (4), since T_ONNot less than 0 and T_OFFEqual to or greater than 0, so Vout < Vin remains. That is, the step-down DC/DC converter shown in fig. 1 is a circuit that outputs an output voltage Vout lower than an input voltage Vin. Then, can be controlled by the control circuit CCEquation (4) control of the switching operation to vary the on-period T_ONAnd an off-period T_OFFTo obtain an arbitrary output voltage Vout lower than the input voltage Vin. In particular, if control is made such that the conduction period T is made_ONAnd a cutoff period T_OFFBecomes constant, a fixed output voltage Vout can be obtained.

In this way, with the step-down DC/DC converter shown in fig. 1, it is possible to output the output voltage Vout lower than the input voltage Vin by controlling on/off of the high MOS transistor QH and on/off of the low MOS transistor QL with the control circuit CC.

< packaging configuration of DC/DC converter >

The control circuit CC, the low MOS transistor QL, and the high MOS transistor QH included in the DC/DC converter are commercialized as, for example, a single-package semiconductor device. Such a single-packaged semiconductor device (neither the inductor L nor the capacitor C shown in fig. 1) is a semiconductor device constituting a part of the DC/DC converter, but for the sake of simplicity, such a semiconductor device may be referred to as a semiconductor device constituting the DC/DC converter.

The semiconductor device is formed of a semiconductor chip having a semiconductor element (e.g., MOSFET (metal-oxide-semiconductor field effect transistor)) formed therein and a package formed to cover the semiconductor chip. The package has a function (1) of electrically coupling a semiconductor element formed within the semiconductor chip to an external circuit, and a function (2) of protecting the semiconductor chip from an external environment (e.g., humidity and temperature) and preventing damage due to vibration or impact and/or deterioration of characteristics of the semiconductor chip. Moreover, the package also has the following functions: such as a function (3) of facilitating the processing of the semiconductor chip, and a function (4) of radiating heat generated during the operation of the semiconductor chip and maximizing the function of the semiconductor element.

The package structure of the semiconductor device includes various types, for example, BGA (ball grid array) packages, QFP (quad flat package) packages, and QFN (quad flat non-lead package) packages. Among these package forms, the semiconductor device constituting a part of the above-described DC/DC converter is packaged and configured as, for example, a QFN package. Then, a package configuration of a semiconductor device including a QFN package constituting a part of the DC/DC converter will be described below.

Fig. 2 is a view showing a package configuration of the semiconductor device PK1 in the present first embodiment. In fig. 2, the pattern shown in the center is a plan view of the semiconductor device PK1 viewed from the upper surface, and shown at each of all sides thereof is a side view. As shown in fig. 2, the semiconductor device PK1 is covered with the resin MR having a rectangular shape in the present first embodiment. Then, as can be seen from the side view, the lead LD is exposed from the resin MR on the side surface of the semiconductor device PK 1.

Next, fig. 3 is a plan view of the semiconductor device PK1 in the present first embodiment as viewed from the lower surface (rear surface). As shown in fig. 3, the rear surface of the semiconductor device PK1 is further covered with the resin MR, whereas the chip mounting portion tab (l), the chip mounting portion tab (h) and the chip mounting portion tab (c) are exposed from the resin MR. Since the chip mounting portion tab (l), the chip mounting portion tab (h), and the chip mounting portion tab (c) are exposed from the rear surface of the semiconductor device PK1 in this manner, the heat radiation efficiency of the semiconductor device PK1 can be improved. In addition, the plurality of rear surface terminals BTE are exposed to the peripheral region (peripheral portion) of the semiconductor device PK1 having a rectangular shape. The rear surface terminal BTE constitutes a part of the lead LD.

Subsequently, the internal configuration of the semiconductor device PK1 is described. Fig. 4 is a view showing an internal configuration of the semiconductor device PK1 in the present first embodiment. In fig. 4, the pattern shown in the center is a plan view of the inside of the semiconductor device PK1 viewed from the upper surface side through the resin MR, and shown at each of all sides thereof is a sectional view.

In the pattern shown in the center of fig. 4, a low MOS chip chp (l) mainly formed of, for example, silicon is mounted on the chip mounting portion tab (l). Then, a source electrode pad sp (l) and a gate electrode pad gp (l), each of which is composed of, for example, an aluminum film, are formed on the upper surface of the low MOS chip chp (l). Note that here, a nickel (Ni) -gold (Au) film is formed over the source electrode pad sp (l) so that a low MOS clip clp (l) described later is electrically coupled to the source electrode pad sp (l) via a high melting point solder HS 2.

The lead line LD is disposed on a portion of the outside of the chip mounting portion tab (l), and is electrically coupled with the source electrode pad sp (l) of the low MOS chip chp (l) by the low MOS clip clp (l). That is, a low MOS clip clp (l) formed of, for example, a copper material is mounted over the source electrode pad sp (l) of the low MOS chip chp (l), and an end of the low MOS clip clp (l) is coupled to the lead LD. Specifically, as shown in the cross-sectional view on the lower side of fig. 4, the low MOS chip chp (l) is mounted over the chip mounting portion tab (l) via the high melting point solder HS1, and the low MOS clip clp (l) is mounted via the high melting point solder HS2 so as to cross over the lead LD from over the low MOS chip chp (l).

Then, in the drawing shown in the center of fig. 4, a high MOS chip chp (h) mainly formed of, for example, silicon is mounted over the chip mounting portion tab (h). Then, on the upper surface of the high MOS chip chp (h), a source electrode pad sp (h) and a gate electrode pad gp (h) each composed of, for example, an aluminum film are formed. Note that over the source electrode pad sp (h), a nickel (Ni) -gold (Au) film is formed here so that a high MOS clip clp (h) described later is electrically coupled to over the source electrode pad sp (h) via a high melting point solder HS 2.

The chip mounting portion tab (l) is disposed adjacent to the chip mounting portion tab (h). The chip mounting portion tab (l) and the source electrode pad sp (h) of the high MOS chip chp (h) are electrically coupled to each other through the high MOS clip clp (h). That is, a high MOS clip clp (h) formed of, for example, a copper material is mounted on the source electrode pad sp (h) of the high MOS chip chp (h), and an end portion of the high MOS clip clp (h) is coupled with the chip mounting portion tab (l). In particular, as shown in the left side sectional view of fig. 4, the high MOS chip chp (h) is mounted over the chip mounting portion tab (h) via the high melting point solder HS1, and the high MOS clip clp (h) is mounted via the high melting point solder HS2 so as to cross over from over the high MOS chip chp (h) to over the chip mounting portion tab (l).

Subsequently, in the drawing shown in the center of fig. 4, a driver IC chip chp (c) mainly formed of, for example, silicon is mounted over the chip mounting portion tab (c). Specifically, as shown in the right or upper side sectional view of fig. 4, the driver IC chip chp (c) is mounted on the chip mounting portion tab (c) via a high melting point solder HS 1. The control circuit CC shown in fig. 1 is formed within the driver IC chip chp (c). Then, an electrode pad PD made of, for example, an aluminum film is formed on the upper surface of the driver IC chip chp (c). A lead LD is arranged at a portion outside the chip mounting portion tab (c), and the lead LD and the electrode pad PD formed on the upper surface of the driver IC chip chp (c) are electrically coupled to each other by a wire W composed of, for example, a gold wire. In addition, as shown in fig. 4, the gate electrode pad gp (l) formed in the low MOS chip chp (l) and the electrode pad PD formed in the driver IC chip chp (c) are coupled to each other by a wire W. Similarly, the gate electrode pad gp (h) formed in the high MOS chip chp (h) and the electrode pad PD formed in the driver IC chip chp (c) are coupled to each other by a wire W.

How the semiconductor device PK1 formed in this manner in the present first embodiment constitutes a part of the DC/DC converter will be described below. In the pattern shown in the center of fig. 4, the low MOS transistor QL shown in fig. 1 is formed inside the low MOS chip chp (l) mounted on the chip mounting portion tab (l). Then, a source electrode pad sp (l) is formed on the upper surface of the low MOS chip chp (l), and the source electrode pad sp (l) is electrically coupled to the source region of the low MOS transistor QL formed within the low MOS chip chp (l). In addition, the gate electrode pad gp (l) is formed on the upper surface of the low MOS chip chp (l), and the source electrode pad gp (l) is electrically coupled to the gate electrode of the low MOS transistor QL formed within the low MOS chip chp (l). In addition, the rear surface of the low MOS chip chp (l) functions as a drain region (drain electrode) of the low MOS transistor QL.

Similarly, in the pattern shown in the center of fig. 4, the high MOS transistor QH shown in fig. 1 is formed within the high MOS chip chp (h) mounted on the chip mounting portion tab (h). Then, a source electrode pad sp (h) is formed on the upper surface of the high MOS chip chp (h), and the source electrode pad sp (h) is electrically coupled to the source region of the high MOS transistor QH formed within the high MOS chip chp (h). In addition, the gate electrode pad gp (h) is formed on the upper surface of the high MOS chip chp (h), and the gate electrode pad gp (h) is electrically coupled to the gate electrode of the high MOS transistor QH formed within the high MOS chip chp (h). In addition, the rear surface of the high MOS chip chp (h) functions as a drain region (drain electrode) of the high MOS transistor QH.

Here, as shown in fig. 4, the rear surface (drain electrode) of the low MOS chip chp (l) is electrically coupled to the chip mounting portion tab (l). Then, the chip mounting portion tab (l) and the source electrode pad sp (h) formed in the high MOS chip chp (h) are coupled to each other by the high MOS clip clp (h). From this, it can be seen that the drain electrode of the low MOS chip chp (l) and the source electrode pad sp (h) of the high MOS chip chp (h) will be electrically coupled to each other, thereby achieving the series connection between the high MOS transistor QH and the low MOS transistor QL shown in fig. 1.

Then, the source electrode pad sp (l) formed on the upper surface of the low MOS chip chp (l) is electrically coupled to the lead LD via the low MOS clip clp (l). Therefore, the source region of the low MOS transistor QL shown in fig. 1 can be coupled to ground GND by coupling the lead LD electrically coupled with the low MOS clip clp (l) to ground.

On the other hand, the rear surface (drain electrode) of the high MOS chip chp (h) is electrically coupled to the chip mounting portion tab (h) via the high melting point solder HS 1. Therefore, by electrically coupling the chip mounting portion tab (h) to the input terminal TE1, the drain region (drain electrode) of the high MOS transistor QH shown in fig. 1 can be coupled to the input terminal TE 1. In this way, the semiconductor device PK1 in the present first embodiment shown in fig. 4 constitutes a part of the DC/DC converter.

In the semiconductor device PK1 of the present first embodiment, for example, shown in fig. 4, the low MOS clip clp (l) is used for electrical coupling between the low MOS chip chp (l) and the lead LD, instead of using a wire. Similarly, in the present first embodiment, the high MOS clip clp (h) is also used for electrical coupling between the high MOS chip chp (h) and the chip mounting portion tab (l) instead of using a wire.

This is because the semiconductor device PK1 is used as a component of the DC/DC converter in the present first embodiment, and a high current flows in the current path coupled through the low MOS clip clp (l) or through the high MOS clip clp (h), and thus it is necessary to reduce the on-resistance as much as possible. That is, in the low MOS chip chp (l) or the high MOS chip chp (h), the low MOS transistor QL or the high MOS transistor QH for feeding a high current is formed, and in order to fully utilize the characteristics of these transistors (power transistors), the low MOS clip clp (l) or the high MOS clip clp (h) is used instead of using a wire. In particular, for the low MOS clip clp (l) and the high MOS clip clp (h), a copper material having a low resistivity is used, and it is also possible to increase the contact area, and thus the on-resistance of the low MOS transistor QL and the high MOS transistor QH can be reduced.

Therefore, from the viewpoint of reducing the on-resistance, for the coupling between the chip mounting portion tab (l) and the low MOS chip chp (l) mounted on the chip mounting portion tab (l) or for the coupling between the low MOS chip chp (l) and the low MOS clip clp (l), solder is used instead of silver paste. From a similar point of view, for the coupling between the chip mounting portion tab (h) and the high MOS chip chp (h) mounted on the chip mounting portion tab (h) or for the coupling between the high MOS chip chp (h) and the high MOS clip clp (h), solder is used instead of silver paste. That is, in the silver paste, silver filler is distributed within the thermosetting resin, and thus electrical conductivity and thermal conductivity become small compared to solder as a metal material. Thus, in the semiconductor device PK1 for the DC/DC converter requiring reduction of the on-resistance, solder having conductivity larger than that of the silver paste is used, thereby reducing the on-resistance of the low MOS transistor QL and the high MOS transistor QH. In particular, in the semiconductor device PK1 of the present first embodiment, since a current is also caused to flow through the rear surface of the low MOS chip chp (l) and the rear surface of the high MOS chip chp (h), it is important to reduce the connection resistance by changing the silver paste to solder from the viewpoint of reducing the on-resistance.

However, after the semiconductor device PK1 in the present first embodiment is completed as a product, it is mounted on a circuit board (mounting board). In this case, solder is used for coupling between the semiconductor device PK1 and the mounting board. In the case of the coupling by solder, heat treatment (reflow) is required in order to melt and couple the solder.

Here, when the solder used for the connection between the semiconductor device PK1 and the mounting board and the above-described solder used in the semiconductor device PK1 are the same material, the solder used inside the semiconductor device PK1 may be melted as well due to the heat treatment (reflow) applied in the coupling of the semiconductor device PK1 and the mounting board. In this case, the following failures occur: cracks are generated in the resin sealing the semiconductor device PK1 due to volume expansion caused by melting of the solder, and the melted solder leaks to the outside.

Thus, the high melting point solder HS1 or the high melting point solder HS2 is used for the connection between the chip mounting portion tab (l) and the low MOS chip chp (l) mounted on the chip mounting portion tab (l) or for the connection between the low MOS chip chp (l) and the low MOS clip clp (l). Similarly, the high-melting solder HS1 or the high-melting solder HS2 is used for the connection between the chip mounting portion tab (h) and the high MOS chip chp (h) mounted on the chip mounting portion tab (h) or for the connection between the high MOS chip chp (h) and the high MOS clip clp (h). In this case, the high-melting-point solder HS1 or the high-melting-point solder HS2 used within the semiconductor device PK1 is not melted by the heat treatment (reflow) applied to the connection between the semiconductor device PK1 and the mounting board. Therefore, it is possible to prevent failures such as a failure in which cracks are generated in the resin sealing the semiconductor device PK1 due to volume expansion caused by melting of the high melting point solder HS1 or the high melting point solder HS2, and a failure in which the melted solder leaks to the outside.

Here, as the solder used for the connection between the semiconductor device PK1 and the mounting board, solder represented by tin (Sn) -silver (Ag) -copper (Cu) whose melting point was about 220 ℃ was used, and the semiconductor device PK1 was heated to about 260 ℃ during reflow. Thus, for example, reference herein to a high melting solder is intended to mean a solder that does not melt even when heated to about 260 ℃. A typical one is, for example, a solder containing 90% by weight or more of Pb (lead) having a melting point of 300 ℃ or more and a reflow temperature of about 350 ℃.

Note that in the present first embodiment, for example, there is a high melting solder HS1 for the connection between the chip mounting portion tab (l) and the low MOS chip chp (l) or for the connection between the chip mounting portion tab (h) and the high MOS chip chp (h). Furthermore, there is a high melting solder HS2 for the connection between the low MOS chip chp (l) and the low MOS clip clp (l) or for the connection between the high MOS chip chp (h) and the high MOS clip clp (h). Basically, in the present first embodiment, it is assumed that the above-described high-melting-point solder HS1 and high-melting-point solder HS2 have the same material composition, but, for example, the high-melting-point solder HS1 and the high-melting-point solder HS2 may each be composed of a different material composition.

< room for improvement in transition from Individual Molding technique to MAP Molding technique >

The package form of the semiconductor device PK1 is a QFN package in the present first embodiment, but in particular, the semiconductor device PK1 corresponds to the form in which the package is manufactured by MAP molding technology (MAP: matrix array package, collective molding technology) in the present first embodiment described above.

Examples of a technique for sealing a semiconductor chip with a resin include a so-called individual molding technique for forming a sealing body for each product region provided in a substrate (a lead frame or a wiring substrate). However, in the individual molding technique, a passage (inlet or runner) for injecting resin needs to be formed for each product region, and the space needs to be secured, so it is difficult to increase the acquisition number of products.

For this reason, in recent years, there is a so-called MAP molding technique in which a plurality of product regions are contained in a cavity and the product regions are collectively sealed with resin. According to the MAP molding technique, the product regions can be densely arranged because it is not necessary to provide a passage for injecting resin for each product region. Thus, according to the MAP molding technique, the number of products to be obtained can be increased and thus cost reduction of the products can be achieved.

Now, attention is mainly paid to a QFN package also employed in the semiconductor device PK1 of the present first embodiment. For example, in the transition from the case where a QFN package is manufactured by the individual molding technique to the case where it is manufactured by the MAP molding technique, the technique typically used in the individual molding technique cannot sufficiently correspond to the transition from the viewpoint of improving the reliability of the QFN package, and thus there is room for improvement. This will be described with reference to the drawings.

Fig. 5 is a sectional view showing an example of a resin sealing step when a general QFN package is formed using an individual molding technique. As shown in fig. 5, a sheet ST is applied to an upper surface of the lower mold BM, and a lead frame is arranged above the sheet ST. Specifically, the chip mounting portion TAB and the lead LD, which are members of the lead frame, are arranged over the sheet ST. Then, the rear surface terminal BTE protrudes from the rear surface of the lead LD. On the other hand, over the chip mounting portion TAB, a semiconductor chip CHP is mounted via, for example, silver paste PST, and a pad (not shown) formed in the semiconductor chip CHP and a lead LD are electrically coupled to each other by a wire W. Then, as shown in fig. 5, in the individual molding technique, the lead frame having the semiconductor chip CHP mounted thereon is sandwiched by the upper mold UM and the lower mold BM via the cavity CAV. The cavity CAV formed at this time is separated for each product region, and the lead LD will be pressed by the protrusion provided in the upper mold UM for separation.

In this way, when the QFN package is manufactured by the individual molding technique, the lead frame (substrate) can be pressed for each product region by the upper die UM, and thus the protruding rear surface terminals BTE formed on the rear surface of the lead frame can be caused to bite into the sheets ST arranged on the lower die BM (sheet molding technique). Thus, when the QFN package is formed using the individual molding technique, the resin can be prevented from leaking into the rear surface terminal BTE (resin burr). That is, when the QFN package is manufactured by the individual molding technique, the leakage of the resin into the rear surface terminal BTE can be effectively suppressed by the sheet molding technique generally used in the individual molding technique. As a result, the reliability of the QFN package can be improved.

Then, consider the case where QFN packages are manufactured by MAP molding techniques. Fig. 6 is a sectional view showing an example of a resin encapsulation step when a general QFN package is formed using the MAP molding technique. As shown in fig. 6, a sheet ST is applied to an upper surface of the lower mold BM, and a lead frame is arranged above the sheet ST. Specifically, the chip mounting portion TAB and the lead LD, which are members of the lead frame, are arranged over the sheet ST. Then, the rear surface terminal BTE protrudes from the rear surface of the lead LD. On the other hand, over the chip mounting portion TAB, a semiconductor chip CHP is mounted via, for example, silver paste PST, and a pad (not shown) formed in the semiconductor chip CHP and a lead LD are electrically coupled to each other by a wire W. Then, as shown in fig. 6, in the MAP molding technique, the lead frame having the semiconductor chip CHP mounted thereon is sandwiched by the upper mold UM and the lower mold BM via the cavity CAV. The cavity CAV formed at this time is not separated for each product region, and a protrusion for separating the product regions is not disposed in the upper mold UM. That is, in the MAP molding technique, a plurality of product regions are contained in the cavity CAV, and thus the lead frame is not pressed by the upper mold UM for each product region. Therefore, when the QFN package is manufactured by the MAP molding technique, the rear surface terminal BTE cannot be urged to sufficiently bite into the sheet ST arranged on the lower mold BM, and thus the leakage of the resin into the rear surface terminal BTE (resin burr) cannot be sufficiently suppressed. As a result, manufacturing failures of QFN packages cannot be effectively suppressed.

As described above, in the transition from the case where a QFN package is manufactured by the individual molding technique to the case where it is manufactured by the MAP molding technique, the sheet molding technique generally used in the individual molding technique cannot sufficiently correspond to the transition from the viewpoint of improving the reliability of the QFN package, and thus there is room for improvement.

Then, when the QFN package is manufactured by the MAP molding technique, a technique for replacing the sheet molding technique employed in the individual molding technique is studied. In particular, as shown in fig. 7, it has been studied to apply an adhesive tape TP to the rear surface of the lead frame LF when the lead frame LF is prepared. In this case, the tape TP can be reliably applied to the rear surface terminals BTE formed on the rear surface of the lead frame LF. Therefore, similarly, in the resin sealing step employing the MAP molding technique, no gap is formed between the rear surface terminal BTE and the belt TP, and thus the leakage of the resin into the rear surface terminal BTE (resin burr) can be sufficiently suppressed.

The configuration in which the tape TP is applied to the rear surface of the lead frame LF in this manner mainly means that resin leakage to the rear side of the rear surface terminal BTE is sufficiently suppressed when the QFN package is manufactured by the MAP molding technique, but has another advantage.

For example, the wire bonding step is mainly focused. In the case of the individual molding technique, since a space region is secured between product regions, the wire bonding step may be performed while the space region disposed within the lead frame is pressed with a window clamp. Thus, the reliability of the wire bonding step can be improved.

However, in the case of the MAP molding technique, since a plurality of product regions are densely arranged, it is difficult to secure a sufficient space region pressed by the window type press plate in the lead frame. Then, within the lead frame corresponding to the MAP molding technique, in the wire bonding step, the lead frame is vacuum-sucked onto the heating block to be arranged, and thus the wire bonding step is performed with the lead frame fixed to the heating block. In this case, since there is a region (gap between patterns) without any lead in the lead frame itself, the lead frame cannot be vacuum-sucked onto the heating block.

In contrast, in a state where the tape TP is applied to the rear surface of the lead frame, the lead frame having the tape TP applied thereto can be easily vacuum-sucked. As a result, even for the lead frame corresponding to the MAP molding technique, the wire bonding step can be performed while the lead frame is reliably fixed by vacuum suction. As described above, in the lead frame corresponding to the MAP molding technique, the configuration in which the tape TP is applied to the rear surface of the lead frame LF has advantages of suppressing the leakage of the resin to the rear side of the rear surface terminal BTE and improving the ease of vacuum suction in the wire bonding step.

< room for further improvement by Using high melting point solder >

As shown in fig. 7, a configuration in which a tape TP is applied to the rear surface of the lead frame LF in advance is useful when the QFN package is manufactured by, for example, MAP molding technology. As shown in fig. 8, if such a configuration is adopted, the semiconductor chip CHP will be mounted on the chip mounting portion TAB in a state where the tape TP is applied to the rear surface of the lead frame LF.

Then, for example, consider a case in which the chip mounting portion TAB and the semiconductor chip CHP are bonded together by a silver paste. The silver paste is formed by, for example, a thermosetting resin (e.g., epoxy resin) dispersed with a silver filler, and is subjected to heat treatment to cure the silver paste. Therefore, the tape TP applied to the rear surface of the lead frame LF is also heated. However, the temperature of the heat treatment for curing the silver paste was about 125-200 ℃ and was lower than the heat-resistant temperature of the tape TP (e.g., about 250 ℃). Therefore, even if the heat treatment for curing the silver paste is performed in a state where the tape TP is applied to the rear surface of the lead frame LF, the tape TP can withstand the heat treatment.

However, as shown in fig. 8, when the chip mounting portion TAB is bonded with the semiconductor chip CHP with the high melting solder HS, the situation will be completely changed. That is, when the chip mounting portion TAB is bonded with the semiconductor chip CHP with the high melting point solder HS, a heat treatment (reflow) for melting the high melting point solder HS is required. The reflux temperature is, for example, about 350 c and exceeds the heat resistant temperature of the tape TP (e.g., about 250 c). Therefore, if the heat treatment for melting the high melting point solder HS is performed in a state where the tape TP is applied to the rear surface of the lead frame LF, the tape TP will not withstand the heat treatment.

Specifically, the tape TP is mainly composed of a base material portion and a paste portion. Typically, for the base material portion with TP, a polyimide resin is generally used and the polyimide resin has a thermal decomposition index of 500 ℃ or more. Therefore, the thermal decomposition temperature of the polyimide resin is higher than the reflow temperature of the above-described high melting point solder HS, and thus the base material portion with TP can withstand the heat in the reflow of the high melting point solder HS. On the other hand, since the heat resistant temperature of the paste portion is lower than the reflow temperature of the high melting point solder HS, the paste portion cannot withstand the reflow of the high melting point solder HS. That is, the heat-resistant temperature of the belt TP means the heat-resistant temperature of the paste portion constituting the belt TP.

As can be seen from the foregoing, when the QFN package is manufactured by the MAP molding technique, a configuration in which the tape TP is applied to the rear surface of the lead frame LF is useful, but when the high-melting solder HS is used for the connection between the chip mounting portion TAB and the semiconductor chip CHP, there is still room for further improvement from the viewpoint of maintaining the heat resistance of the tape TP. In particular, in the semiconductor device PK1 of the present first embodiment for the DC/DC converter that requires a reduction in on-resistance, a device for maintaining the heat resistance of the tape TP is required because a high melting point solder having higher electrical conductivity than that of the silver paste is used.

In this regard, the following techniques can be conceived to maintain the heat resistance of the tape TP. That is, as shown in fig. 9, the semiconductor chip CHP is mounted on the chip mounting portion TAB via the high melting point solder HS without applying the tape TP to the rear surface of the lead frame LF prepared in advance. Then, in this state, heat treatment (reflow) for melting the high melting point solder HS is performed. In this case, even if the reflow temperature of the high melting point solder HS is higher than the heat resistant temperature of the tape TP, the heat resistance of the tape TP does not cause a problem because the tape TP is not initially applied to the rear surface of the lead frame LF. That is, as shown in fig. 9, if the heat treatment (reflow) of the high melting point solder HS is performed before the tape TP is applied to the rear surface of the lead frame LF, the tape TP will withstand the heat treatment regardless of the temperature of the heat treatment. Then, subsequently, as shown in fig. 10, the tape TP is applied to the rear surface of the lead frame LF in a state where the semiconductor chip CHP is mounted over the chip mounting portion TAB via the high melting point solder HS.

In this case, unless the tape TP is applied to the rear surface of the lead frame LF in a state where the upper surface of the lead frame LF opposite to the rear surface to which the tape TP is applied is supported by, for example, a support member, it is difficult to stably apply the tape TP to the rear surface of the lead frame LF. That is, if the tape TP is applied to the rear surface of the lead frame LF in a state where the upper surface of the lead frame LF opposite to the rear surface to which the tape TP is applied is not supported by, for example, a support member, the lead frame LF will not be fixed. Thus, it is difficult to reliably apply the tape TP to the rear surface of the lead frame LF without including voids and the like.

However, as shown in fig. 10, the semiconductor chip CHP is mounted on an upper surface of the lead frame LF opposite to the rear surface to which the tape TP is applied. Therefore, when the upper surface of the lead frame LF opposite to the rear surface to which the tape TP is applied is directly supported by the support member, the upper surface of the semiconductor chip CHP will be also supported by the support member, and thus the pressing pressure from the support member is transmitted to the semiconductor chip CHP, and the semiconductor chip CHP may be damaged.

In summary, a configuration in which the tape TP is applied to the rear surface of the lead frame LF is useful when the QFN package is manufactured by MAP molding technology. However, when the high-melting solder HS is used for the connection between the chip mounting portion TAB and the semiconductor chip CHP, the configuration in which the tape TP is applied to the rear surface of the lead frame LF in advance has room for improvement from the viewpoint of maintaining the heat resistance of the tape TP. Then, it is thought that heat treatment (reflow) of the high melting point solder HS is performed before the tape TP is applied to the rear surface of the lead frame LF. In this case, however, the tape TP will be applied to the rear surface of the lead frame LF in a state where the semiconductor chip CHP is mounted on the chip mounting portion TAB via the high melting point solder HS. Then, although a configuration can be conceived in which the upper surface of the lead frame LF opposite to the rear surface to which the tape TP is applied is directly supported by the support member, the upper surface of the semiconductor chip CHP will be supported by the support member as well, and the pressing pressure from the support member is transmitted to the semiconductor chip CHP and thus may damage the semiconductor chip CHP. Here, there is room for improvement.

Thus, in the method for manufacturing the semiconductor device in the present first embodiment shown below, a device is realized that is free from the disclosed improvement. Hereinafter, a method for manufacturing the semiconductor device in the present first embodiment to realize the device is described with reference to the drawings.

< method of manufacturing semiconductor device in first embodiment >

The semiconductor device in the present first embodiment is, for example, a semiconductor device PK1 constituting a part of a DC/DC converter and is packaged and configured as a QFN package, as shown in fig. 4. Then, hereinafter, the technical idea in the present first embodiment will be described by taking, as an example, a method for manufacturing the semiconductor device PK1 configured by a QFN package constituting a part of the DC/DC converter.

Fig. 11 to 13 show a flowchart for explaining the manufacturing flow of the semiconductor device PK1 in the present first embodiment. Further, fig. 14A to 25C are views each showing a manufacturing process of the semiconductor device PK1 in the present first embodiment.

First, as shown in fig. 14A to 14C, a lead frame LF1 is prepared (S101 of fig. 11). A schematic overall configuration of the lead frame LF1 is shown in fig. 14A, while a part of the lead frame LF1 is enlarged and shown in fig. 14B. In addition, in fig. 14C, the portion of the lead frame LF1 shown in fig. 14B is further enlarged and shown.

As shown in fig. 14C, in the lead frame LF1 of the present first embodiment, a plurality of product regions PR each including a chip mounting portion tab (C), a chip mounting portion tab (h), a chip mounting portion tab (l), and leads LD are arranged in a matrix.

Further, in the present first embodiment, a clip subassembly CLP shown in fig. 15A and 15B was also prepared. A schematic overall configuration of the clip subassembly CLP is shown in fig. 15A, and a part of the clip subassembly CLP is enlarged and shown in fig. 15B. As shown in fig. 15B, a plurality of cell regions UR each including a high MOS clip CLP (h) and a low MOS clip CLP (l) are included in the clip subassembly CLP, and the cell regions UR are arranged in a line. Here, the high MOS clip clp (h) and the low MOS clip clp (l) are composed of, for example, a metal plate containing copper as a material component.

Then, as shown in fig. 16, in each product region PR formed in the lead frame LF1, a high melting solder HS1 is formed over the chip mounting portion tab (c), the chip mounting portion tab (h), and the chip mounting portion tab (l) (S102 of fig. 11). Specifically, for example, the high melting solder HS1 is printed over the chip mounting portion tab (c), the chip mounting portion tab (h), and the chip mounting portion tab (l) using a solder printing method.

The high melting point solder HS1 mentioned herein means a solder that does not melt even if heated to about 260 ℃, and examples of the solder include a lead-rich high melting point solder containing a large amount of Pb (lead), in which the melting point of lead is equal to or greater than 300 ℃ and the reflow temperature of lead is about 350 ℃.

Subsequently, as shown in fig. 17, in each product region PR formed in the lead frame LF1, first, the driver IC chip chp (c) is mounted on the chip mounting portion tab (tab c) (S103 of fig. 11). Then, the high MOS chip chp (h) is mounted on the chip mounting portion tab (h) (S104 of fig. 11), and thereafter, the low MOS chip chp (l) is mounted on the chip mounting portion tab (l) (S105 of fig. 11). Note that the mounting order of the driver IC chip chp (c), the high MOS chip chp (h), and the low MOS chip chp (l) is not limited thereto, and may be changed as needed.

Then, as shown in fig. 18, in each product region PR formed in the lead frame LF1, a high-melting solder HS2 is formed over the high MOS chip chp (h) (S106 of fig. 11). Thereafter, the high melting solder HS2 is formed on the low MOS chip chp (l) (S107 of fig. 11). Specifically, high melting point solder HS2 is formed over a source electrode pad (high MOS pad) (not shown) formed in high MOS chip chp (h), and high melting point solder HS2 is also formed over a source electrode pad (low MOS pad) (not shown) formed in low MOS chip chp (l). Further, as shown in fig. 18, a high melting point solder HS2 is also formed over a partial region of the chip mounting portion tab (l) and over a partial region of the lead line.

In particular, high melting solder HS2 is also applied over the high MOS chip chp (h), over the low MOS chip chp (l), over a local area of the chip mounting portion tab (l), and over a local area of the lead, for example, using a coating method. The high melting point solder HS2 formed at this time may have the same material composition as the high melting point solder HS1 described above or may have a different material composition.

Subsequently, as shown in fig. 19, in each product region PR formed in the lead frame LF1, the high MOS clip CLP (h) taken out from the cell region UR of the clip subassembly CLP is mounted to span from above the high MOS chip chp (h) to the chip mounting portion tab (l) (S108 of fig. 11). Thus, the source electrode pad formed on the high MOS chip chp (h) and the chip mounting portion tab (l) will be electrically coupled to each other through the high MOS clip clp (h). Further, the low MOS clip CLP (l) taken out from the cell region UR of the clip subassembly CLP is mounted to cross over from above the low MOS chip chp (l) to the lead line to which the reference potential (GND potential) is supplied (S109 of fig. 11). Thus, the source electrode pad formed on the low MOS chip chp (l) and the lead line to which the reference potential is supplied will be electrically coupled to each other through the low MOS clip clp (l).

Note that the mounting order of the high MOS clip clp (h) and the low MOS clip clp (l) is not limited thereto, but may be changed as needed.

Subsequently, reflow is performed for the high melting point solder HS1 and the high melting point solder HS2 (S110 of fig. 12). In particular, the lead frame LF1 containing the high melting point solder HS1 and the high melting point solder HS2 is heated at a temperature (first temperature) of, for example, about 350 ℃. Thus, the high melting point solder HS1 and the high melting point solder HS2 can be melted.

Then, in the present first embodiment, the heat treatment (reflow) for melting the high melting point solder HS1 and the high melting point solder HS2 is performed in a state where the tape is not applied to the rear surface of the lead frame LF1 prepared in advance. Therefore, in the case of the present first embodiment, even if the reflow temperatures of the high-melting-point solder HS1 and the high-melting-point solder HS2 are higher than the heat-resistant temperature of the tape, the heat resistance of the tape does not cause a problem because the tape is not initially applied to the rear surface of the lead frame LF 1. That is, according to the present first embodiment, the heat treatment (reflow) of the high melting point solder HS1 and the high melting point solder HS2 is performed before the tape is applied to the rear surface of the lead frame LF1, and therefore the heat resistance of the tape can be ensured regardless of the temperature of the heat treatment (reflow).

Thereafter, in order to remove the flux contained in the high-melting solder HS1 and the high-melting solder HS2, flux cleaning is performed (S111 of fig. 12). Then, from the viewpoint of improving the bonding characteristics of the wires in the wire bonding step performed in the subsequent step, the upper surface of the lead frame LF1 is cleaned by performing plasma treatment on the upper surface of the lead frame LF1 (S112 of fig. 12).

Then, as shown in fig. 20A and 20B, the tape TP is applied to the rear surface of the lead frame LF1 (S113 of fig. 12). That is, in the face of the lead frame LF1, the tape TP is applied to the face opposite to the face on which the driver IC chip chp (c), the high MOS chip chp (h), and the low MOS chip chp (l) are mounted. Then, as described above, the heat treatment (reflow) at about 350 ℃ for the high melting point solder HS1 and the high melting point solder HS2 has been completed in a step before the step of applying the tape TP, and therefore, in the present first embodiment, the heat resistance of the tape TP will not be an issue.

That is, the reflow temperature of the above-described high-melting-point solder HS1 and high-melting-point solder HS2 is, for example, about 350 ℃, and exceeds the heat-resistant temperature of the tape TP (for example, about 250 ℃). Therefore, if the heat treatment for melting the high melting point solder HS1 and the high melting point solder HS2 is performed in a state where the tape TP is applied to the rear surface of the lead frame LF, the tape TP will not withstand the heat treatment. In this regard, in the present first embodiment, in the step before the step of applying the tape TP, the heat treatment (reflow) at about 350 ℃ for the high melting point solder HS1 and the high melting point solder HS2 has been completed. For this reason, in the present first embodiment, the heat resistance of the tape TP will not be a problem.

Here, unless the tape TP is applied to the rear surface of the lead frame LF1 in a state where the upper surface of the lead frame LF1 opposite to the rear surface to which the tape TP is applied is supported by, for example, a support member, it may be difficult to stably apply the tape TP to the rear surface of the lead frame LF 1. That is, if the tape TP is applied to the rear surface of the lead frame LF1 in a state where the upper surface of the lead frame LF1 opposite to the rear surface to which the tape TP is applied is not supported by, for example, a support member, the lead frame LF1 will not be fixed. Therefore, the reaction force generated by the lead frame LF1 in applying the tape TP to the rear surface of the lead frame LF1 becomes weak. As a result, it is difficult to reliably apply the tape TP to the rear surface of the lead frame LF1 without including voids and the like.

However, in the present first embodiment, in the step before the step of applying the tape TP, the driver IC chip chp (c), the high MOS chip chp (h), and the low MOS chip chp (l) have been mounted on the lead frame LF 1. Therefore, when the upper surface of the lead frame LF opposite to the rear surface to which the tape TP is applied is directly supported by the support member, for example, the upper surface of the driver IC chip chp (c) will be supported by the support member as well, and the pressing pressure from the support member is transmitted to the driver IC chip chp (c) and thus may damage the driver IC chip chp (c). Here, there is room for improvement.

Therefore, in the present first embodiment, a device is realized which is directed to significant room for improvement. That is, the present first embodiment features a method for fixing the lead frame LF1 while applying the tape TP to the rear surface of the lead frame LF 1. This characteristic will be described later.

Subsequently, as shown in fig. 21A and 21B, a wire bonding step (S114 of fig. 12) is performed. Fig. 21A is a view showing the lead frame LF1 when a lead frame bonding step is performed after the tape TP is applied to the rear surface of the lead frame LF 1. However, in fig. 21A, a member (wire) required when the actual wire bonding step is performed is omitted, and is shown in fig. 21B which is an enlarged view of one product region PR shown in fig. 21A.

In fig. 21B, a plurality of electrode pads PD and a plurality of leads LD formed in the driver IC chip chp (c) are coupled to each other by a plurality of wires W. In addition, as shown in fig. 21B, the gate electrode pad gp (h) formed in the high MOS chip chp (h) and the electrode pad PD formed in the driver IC chip chp (c) are coupled to each other by a wire W. Similarly, the gate electrode pad gp (l) formed in the low MOS chip chp (l) and the electrode pad PD formed in the driver IC chip chp (c) are coupled to each other by a wire W. Thus, according to the present first embodiment, the high MOS transistor QH (see fig. 1) formed in the high MOS chip chp (h) and the low MOS transistor QL (see fig. 1) formed in the low MOS chip chp (l) are electrically controlled by the control circuit CC (see fig. 1) formed in the driver IC chip chp (c).

Here, in the present first embodiment, since the MAP molding technique is applied to the molding step, the product regions PR are densely arranged in, for example, the lead frame LF1 shown in fig. 21A. For this reason, in the wire bonding step, it is difficult to secure a space area in the lead frame LF1 sufficient for pressing with the window type press plate.

Then, in the lead frame LF1 corresponding to the MAP molding technique, in the wire bonding step, the lead frame LF1 is vacuum-sucked to the heating block to be arranged, and thus the wire bonding step will be performed with the lead frame LF1 fixed to the heating block. In this case, for example, when the tape TP is not applied to the rear surface of the lead frame LF1, there is a region without any lead (a gap between patterns) and thus it is difficult to vacuum-suck the lead frame LF1 and fix it onto the heating block.

In contrast, according to the present first embodiment, the tape TP is applied to the rear surface of the lead frame LF1 in a step before the wire bonding step is performed. Therefore, according to the present first embodiment, the lead frame LF1 having the tape TP applied thereto can be easily vacuum-sucked. As a result, even with the lead frame LF1 corresponding to the MAP molding technique, the wire bonding step can be performed with the lead frame LF1 reliably fixed by vacuum suction. As a result, according to the present first embodiment, the reliability in the wire bonding step can be improved.

Note that the wire bonding step is performed in a state where the lead frame LF1 is heated to about 200 to about 250 ℃ for stabilizing the bonding of the wire W. However, since the heat-resistant temperature of the tape TP applied to the rear surface of the lead frame LF1 is about 250 ℃, the heat-resistant temperature of the tape TP does not cause a problem caused by the heat treatment applied in the wire bonding step.

Then, as shown in fig. 22, the product regions formed in the lead frame LF1 are collectively sealed (molded) with the resin MR (S115 of fig. 12). In other words, the sealing body is formed by collectively sealing the product region PR in the lead frame LF1 with the resin MR, thereby covering the driver IC chip chp (c), the high MOS chip chp (h), and the low MOS chip chp (l) shown in fig. 21B. That is, in the present first embodiment, as a technique for sealing the semiconductor chip with resin, a so-called MAP molding technique is employed in which the product region PR is contained in the cavity and the product region PR is collectively sealed with resin. According to this MAP molding technique, since it is not necessary to provide a passage for injecting resin for each product region PR, the product regions PR can be densely arranged. Therefore, according to the MAP molding technique, the number of products to be obtained can be increased and thus cost reduction of the products can be achieved.

Then, in the present first embodiment, the adhesive tape TP is applied to the rear surface of the lead frame LF1 in a step before the resin sealing step (molding step) performed with the MAP molding technique. Therefore, according to the present first embodiment, for example, as shown in fig. 23, the tape can be reliably applied to the rear surface terminals (leads) formed on the rear surface of the lead frame LF 1. As a result, similarly, in the resin sealing step employing the MAP molding technique, no gap is formed between the rear surface terminal and the tape TP, and thus the leakage of the resin to the rear side of the rear surface terminal (resin burr) can be sufficiently suppressed.

Note that as the resin used in the resin sealing step, for example, a thermosetting resin is used. Therefore, the resin sealing step is performed in a state of being heated to about 160 to about 200 ℃, so as to cure the thermosetting resin. However, since the heat-resistant temperature of the tape TP applied to the rear surface of the lead frame LF1 is about 250 ℃, the heat treatment applied in the resin sealing step does not cause a problem in the heat resistance of the tape TP.

Thereafter, the tape TP applied to the rear surface of the lead frame LF1 is peeled off from the lead frame LF1 (S116 of fig. 12). Then, plating films are formed on the upper surfaces of the chip mounting portion tab (c), the chip mounting portion tab (h), the chip mounting portion tab (l), and the rear surface terminals BTE exposed from the rear surface of the resin MR (sealing body) (see fig. 3) (S117 of fig. 12). Further, a mark is formed on the upper surface of the sealing body formed of the resin MR (marking step) (S118 of fig. 12).

Then, as shown in fig. 24A and 24B, a dicing tape DT is applied to the upper surface of the sealing body formed of the resin MR (S119 of fig. 13). Then, as shown in fig. 25A and 25B, the seal body formed of the resin MR is cut (package cut) for each product region PR (S120 of fig. 13). Specifically, the separation regions (boundary regions) for separating the product regions PR formed in the lead frame LF1 are cut with a dicing blade, and thereby each product region PR is singulated. Thus, for example, the semiconductor device PK1 in the present first embodiment as shown in fig. 25C can be obtained.

Thereafter, the singulated individual semiconductor devices PK1 are sorted by electronic testing (S121 of fig. 13), and the semiconductor devices PK1 that have been determined to be defect-free are packaged and shipped (S122 of fig. 13). In this way, the semiconductor device in the present first embodiment can be manufactured.

Note that an example for performing the plasma processing shown in S112 of fig. 12 is given and described here, but not limited thereto. If the connection strength (connection reliability) between the wire W and the lead frame LF1 (the plurality of leads LD) and between the wire W and the electrode pad of each semiconductor chip can be ensured without performing the plasma treatment, the plasma treatment can be omitted and the number of treatment steps can be reduced. The same can be applied to the embodiments and modifications described below.

< characteristics of the first embodiment >

Next, features in the present first embodiment are described with reference to the drawings. As described above, the present first embodiment is characterized by the method of fixing the lead frame LF1 when the tape TP is to be applied to the rear surface of the lead frame LF 1. In particular, the technical idea in the present first embodiment is to apply a tape to the rear surface of the lead frame in a state of supporting the upper surface side of the lead frame while reducing damage to the semiconductor device. Hereinafter, the technical idea in the present first embodiment will be specifically described.

Fig. 26A is a view showing the configuration of the lead frame LF1 immediately before the tape TP is applied to the rear surface of the lead frame LF1, and fig. 26B is an enlarged view showing a part of fig. 26A. As shown in fig. 26B, in the lead frame LF1 of the present first embodiment, the product zones PR are arranged in a matrix, and each product zone PR is partitioned by a partition zone (boundary zone) DIV. Now, each product zone PR is of interest. A chip mounting portion tab (c), a chip mounting portion tab (h), and a chip mounting portion tab (l) are disposed in each product region PR, and a driver IC chip chp (c) is mounted on the chip mounting portion tab (c). Further, the high MOS chip chp (h) is mounted on the chip mounting portion tab (h), and the low MOS chip chp (l) is mounted on the chip mounting portion tab (l). Further, the high MOS clip clp (h) is arranged to cross over the high MOS chip chp (h) to the chip mounting portion tab (l), and the low MOS clip clp (l) is arranged to cross over the low MOS chip chp (l) to the lead.

In the present first embodiment, the tape TP is to be applied to the rear surface of the lead frame LF1 formed in this manner. Then. In the present first embodiment, among the faces of the lead frame LF1, the tape TP is to be applied to the rear surface of the lead frame LF1, and the upper surface opposite to the rear surface to which the tape TP is applied is supported by the support member. Here, in the present first embodiment, although the upper surface side of the lead frame LF1 is to be supported by the supporting member, the driver IC chip chp (c), the high MOS chip chp (h), and the low MOS chip chp (l) have been mounted on the upper surface side of the lead frame LF1 as described above. Therefore, in the present first embodiment, the device is realized to support the upper surface side of the lead frame LF1 with the support member without damaging the driver IC chip chp (c), the high MOS chip chp (h), and the low MOS chip chp (l).

Fig. 27A is a plan view showing a schematic overall configuration of the support member SU used in the present first embodiment, and fig. 27B is an enlarged view of a part of fig. 27A. As shown in FIGS. 27A and 27B, the support unit SU includes a plurality of support portions FU, and the channels DIT are separated by frame portions FU. As can be seen by comparing FIG. 26B with FIG. 27B, the frame portion FU of the support member SU shown in FIG. 27B is arranged to correspond to the partition DIV shown in FIG. 26B. Then, the channels DIT provided in the support part SU shown in fig. 27B are arranged to correspond to the product region PR shown in fig. 26B.

Fig. 28 is a sectional view showing how the tape TP is applied to the rear surface of the lead frame LF1 in a state where the upper surface side of the lead frame LF1 is supported by the support member SU. As shown in fig. 28, the product block PR disposed in the lead frame LF1 is sandwiched by the separation block DIV. Then, a chip mounting portion tab (c) and a chip mounting portion tab (l) are disposed in the product region PR, and a driver IC chip chp (c) is mounted on the chip mounting portion tab (c) via a high melting point solder HS 1. Further, a low MOS chip chp (l) is mounted on the chip mounting portion tab (l) via a high melting point solder HS1, and a low MOS clip clp (l) is arranged on the low MOS chip chp (l) via a high melting point solder HS 2. Note that, although not shown in, for example, fig. 28, it can also be seen from 26B that a chip mounting portion tab (h) is also arranged in the product region PR, a high MOS chip chp (h) is mounted over the chip mounting portion tab (h) via a high melting point solder HS1, and a high MOS clip clp (h) is arranged over the high MOS chip chp (h) via a high melting point solder HS 2.

Here, the upper surface side of the lead frame LF1 is supported by the support member SU so that the frame portion FU contacts the separation region DIV of the lead frame LF 1. Thus, the channel DIT sandwiched by the frame portion FU will be arranged at a position where it overlaps in a planar manner with the product region PR formed in the lead frame LF 1. Then, in the present first embodiment, as shown in fig. 28, there is a gap between the bottom surface BS of the channel DIT provided in the support member SU and the upper surface of the driver IC chip chp (c). As a result, according to the present first embodiment, the supporting member SU will support the upper surface side of the lead frame LF1 in a state of not contacting the driver IC chip chp (c). Therefore, according to the present first embodiment, the upper surface side of the lead frame LF1 can be supported without breaking the driver IC chip chp (c).

On the other hand, as shown in fig. 28, the upper surface side of the lead frame LF1 will be supported by the support member SU so that the bottom surface BS of the channel DIT contacts the upper surface of the low MOS clip clp (l) mounted on the low MOS chip chp (l).

For example, from the viewpoint of not causing damage to the low MOS chip chp (l) due to the support member SU, the upper surface of the low MOS clip clp (l) mounted above the low MOS chip chp (l) may be configured not to contact the bottom surface BS of the channel DIT disposed within the support member SU. However, if such a configuration is adopted, the product region PR formed in the lead frame LF1 will not be supported at all by the support member SU. That is, when the upper surface of the low MOS clip clp (l) is configured not to contact the bottom surface BS of the channel DIT provided in the support member SU, the upper surface side of the lead frame LF1 will be supported only in the case where the frame portion FU of the support member SU contacts the separation region DIV surrounding the product region PR. In this case, assuming that the tape TP is applied to the rear surface of the lead frame LF1, the product region PR itself will not be supported at all by the support member SU. That is, if the tape TP is applied to the rear surface of the lead frame LF1 without support of the upper surface of the lead frame LF1 opposite to the rear surface to which the tape TP is applied (for example, without support of the product region PR itself at all), among the regions of the lead frame LF1, in particular, the product region PR is not stably fixed. As a result, in product region PR of lead frame LF1, the reaction force generated by lead frame LF1 when strip TP is applied to the rear surface of lead frame LF1 will be relatively weak. Thus, it is difficult to reliably apply the tape TP to the rear surface of the product region PR formed in the lead frame LF1 without including voids or the like.

Then, in the present first embodiment, as shown in fig. 28, the upper surface side of the lead frame LF1 is supported by the support member SU so that the bottom surface BS of the channel DIT formed in the support member SU contacts the upper surface of the low MOS clip clp (l) mounted on the low MOS chip chp (l). Similarly, although not shown in fig. 28, the upper surface side of the lead frame LF1 is supported by the support member SU so that the bottom surface BS of the channel DIT formed in the support member SU contacts the upper surface of the high MOS clip clp (h) mounted over the high MOS chip chp (h). In this way, the upper surface of high MOS clip clp (h) is also configured to contact bottom surface BS of channel DIT, as is the upper surface of low MOS clip clp (l), but will be described below from the perspective of attention to low MOS clip clp (l) shown in fig. 28.

In the present first embodiment, when the upper surface side of the lead frame LF1 is supported by the support member SU, there is a gap between the bottom surface BS of the channel DIT provided in the support member SU and the upper surface of the driver IC chip chp (c), for example, as shown in fig. 28. On the other hand, in the present first embodiment, the bottom surface BS of the channel DIT formed in the support member SU contacts the upper surface of the low MOS clip clp (l) mounted on the low MOS chip chp (l).

Thus, since the product section PR itself formed in the lead frame LF1 is not in a state of being not supported at all by the support member SU, the stability of fixing of the product section PR can be improved. As a result, similarly, in the product region PR of the lead frame LF1, a sufficiently large reaction force (repulsive force) generated by the lead frame LF1 when the tape TP is applied to the rear surface of the lead frame LF1 can be ensured. Therefore, according to the present first embodiment, the tape TP can be reliably applied to the rear surface of the product region PR formed in the lead frame LF1 without including voids or the like. That is, according to the present first embodiment, even in a state where the driver IC chip chp (c), the high MOS chip chp (h), and the low MOS chip chp (l) are mounted on the upper surface side of the lead frame LF1, the tape TP can be reliably applied to the rear surface of the lead frame LF1 (in particular, to the rear surface of the product region PR).

Here, in the present first embodiment, for example, as shown in fig. 28, a gap exists between the bottom surface BS of the channel DIT provided in the support member SU and the upper surface of the driver IC chip chp (c). On the other hand, the bottom surface BS of the channel DIT formed in the support member SU is configured to contact the upper surface of the low MOS clip clp (l) mounted on the low MOS chip chp (l). Now, the reason will be described.

First, from the viewpoint of reliably supporting the product region PR itself formed in the lead frame LF1 by the support member SU, the bottom surface BS of the channel DIT formed in the support member SU may be configured to contact both the upper surface of the driver IC chip chp (c) and the upper surface of the low MOS clip clp (l).

However, the configuration is such that the bottom surface BS of the channel DIT contacts the upper surface of the driver IC chip chp (c), meaning that the driver IC chip chp (c) is directly supported by the support member SU. In this case, the pressure from the support part SU will be directly applied to the driver IC chip chp (c), and thus damage to the driver IC chip chp (c) may increase. Therefore, in the present first embodiment, for example, as shown in fig. 28, there is a gap between the bottom surface BS of the channel DIT provided in the support member SU and the upper surface of the driver IC chip chp (c). That is, in the present first embodiment, the bottom surface BS of the channel DIT is configured not to contact the upper surface of the driver IC chip chp (c).

On the other hand, the upper surface of the low MOS clip clp (l) mounted on the low MOS chip chp (l) may also be configured not to contact the bottom surface BS of the channel DIT disposed in the support member SU. However, if such a configuration is adopted, the product region PR formed in the lead frame LF1 will not be supported at all by the support member SU. As a result, the product region PR is not stably fixed. For this reason, in the product region PR of the lead frame LF1, the reaction force generated by the lead frame LF1 when the tape TP is applied to the rear surface of the lead frame LF1 will be considerably weak. Therefore, it is difficult to reliably apply the tape TP to the rear surface of the product region PR formed in the lead frame LF1 without including voids or the like.

Then, in the present first embodiment, the upper surface side of the lead frame LF1 is supported by the support member SU, so that the bottom surface BS of the channel DIT formed in the support member SU contacts the upper surface of the low MOS clip clp (l) mounted on the low MOS chip chp (l).

Here, the upper surface side of the lead frame LF1 is supported by the support member SU so that the bottom surface BS of the channel DIT contacts the upper surface of the low MOS clip clp (l). In this case, it is a problem whether damage to the low MOS chip chp (l) disposed in the bottom layer of the low MOS clip clp (l) causes a problem. However, low MOS chip chp (l) is not configured to cause bottom surface BS of channel DIT to directly contact the upper surface of low MOS chip chp (l), but is configured such that low MOS clip clp (l) is interposed between low MOS chip chp (l) and bottom surface BS of channel DIT. That is, in the low MOS chip chp (l), the bottom surface BS of the channel DIT does not directly contact the upper surface of the low MOS chip chp (l). That is, in the present first embodiment, the low MOS clip clp (l) interposed between the low MOS chip chp (l) and the bottom surface BS of the channel DIT functions as a buffer material. For this reason, even if the upper surface side of the lead frame LF1 is supported by the support member SU so that the bottom surface BS of the channel DIT contacts the low MOS clip clp (l), damage to the low MOS chip chp (l) can be reduced to a level without problems.

From the above, in the present first embodiment, there is a gap between the bottom surface BS of the channel DIT provided in the support member SU and the upper surface of the driver IC chip chp (c). On the other hand, the bottom surface BS of the channel DIT formed in the support member SU is configured to contact the upper surface of the low MOS clip clp (l) mounted on the low MOS chip chp (l).

Thus, according to the present first embodiment, such a significant effect can be obtained: the tape TP can be reliably applied to the rear surface of the lead frame LF1 (particularly, to the rear surface of the product region PR) while reducing damage to the driver IC chips chp (c), the high MOS chips chp (h), and the low MOS chips chp (l).

Here, in the configuration of the present first embodiment, since the upper surface of the driver IC chip chp (c) is not pressed by the supporting members SU, the entire product region PR is not pressed by the supporting members SU. However, for example, as shown in fig. 26A and 26B, in the case where the area occupied by the driver IC chip chp (c) in the product region PR is sufficiently small compared to the area occupied by the high MOS chip chp (h) or the low MOS chip chp (l), even if a partial region of the product region PR is not pressed by the supporting member SU, the tape TP can be sufficiently and reliably applied to the rear surface of the lead frame LF1 (in particular, to the rear surface of the product region PR).

Note that the originality of the technical idea in the present first embodiment is that it has been found that it functions as a buffer material in the low MOS clip clp (l) mounted over the low MOS chip chp (l) via the high melting point solder HS2, for example, as shown in fig. 28. Originally, the function of the low MOS clip clp (l) was a function for reducing on-resistance, but the function as a buffer material was not adopted. In this regard, the technical idea in the present first embodiment, which is conceived by finding the function as a buffer material in the low MOS clip clp (l), is original.

Here, from the viewpoint of sufficiently exhibiting the function as a buffer material within the low MOS clip clp (l), for example, the thickness of the low MOS clip clp (l) may be set as large as possible. In this case, since the sectional area of the low MOS clip clp (l) is also increased, the resistance of the low MOS clip clp (l) can be reduced, so that the on-resistance of the semiconductor device PK1 in the present first embodiment can be further reduced.

< modification 1>

Next, a modified example 1 of the present first embodiment is described. Fig. 29 is a sectional view showing how the tape TP is applied to the rear surface of the lead frame LF1 in the state where the upper surface side of the lead frame LF1 is supported by the support member SU in this modification 1.

As shown in fig. 29, in the present modification 1, the buffer material BUF is interposed between the bottom surface BS of the channel DIT provided in the support member SU and the upper surface of the driver IC chip chp (c). Thus, the driver IC chip chp (c) will be supported by the support member SU as well. As a result, according to the present modification 1, since the entire product region PR can be supported by the support member SU, the tape TP can be reliably applied to the rear surface of the lead frame LF1 (in particular, to the rear surface of the product region PR).

Then, in the present modification 1, the upper surface of the driver IC chip chp (c) does not directly contact the bottom surface BS of the channel DIT provided in the support member SU, but indirectly contacts the bottom surface BS of the channel DIT via the buffer material BUF. Therefore, even when the upper surface of the driver IC chip chp (c) is supported by the support member SU, damage to the driver IC chip chp (c) can be reduced to a level without problems.

According to the above, according to the present modification 1, such a remarkable effect can be obtained: the tape TP can be reliably applied to the rear surface of the lead frame LF1 (particularly, to the entire rear surface of the product region PR) while reducing damage to the driver IC chips chp (c), the high MOS chips chp (h), and the low MOS chips chp (l).

< modification 2>

Subsequently, a modification 2 of the present first embodiment is described. Fig. 30 is a sectional view showing how the tape TP is applied to the rear surface of the lead frame LF1 in a state where the upper surface side of the lead frame LF1 is supported by the support member SU in modification 2.

As shown in fig. 30, in the present modification 2, the buffer material BUF is interposed between the bottom surface BS of the channel DIT provided in the support member SU and the upper surface of the driver IC chip chp (c). Thus, the driver IC chip chp (c) will be supported by the support member SU as well. As a result, according to the present modification 2, since the entire product region PR can be supported by the support member SU, the tape TP can be reliably applied to the rear surface of the lead frame LF1 (in particular, to the rear surface of the product region PR).

Then, similarly, in the present modification 2, the upper surface of the driver IC chip chp (c) does not directly contact the bottom surface BS of the channel DIT provided in the support member SU, but indirectly contacts the bottom surface BS of the channel DIT via the buffer material BUF. Therefore, even when the upper surface of the driver IC chip chp (c) is supported by the support member SU, damage to the driver IC chip chp (c) can be reduced to a level without problems.

Further, in the present modification 2, the buffer material BUF is also interposed between the upper surface of the low MOS clip clp (l) and the bottom surface BS of the channel DIT provided in the support member SU. That is, in the present modification 2, the low MOS clip clp (l) and the buffer material BUF are interposed between the low MOS chip chp (l) and the bottom surface BS of the channel DIT. That is, in the present modification 2, the low MOS clip clp (l) interposed between the low MOS chip chp (l) and the bottom surface BS of the channel DIT functions as a buffer material, and the buffer material BUF is further disposed between the low MOS clip clp (l) and the bottom surface BS of the channel DIT. For this reason, even if the upper surface side of the lead frame LF1 is supported by the support member SU, damage to the low MOS chip chp (l) can be reduced to a level without problems more reliably.

From the above, with the present modification 2, such a remarkable effect can be obtained as well: the tape TP can be reliably applied to the rear surface of the lead frame LF1 (in particular, to the entire rear surface of the product region PR) while reducing damage to the driver IC chips chp (c), the high MOS chips chp (h), and the low MOS chips chp (l).

< specific configuration of buffer Material >

Next, specific configurations and advantages of the buffer materials (the low MOS clip clp (l) and/or the buffer material BUF) described in the above-described first embodiment, modification 1, and modification 2 are described.

Fig. 31 is a view showing the longitudinal elastic modulus, shore hardness, and vickers hardness of various materials. In fig. 31, urethane rubber, silicone rubber (silicone rubber), and nitrile rubber are listed as examples of the buffer material BUF. Further, as a material to be compared, for example, silicon is listed as a component of a semiconductor chip typified by a driver IC chip chp (c), a high MOS chip chp (h), and a low MOS chip chp (l). Further, copper (oxygen-free copper) as a constituent of the low MOS clip clp (l) functioning as a buffer material and stainless steel (SUs 304) as a constituent of the support member SU are listed.

In FIG. 31, the longitudinal elastic modulus is first described, and the longitudinal elastic modulus of urethane rubber is 24.0 to 29.4 (MPa), that of silicone rubber is 5 to 7 (MPa), and that of nitrile rubber is 8.1 to 20.2 (MPa). Further, the longitudinal elastic modulus of silicon is 185,000 (MPa), the longitudinal elastic modulus of copper (oxygen-free copper) is 220 (MPa), and the longitudinal elastic modulus of stainless steel is 620 (MPa).

Then, in FIG. 31, Shore hardness is described, the Shore hardness of the urethane rubber is 50 to 90 (Hs), the Shore hardness of the silicone rubber is 50 to 70 (Hs), and the Shore hardness of the nitrile rubber is 50 to 70 (Hs).

Subsequently, in fig. 31, vickers hardnesses are described, with silicon (Si) 1040 (HV), copper (oxygen-free copper) 105 (HV), and stainless steel 196 (HV).

(1) In the case of the first embodiment

Referring to fig. 31, consider the components of the first embodiment. In the first embodiment, for example, as shown in fig. 28, the low MOS clip clp (l) is mounted on the low MOS chip chp (l) via the refractory solder HS2, and the upper surface of the low MOS clip clp (l) contacts the support member SU.

Then, the low MOS chip chp (l) is a semiconductor chip containing silicon as a main component, and the low MOS clip clp (l) is formed of, for example, a copper material. Further, the support member SU is formed of, for example, stainless steel.

Thus, when silicon, copper and stainless steel are compared for the longitudinal modulus of elasticity, the longitudinal modulus of elasticity of silicon is the greatest followed by the longitudinal modulus of elasticity of stainless steel, while the longitudinal modulus of elasticity of copper is the least. Here, focusing on the longitudinal elastic modulus, the larger the longitudinal elastic modulus, the harder the material becomes. In other words, the smaller the longitudinal elastic modulus, the softer the material becomes. Thus, when comparing silicon, copper and stainless steel, the hardest material is silicon, the second hardest material is stainless steel, and the softest material is copper.

Thus, for example, a case where the support part SU formed of stainless steel is directly in contact over the low MOS chip chp (l) formed of silicon is compared with a case where the support part SU formed of stainless steel is arranged over the low MOS chip chp (l) formed of silicon via the low MOS clip clp (l) formed of copper. In this case, the latter case in which the low MOS clip clp (l) formed of copper is inserted can better protect the low MOS chip chp (l) from the pressure due to the supporting part SU than the former case. That is, since the low MOS clip clp (l) is softest, it sufficiently functions as a buffer material in the case where the low MOS chip chp (l) is supported by the supporting part SU. As a result, even if the upper surface side of the lead frame LF1 is supported by the support member SU so that the bottom surface BS of the channel DIT contacts the low MOS clip clp (l), damage to the low MOS chip chp (l) can be reduced to a level without problems.

(2) In the case of modification 1

Referring to fig. 31, a member of modification 1 is considered. In modification 1, for example, as shown in fig. 29, the buffer material BUF is disposed over the driver IC chip chp (c), and the support member SU is disposed over the buffer material BUF.

Then, the driver IC chip chp (c) is a semiconductor chip containing silicon as a main component, and the buffer material BUF is formed of, for example, a rubber material (e.g., urethane rubber, silicone rubber (silicone rubber), and nitrile rubber). Further, the support building SU is formed of, for example, stainless steel.

Thus, when silicon, rubber material and stainless steel are compared for the longitudinal elastic modulus, the longitudinal elastic modulus of silicon is the greatest followed by the longitudinal elastic modulus of stainless steel, while the longitudinal elastic modulus of rubber material is the smallest. In particular, the longitudinal elastic modulus of the rubber material is extremely small compared to silicon and stainless steel, and the rubber material is found to be an extremely soft material.

Thus, since the rubber material is softest, it sufficiently functions as the buffer material BUF in the case where the driver IC chip chp (c) is supported by the support member SU. As a result, even if the upper surface side of the lead frame LF1 is supported by the support member SU so that the bottom surface BS of the channel DIT contacts the buffer material BUF, damage to the driver IC chip chp (c) can be reduced to a level without problems.

In particular, since the rubber material used as the buffer material BUF in modification 1 is extremely soft, even if there is any variation in the height of the upper surface of the driver IC chip chp (c) mounted above the chip mounting portion tab (c) via the high melting point solder HS1, the buffer material BUF can absorb the variation in height and suppress an increase in the pressure that is unnecessarily applied to the driver IC chip chp (c). For example, consider a case in which the height of the driver IC chip chp (c) becomes higher than the average height due to manufacturing variations of the chip mounting portion tab (c), the high-melting solder HS1, and/or the driver IC chip chp (c). In this case, for example, when the upper surface of the driver IC chip chp (c) is supported by the support member SU formed of stainless steel, the pressure that is optionally applied to the driver IC chip chp (c) may increase. In contrast, when the driver IC chip chp (c) is supported by the supporting member SU with the buffer material BUF inserted above the driver IC chip chp (c), the height variation can be absorbed by the soft buffer material BUF, and thus the increase of unnecessary pressure applied to the driver IC chip chp (c) can be suppressed.

(3) In the case of modification 2

Referring to fig. 31, a member of modification 2 is considered. In modification 2, for example, as shown in fig. 30, a buffer material BUF is also interposed between the upper surface of the low MOS clip clp (l) and the bottom surface BS of the channel DIT provided in the support member SU. That is, in the present modification 2, the low MOS clip clp (l) and the buffer material BUF are interposed between the low MOS chip chp (l) and the bottom surface BS of the channel DIT.

Then, the low MOS chip chp (l) is a semiconductor chip containing silicon as a main component, and the low MOS clip clp (l) is formed of copper. Further, the cushioning material BUF is formed of, for example, a rubber material (e.g., urethane rubber, silicone rubber, and nitrile rubber), and the support member SU is formed of, for example, stainless steel.

Therefore, for example, when comparing the longitudinal elastic moduli of copper and a rubber material, the longitudinal elastic modulus of the rubber material is extremely small as compared with the longitudinal elastic modulus of copper, and the rubber material is found to be extremely soft.

Thus, since the rubber material is softest, when the low MOS chip chp (l) is supported by the supporting member SU, it sufficiently functions as the buffer material BUF. As a result, damage to the low MOS chip chp (l) can be further reduced to a level without problems even if the upper surface side of the lead frame LF1 is supported by the supporting member SU, as compared with the first embodiment including only the low MOS clip clp (l) formed of copper.

In particular, the rubber material used as the cushioning material BUF in modification 2 is extremely soft. Therefore, even if there is a variation in the height of the upper surface of the low MOS chip chp (l) mounted on the low MOS chip chp (l) via the high melting point solder HS2, the low MOS clip clp (l) mounted on the chip mounting portion tab (l) via the high melting point solder HS1, the buffer material BUF can absorb this variation in height and suppress an increase in the pressure unnecessarily applied to the low MOS chip chp (l). For example, consider a situation in which the height of the low MOS clip clp (l) becomes higher than the average height due to manufacturing variations of the chip manufacturing part tab (c), the high melting solder HS1, the low MOS chip chp (l), the high melting solder HS2, and/or the low MOS clip clp (l). In this case, for example, when the upper surface of the low MOS clip clp (l) is supported by the support part SU formed of stainless steel, the pressure applied to the low MOS chip chp (l) may be unnecessarily increased. In contrast, when supported by the support member SU inserted above the low MOS clip clp (l) by the buffer material BUF, since the height variation can be absorbed by the soft buffer material BUF, an unnecessary increase in the pressure applied to the low MOS chip chp (l) can be suppressed.

(second embodiment)

In the present second embodiment, a technical idea for manufacturing a semiconductor device using a clip frame having therein a plurality of unit regions arranged in a matrix, each unit region having a high MOS clip and a low MOS clip formed therein, is described.

< packaging configuration of semiconductor device in second embodiment >

The package configuration of the semiconductor device PK2 in the present second embodiment is substantially the same as that of the semiconductor device PK1 in the above-described first embodiment.

Fig. 32 is a view showing a package configuration of the semiconductor device PK2 in the present second embodiment. In fig. 32, the pattern shown in the center is a plan view of the semiconductor device PK2 viewed from the upper surface, and shown on each of all side edges thereof is a side view. As shown in fig. 32, the semiconductor device PK2 in the present second embodiment is covered with the resin MR having a rectangular shape. Then, as can be seen from the side view, the lead LD is exposed from the resin MR to the side surface of the semiconductor device PK 2. Further, in the present second embodiment, the cross section of the suspension wire HL is exposed from the side surface of the semiconductor device PK 2. This is a difference between the semiconductor device PK2 in the present second embodiment and the semiconductor device PK1 in the above-described first embodiment.

Next, fig. 33 is a plan view of the semiconductor device PK2 in the present second embodiment as viewed from the lower surface (rear surface). As shown in fig. 33, also in the semiconductor device PK2 of the present second embodiment, the rear surface of the semiconductor device PK2 is covered with the resin MR, whereas the chip mounting portion tab (l), the chip mounting portion tab (h) and the chip mounting portion tab (c) are exposed from the resin MR. Since the chip mounting portion tab (l), the chip mounting portion tab (h), and the chip mounting portion tab (c) are exposed from the rear surface of the semiconductor device PK2 in this manner, the heat radiation efficiency of the semiconductor device PK2 can be improved. Further, the plurality of rear surface terminals BTE are exposed to the peripheral region (peripheral portion) of the semiconductor device PK2 having a rectangular shape. The rear surface terminal BTE constitutes a part of the lead LD.

Subsequently, the internal configuration of the semiconductor device PK2 is described. Fig. 34 is a view showing an internal configuration of the semiconductor device PK2 in the present second embodiment. In fig. 34, the pattern shown in the center is a plan view of the inside of the semiconductor device PK2 viewed from the upper surface side through the resin MR, and a sectional view is shown on each of all sides thereof.

Here, since the internal configuration of the semiconductor device PK2 of this second embodiment shown in fig. 34 has substantially the same configuration as that of the semiconductor device PK1 of the above-described first embodiment shown in fig. 4, description about the same configuration is omitted, and differences are described. In fig. 34, the present second embodiment is characterized in that: the suspension lead HL is formed integrally with the high MOS clip clp (h), and reaches an outer edge portion of the sealing body formed of the resin MR. Similarly, the suspension lead HL is also integrally formed in the low MOS clip clp (l), and the suspension lead HL reaches an outer edge portion of the sealing body formed of the resin MR. The other configurations are the same as those of the first embodiment described above.

< method for manufacturing semiconductor device in second embodiment >

The semiconductor device PK2 in the present second embodiment is configured as described above, and its manufacturing method will be described below with reference to the drawings.

Fig. 35 to 37 show a flowchart showing the manufacturing flow of the semiconductor device PK2 in the present second embodiment. Further, fig. 38A to 41B are views each showing a manufacturing process of the semiconductor device PK2 in the present second embodiment.

First, a lead frame LF1 is prepared (S201 of fig. 35). This lead frame LF1 has, for example, the same configuration as that of the lead frame LF1 used in the above-described first embodiment shown in fig. 14A to 14C. For example, as shown in fig. 14C, in the lead frame LF1 of the present second embodiment, a plurality of product sections PR are arranged in a matrix, each product section PR including a chip mounting portion tab (C), a chip mounting portion tab (h), a chip mounting portion tab (l), and leads LD.

Further, in the present second embodiment, a clip frame CLF as shown in fig. 38A and 38B was prepared. The present second embodiment is characterized by using the clip frame CLF. In fig. 38A, a schematic overall configuration of the clip frame CLF is shown, and in fig. 38B, a part of the clip frame CLF is enlarged and shown. As shown in fig. 38B, a plurality of cell regions UR each including a high MOS clip clp (h) and a low MOS clip clp (l) are included in the clip frame CLF, and the cell regions UR are arranged in a matrix. Here, the high MOS clip clp (h) and the low MOS clip clp (l) are configured by, for example, a metal plate containing copper as a material component.

Hereinafter, a detailed configuration of the clip frame CLF shown in fig. 38A and 38B is described. For example, as shown in fig. 38B, in each of the plurality of cell regions UR arranged in a matrix, a high MOS clip clp (h) and a low MOS clip clp (l) are formed, and both the high MOS clip clp (h) and the low MOS clip clp (l) are coupled to the frame body of the clip frame CLF through the suspension lead HL. Therefore, in the entire clip frame CLF, the plurality of high MOS clips clp (h) and the plurality of low MOS clips clp (l) will be integrally formed.

In the clip frame CLF of the present second embodiment, as shown in fig. 38A and 38B, the unit regions UR are arranged to be aligned in the X direction and in the Y direction. That is, in the clip frame CLF of the present second embodiment, the cell regions UR are formed in a matrix along the X direction as well as along the Y direction. For example, in the clip frame CLF of the present second embodiment, the unit regions UR are arranged at first predetermined intervals (first pitches) in the X direction and also at second predetermined intervals (second pitches) in the Y direction.

Now, attention is mainly paid to the lead frame LF1 shown in fig. 14A to 14C. For example, as shown in fig. 14C, the product zones PR formed in the lead frame LF1 are arranged so as to be aligned in the X direction and in the Y direction. That is, in the lead frame LF1 shown in fig. 14A to 14C, the product regions PR are formed in a matrix along the X direction as well as along the Y direction. For example, in the lead frame LF1, the product zones PR are arranged at first predetermined intervals (first pitches) in the X direction and also at second predetermined intervals (second pitches) in the Y direction.

That is, in the present second embodiment, the layout pitch in the X direction of the product regions PR formed in the lead frame LF1 is the same as the layout pitch in the X direction of the unit regions UR formed in the clip frame CLF. Further, the layout pitch in the Y direction of the product regions PR formed in the lead frame LF1 is the same as the layout pitch in the Y direction of the unit regions UR formed in the clip frame CLF.

Here, the layout pitch in the X direction (first direction) and the layout pitch in the Y direction (second direction) perpendicular to the X direction of the plurality of high MOS clips clp (h) or low MOS clips clp (l) formed in the clip frame CLF are referred to as a first pitch and a second pitch, respectively.

In this case, the layout pitch in the X direction and the layout pitch in the Y direction of the chip mounting portions (chip mounting portion tab (c), chip mounting portion tab (h), and chip mounting portion tab (l)) formed in the lead frame LF1 are also the first pitch and the second pitch, respectively.

As a result, in the present second embodiment, each product region PR formed in the lead frame LF1 and each unit region UR formed in the clip frame CLF can be arranged to overlap each other in a plan view. More specifically, for example, the chip mounting portion tab (h) shown in fig. 14C and the high MOS clip clp (h) shown in fig. 38B can be arranged to overlap each other in a planar manner, and the chip mounting portion tab (l) shown in fig. 14C and the low MOS clip clp (l) shown in fig. 38B can be arranged to overlap each other in a planar manner.

Then, in each product region PR formed in the lead frame LF1, high melting point solder is formed on the chip mounting portion tab (c), the chip mounting portion tab (h), and the chip mounting portion tab (l) (S202 of fig. 35). Specifically, for example, a high melting solder is printed over the chip mounting portion tab (c), the chip mounting portion tab (h), and the chip mounting portion tab (l) using a solder printing method.

Subsequently, in each product region PR formed in the lead frame LF1, the driver IC chip chp (c) is first mounted on the chip mounting portion tab (c) (S203 of fig. 35). Then, the high MOS chip chp (h) is mounted on the chip mounting portion tab (h) (S204 of fig. 35), and thereafter the low MOS chip chp (l) is mounted on the chip mounting portion tab (l) (S205 of fig. 35). Note that the mounting order of the driver IC chip chp (c), the high MOS chip chp (h), and the low MOS chip chp (l) is not limited thereto, and may be changed as needed.

Thereafter, the lead frame LF1 is set in a positioning-dedicated jig (S206 in fig. 35). Specifically, as shown in fig. 39, the lead frame LF1 is positioned by inserting an opening OP1 formed in the lead frame LF1 into a protruding pin of, for example, a dedicated jig.

Then, as shown in fig. 39, in each product region PR formed in the lead frame LF1, a high-melting solder HS2 is formed over the high MOS chip chp (h) (S207 of fig. 35). Thereafter, the high melting solder HS2 is formed on the low MOS chip chp (l) (S208 of fig. 35). Specifically, high melting point solder HS2 is formed over a source electrode pad (high MOS pad) (not shown) formed in high MOS chip chp (h), and high melting point solder HS2 is formed over a source electrode pad (low MOS pad) (not shown) formed in low MOS chip chp (l). Further, as shown in fig. 39, a high melting point solder HS2 is also formed on a partial region of the chip mounting portion tab (l) and on a partial region of the lead line.

Specifically, the high melting point solder HS2 is also applied over the high MOS chip chp (h), over the low MOS chip chp (l), over a partial region of the chip mounting portion tab (l), and over a partial region of the lead line, for example, using a coating method. The high melting point solder HS2 formed at this time may have the same material composition as the high melting point solder HS1 described above, or may have a different material composition.

Thereafter, as shown in fig. 39, the clip frame CLF is set to the positioning-dedicated clip (S209 of fig. 35). Specifically, as shown in fig. 39, the opening OP2 formed in the clip frame CLF is further inserted into a protruding pin that has been inserted into the opening OP1 formed in the lead frame LF 1. Thus, according to the present second embodiment, it is possible to arrange the clip frame CLF over the lead frame LF1 so as to overlap each other. The present second embodiment is characterized in this point. That is, as described above, by inserting the opening OP1 formed in the lead frame LF1 and the opening OP2 formed in the clip frame CLF into the protruding pins provided in the dedicated jig, each product region PR formed in the lead frame LF1 and each unit region UR formed in the clip frame CLF can be overlapped with each other in a planar manner.

That is, in the present second embodiment, the layout pitch in the X direction of the product regions PR formed in the lead frame LF1 is the same as the layout pitch in the X direction of the unit regions UR formed in the clip frame CLF. Also, the layout pitch in the Y direction of the product regions PR formed in the lead frame LF1 is the same as the layout pitch in the Y direction of the unit regions UR formed in the clip frame CLF.

As a result, in the present second embodiment, each product region PR formed in the lead frame LF1 and each unit region UR formed in the clip frame CLF can be arranged to overlap each other in plan view. More specifically, for example, the high MOS chip chp (h) shown in fig. 39 and the high MOS clip clp (h) shown in fig. 39 can be arranged to overlap each other in a planar manner, and the low MOS chip chp (l) shown in fig. 39 and the low MOS clip clp (l) shown in fig. 39 can be arranged to overlap each other in a planar manner.

Thus, according to the present second embodiment, each product region PR and each unit region UR can be overlapped with each other in a planar manner by simply overlapping the lead frame LF1 with the lead frame CLF. This means that the high MOS clip clp (h) formed in each cell region UR can be mounted immediately on the high MOS chip chp (h) formed in each product region PR. Similarly, this means that the low MOS clip clp (l) formed in each cell region UR can be mounted immediately on the low MOS chip chp (l) formed in each product region PR. As a result, according to the present second embodiment, the manufacturing process can be simplified, and thereby the manufacturing cost of the semiconductor device PK2 can be reduced.

In this way, the source electrode pad formed in the high MOS chip chp (h) and the chip mounting portion tab (l) will be electrically coupled to each other through the high MOS clip clp (h). In addition, the source electrode pad formed in the low MOS chip chp (l) and the lead line to which the reference potential is supplied will be electrically coupled to each other through the low MOS clip clp (l).

Subsequently, reflow is performed for the high melting point solder (e.g., the high melting point solder HS 2) (S210 of fig. 36). Specifically, the lead frame LF1 containing the high melting point solder is heated at a temperature (first temperature) of, for example, about 350 ℃. In this way, the high melting point solder can be melted.

Then, in the present second embodiment, heat treatment (reflow) for melting the high melting point solder is performed in a state where the tape is not applied to the rear surface of the lead frame LF1 prepared in advance. Therefore, in the case of the present second embodiment, even if the reflow temperature of the high melting point solder is higher than the heat resistant temperature of the tape, the heat resistance of the tape does not cause a problem because the tape is not originally applied to the rear surface of the lead frame LF 1. That is, according to the present second embodiment, since the heat treatment (reflow) of the high melting point solder is performed before the tape is applied to the rear surface of the lead frame LF1, the heat resistance of the tape can be ensured regardless of the temperature of the heat treatment (reflow).

Thereafter, flux cleaning is performed so as to remove the flux contained in the high-melting-point solder (S211 of fig. 36). Then, from the viewpoint of improving the bonding characteristics of the wires in the wire bonding step performed in the subsequent step, the upper surface of the lead frame LF1 is cleaned by performing plasma treatment on the upper surface of the lead frame LF1 (S212 of fig. 36).

Then, as shown in fig. 40A and 40B, the tape TP is applied to the rear surface of the lead frame LF1 (S213 of fig. 36). That is, in the face of the lead frame LF1, the tape TP is applied to the face opposite to the face on which the driver IC chip chp (c), the high MOS chip chp (h), and the low MOS chip chp (l) are mounted. At this time, as described above, the heat treatment (reflow) at about 350 ℃ for the high melting point solder has been completed in a step before the step of applying the tape TP, and therefore the heat resistance of the tape TP will not become an issue in the present second embodiment.

That is, the reflow temperature of the above-described high melting point solder is, for example, about 350 ℃, and exceeds the heat resistant temperature of the tape TP (for example, about 250 ℃). Therefore, if the heat treatment for melting the high melting point solder is performed in a state where the tape TP is applied to the rear surface of the lead frame LF, the tape TP will not withstand the heat treatment. In this regard, in the present second embodiment, the heat treatment (reflow) at about 350 ℃ for the high melting point solder has been completed in a step before the step of applying the tape TP. For this reason, in the present second embodiment, the heat resistance of the tape TP will not be a problem.

Subsequently, as shown in fig. 41A and 41B, a wire bonding step (S214 of fig. 36) is performed. Fig. 41A is a view showing the lead frame LF1 when a wire bonding step is performed after a tape TP is applied to the rear surface of the lead frame LF 1. However, in fig. 41A, a member (wire) required to perform an actual wire bonding step is omitted, and is shown in fig. 41B which is an enlarged view of one product region PR shown in fig. 41A.

In fig. 41B, a plurality of electrode pads PD and a plurality of leads LD formed in the driver IC chip chp (c) are coupled to each other by a plurality of wires W. In addition, as shown in fig. 41B, the gate electrode pad gp (h) formed in the high MOS chip chp (h) and the electrode pad PD formed in the driver IC chip chp (c) are coupled to each other by a wire W. Similarly, the gate electrode pad gp (l) formed in the low MOS chip chp (l) and the electrode pad PD formed in the driver IC chip chp (c) are coupled to each other by a wire W. Thus, according to the present second embodiment, the high MOS transistor QH (see fig. 1) formed in the high MOS chip chp (h) and the low MOS transistor QL (see fig. 1) formed in the low MOS chip chp (l) are electrically controlled by the control circuit CC (see fig. 1) formed in the driver IC chip chp (c).

Here, according to the present second embodiment, the tape TP is applied to the rear surface of the lead frame LF1 in a step before the wire bonding step is performed. Therefore, according to the present second embodiment, the lead frame LF1 having the tape TP applied thereto can be easily vacuum-sucked. As a result, even with the lead frame LF1 corresponding to the MAP molding technique, the wire bonding step can be performed with the lead frame LF1 reliably fixed by vacuum suction. As a result, according to the present second embodiment, the reliability in the wire bonding step can be improved.

Note that the wire bonding step is performed in a state where the lead frame LF1 is heated to about 250 c of about 200 in order to stabilize the bonding of the wire W. However, since the heat-resistant temperature of the tape TP applied to the rear surface of the lead frame LF1 is about 250 ℃, the heat treatment applied in the wire bonding step does not cause a problem in the heat resistance of the tape TP.

Then, the product areas formed in the lead frame LF1 are collectively sealed (molded) with resin (S215 of fig. 36). In other words, the sealing body is formed by collectively sealing the product region PR in the lead frame LF1 with the resin MR, thereby covering the driver IC chip chp (c), the high MOS chip chp (h), and the low MOS chip chp (l) shown in fig. 41B. That is, in the present second embodiment, as a technique for sealing the semiconductor chip with resin, a so-called MAP molding technique is employed in which the product regions PR are contained in the cavity and the product regions PR are collectively sealed with resin. According to this MAP molding technique, since it is not necessary to provide a passage for injecting resin for each product region PR, the product regions PR can be densely arranged. Thus, according to the MAP molding technique, the number of products to be obtained can be increased, and thus cost reduction of the products can be achieved.

Then, in the present second embodiment, the adhesive tape TP is applied to the rear surface of the lead frame LF1 in a step before the resin sealing step (molding step) by the MAP molding technique. Therefore, according to the present second embodiment, the tape TP can be reliably applied to the rear surface terminals (leads) formed on the rear surface of the lead frame LF 1. As a result, also in the resin sealing step using the MAP molding technique, no gap is formed between the rear surface terminal and the tape TP, and thus the leakage of the resin into the rear surface of the rear surface terminal (resin burr) can be sufficiently suppressed.

Note that as the resin used in the resin sealing step, for example, a thermosetting resin can be used. Therefore, the resin sealing step is performed in a state of being heated to about 160 to about 200 ℃, so as to cure the thermosetting resin. However, since the heat-resistant temperature of the tape TP applied to the rear surface of the lead frame LF1 is about 250 ℃, the heat treatment applied in the resin molding step does not cause a problem in the heat resistance of the tape TP.

Thereafter, the tape TP applied to the rear surface of the lead frame LF1 is peeled off from the lead frame LF1 (S216 of fig. 36). Then, a plating film is formed on the surfaces of the chip mounting portion tab (c), the chip mounting portion tab (h), the chip mounting portion tab (l), and the rear surface terminal BTE exposed from the rear surface of the resin MR (sealing body) (see fig. 33) (S217 of fig. 36). Further, a mark is formed on the surface of the sealing body formed of the resin MR (marking step) (S218 of fig. 36).

Subsequently, a dicing tape is applied to the upper surface of the sealing body formed of resin (S219 of fig. 37). Then, the sealing body formed of resin is cut for each product area (package cutting) (S220 of fig. 37). Specifically, the separation regions (boundary regions) for separating the product regions PR formed in the lead frame LF1 are cut with a dicing blade and thereby each product region is singulated. Thus, for example, the semiconductor device PK2 shown in fig. 32 and 33 in the present second embodiment can be obtained. At this time, the suspension wires HL formed within the clip frame CLF are cut along with the resin MR. As a result, for example, as shown in fig. 32, the cross section of the suspension wires HL is exposed from the side surface of the semiconductor device PK2, and the side surface of the semiconductor device PK2 and the cross section of the suspension wires HK are located in the same plane.

Thereafter, the singulated individual semiconductor devices PK2 are sorted by electronic testing (S221 of fig. 37), and the semiconductor devices PK2 that have been determined to be defect-free are packaged and shipped (S222 of fig. 37). In this way, the semiconductor device in the present second embodiment can be manufactured.

< characteristics of the second embodiment >

Next, features in the present second embodiment are described with reference to the drawings. The present second embodiment is characterized by a method of fixing the lead frame LF1 while applying the tape TP to the rear surface of the lead frame LF 1. In particular, the technical idea in the present second embodiment is to apply a tape to the rear surface of the lead frame in a state where the upper surface side of the lead frame is supported, while reducing damage to the semiconductor chip. Thereafter, the technical idea in the present second embodiment will be specifically described.

Fig. 42A is a view showing the configuration of the lead frame LF1 immediately before the tape TP is applied to the rear surface of the lead frame LF1, and fig. 42B is an enlarged view showing a part of fig. 42A. As shown in fig. 42B, in the lead frame LF1 of the present second embodiment, the product zones PR are arranged in a matrix, and each product zone PR is partitioned by a partition zone (boundary zone). Now, each product zone PR is of primary interest. A chip mounting portion tab (c), a chip mounting portion tab (h), and a chip mounting portion tab (l) are disposed in each product region PR, and a driver IC chip chp (c) is mounted on the chip mounting portion tab (c). Further, the high MOS chip chp (h) is mounted on the chip mounting portion tab (h), and the low MOS chip chp (l) is mounted on the chip mounting portion tab (l). Further, in the present second embodiment, the clip frame CLF is installed to overlap the lead frame LF1 in a planar manner. In this clip frame CLF, the cell regions UR are arranged in a matrix, and each cell region UR is partitioned by a partition region (boundary region) DIV 2. Now, each cell region UR is mainly focused. A high MOS clip clp (h) and a low MOS clip clp (l) are disposed within each cell region UR. Thus, in this second embodiment, the high MOS clip clp (h) is arranged to span from above the high MOS chip chp (h) to above the chip mounting portion tab (l), and the low MOS clip clp (l) is arranged to span from above the low MOS chip chp (l) to above the lead. Then, the high MOS clip clp (h) and the low MOS clip clp (l) are coupled to the partition DIV2 of the clip frame CLF through the suspension lead HL.

Fig. 43A is a plan view showing a schematic overall configuration of the support member SU used in the present second embodiment, and fig. 43B is an enlarged view of a part of fig. 43A. As shown in fig. 43A and 43B, the support member SU includes an outer frame portion, and a channel DIT is formed in an inner region of the outer frame portion. Then, the channel DIT provided in the support member SU is arranged to include the product region PR formed in the lead frame LF 1.

Fig. 44 is a sectional view showing how the tape TP is applied to the rear surface of the lead frame LF1 in a state where the upper surface side of the lead frame LF1 is supported by the support member SU. As shown in fig. 44, the product region PR disposed in the lead frame LF1 is sandwiched by the separation region DIV. Then, a chip mounting portion tab (c) and a chip mounting portion tab (l) are disposed in the product region PR, and a driver IC chip chp (c) is mounted on the chip mounting portion tab (c) via a high melting point solder HS 1. Further, a low MOS chip chp (l) is mounted on the chip mounting portion tab (l) via a high melting point solder HS1, and a low MOS clip clp (l) is arranged on the low MOS chip chp (l) via a high melting point solder HS 2. Note that, although not shown in fig. 44, it can also be seen from, for example, fig. 42B that a chip mounting portion tab (h) is also arranged in the product region PR, a high MOS chip chp (h) is mounted over the chip mounting portion tab (h) via a refractory solder HS1, and a high MOS clip clp (h) is arranged over the high MOS chip chp (h) via a refractory solder HS 2.

Here, above the partition DIV of the lead frame LF1, the partition DIV2 of the clip frame CLF is arranged, and the upper surface side of the lead frame LF1 is supported by the support member SU so that the partition DIV2 contacts the support member SU. Thus, the channel DIT of the support member SU will be arranged at a position where it overlaps the product region PR formed in the lead frame LF1 in a planar manner. Then, in the present second embodiment, as shown in fig. 44, there is a gap between the bottom surface BS of the channel DIT provided in the support member SU and the upper surface of the driver IC chip chp (c). As a result, according to the present second embodiment, the support member SU will support the upper surface side of the lead frame LF1 in a state of not contacting the driver IC chip chp (c). Therefore, according to the present second embodiment, the upper surface side of the lead frame LF1 can be supported without breaking the driver IC chip chp (c).

On the other hand, as shown in fig. 44, the upper surface side of the lead frame LF1 is supported by the support member SU so that the bottom surface BS of the channel DIT contacts the upper surface of the low MOS clip clp (l) mounted on the low MOS chip chp (l).

Thus, since the product section PR itself formed in the lead frame LF1 is in a state of being not supported at all by the support member SU, the stability of fixing of the product section PR can be improved. As a result, also in the product region PR of the lead frame LF1, a sufficiently large reaction force (repulsive force) generated by the lead frame LF1 in applying the tape TP to the rear surface of the lead frame LF1 can be ensured. Therefore, according to the present second embodiment, the tape TP can be reliably applied to the rear surface of the product region PR formed in the lead frame LF1 without including voids or the like. That is, according to the present second embodiment, even in a state where the driver IC chip chp (c), the high MOS chip chp (h), and the low MOS chip chp (l) are mounted on the upper surface side of the lead frame LF1, the tape TP can be reliably applied to the rear surface of the lead frame LF1 (in particular, to the rear surface of the product region PR).

Here, the low MOS chip chp (l) is not configured such that the bottom surface BS of the channel DIT directly contacts the upper surface of the low MOS chip chp (l), but is configured such that the low MOS clip clp (l) is interposed between the low MOS chip chp (l) and the bottom surface BS of the channel DIT. That is, in the low MOS chip chp (l), the bottom surface BS of the channel DIT does not directly contact the upper surface of the low MOS chip chp (l). That is, in the present second embodiment, the low MOS clip clp (l) interposed between the low MOS chip chp (l) and the bottom surface BS of the channel DIT functions as a buffer material. For this reason, even if the upper surface side of the lead frame LF1 is supported by the support member SU so that the bottom surface BS of the channel DIT contacts the low MOS clip clp (l), damage to the low MOS chip chp (l) can be reduced to a level without problems.

From the above, also in the present second embodiment, as in the above-described first embodiment, there is a gap between the bottom surface BS of the channel DIT provided in the support member SU and the upper surface of the driver IC chip chp (c). On the other hand, the bottom surface BS of the channel DIT formed in the support member SU contacts the upper surface of the low MOS clip clp (l) mounted on the low MOS chip chp (l).

Thus, according to the present second embodiment, such a significant effect can be obtained: the tape TP can be reliably applied to the rear surface of the lead frame LF1 (particularly, to the rear surface of the product region PR) while reducing damage to the driver IC chips chp (c), the high MOS chips chp (h), and the low MOS chips chp (l).

< modification 1>

Next, a modification 1 of the present second embodiment is described. Fig. 45 is a sectional view showing how the tape TP is applied to the rear surface of the lead frame LF1 in the state where the upper surface side of the lead frame LF1 is supported by the support member SU in this modification 1.

As shown in fig. 45, in the present modification 1, the buffer material BUF is interposed between the bottom surface BS of the channel DIT provided in the support member SU and the upper surface of the driver IC chip chp (c). Thus, the driver IC chip chp (c) will be supported by the support member SU as well. As a result, according to the present modification 1, since the entire product region PR can be supported by the support members SU, the tape TP can be reliably applied to the rear surface of the lead frame LF1 (in particular, to the rear surface of the product region PR).

Then, in the present modification 1, the upper surface of the driver IC chip chp (c) does not directly contact the bottom surface BS of the channel DIT provided in the support member SU, but indirectly contacts the bottom surface tube BS of the channel DIT via the buffer material BUF. Therefore, even when the upper surface of the driver IC chip chp (c) is supported by the support member SU, damage to the driver IC chip chp (c) can be reduced to a level without problems.

According to the above, according to the present modification 1, such a remarkable effect can be obtained: the tape TP can be reliably applied to the rear surface of the lead frame LF1 (in particular, to the entire rear surface of the product region PR) while reducing damage to the driver IC chips chp (c), the high MOS chips chp (h), and the low MOS chips chp (l).

< modification 2>

Subsequently, a modification 2 of the present second embodiment is described. Fig. 46 is a sectional view showing how the tape TP is applied to the rear surface of the lead frame LF1 in the state where the upper surface side of the lead frame LF1 is supported by the support member SU in this modification 2.

As shown in fig. 46, in the present modification 2, the buffer material BUF is interposed between the bottom surface BS of the channel DIT provided in the support member SU and the upper surface of the driver IC chip chp (c). Thus, the driver IC chip chp (c) will be supported by the support member SU as well. As a result, according to the present modification 2, since the entire product region PR can be supported by the support member SU, the tape TP can be reliably applied to the rear surface of the lead frame LF1 (in particular, to the rear surface of the product region PR).

Then, also in the present modification 2, the upper surface of the driver IC chip chp (c) does not directly contact the bottom surface BS of the channel DIT provided in the support member SU, but indirectly contacts the bottom surface BS of the channel DIT via the buffer material BUF. Therefore, even when the upper surface of the driver IC chip chp (c) is supported by the support member SU, damage to the driver IC chip chp (c) can be reduced to a level without problems.

Further, in the present modification 2, the buffer material BUF is also interposed between the upper surface of the low MOS clip clp (l) and the bottom surface BS of the channel DIT provided in the support member SU. That is, in the present modification 2, the low MOS clip clp (l) and the buffer material BUF are interposed between the low MOS chip chp (l) and the bottom surface BS of the channel DIT. That is, in the present modification 2, the low MOS clip clp (l) interposed between the low MOS chip chp (l) and the bottom surface BS of the channel DIT functions as a buffer material, and the buffer material BUF is further disposed between the low MOS clip clp (l) and the bottom surface BS of the channel DIT. For this reason, even if the upper surface side of the lead frame LF1 is supported by the support member SU, damage to the low MOS chip chp (l) can be further reduced to a level without problems.

From the above, with the present modification 2 as well, such a significant effect can be obtained: the tape TP can be reliably applied to the rear surface of the lead frame LF1 (particularly, to the entire rear surface of the product region PR) while reducing damage to the driver IC chips chp (c), the high MOS chips chp (h), and the low MOS chips chp (l).

(third embodiment)

Also in the present third embodiment, the high-melting solder HS1 is used for the connection between the chip mounting portion tab (h) and the high MOS chip chp (h) and for the connection between the chip mounting portion tab (l) and the low MOS chip chp (l). On the other hand, described in the present third embodiment is an example in which the silver paste PST is used for connection between the chip mounting portion tab (c) and the driver IC chip chp (c).

< packaging configuration of semiconductor device in third embodiment >

Since the package configuration of the semiconductor device in this third embodiment is substantially the same as that of the semiconductor device PK2 in the above-described second embodiment, the description will focus on the differences.

Fig. 47 is a view showing an internal configuration of the semiconductor device PK3 in the present third embodiment. In fig. 47, the pattern shown in the center is a plan view of the inside of the semiconductor device PK3 viewed from the upper surface side through the resin MR, and a sectional view is shown on each of all sides thereof.

In fig. 47, also in the present third embodiment, the suspension lead HL is formed integrally with the high MOS clip clp (h), and the suspension lead HL reaches the outer edge portion of the sealing body formed of the resin MR. Similarly, the suspension lead HL is also integrally formed within the low MOS clip clp (l), and the suspension lead HL reaches an outer edge portion of the sealing body formed of the resin MR.

Here, also in the present third embodiment, as shown in fig. 47, the high-melting solder HS1 is used for the connection between the chip mounting portion tab (h) and the high MOS chip chp (h) and for the connection between the chip mounting portion tab (l) and the low MOS chip chp (l). On the other hand, in the present third embodiment, the silver paste PST is used for connection between the chip mounting portion tab (c) and the driver IC chip chp (c). That is, in the present third embodiment, the connection material for the connection between the chip mounting portion tab (h) and the high MOS chip chp (h) and for the connection between the chip mounting portion tab (l) and the low MOS chip chp (l) is different from the connection material for the connection between the chip mounting portion tab (c) and the driver IC chip chp (c). The other configurations are the same as those of the above-described second embodiment.

< method for manufacturing semiconductor device in third embodiment >

The semiconductor device in the present third embodiment is configured as described above, and a method for manufacturing the semiconductor device in the present third embodiment is described below with reference to the drawings.

Fig. 48 to 50 show a flowchart showing a manufacturing flow of the semiconductor device in the present third embodiment. Further, fig. 51 to 57 are views each showing a manufacturing process of the semiconductor device in the present third embodiment.

First, a lead frame LF1 is prepared (S301 of fig. 48). This lead frame LF1 has, for example, the same configuration as that of the lead frame LF1 used in the above-described first embodiment shown in fig. 14A to 14C. For example, as shown in fig. 14C, in the lead frame LF1 of the present third embodiment, a plurality of product sections PR are arranged in a matrix, each product section PR including a chip mounting portion (tab C), a chip mounting portion tab (h), a chip mounting portion tab (l), and leads LD.

Further, also in this third embodiment, as in the above-described second embodiment, a clip frame CLF as shown in fig. 38A and 38B was prepared. A schematic overall configuration of the clip frame CLF is shown in fig. 38A, and a part of the clip frame CLF is enlarged and shown in fig. 38B. As shown in fig. 38B, a plurality of cell regions UR each including a high MOS clip clp (h) and a low MOS clip clp (l) are included in the clip frame CLF, and the cell regions UR are arranged in a matrix.

Here, for example, as shown in fig. 38B, within each of the plurality of cell regions UR arranged in a matrix, a high MOS clip clp (h) and a low MOS clip clp (l) are formed, and both the high MOS clip clp (h) and the low MOS clip clp (l) are coupled to the frame body of the clip frame CLF through the suspension lead HL. Therefore, in the entire clip frame CLF, the plurality of high MOS clips clp (h) and the plurality of low MOS clips clp (l) will be integrally formed.

Then, as shown in fig. 51, in each product region PR formed in the lead frame LF1, a high-melting solder HS1 is formed over the chip mounting portion tab (h) and the chip mounting portion tab (l) (S302 of fig. 48). Specifically, for example, the high melting point solder HS1 is printed over the chip mounting portion tab (h) and the chip mounting portion tab (l) using a solder printing method. Here, the emphasis is on: as shown in fig. 51, the high-melting solder HS1 is not formed on the chip mounting portion tab (c). This constitutes a part of the characteristics of the present third embodiment.

Then, as shown in fig. 52, in each product region PR formed in the lead frame LF1, the high MOS chip chp (h) is first mounted on the chip mounting portion tab (h) (S303 of fig. 48), and then the low MOS chip chp (l) is mounted on the chip mounting portion tab (l) (S304 of fig. 48). Note that the mounting order of the high MOS chip chp (h) and the low MOS chip chp (l) is not limited thereto, and may be changed as needed. Here too, the emphasis is on: the driver IC chip chp (c) is not mounted on the chip mounting portion tab (c) at this stage, but also relates to a case where the high melting point solder HS1 is not formed on the chip mounting portion tab (c). This also constitutes part of the characteristics of the third embodiment.

Thereafter, the lead frame LF1 is set in a positioning-dedicated jig (S305 in fig. 48). Specifically, as shown in fig. 52, the lead frame LF1 is positioned by inserting an opening OP1 formed in the lead frame LF1 into a protruding pin of, for example, a dedicated jig.

Then, as shown in fig. 53, in each product region PR formed in the lead frame LF1, a high-melting solder HS2 is formed over the high MOS chip chp (h) (S306 of fig. 48). Thereafter, the high-melting-point solder HS2 is formed on the low MOS chip chp (l) (S307 of fig. 48). Specifically, the high-melting-point solder HS2 is formed over the source electrode pad (high MOS pad) (not shown) formed in the high MOS chip chp (h), and the high-melting-point solder HS2 is formed over the source electrode pad (low MOS pad) (not shown) formed in the low MOS chip chp (l). Further, as shown in fig. 53, a high melting solder HS2 is also formed over a partial area of the chip mounting portion tab (l) and over a partial area of the lead line.

Specifically, the high melting point solder HS2 is also applied over the high MOS chip chp (h), over the low MOS chip chp (l), over a partial region of the chip mounting portion tab (l), and over a partial region of the lead line, for example, using a coating method. The high-melting-point solder HS2 formed at this time may have the same material composition as that of the above-described high-melting-point solder HS1, or may have a different material composition.

Thereafter, as shown in fig. 54, the clip frame CLF is set to the positioning-dedicated clip (S308 of fig. 48). Specifically, as shown in fig. 54, the opening OP2 formed in the clip frame CLF is further inserted into a protruding pin that has been inserted into the opening OP1 formed in the lead frame LF 1. Thus, according to the present third embodiment, the clip frames CLF can be arranged above the lead frame LF1 so as to overlap each other. That is, as described above, by inserting the opening OP1 formed in the lead frame LF1 and the opening OP2 formed in the clip frame CLF into the protruding pins provided in the dedicated jig, each product region PR formed in the lead frame LF1 and each unit region UR formed in the clip frame CLF can be overlapped with each other in a planar manner.

Thus, according to the present third embodiment, each product region PR and each unit region UR can be overlapped with each other in a planar manner by simply overlapping the lead frame LF1 with the clip frame CLF. This means that the high MOS clip clp (h) formed in each cell region UR can be immediately mounted on the high MOS chip chp (h) formed in each product region PR. Similarly, this means that the low MOS clip clp (l) formed in each cell region UR can be immediately mounted on the low MOS chip chp (l) formed in each product region PR. As a result, according to the present third embodiment, the manufacturing process can be simplified and thus the manufacturing cost of the semiconductor device PK3 can be reduced.

In this way, the source electrode pad formed in the high MOS chip chp (h) and the chip mounting portion tab (l) will be electrically coupled to each other through the high MOS clip clp (h). In addition, the source electrode pad formed in the low MOS chip chp (l) and the lead line to which the reference potential is supplied will be electrically coupled to each other through the low MOS clip clp (l).

Subsequently, reflow is performed for the high melting point solder HS1 and the high melting point solder HS2 (S309 of fig. 48). In particular, the lead frame LF1 containing the high melting point solder HS1 and the high melting point solder HS2 is heated at a temperature (first temperature) of, for example, about 350 ℃. Thus, the high melting point solder HS1 and the high melting point solder HS2 can be melted.

Then, in the present third embodiment, heat treatment (reflow) for melting the high melting point solder HS1 and the high melting point solder HS2 is performed in a state where the tape is not applied to the rear surface of the lead frame LF1 prepared in advance. Therefore, in the case of the present third embodiment, even if the reflow temperatures of the high-melting-point solder HS1 and the high-melting-point solder HS2 are higher than the heat-resistant temperature of the tape, the heat treatment of the tape does not cause a problem because the tape is not initially applied to the rear surface of the lead frame LF 1. That is, according to the present third embodiment, since the heat treatment (reflow) of the high melting point solder is performed before the tape is applied to the rear surface of the lead frame LF1, the heat resistance of the tape can be ensured regardless of the temperature of the heat treatment (reflow).

Thereafter, in order to remove the flux contained in the high-melting solder HS1 and the high-melting solder HS2, flux cleaning is performed (S310 of fig. 49). Then, from the viewpoint of improving the bonding characteristics of the wires in the wire bonding step performed in the subsequent step, the upper surface of the lead frame LF1 is cleaned by performing plasma treatment on the upper surface of the lead frame LF1 (S311 of fig. 49).

Then, as shown in fig. 55A and 55B, the tape TP is applied to the rear surface of the lead frame LF1 (S312 of fig. 49). That is, of the faces of the lead frame LF1, the tape TP is applied to the face opposite to the face on which the high MOS chip chp (h) and the low MOS chip chp (l) are mounted. At this time, as described above, the heat treatment (reflow) at about 350 ℃ for the high melting point solder HS1 and the high melting point solder HS2 has been completed in a step before the step of applying the tape TP, and therefore, in the present third embodiment, the heat resistance of the tape TP will not be an issue.

That is, the reflow temperature of the above-described high-melting-point solder HS1 and high-melting-point solder HS2 is approximately 350 ℃, for example, and exceeds the heat-resistant temperature of the tape TP (for example, about 250 ℃). Therefore, if the heat treatment for melting the high melting point solder HS1 and the high melting point solder HS2 is performed in a state where the tape TP is applied to the rear surface of the lead frame LF, the tape TP will not withstand the heat treatment. In this connection, in the present third embodiment, in the step before the step of applying the tape TP, the heat treatment (reflow) at about 350 ℃ for the high melting point solder HS1 and the high melting point solder HS2 has been completed. For this reason, in the present third embodiment, the heat resistance of the tape TP will not be a problem.

Here, in the present third embodiment, the driver IC chip chp (c) has not yet been mounted on the chip mounting portion tab (c) at the time of performing the step of applying the tape TP to the current rear surface of the lead frame LF 1. For this reason, in the present third embodiment as well, the chip mounting portion tab (c) in which the driver IC chip chp (c) is not mounted can be pressed. Therefore, the present third embodiment is characterized in that: the area for pressing the lead frame LF1 is increased, and thus the tape TP can be reliably applied to the rear surface of the lead frame LF 1. Details about this feature will be described later.

Subsequently, as shown in fig. 56, in each product region PR formed in the lead frame LF1, silver paste PST is formed over the chip mounting portion tab (c) (S313 of fig. 49). Specifically, for example, silver paste PST is applied over the chip mounting portion tab (c).

Then, as shown in fig. 57, in each product region PR formed in the lead frame LF1, a driver IC chip chp (c) is mounted on the chip mounting portion tab (c) (S314 of fig. 49). After that, a heat treatment (baking treatment) is performed to cure the silver paste PST (S315 of fig. 49). The heat treatment is performed at, for example, about 125 to about 200 ℃. Here, since the tape TP has been applied to the rear surface of the lead frame LF1 and the heat resistant temperature of the tape TP is about 250 ℃, the heat treatment applied in the above-described curing step of the silver paste PST does not cause a problem in the heat resistance of the tape TP.

That is, in the present third embodiment, in the step after the tape TP is applied to the rear surface of the lead frame LF1, the driver IC chip chp (c) is mounted on the chip mounting portion tab (c). The purpose is as follows: by configuring such that the driver IC chip chp (c) is not yet mounted on the chip mounting portion tab (c) at this stage when the tape TP is applied to the rear surface of the lead frame LF1, the chip mounting portion tab (c) itself is supported without breaking the driver IC chip chp (c).

That is, in the present third embodiment, in applying the tape TP to the rear surface of the lead frame LF1, mounting of the driver IC chip chp (c) to the chip mounting portion tab (c) is performed in a step after applying the tape TP to the rear surface of the lead frame LF1, so that the upper surface itself of the chip mounting portion tab (c) can be pressed as well. Thus, according to the present third embodiment, since the area for supporting the upper surface side of the lead frame LF1 can be increased, the tape TP can be reliably applied to the rear surface of the lead frame LF 1.

With this configuration, if the high melting point solder HS1 is used for connection between the chip mounting portion tab (c) and the driver IC chip chp (c), the heat treatment (reflow) applied to the high melting point solder HS1 will cause a problem in heat resistance of the tape TP. Then, in the present third embodiment, the silver paste PST is used for connection between the chip mounting portion tab (c) and the driver IC chip chp (c).

In this case, a heat treatment (baking treatment) is performed to cure the silver paste PST, and the heat treatment is performed at, for example, about 125 to about 200 ℃. On the other hand, since the tape TP has been applied to the rear surface of the lead frame LF1 and the heat resistant temperature of the tape TP is about 250 ℃, the heat treatment applied in the curing step of the silver paste PST does not cause a problem in the heat resistance of the tape TP.

As described above, in the present third embodiment, in applying the tape TP to the rear surface of the lead frame LF1, mounting of the driver IC chip chp (c) to the chip mounting portion tab (c) is performed in a step after applying the tape TP to the rear surface of the lead frame LF1, so that the upper surface itself of the chip mounting portion tab (c) can be pressed as well. Then, consider the following case: if the high melting point solder HS1 is used for the connection between the chip mounting portion tab (c) and the driver IC chip chp (c), the heat treatment (reflow) applied to the high melting point solder HS1 causes a problem in terms of heat resistance with TP, and the silver paste PST is used for the connection between the chip mounting portion tab (c) and the driver IC chip chp (c).

Here, even if not the high melting point solder HS1 but the silver paste PST is used for the connection between the chip mounting portion tab (c) and the driver IC chip chp (c), there is no problem in terms of performance. The reason for this will be described below. For example, the power MOSFET is formed in the high MOS chip chp (h) and the low MOS chip chp (l), and the rear surface of the chip functions as a drain electrode (drain region) of the power MOSFET. Therefore, in order to reduce the on-resistance, it is necessary to use the high melting point solder HS1 having a low resistance for the connection member for connecting the rear surface of the high MOS chip chp (h) or the low MOS chip chp (l) and the chip mounting portion (chip mounting portion tab (h) or the chip mounting portion tab (l)).

On the other hand, in the driver IC chip chp (c), although a MOSFET (field effect transistor) and a wiring layer for constituting the control circuit CC are formed, a power MOSFET is not formed, and thus the rear surface of the driver IC chip chp (c) is not used as a drain electrode. That is, current does not flow through the rear surface of the driver IC chip chp (c). Therefore, the driver IC chip chp (c) has a lower necessity of reducing the on-resistance than the high MOS chip chp (h) and the low MOS chip chp (l). That is, in the driver IC chip chp (c), for the connection between the chip mounting portion tab (c) and the rear surface of the driver IC chip chp (c), the use of the high melting point solder HS1 is not necessarily required, and the silver paste PST is sufficient for this purpose.

The following is noted: in the present third embodiment, the refractory solder HS1 is not used for the connection between the chip mounting portion tab (c) and the driver IC chip chp (c), but the silver paste PST is used for the connection between the chip mounting portion tab (c) and the driver IC chip chp (c). As a result, according to the present third embodiment, since the heat resistance of the tape TP can be ensured, the driver IC chip chp (c) can be mounted on the chip mounting portion tab (c) in the step after the tape TP is applied to the rear surface of the lead frame LF 1.

This means that: when the tape TP is applied to the rear surface of the lead frame LF1, the driver IC chip chp (c) can be configured so as not to be mounted on the chip mounting portion tab (c) at this stage. Thus, according to the present third embodiment, the chip mounting portion tab (c) itself can be supported without breaking the driver IC chip chp (c). Therefore, according to the present third embodiment, the area for supporting the upper surface side of the lead frame LF1 can be increased, and thus the tape TP can be reliably applied to the rear surface of the lead frame LF 1.

Subsequently, as in the second embodiment described above, the wire bonding step is performed (S316 of fig. 49). Here, also in the present third embodiment, the tape TP is applied to the rear surface of the lead frame LF1 in a step before the wire bonding step is performed. Therefore, according to the present third embodiment, the lead frame LF1 having the tape TP applied thereto can be easily vacuum-sucked. As a result, even with the lead frame LF1 corresponding to the MAP molding technique, the wire bonding step can be performed with the lead frame LF1 reliably fixed by vacuum suction. As a result, according to the third embodiment, the reliability in the wire bonding step can be improved.

Note that the wire bonding step is performed in a state where the lead frame LF1 is heated to about 200 to about 250 ℃ in order to stabilize the bonding of the wire W. However, since the heat-resistant temperature of the tape TP applied to the rear surface of the lead frame LF1 is about 250 ℃, the heat treatment applied in the wire bonding step does not cause a problem in the heat resistance of the tape TP.

Here, in the present third embodiment, in the step after the flux cleaning is performed, the driver IC chip chp (c) is mounted on the chip mounting portion tab (c), and the lead wire is bonded to the electrode pad formed in the driver IC chip chp (c) in the subsequent step. One of the characteristics of the present third embodiment is such a processing order.

That is, as the cleaning liquid used in the flux cleaning, for example, a cleaning liquid containing hydrocarbon may be used. At this time, if the flux cleaning step is performed in a stage after the driver IC chip chp (c) is mounted on the chip mounting portion tab (c), the electrode pads formed in the driver IC chip chp (c) will be exposed to the cleaning liquid. As a result, the electrode pads formed in the driver IC chip chp (c) will be contaminated by the cleaning liquid, which may adversely affect the coupling between the electrode pads and the wires.

In contrast, in the present third embodiment, in the step after the flux cleaning is performed, the driver IC chip chp (c) is mounted on the chip mounting portion tab (c). Therefore, there is no fear of contamination of the electrode pads formed in the driver IC chip chp (c) due to the cleaning liquid used in the flux cleaning. That is, according to the present third embodiment, since there is no adverse effect on the electrode pads formed in the driver IC chip chp (c) due to flux cleaning, the reliability of the coupling between the electrode pads formed in the driver IC chip chp (c) and the wires can be improved.

Then, the product areas formed in the lead frame LF1 are collectively sealed (molded) by resin (S317 of fig. 49). In other words, the product region PR in the lead frame LF1 is collectively sealed by the resin MR so as to cover the driver IC chip chp (c), the high MOS chip chp (h), and the low MOS chip chp (l), and thereby form a sealed body. That is, in the present third embodiment, as a technique for sealing the semiconductor chip by the resin, a so-called MAP molding technique is employed in which the product regions PR are contained in the cavity, and the product regions PR are collectively sealed by the resin. According to this MAP molding technique, since it is not necessary to provide a passage for injecting resin for each product region PR, the product regions PR can be densely arranged. Thus, according to the MAP molding technique, the number of products to be obtained can be increased, and thus cost reduction of the products can be achieved.

Then, in the present third embodiment, the adhesive tape TP is applied to the rear surface of the lead frame LF1 in a step before the resin sealing step (molding step) by the MAP molding technique. Therefore, according to the present third embodiment, the tape TP can be reliably applied to the rear surface terminals (leads) formed in the rear surface of the lead frame LF 1. As a result, also in the resin sealing step using the MAP molding technique, no gap is formed between the rear surface terminal and the tape TP, and thus the leakage of the resin into the rear surface of the rear surface terminal (resin burr) can be sufficiently suppressed.

Note that as the resin used in the resin sealing step, for example, a thermosetting resin is used. Therefore, the resin sealing step is performed in a state of being heated to about 160-200 ℃ so as to cure the thermosetting resin. However, since the heat-resistant temperature of the tape TP applied to the rear surface of the lead frame LF1 is about 250 ℃, the heat treatment applied in the resin sealing step does not cause a problem in the heat resistance of the tape TP.

Thereafter, the tape TP applied to the rear surface of the lead frame LF1 is peeled off from the lead frame LF1 (S318 of fig. 49). Then, plating films are formed on the upper surfaces of the chip mounting portion tab (c), the chip mounting portion tab (h), the chip mounting portion tab (l), and the rear surface terminals BTE exposed from the rear surface of the resin MR (sealing body) (see fig. 33) (S319 in fig. 50). Further, a mark is formed in the upper surface of the sealing body formed of the resin MR (marking step) (S320 of fig. 50).

Subsequently, a dicing tape is applied to the upper surface of the sealing body formed of resin (S321 of fig. 50). Then, the sealing body formed of resin is cut for each product area (package cutting) (S322 of fig. 50). Specifically, the separation regions (boundary regions) for separating the product regions PR formed in the lead frame LF1 are cut by a dicing blade, and each product region is singulated. Thus, for example, the semiconductor device PK3 shown in fig. 47 in the third embodiment can be obtained. Then, the suspended lead HL formed within the clip frame CLF is cut. As a result, the cross section of the suspension wire HL will be exposed from the side surface of the semiconductor device PK 3.

Thereafter, the singulated individual semiconductor devices PK3 are sorted by electronic testing (S323 of fig. 50), and the semiconductor devices PK3 that have been determined to be defect-free are packaged and shipped (S324 of fig. 50). In this way, the semiconductor device in the present third embodiment can be manufactured.

Note that in the present third embodiment, description has been made using an example of a clip frame CLF such as that shown in fig. 38A and 38B, but is not limited thereto, and a clip subassembly CLP such as that shown in fig. 15A and 15B may be used.

< characteristics of the third embodiment >

Next, features in the present third embodiment are described with reference to the drawings. The third embodiment is characterized in that: a method for fixing the lead frame LF1 while applying the tape TP to the rear surface of the lead frame LF 1. Specifically, the technical idea in the present third embodiment is: after the tape TP is applied to the rear surface of the lead frame LF1, the driver IC chip chp (c) is mounted on the chip mounting portion tab (c), so that the top of the chip mounting portion tab (c) can be pressed by the supporting member SU. Hereinafter, the technical idea in the present third embodiment will be specifically described.

Fig. 58A is a view showing the configuration of the lead frame LF1 immediately before the tape TP is applied to the rear surface of the lead frame LF1, and fig. 58B is an enlarged view showing a part of fig. 58A. As shown in fig. 58B, in the lead frame LF1 of the present third embodiment, the product zones PR are arranged in a matrix, and each product zone PR is partitioned by a partition zone (boundary zone). Now, each product zone PR is of interest. A chip mounting portion tab (c), a chip mounting portion tab (h), and a chip mounting portion tab (l) are disposed in each product region PR, a high MOS chip chp (h) is mounted on the chip mounting portion tab (h), and a low MOS chip chp (l) is mounted on the chip mounting portion tab (l). On the other hand, in the present third embodiment, the driver IC chip chp (c) is not mounted on the chip mounting portion tab (c).

In the present third embodiment, the clip frame CLF is installed to overlap the lead frame LF1 in a planar manner. In this clip frame CLF, the cell regions UR are arranged in a matrix, and each cell region UR is partitioned by a partition region (boundary region) DIV 2. Now, attention is paid to each cell region UR. A high MOS clip clp (h) and a low MOS clip clp (l) are disposed within each cell region UR. Thus, in this third embodiment, the high MOS clip clp (h) is arranged to span from above the high MOS chip chp (h) to above the chip mounting portion tab (l), and the low MOS clip clp (l) is arranged to span from above the low MOS chip chp (l) to above the lead. Then, high MOS clip clp (h) and low MOS clip clp (l) are coupled to partition DIV2 of clip frame CLF through suspension leads HL.

Fig. 59A is a plan view showing a schematic overall configuration of the support member SU used in the present third embodiment, and fig. 59B is an enlarged view of a part of fig. 59A. As shown in fig. 59A and 59B, the support member SU includes an outer frame portion, and a channel DIT is formed in an inner region of the outer frame portion. Then, the channel DIT provided in the support member SU is arranged to include the product region PR formed in the lead frame LF 1. Then, as shown in fig. 59B, in the support member SU used in the present third embodiment, a plurality of projections PJN are provided in the channel DIT. Each of these protrusions PJN of the protrusions PJN is provided to correspond to the chip mounting portion tab (c) arranged in each product region PR of the lead frame LF 1. In other words, the protrusion PJN is disposed within the channel DIT such that the protrusion PJN and the chip mounting portion tab (c) overlap each other in a planar manner.

Fig. 60 is a sectional view showing how the tape TP is applied to the rear surface of the lead frame LF1 in a state where the upper surface side of the lead frame LF1 is supported by the support member SU. As shown in fig. 60, the product region PR disposed in the lead frame LF1 is sandwiched by the separation region DIV. Then, a chip mounting portion tab (c) and a chip mounting portion tab (l) are disposed in the product region PR. Then, a low MOS chip chp (l) is mounted over the chip mounting portion tab (l) via a high melting point solder HS1, and a low MOS clip clp (l) is arranged over the low MOS chip chp (l) via a high melting point solder HS 2. Note that, although not shown in fig. 60, it can be seen from, for example, fig. 58B that a chip mounting portion tab (h) is also arranged in the product region PR, a high MOS chip chp (h) is mounted over the chip mounting portion tab (h) via a high melting point solder HS1, and a high MOS clip clp (h) is arranged over the high MOS chip chp (h) via a high melting point solder HS 2. On the other hand, in the present third embodiment, the driver IC chip chp (c) is not mounted on the chip mounting portion tab (c).

Here, above the partition DIV of the lead frame LF1, the partition DIV2 of the clip frame CLF is arranged, and the upper surface side of the lead frame LF1 is supported by the support member SU so that the partition DIV2 contacts the support member SU. Thus, the channel DIT of the support member SU will be arranged at a position where it overlaps the product region PR formed in the lead frame LF1 in a planar manner.

Then, in the present third embodiment, as shown in fig. 60, the protrusion PJN formed in the channel DIT provided in the support member SU is configured to press the chip mounting portion tab (c). As a result, according to the present third embodiment, the supporting member SU will support the upper surface side of the lead frame LF1 while pressing the chip mounting portion tab (c). Therefore, according to the present third embodiment, the area for supporting the upper surface side of the lead frame LF1 can be increased. Thus, according to the present third embodiment, the tape TP can be reliably applied to the rear surface of the lead frame LF1 (in particular, to the rear surface of the product region PR). In particular, in the present third embodiment, the chip mounting portion tab (c) can be sufficiently pressed by the protrusion PJN. Therefore, also in the rear surface of the chip mounting portion tab (c), the tape TP can be reliably applied. That is, according to the present third embodiment, the adhesion of the tape TP in the rear surface of the chip mounting portion tab (c) can be improved.

Thus, the following effects can be obtained. That is, above the chip mounting portion tab (c), the driver IC chip chp (c) is mounted in a subsequent step. In the driver IC chip chp (c), a large number of electrode pads are formed, and wires are electrically coupled to the electrode pads in a wire bonding step. This wire bonding step is performed with a wire frame LF1 vacuum suction lead to, for example, a heating block. At this time, for example, if the adhesion between the chip mounting portion tab (c) and the tape TP is not large enough due to the sandwiched gap (bubble) or the like, the chip mounting portion tab (c) cannot be firmly fixed, and the transmission of the ultrasonic vibration used in the wire bonding step is not sufficiently achieved, and thus the reliability of the wire connection to the driver IC chip chp (c) may be lowered.

In this connection, in the present third embodiment, particularly because the chip mounting portion tab (c) is directly pressed by the projection PJN, a sufficiently large reaction force (repulsive force) can be obtained from the chip mounting portion tab (c) side when the tape TP is applied to the rear surface of the chip mounting portion tab (c). And (6) obtaining the result. According to the present third embodiment, the tape TP can be reliably applied to the rear surface of the chip mounting portion tab (c). Thus, according to the present third embodiment, also in the wire bonding step, the chip mounting portion tab (c) can be firmly fixed to the heating block, and also the transmission of the ultrasonic vibration can be sufficiently achieved and the reliability of the wire connection to the driver IC chip chp (c) can be improved.

In particular, the present third embodiment has an advantage of pressing the chip mounting portion tab (c) on which the driver IC chip chp (c) is to be mounted by the protrusion PJN. This is because the number of electrode pads formed in the driver IC chip chp (c) is the largest among the high MOS chip chp (h), the low MOS chip chp (l), and the driver IC chip chp (c), and thus the reliability of wire connection is important in the wire bonding step here. Also from this point of view, the configuration of the present third embodiment is very advantageous in which the chip mounting portion tab (c) on which the driver IC chip chp (c) is to be mounted is directly pressed by the protrusion PJN.

On the other hand, also in the present third embodiment, as shown in fig. 60, the upper surface side of the lead frame LF1 is supported by the support member SU so that the bottom surface BS of the channel DIT contacts the upper surface of the lower MOS clip clp (l) mounted on the lower MOS chip chp (l).

Since this increases the area for supporting the product region PR formed in the lead frame LF1, reliability in fixing the product region PR can be improved. As a result, also in the product region PR of the lead frame LF1, a sufficiently large reaction force (repulsive force) generated by the lead frame LF1 in applying the tape TP to the rear surface of the lead frame LF1 can be ensured. Therefore, according to the present third embodiment, the tape TP can be reliably applied to the rear surface of the product region PR formed in the lead frame LF1 without including voids or the like. That is, according to the present third embodiment, even in a state where the high MOS chip chp (h) and the low MOS chip chp (l) are mounted on the upper surface side of the lead frame LF1, the tape TP can be reliably applied to the rear surface of the lead frame LF1 (in particular, to the rear surface of the product region PR).

Here, the low MOS chip chp (l) is not configured to cause the bottom surface BS of the channel DIT to directly contact the upper surface of the low MOS chip chp (l), but is configured such that the low MOS clip clp (l) is interposed between the low MOS chip chp (l) and the bottom surface BS of the channel DIT. That is, in the low MOS chip chp (l), the bottom surface BS of the channel DIT does not directly contact the upper surface of the low MOS chip chp (l). That is, in the present third embodiment, the low MOS clip clp (l) interposed between the low MOS chip chp (l) and the bottom surface BS of the channel DIT functions as a buffer material. For this reason, even if the upper surface side of the lead frame LF1 is supported by the support member SU so that the bottom surface BS of the channel DIT contacts the low MOS clip clp (l), damage to the low MOS chip chp (l) can be reduced to a level without problems.

In view of the above, in the present third embodiment, the protrusion PJN protruding from inside the channel DIT is configured to directly press the chip mounting portion tab (c). In addition, in the present third embodiment, the bottom surface BS of the channel DIT formed in the support member SU contacts the upper surface of the low MOS clip clp (l) mounted on the low MOS chip chp (l).

Thus, according to the present third embodiment, such a significant effect can be obtained: the tape TP can be reliably applied to the rear surface of the lead frame LF1 (particularly, to the rear surface of the product region PR) while reducing damage to the high MOS chip chp (h) and the low MOS chip chp (l).

< modification >

Subsequently, a modification of the present third embodiment is described. Fig. 61 is a sectional view showing how the tape TP is applied to the rear surface of the lead frame LF1 in the state where the upper surface side of the lead frame LF1 is supported by the support member SU in the present modification.

As shown in fig. 61, in the present modification, as in the third embodiment, the protrusion PJN is provided inside the channel DIT, and in the present modification, the buffer material BUF is interposed between the upper surface of the low MOS clip clp (l) and the bottom surface BS of the channel DIT provided inside the support member SU. That is, in the present modification, the low MOS clip clp (l) and the buffer material BUF are interposed between the low MOS chip chp (l) and the bottom surface BS of the channel DIT. That is, in the present modification, the low MOS clip clp (l) interposed between the low MOS chip chp (l) and the bottom surface BS of the channel DIT functions as a buffer material, and the buffer material BUF is also disposed between the low MOS clip clp (l) and the bottom surface BS of the channel DIT. For this reason, even if the upper surface side of the lead frame LF1 is supported by the support member SU, damage to the low MOS chip chp (l) can be further reduced to a level without problems.

From the above, with the present modification as well, such a significant effect can be obtained: the tape TP can be reliably applied to the rear surface of the lead frame LF1 (in particular, to the entire rear surface of the product region PR) while reducing damage to the high MOS chip chp (h) and the low MOS chip chp (l).

(fourth embodiment)

In the above-described first to third embodiments, the semiconductor device in which the driver IC chip chp (c), the high MOS chip chp (h), and the low MOS chip chp (l) are sealed by the sealing body has been described, but the technical ideas in the above-described first to third embodiments can be equally applied to, for example, the semiconductor device in which the high MOS chip chp (h) and the low MOS chip chp (l) are sealed by the sealing body.

Fig. 62 is a view showing the configuration of the lead frame LF2 immediately before the tape TP is applied to the rear surface of the lead frame LF2 in the present fourth embodiment. As shown in fig. 62, in the lead frame LF2 of the present fourth embodiment, the product fields PR are arranged in a matrix, and each product field PR is divided by a dividing field (boundary field) DIV. Then, focusing on each product region PR, a chip mounting portion tab (h) and a chip mounting portion tab (l) are arranged in each product region PR. At this time, the high MOS chip chp (h) is mounted on the chip mounting portion tab (h), and the low MOS chip chp (l) is mounted on the chip mounting portion tab (l). Further, the high MOS clip clp (h) is arranged to cross over the high MOS chip chp (h) to the chip mounting portion tab (l), and the low MOS clip clp (l) is arranged to cross over the low MOS chip chp (l) to the lead.

In the present fourth embodiment, the tape TP is to be applied to the rear surface of the lead frame LF2 configured in this manner. Fig. 63 is a view showing a state in which the tape TP has been applied to the rear surface of the lead frame LF2 in the present fourth embodiment. As shown in fig. 63, the tape TP is applied to the entire rear surface of the lead frame LF 2.

Then, in the present fourth embodiment, in the face of the lead frame LF2, the tape TP is to be applied to the rear surface of the lead frame LF2 with the upper surface opposite to the rear surface to which the tape TP is applied being supported by the support member. Here, in the present fourth embodiment, the upper surface side of the lead frame LF2 is to be supported by the supporting member, but the high MOS chip chp (h) and the low MOS chip chp (l) have been mounted on the upper surface side of the lead frame LF2 as described above. Therefore, also in the present fourth embodiment, as in the above-described first to third embodiments, the upper surface side of the lead frame LF2 needs to be supported by the supporting member without damaging the high MOS chip chp (h) and the low MOS chip chp (l).

Fig. 64 is a plan view showing a schematic overall configuration of the support member SU used in the present fourth embodiment. As shown in fig. 64, the support member SU includes a plurality of frame portions, and the channels DIT are partitioned by the frame portions. Then, for example, channels DIT provided in the support member SU shown in fig. 64 are arranged corresponding to the product region PR of the lead frame LF2 shown in fig. 62.

Fig. 65 is a sectional view showing how the tape TP is applied to the rear surface of the lead frame LF2 in a state where the upper surface side of the lead frame LF2 is supported by the support member SU in the present fourth embodiment.

As shown in fig. 65, in the present fourth embodiment, the buffer material BUF is also interposed between the upper surface of the high MOS clip clp (h) and the bottom surface BS of the channel DIT provided in the support member SU. That is, in the present fourth embodiment, the high MOS clip clp (h) and the buffer material BUF are interposed between the high MOS chip chp (h) and the bottom surface BS of the channel DIT. That is, in the present fourth embodiment, the high MOS clip clp (h) interposed between the high MOS chip chp (h) and the bottom surface BS of the channel DIT functions as a buffer material, and the buffer material BUF is further disposed between the high MOS clip clp (h) and the bottom surface BS of the channel DIT. For this reason, even if the upper surface of the lead frame LF2 is supported by the support member SU, damage to the high MOS chip chp (h) can be further reduced to a level without problems.

Similarly, in the present fourth embodiment, the buffer material BUF is also interposed between the upper surface of the low MOS clip clp (l) and the bottom surface BS of the channel DIT provided in the support member SU. That is, in the present fourth embodiment, the low MOS clip clp (l) and the buffer material BUF are interposed between the low MOS chip chp (l) and the bottom surface BS of the channel DIT. That is, in the present fourth embodiment, the low MOS clip clp (l) interposed between the low MOS chip chp (l) and the bottom surface BS of the channel DIT functions as a buffer material, and the buffer material BUF is further disposed between the low MOS clip clp (l) and the bottom surface BS of the channel DIT. For this reason, even if the upper surface side of the lead frame LF2 is supported by the support member SU, damage to the low MOS chip chp (l) can be further reduced to a level without problems.

From the above, with the present fourth embodiment as well, such a significant effect can be obtained: the tape TP can be reliably applied to the rear surface of the lead frame LF2 (in particular, to the entire rear surface of the product region PR) while reducing damage to the high MOS chip chp (h) and the low MOS chip chp (l).

Note that, in the present fourth embodiment, the example using the buffer material BUF has been described, but as in the above-described first embodiment, the bottom surface BS of the channel DIT may be configured to contact the top of the high MOS clip clp (h) and the top of the low MOS clip clp (l) without using the buffer material BUF.

Subsequently, as shown in fig. 66, the gate electrode pad gp (h) formed in the high MOS chip chp (h) and the lead LD are electrically coupled to each other by the wire W, and the gate electrode pad gp (l) formed in the low MOS chip chp (l) and the lead LD are electrically coupled to each other by the wire W. The subsequent steps are the same as those of the first embodiment described above. In this way, the semiconductor device in the present fourth embodiment can be manufactured.

< modification 1>

As with the fourth embodiment, modification 1 is also directed to a semiconductor device in which a high MOS chip chp (h) and a low MOS chip chp (l) are sealed by a sealing body, but particularly, an example in which a high MOS clip clp (h) is not mounted on the high MOS chip chp (h) is described in this modification 1.

Fig. 67 is a view showing the configuration of the lead frame LF2 immediately before the tape TP is applied to the rear surface of the lead frame LF2 in this modification 1. As shown in fig. 67, in the lead frame LF2 of this modification 1, the product fields PR are arranged in a matrix, and each product field PR is partitioned by a partition field (boundary region) DIV. Then, focusing on each product region PR, a chip mounting portion tab (h) and a chip mounting portion tab (l) are arranged in each product region PR. At this time, the high MOS chip chp (h) is not mounted on the chip mounting portion tab (h), and the low MOS chip chp (l) is mounted on the chip mounting portion tab (l). Further, the low MOS clip clp (l) is arranged to span from above the low MOS chip chp (l) to above the leads.

In the present modification 1, the tape TP is to be applied to the rear surface of the lead frame LF2 configured in this manner. Fig. 68 is a view showing a state in which the tape TP has been applied to the rear surface of the lead frame LF2 in the present modification 1. As shown in fig. 68, the tape TP is applied over the entire rear surface of the lead frame LF 2.

Then, in the present modification 1, in the face of the lead frame LF2, the tape TP will be applied to the rear surface of the lead frame LF2 while the upper surface opposite to the rear surface to which the tape TP is applied is supported by the support member. Here, in the present modification 1, although the upper surface side of the lead frame LF2 is to be supported by the supporting member, the driver IC chip chp (c) has been mounted on the upper surface side of the lead frame LF2 as described above. Therefore, also in this modification 1, the upper surface side of the lead frame LF2 needs to be supported by the supporting member without breaking the low MOS chip chp (l).

Fig. 69 is a sectional view showing how the tape TP is applied to the rear surface of the lead frame LF2 in the state where the upper surface side of the lead frame LF2 is supported by the support member SU in this modification 1. As shown in fig. 69, the high MOS chip chp (h) has not yet been mounted on the chip mounting portion tab (tab h) at the time of performing the step of applying the tape TP to the current rear surface of the lead frame LF 2. For this reason, in the present modification 1, the chip mounting portion tab (h) on which the high MOS chip chp (h) is not mounted can be pressed by the support member SU. Therefore, in the present modification 1, the area for pressing the lead frame LF2 is increased, and thus the tape TP can be reliably applied to the rear surface of the lead frame LF 2.

Further, in the present modification 1, the buffer material BUF is also interposed between the upper surface of the low MOS clip clp (l) and the bottom surface BS of the channel DIT provided in the support member SU. That is, in the present modification 1, the low MOS clip clp (l) and the buffer material BUF are interposed between the low MOS chip chp (l) and the bottom surface BS of the channel DIT. That is, in the present modification 1, the low MOS clip clp (l) interposed between the low MOS chip chp (l) and the bottom surface BS of the channel DIT functions as a buffer material, and the buffer material BUF is further disposed between the low MOS clip clp (l) and the bottom surface BS of the channel DIT. For this reason, even if the upper surface side of the lead frame LF2 is supported by the support member SU, damage to the low MOS chip chp (l) can be reduced to a level without problems.

Note that, also in the present modification 1, the example using the buffer material BUF has been described, but for example, the bottom surface BS of the channel DIT may also be configured to contact the top of the low MOS clip clp (l) without using the buffer material BUF.

Subsequently, in each product region PR formed in the lead frame LF2, silver paste is applied over the chip mounting portion tab (h). Then, as shown in fig. 70, in each product region PR formed in the lead frame LF2, a high MOS chip chp (h) is mounted on the chip mounting portion tab (h). Subsequently, as shown in fig. 71, the gate electrode pad gp (h) formed in the high MOS chip chp (h) and the lead line LD are electrically coupled to each other through a wire W, and the source electrode pad sp (h) formed in the high MOS chip chp (h) and the chip mounting portion tab (l) are electrically coupled to each other through a wire W. In addition, the gate electrode pad gp (l) formed in the low MOS chip chp (l) and the lead LD are electrically coupled to each other by the wire W. The subsequent steps are the same as those of the first embodiment described above. In this way, the semiconductor device in the present modification 1 can be manufactured.

< modification 2>

In modification 2, a semiconductor device in which a single semiconductor device, for example, a power MOSFET (switching field effect transistor) having formed therein is sealed by a sealing body is described.

Fig. 72 is a view showing the configuration of the lead frame LF3 immediately before the tape TP is applied to the rear surface of the lead frame LF3 in this modification 2. As shown in fig. 72, in the lead frame LF3 of the present modification 2, the product fields PR are arranged in a matrix, and each product field PR is partitioned by a partition field (boundary region) DIV. Focusing on each product region PR, a chip mounting portion TAB2 is disposed in each product region PR. Then, the semiconductor chip CHP2 is mounted over the chip mounting portion TAB2, and the clip CLP2 is arranged to cross over the semiconductor chip CHP2 over the lead LD 1.

In the present modification 2, the tape TP is to be applied to the rear surface of the lead frame LF3 configured in this way. Fig. 73 is a view showing a state in which the tape TP has been applied to the rear surface of the lead frame LF3 in the present modification 2. As shown in fig. 73, the tape TP is applied over the entire rear surface of the lead frame LF 3.

Then, in the present modification 2, of the faces of the lead frame LF3, the tape TP is to be applied to the rear face of the lead frame LF3 in a state where the upper face opposite to the rear face to which the tape TP is applied is supported by the support member. Here, in the present modification 2, the upper surface side of the lead frame LF3 is to be supported by the supporting member, but the semiconductor chip CHP2 has been mounted on the upper surface side of the lead frame LF3 as described above. Therefore, also in the present modification 2, the upper surface side of the lead frame LF3 needs to be supported by the supporting member without breaking the semiconductor chip CHP 2.

Fig. 74 is a sectional view showing how the tape TP is applied to the rear surface of the lead frame LF3 in the state where the upper surface of the lead frame LF3 is supported by the support member SU in this modification 2. As shown in fig. 74, in the present modification 2, the buffer material BUF is also interposed between the upper surface of the clip CLP2 and the bottom surface BS of the channel DIT provided in the support member SU. That is, in the present modification 2, the clip CLP2 and the buffer material BUF are interposed between the semiconductor chip CHP2 and the bottom surface BS of the channel DIT. That is, in the present modification 2, the clip CLP2 interposed between the semiconductor chip CHP2 and the bottom surface BS of the channel DIT functions as a buffer material, and further, the buffer material BUF is also disposed between the clip CLP2 and the bottom surface BS of the channel DIT. For this reason, even if the upper surface side of the lead frame LF3 is supported by the support member SU, damage to the semiconductor chip CHP2 can be reduced to a level without problems.

Note that, also in the present modification 2, an example using the buffer material BUF has been described, but for example, the bottom surface BS of the channel DIT may be fitted to contact the top of the clip CLP2 without using the buffer material BUF.

Thereafter, as shown in fig. 75, the gate electrode pad GP2 formed in the semiconductor device CHP2 and the lead LD2 are electrically coupled to each other by a wire W. The subsequent steps are the same as those of the first embodiment described above. In this way, the semiconductor device in the present modification 2 can be manufactured.

This invention of the present inventors has been described specifically according to the embodiments. However, it is apparent that the present invention is not limited to these embodiments, and various modifications are possible without departing from the scope of the present invention.

Claims (18)

1. A method of manufacturing a semiconductor device, comprising the steps of:

(a) preparing a first lead frame having a plurality of first regions arranged in a matrix therein, each first region including a first chip mounting portion, a second chip mounting portion and a first lead,

(b) mounting a first semiconductor chip over an upper surface of the first chip mounting portion via a first conductive adhesive, and mounting a second semiconductor chip over an upper surface of the second chip mounting portion via the first conductive adhesive,

(c) mounting a first metal plate to a first electrode pad of the first semiconductor chip and to the first lead via a second conductive adhesive,

(d) heating the first conductive adhesive and the second conductive adhesive at a first temperature,

(e) after step (d), applying a tape to a first face of the first lead frame opposite to the face on which the first semiconductor chip is mounted and a second face opposite to the face on which the second semiconductor chip is mounted, and

(f) after step (e), forming a sealing body so as to cover the first semiconductor chip and the second semiconductor chip by collectively sealing the plurality of first regions in the first lead frame,

wherein the step (e) applies the tape to the first lead frame while supporting the first metal plate, and

wherein step (e) is performed without the second semiconductor chip being supported.

2. The method of manufacturing a semiconductor device according to claim 1,

wherein step (e) applies the tape to the first lead frame while supporting the first semiconductor chip via a buffer material.

3. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of:

after step (e) and before step (f), electrically coupling the second electrode pad of the first semiconductor chip and the electrode pad of the second semiconductor chip to each other through a metal wire.

4. The method of manufacturing a semiconductor device according to claim 2,

wherein step (e) supports the first metal plate via the buffer material.

5. The method of manufacturing a semiconductor device according to claim 2,

wherein a longitudinal elastic modulus of the buffer material is lower than a longitudinal elastic modulus of the first semiconductor chip.

6. The method of manufacturing a semiconductor device according to claim 1,

wherein the step (c) is performed by overlapping a second lead frame in which a plurality of first metal plates are arranged in a matrix with a surface of the first lead frame on which the first semiconductor chip is mounted.

7. The method of manufacturing a semiconductor device according to claim 6,

wherein a layout pitch in a first direction of the plurality of first metal plates of the second lead frame and in a second direction perpendicular to the first direction is the same as a layout pitch in the first direction and the second direction of the first chip mounting portion of the first lead frame.

8. The method of manufacturing a semiconductor device according to claim 1, further comprising the steps of:

(g) after step (f), peeling the tape from the first lead frame, and

(h) after step (g), singulating by cutting an area between each of the plurality of first areas in the first lead frame with a dicing blade.

9. The method of manufacturing a semiconductor device according to claim 1,

wherein the first temperature is higher than the heatproof temperature of the belt.

10. The method of manufacturing a semiconductor device according to claim 9,

wherein the first conductive adhesive and the second conductive adhesive are solder.

11. The method of manufacturing a semiconductor device according to claim 3,

wherein the first semiconductor chip includes a field effect transistor,

wherein the first semiconductor chip includes an upper surface in which the first electrode pad and the second electrode pad are arranged, and a rear surface opposite to the upper surface,

wherein the second semiconductor chip includes a control circuit that controls the field effect transistor,

wherein the first electrode pad of the first semiconductor chip is a source electrode pad,

wherein the second electrode pad of the first semiconductor chip is a gate electrode pad, and

wherein a drain electrode is formed on the rear surface of the first semiconductor chip.

12. A method of manufacturing a semiconductor device, comprising the steps of:

(a) preparing a lead frame in which a plurality of first regions including a first chip mounting portion, a second chip mounting portion and first leads are arranged in a matrix,

(b) mounting a first semiconductor chip over an upper surface of the first chip mounting portion via a first conductive adhesive,

(c) mounting a first metal plate to a first electrode pad of the first semiconductor chip and to the first lead via a second conductive adhesive,

(d) heating the first conductive adhesive and the second conductive adhesive at a first temperature,

(e) after step (d), cleaning the leadframe,

(f) applying a tape to a face of the lead frame opposite to a face on which the first semiconductor chip is mounted after step (e),

(g) after step (f), mounting a second semiconductor chip over the upper surface of the second chip mounting portion via a third conductive adhesive,

(h) after step (g), heating the third conductive adhesive at a second temperature, and

(i) after step (h), forming a sealing body so as to cover the first semiconductor chip and the second semiconductor chip by collectively sealing a plurality of first regions within the lead frame,

wherein the second temperature is lower than the first temperature.

13. The method of manufacturing a semiconductor device according to claim 12,

wherein the first temperature is higher than the heat resistant temperature of the belt, and

wherein the second temperature is lower than the heat resistant temperature of the belt.

14. The method of manufacturing a semiconductor device according to claim 13,

wherein the first conductive adhesive and the second conductive adhesive are solders, and

wherein the third conductive adhesive is a silver paste.

15. The method of manufacturing a semiconductor device according to claim 12, further comprising the steps of:

after step (h) and before step (i), electrically coupling the second electrode pad of the first semiconductor chip and the electrode pad of the second semiconductor chip to each other through a metal wire.

16. The method of manufacturing a semiconductor device according to claim 15,

wherein the first semiconductor chip includes a field effect transistor,

wherein the first semiconductor chip includes an upper surface on which the first electrode pad and the second electrode pad are arranged, and a rear surface opposite to the upper surface,

wherein the second semiconductor chip includes a control circuit that controls the field effect transistor,

wherein the first electrode pad of the first semiconductor chip is a source electrode pad,

wherein the second electrode pad of the first semiconductor chip is a gate electrode pad, and

wherein a drain electrode is formed over the back surface of the first semiconductor chip.

17. The method of manufacturing a semiconductor device according to claim 12, further comprising the steps of:

(j) (ii) after step (i), peeling the tape from the lead frame, and

(k) after step (j), singulating by cutting an area between each of the plurality of first areas in the lead frame with a dicing blade.

18. The method of manufacturing a semiconductor device according to claim 12,

wherein the step (f) is performed with the second chip mounting portion supported.