HK1195164A

HK1195164A - Rfid tags based on self-assembly nanoparticles

Info

Publication number: HK1195164A
Application number: HK14108187.0A
Authority: HK
Inventors: 华礼生; 周晔; 韩素婷; 许宗祥
Original assignee: 纳米及先进材料研发院有限公司
Priority date: 2013-01-11
Filing date: 2014-08-11
Publication date: 2014-10-31

Abstract

A semiconductor device comprising a gate electrode; an insulating layer in electrical connection with the gate electrode; a source electrode and a drain electrode; and a semiconducting channel layer configured to selectively allow electrically connection between the source electrode and the drain electrode based on the voltage on the gate electrode; wherein the semiconducting channel layer comprises metal nanoparticles; and the semiconducting channel layer is in contact with the source electrode, the drain electrode and the insulating layer. A method of manufacturing the semiconductor device of the present invention is also disclosed.

Description

RFID tag based on self-assembled nanoparticles

Technical Field

The present invention relates to a semiconductor device such as a thin film transistor and a method for manufacturing the same.

Background

Conventionally, silicon is used as a main raw material for manufacturing a semiconductor device including a transistor. Semiconductor devices are fabricated relying on the unique semiconductor properties of silicon. However, current silicon-based manufacturing processes are expensive and not suitable for forming semiconductor devices on many flexible substrates, such as plastic materials. This is because some conventional production steps involve high temperatures, which tend to melt the flexible substrate. The function of the semiconductor device can be remarkably enhanced and expanded by forming the semiconductor device on the flexible substrate; therefore, it is commercially attractive to fabricate semiconductor devices on flexible substrates.

Summary of The Invention

In light of the foregoing background, it is an object of the present invention to provide an alternative semiconductor device and method of manufacturing the same.

Accordingly, one aspect of the present invention is a semiconductor device comprising: a gate electrode; an insulating layer connected to the gate electrode; a source and a drain; and a semiconductor channel layer selectively allowing electrical connection between the source and the drain according to a voltage on the gate electrode; wherein the semiconductor channel layer comprises metal nanoparticles; and the semiconductor channel layer is in contact with the source electrode, the drain electrode, and the insulating layer.

In one embodiment, the semiconductor device has a hole mobility greater than about 20cm²V^-1s^-1。

In another embodiment, the semiconductor device has an electron mobility greater than about 18cm²/Vs。

In yet another embodiment, the metal nanoparticles are selected from Au, Ag, Pd, Pt, and any combination thereof.

In a further another embodiment, the semiconductor channel layer further comprises metal oxide nanoparticles.

In another embodiment, the metal oxide nanoparticles are selected from ZnO and CuO.

In another embodiment, the semiconductor channel layer is in the form of a nanostructure.

In another embodiment, the semiconductor channel layer has a thickness of 5-20 nm.

In another embodiment, the semiconductor device is a thin film transistor of an inverter of a ring oscillator for an RFID tag.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including the steps of: providing a nanoparticle solution comprising nanoparticles; subjecting the nanoparticles to self-assembly into an array of nanoparticles; forming the nanoparticle array on a substrate to form a semiconductor channel layer; and forming a source electrode and a drain electrode in contact with the semiconductor channel layer.

In one embodiment, the metal nanoparticles are selected from Au, Ag, Pd, Pt, and any combination thereof.

In another embodiment, the nanoparticle solution further comprises metal oxide nanoparticles.

In yet another embodiment, the metal oxide nanoparticles are selected from ZnO and CuO.

In another embodiment, the substrate is immersed in the nanoparticle solution for 1 to 3 hours.

An advantage of the present invention is to provide a semiconductor device that can be manufactured at low cost and can operate with low power consumption. Low manufacturing costs can be achieved by using solution-processed methods at low temperatures (below 100 degrees celsius). Another advantage of the present invention, in one embodiment, the solution processing method prints a semiconductor channel layer on various substrates by using a nanoparticle solution containing metal nanoparticles. Compared with other conventional printable semiconductors, the metal nanoparticles of the present invention are very stable in air. Another advantage of the present invention is that the semiconductor device can be easily scaled down.

These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Drawings

Fig. 1 is a cross-sectional view of a semiconductor device 100 showing the key structure thereof, according to one embodiment of the present invention.

Fig. 2 shows a drain current-voltage diagram of a semiconductor device having metal nanoparticles as a material of an n-type semiconductor channel layer according to an exemplary embodiment of the present invention.

Fig. 3 shows a drain current-voltage diagram of a semiconductor device having metal nanoparticles as a material of a p-type semiconductor channel layer according to an exemplary embodiment of the present invention.

Fig. 4 shows an input voltage-output voltage diagram of an inverter using a Thin Film Transistor (TFT), according to an exemplary embodiment of the present invention.

Fig. 5 shows a gain diagram of an inverter according to an exemplary embodiment of the present invention.

Fig. 6 illustrates a nanoparticle-based ring oscillator for an RFID tag according to an exemplary embodiment of the present invention.

Fig. 7 shows a series of steps of a method of manufacturing a semiconductor device of the present invention.

Detailed Description

As used herein and in the claims, "comprising" means including the elements that follow, but not excluding others.

Fig. 1 is a cross-sectional view of a semiconductor device 100 in accordance with one embodiment of the present invention, wherein the key structure of the semiconductor device 100 is shown. For example, the semiconductor device 100 includes a substrate 20, which in one exemplary embodiment is made of silicon; a gate electrode 22 disposed on the substrate 20; and an insulating layer 24 stacked over the gate electrode 22. In another embodiment, the substrate is made of polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or any plastic substrate. In an exemplary embodiment, the insulating layer 24 has a layer thickness of 20 to 200nm and is made of a polymer dielectric and a metal oxide. Semiconductor device 100 also includes a source electrode 26 and a drain electrode 28 disposed on insulating layer 24. In one exemplary embodiment, the electrodes 26, 28 are made of gold (Au) or silver (Ag). A semiconductor channel layer 30 is disposed on the insulating layer 24. In one embodiment, the source electrode 26 and the drain electrode 28 are disposed on the semiconductor channel layer 30 such that electrical connection may be made between the source electrode 26 and the drain electrode 28. In a further embodiment, the semiconducting channel layer 30 is disposed between the source 26 and drain 28 such that electrical connection may be made between the source 26 and drain 28. By varying the voltage at the gate electrode 22 (i.e., the gate electrode voltage), the semiconducting channel layer 30 selectively allows and/or regulates electrical connection between the source 26 and the drain 28.

In one embodiment, the semiconductor channel layer 30 includes nanostructures of an array of colloidal nanoparticles 32 (an array of nanoparticles 32). Depending on the material used as the nanoparticles, the nanostructures provide p-type or n-type transport properties. The carriers of the semiconductor channel layer 30 are configured to have sufficient mobility (mobilities) to ensure that the charge induced in the semiconductor channel layer 30 can actually contribute to the current. Preferably, the semiconducting channel layer 30 has greater than about 20cm²V^-1s^-1And a hole mobility of greater than about 18cm²Electron mobility of/Vs. More preferably, the hole mobility is at 20cm²V^-1s^-1-125cm²V^-1s^-1In a range of 18cm, and an electron mobility of 18cm²/Vs-100cm²In the range of/Vs. According to one embodiment of the invention, the material used as nanoparticles is a metal. In further embodiments, the nanoparticles are selected from gold (Au), silver (Ag), palladium (Pd), platinum (Pt), and any combination thereof. In another embodiment, other materials may be used for the semiconductor channel layer 30 as long as the material has a narrower band gap than the insulating layer 22. In another embodiment of the present invention, the nanoparticles are a combination of metal nanoparticles and metal oxide nanoparticles. In another further embodiment of the present invention, the metal nanoparticles of the metal nanoparticle and metal oxide nanoparticle combination are selected from the group consisting of gold (Au), silver (Ag), palladium (Pd), platinum (Pt), and any combination thereof. The metal oxide nanoparticles are selected from ZnO and CuO.

According to one embodiment of the present invention, the thickness of the semiconductor channel layer 30 is in the range of 5nm to 20 nm. In another embodiment, the array of nanoparticles 32 is a monolayer. The semiconductor channel layer 30 with free carriers must be as thin as possible to prevent parallel conduction (parallel conduction). In another embodiment, the semiconductor channel layer 30 is a monolayer of nanoparticles. In another embodiment, there is no limitation on the thickness of the semiconductor channel layer 30 if the semiconductor channel layer 30 does not have free carriers. Such a semiconductor channel layer 30 may be made of metal nanoparticles such as Au, Ag, and Pt.

Turning now to the key operation of semiconductor device 100. The resistance of the semiconductor channel layer 30 of the semiconductor device 100 of the present invention changes with changes in gate voltage. In one embodiment, the semiconductor channel layer 30 is made of a material other than a semiconductor; in further embodiments, the material is a metal nanoparticle, or a combination of a metal nanoparticle and a metal oxide nanoparticle. Fig. 2 and 3 show drain current-voltage curves of the semiconductor device 100 at different gate electrode voltages, in which metal nanoparticles are used as materials of the n-type semiconductor channel layer 30 and the p-type semiconductor channel layer 30 according to an exemplary embodiment of the present invention, respectively.

In fig. 2, the metal nanoparticle-containing n-type semiconductor channel layer 30 allows and/or regulates electrical connection between the source 26 and drain 28 as the gate voltage increases. In contrast, the metal nanoparticle-containing n-type semiconductor channel layer 30 blocks the electrical connection between the source 26 and the drain 28 when the gate voltage is reduced to 0.

In fig. 3, the metal nanoparticle-containing p-type semiconductor channel layer 30 allows and/or regulates electrical connection between the source 26 and drain 28 when the gate voltage is below 0. In contrast, the metal nanoparticle-containing p-type semiconductor channel layer 30 blocks the electrical connection between the source 26 and the drain 28 when the gate voltage is increased to 0. Preferably, the gate bias voltages of the n-type semiconductor channel layer 30 and the p-type semiconductor channel layer 30 of the present invention are 3V and-3V, respectively.

In one embodiment, the semiconductor device 100 of the present invention is a Thin Film Transistor (TFT). In another embodiment of the present invention, the semiconductor device 100 is a TFT component of an inverter for a ring oscillator of an RFID tag having various frequencies, including frequencies of 13.56MHz and 13.54 MHz. Fig. 4 shows an input voltage-output voltage diagram of an inverter using a TFT according to an exemplary embodiment of the present invention. As shown in fig. 4, when the input voltage is about 0V, the output voltage is about 3.0V, and vice versa. Fig. 5 shows the gain of an inverter according to an exemplary embodiment of the present invention. It shows that the inverter has a peak gain when the source voltage is about 1.5V. Fig. 6 shows a nanoparticle-based ring oscillator 200 for an RFID tag, according to an exemplary embodiment of the invention. Ring oscillator 200 includes semiconductor device 100, power supply electrode 34, and ground electrode 36. The power supply electrode 34 and the ground electrode 36 are connected to the semiconductor device 100.

Fig. 7 shows a series of steps in a method of manufacturing the semiconductor device 100 of the present invention. The semiconductor device 100 is formed by a solution method. First, in step 40, the substrate 20 is ultrasonically cleaned using solvents such as DI-water, acetone, and 2-propanol, and modified using (3-aminopropyl) triethoxysilane or (3-aminopropyl) trimethoxysilane. Thereafter, in step 42, the substrate 20 is coated with the gate electrode 22. After the gate electrode 22 is coated, an insulating layer 24 is coated over the gate electrode 22. In step 44, the insulating layer is deposited as a gate dielectric using a Savannah100ALD system at a substrate temperature of 80 ℃. Subsequently, in step 46, the semiconductor channel layer 30 is formed on the insulating layer 24 by coating an array of nanoparticles on the substrate 20. The following are two exemplary embodiments of a method of coating an array of nanoparticles on a substrate 20.

First embodiment

In a first embodiment, the array of nanoparticles 32 is formed by first immersing the substrate 20 in a nanoparticle solution comprising the nanoparticles 32 to be coated onto the substrate 20 for 1-3 hours. In one embodiment, the substrate 20 is immersed in the nanoparticle solution for 2 hours. Upon immersion of the substrate 20 in the nanoparticle solution, the nanoparticles 32 in the nanoparticle solution undergo self-assembly to form an array of nanoparticles 32. During the immersion stepInstead, an array of nanoparticles 32 is formed directly on the substrate 20. In one embodiment, the nanoparticles 32 undergo self-assembly (i.e., dipping the substrate 20 into the nanoparticle solution) in a glove box to prevent O₂And H₂And (4) pollution of O. After the dipping step, the substrate 20 coated with the array of nanoparticles 32 is dried by completely evaporating the residual nanoparticle solution remaining on the substrate.

Second embodiment

In a second embodiment, a nanoparticle solution is placed in a container and the nanoparticles 32 in the nanoparticle solution are caused to undergo self-assembly to form a 2D self-assembled monolayer of nanoparticles on the surface of the nanoparticle solution. In one embodiment, the self-assembly is performed in a glove box to prevent O₂And H₂And (4) pollution of O. After the solvent for dispersing (dispersion) the nanoparticles was completely evaporated, the two-dimensional self-assembled array of nanoparticles 32 was first lifted from the solution surface (lifted) by Langmuir-Schaefer deposition method using a PDMS pad, and then the PDMS pad was brought into conformal contact with the substrate 20 (conformal contact) for about 10 seconds. The prepared array of such ordered nanoparticles 32 can be transferred intact to both hydrophobic and hydrophilic substrates 20.

After step 46, source 26 and drain 28 are formed on semiconductor device 100 through a shadow mask in step 48. The source and drain electrodes 26, 28 are formed as described in the last paragraph of the third page of the specification.

In one embodiment of the present invention, the above manufacturing steps are used to manufacture a TFT. In another embodiment, the above fabrication steps are used to fabricate TFTs for inverters of a ring oscillator during fabrication of RFID tags having various frequencies, including frequencies of 13.56MHz and 13.54 MHz.

The following is an example showing how to prepare nanoparticle solutions of gold (Au), silver (Ag) and palladium (Pd):

au nanoparticles are prepared by the presence of Na in an ice-cold environment₃Ct also under the conditions ofOriginal HAuCl₄·3H₂O is prepared.

Ag nanoparticles by mixing AgNO₃Sodium citrate and NaBH₄To prepare the compound.

Pd nanoparticles were prepared by mixing H at 100 deg.C₂PdCl₄L-ascorbic acid and PVP.

The following table shows hole mobility and electron mobility of a semiconductor device having a semiconductor channel layer using nanoparticles of gold (Au), silver (Ag), and palladium (Pd).

TABLE 1

	Au nanoparticles	Ag nanoparticles	Pd nanoparticles
				Hole mobility	125cm²/Vs	20cm²/Vs	26cm²/Vs
Electron mobility	91cm²/Vs	18cm²/Vs	19cm²/Vs

Platinum (Pt) nanoparticles by the presence of Na at room temperature₃Reduction of the Pt (IV) salt under Ct conditions.

Exemplary embodiments of the present invention have thus been fully described. Although the description refers to particular embodiments, it will be apparent to those skilled in the art that the present invention may be practiced with variations of these specific details. The present invention should therefore not be construed as being limited to the embodiments set forth herein.

Claims

1. A semiconductor device, comprising:

a) a gate electrode;

b) an insulating layer connected to the gate electrode;

c) a source and a drain; and

d) a semiconductor channel layer configured to selectively allow electrical connection between the source and the drain according to a voltage on the gate electrode;

wherein the semiconductor channel layer comprises metal nanoparticles; and the semiconductor channel layer is in contact with the source electrode, the drain electrode, and the insulating layer.

2. The semiconductor device of claim 1, wherein the metal nanoparticles are selected from the group consisting of Au, Ag, Pd, Pt, and any combination thereof.

3. The semiconductor device of claim 1, wherein the semiconductor channel layer further comprises metal oxide nanoparticles.

4. The semiconductor device of claim 3, wherein the metal oxide nanoparticles are selected from ZnO and CuO.

5. The semiconductor device according to claim 1, wherein the semiconductor device is a thin film transistor of an inverter of a ring oscillator for an RFID tag.

6. A method of manufacturing a semiconductor device, comprising the steps of:

a) providing a nanoparticle solution comprising nanoparticles;

b) subjecting the nanoparticles to self-assembly into an array of nanoparticles;

c) forming the nanoparticle array onto a substrate to form a semiconductor channel layer; and

d) forming a source and a drain in contact with the semiconductor channel layer.

7. The method of manufacturing a semiconductor device according to claim 6, wherein the metal nanoparticles are selected from the group consisting of Au, Ag, Pd, Pt, and any combination thereof.

8. The method for manufacturing a semiconductor device according to claim 6, wherein the nanoparticle solution further comprises metal oxide nanoparticles.

9. The method for manufacturing a semiconductor device according to claim 8, wherein the metal oxide nanoparticles are selected from ZnO and CuO.

10. The method for manufacturing a semiconductor device according to claim 6, wherein the substrate is immersed in the nanoparticle solution for 1 to 3 hours.