HK1195167B - Image sensor with tolerance optimizing interconnects - Google Patents

Abstract

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.

Description

Image sensor with interconnects that optimize tolerances

Technical Field

The present disclosure relates generally to electromagnetic sensing and sensors, and also relates to low energy electromagnetic input conditions and low energy electromagnetic throughput conditions. In particular, the present disclosure relates to (but not necessarily exclusively to) optimizing the tolerances and associated systems, methods and features required to use a stacking scheme for hybrid image sensors with minimal vertical interconnection between substrates.

Background

In general, the number of electronic devices that utilize and include the use of imaging/camera technology has become widespread. For example, smart phones, tablets, or other handheld computing devices include and utilize imaging/camera technology. The use of imaging/camera technology is not limited to the consumer electronics industry. Various other fields of use also utilize imaging/camera technology, including various industrial applications, medical applications, home and business safety/surveillance applications, and more. In fact, imaging/camera technology is utilized in virtually all industries in the neighborhood.

As imaging sensors are very popular, the demand in the market for ever smaller high-definition imaging sensors has increased dramatically. High resolution and high definition means that more data must be moved within a relatively small space. The apparatus, systems, and methods of the present disclosure may be used in any imaging application that takes into account size and shape factors. The disclosure may utilize a variety of different types of imaging sensors, such as a Charge Coupled Device (CCD) or a Complementary Metal Oxide Semiconductor (CMOS), or any other image sensor that is currently known or that may become known in the future.

CMOS image sensors typically mount an entire pixel array and associated circuitry (e.g., analog-to-digital converters and/or amplifiers) on a single chip. The size limitations of CMOS image sensors generally require moving more and more data within smaller and smaller ranges. Since a number of considerations need to be addressed in the design and manufacture of CMOS image sensors, contact pads between circuits can be made smaller and smaller between the sensor and other important functions (e.g., signal processing). Thus, for example, increasing the pixel array area may be accompanied by compromises (e.g., a/D conversion or other signal processing functions) in other areas, as the area that the circuitry of interest may occupy is reduced.

The present disclosure optimizes and maximizes a pixel array without sacrificing data processing quality by optimizing and maximizing the pixel array on a first substrate and the associated circuitry of a stack on a subsequent substrate. The present disclosure takes advantage of advances in back-lighting and other fields to optimize the area of a pixel array on a substrate. The stacking scheme and structure allows higher-functioning, large circuits to be utilized while maintaining a small chip size.

Features and advantages of the present disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present disclosure without undue experimentation. The features and advantages of the disclosure may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims.

Drawings

The features and advantages of the present disclosure will become apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which:

FIG. 1a is a schematic diagram of an embodiment of an imaging sensor built on a single substrate;

FIG. 1b is a schematic diagram of an embodiment of an imaging sensor showing remote placement of processing circuitry relative to a pixel array according to the teachings and principles of the present disclosure;

FIG. 2 illustrates a schematic diagram of an embodiment of an imaging sensor built on multiple substrates according to the teachings and principles of the present disclosure;

FIG. 3a shows a perspective view of an embodiment of an imaging sensor fabricated on a single chip and showing a plurality of columns including pixels and support circuitry, wherein the support circuitry is one pixel wide;

FIG. 3b shows a top view of an embodiment of an imaging sensor fabricated on a single chip and showing a plurality of columns including pixels and support circuitry, wherein the support circuitry is one pixel wide;

FIG. 3c shows a perspective view of a single column including pixels and support circuitry taken from FIG. 3 a;

FIG. 3d shows a top view of a single column taken from FIG. 3b including pixels and support circuitry;

FIG. 3e shows a perspective view of an embodiment of an imaging sensor fabricated on a single chip and showing a plurality of columns including pixels and support circuitry, wherein the support circuitry is two pixels wide;

FIG. 3f shows a top view of an embodiment of an imaging sensor fabricated on a single chip and showing a plurality of columns including pixels and support circuitry, wherein the support circuitry is two pixels wide;

FIG. 3g illustrates a perspective view of an embodiment of an imaging sensor built on multiple substrates with a pixel array on a first substrate and supporting circuitry on a second or subsequent substrate with interconnects and vias shown connecting the multiple substrates, according to the teachings and principles of the present disclosure;

FIG. 3h shows a front view of an embodiment of an imaging sensor built on the plurality of substrates of FIG. 3 g;

FIG. 3i shows a perspective view of an embodiment of an imaging sensor built on multiple substrates, wherein multiple pixel columns forming a pixel array are located on a first substrate and multiple circuit columns are located on a second substrate, and showing electrical connections and communications between one pixel column and the circuit column associated with or corresponding to that pixel column;

FIG. 3j shows a perspective view of a single pixel column and a single circuit column taken from FIG. 3i to illustrate electrical connections between the single pixel column and the single circuit column;

FIG. 3k shows a front view of a single pixel column and a single circuit column taken from FIGS. 3i and 3j to illustrate electrical connections between the single pixel column and the single circuit column;

FIG. 3l shows a side view of a single pixel column and a single circuit column taken from FIGS. 3i and 3j to illustrate electrical connections between the single pixel column and the single circuit column;

FIG. 3m shows a perspective view of an embodiment of an imaging sensor built on multiple substrates, wherein multiple pixel columns forming a pixel array are located on a first substrate and multiple circuit columns are located on a second substrate, and showing multiple electrical connections and communications between the multiple pixel columns and multiple circuit columns associated with or corresponding to the multiple pixel columns;

FIG. 3n shows a perspective view of an embodiment of an imaging sensor built on multiple substrates, wherein multiple pixel columns forming a pixel array are located on a first substrate and multiple circuit columns are located on a second substrate, wherein the circuit columns are two pixels wide and the length of the circuit columns is half the length of the pixel columns, and showing multiple electrical connections and communications between the multiple pixel columns and circuit columns associated with or corresponding to the multiple pixel columns;

FIG. 3o shows a perspective view of a single pixel column and a single circuit column taken from the rightmost column of FIG. 3n to illustrate electrical connections between the single pixel column and the single circuit column;

FIG. 3p shows a front view of a single pixel column and a single circuit column taken from FIGS. 3n and 3o to illustrate electrical connections between the single pixel column and the single circuit column;

FIG. 3q shows a side view of a single pixel column and a single circuit column taken from FIGS. 3n and 3o to illustrate electrical connections between the single pixel column and the single circuit column;

FIG. 3r shows a perspective view of a single pixel column and a single circuit column taken from the leftmost column of FIG. 3n to illustrate electrical connections between the single pixel column and the single circuit column;

FIG. 3s shows a front view of a single pixel column and a single circuit column taken from FIGS. 3n and 3r to illustrate electrical connections between the single pixel column and the single circuit column;

FIG. 3t shows a side view of a single pixel column and a single circuit column taken from FIGS. 3n and 3r to illustrate electrical connections between the single pixel column and the single circuit column;

FIG. 3u illustrates a perspective view of an embodiment of an imaging sensor built on multiple substrates, wherein multiple pixel columns forming a pixel array are located on a first substrate and multiple circuit columns are located on a second substrate, wherein the circuit columns are four pixels wide and illustrate multiple electrical connections and communications between the multiple pixel columns and circuit columns associated with or corresponding to the multiple pixel columns;

FIG. 3v shows a perspective view of a single pixel column and a single circuit column taken from the rightmost column of FIG. 3u to illustrate electrical connections between the single pixel column and the single circuit column;

FIG. 3w illustrates a front view of a single pixel column and a single circuit column taken from FIGS. 3u and 3v to illustrate electrical connections between the single pixel column and the single circuit column;

FIG. 3x shows a side view of a single pixel column and a single circuit column taken from FIGS. 3u and 3v to illustrate electrical connections between the single pixel column and the single circuit column;

FIG. 3y shows a perspective view of a single pixel column and a single circuit column taken from the left column adjacent to the rightmost column of FIG. 3u to illustrate electrical connections between the single pixel column and the single circuit column;

FIG. 3z shows a front view of a single pixel column and a single circuit column taken from FIGS. 3u and 3y to illustrate electrical connections between the single pixel column and the single circuit column;

FIG. 3aa shows a side view of a single pixel column and a single circuit column taken from FIGS. 3u and 3y to illustrate electrical connections between the single pixel column and the single circuit column;

FIG. 4 illustrates an embodiment of an imaging sensor built on multiple substrates, and also illustrates an embodiment of a specific arrangement of support circuitry, in accordance with the teachings and principles of the present disclosure;

FIG. 5 illustrates an embodiment of an imaging sensor built on multiple substrates, and also illustrates an embodiment of a specific arrangement of supporting circuits, wherein some of these circuits are arranged relatively remotely, in accordance with the teachings and principles of the present disclosure;

FIG. 6 illustrates an embodiment of a first substrate having different coverage percentages by different pixel arrays according to the teachings and principles of the present disclosure;

FIG. 7 illustrates an embodiment having a plurality of pixel arrays according to the teachings and principles of the present disclosure;

FIG. 8 illustrates an embodiment of an image sensor with an optimized pixel array and associated or stacked support circuitry and showing light sources in accordance with the teachings and principles of the present disclosure;

FIG. 9 illustrates an embodiment of backside illumination of an image sensor with an optimized pixel array and associated or stacked support circuitry in accordance with the teachings and principles of the present disclosure;

FIG. 10 illustrates an embodiment of an image sensor in which the pixel array is located further away from all of the support circuitry in accordance with the teachings and principles of the present disclosure;

FIG. 11 illustrates an embodiment of an image sensor having stacked substrates of different sizes in accordance with the teachings and principles of the present disclosure;

FIG. 12 illustrates an embodiment of a pixel architecture in which each column of pixels does not share a read bus with another column of pixels;

fig. 13 shows an embodiment of a pixel architecture in which there is horizontal bidirectional sharing of the pixel columns with respect to the read bus, so that there is one read bus for every two pixel columns.

FIG. 14 illustrates an embodiment of an imaging sensor built on a pixel array multiple substrate with front illumination according to the teachings and principles of the present disclosure;

FIG. 15 illustrates an embodiment of an imaging sensor having a pixel array divided into a read region containing a plurality of pixels;

FIG. 16 illustrates an embodiment of an imaging sensor having multiple substrates and connections for multiple buses for accessing data from a pixel array divided into a read region containing multiple pixels;

FIG. 17a illustrates an embodiment of a pixel array wherein interconnects are spaced relative to pixels within the pixel array in accordance with the teachings and principles of the present disclosure;

FIG. 17b illustrates an embodiment of a pixel array wherein interconnects are spaced relative to columns within the pixel array in accordance with the teachings and principles of the present disclosure;

FIG. 17c illustrates an embodiment of a pixel array wherein interconnects are spaced relative to regions within the pixel array in accordance with the teachings and principles of the present disclosure;

18 a-18 f illustrate embodiments of pixel arrays in which interconnects may be spaced relative to defined pixel regions within the pixel array according to the teachings and principles of the present disclosure;

FIG. 19 illustrates a method of spacing interconnects/bumps (bump) in accordance with the teachings and principles of the present disclosure;

FIG. 20 illustrates an embodiment in which pixel region specific support circuitry may be used, such that each pixel region may have at least one support circuit dedicated to only processing data generated by pixels within the dedicated pixel region

FIG. 21 illustrates an embodiment of a schematically large image sensor showing scalability of the teachings and principles of the present disclosure; and is

Fig. 22 illustrates an embodiment of a schematically large image sensor showing the scalability of the teachings and principles of the present disclosure.

Detailed Description

For the purposes of promoting an understanding of the principles in accordance with the present disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the disclosure is thereby intended. Any alterations and further modifications of the inventive features as described herein, and any additional applications of the principles of the disclosure as illustrated herein, which would normally occur to one skilled in the relevant art and having possession of this disclosure, are to be considered within the scope of the disclosure as claimed.

Before the apparatus, systems, methods, and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor through the use of vertical interconnects are disclosed and described, it is to be understood that this disclosure is not limited to the particular structures, configurations, processing steps, and materials disclosed herein as such structures, configurations, processing steps, and materials may vary somewhat. It is also to be understood that the terminology employed herein is used for the purpose of describing particular embodiments only and is not intended to be limiting, since the scope of the present disclosure will be limited only by the appended claims and equivalents thereof.

It must be noted that, as used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise.

When describing and claiming the subject matter of the present disclosure, the following terminology will be used in accordance with the definitions set forth below.

As used herein, the terms "comprises," "comprising," "includes," "including," "characterized by," and grammatical equivalents thereof are inclusive or open-ended terms that do not exclude additional, unrecited elements or method steps.

As used herein, the phrase "consisting of … …" and its grammatical equivalents excludes any elements or steps not specified in the claims.

As used herein, the phrase "consisting essentially of … …" and its grammatical equivalents limit the scope of the claims to specified substances or steps as well as those substances or steps that do not materially affect the basic and novel characteristics or features of the disclosure as claimed.

As used herein, the term "proximal" shall refer broadly to the concept of the portion closest to the origin.

As used herein, the term "distal" shall generally refer to the opposite of proximal, and thus refers to the concept of a portion further away from the origin or the farthest away, depending on the context.

Digital imaging, whether it is still or motion picture, has many constraints imposed on the devices used to record the image data. As discussed herein, an imaging sensor may include a pixel array and supporting circuitry disposed on at least one substrate. The device typically has practical and optimal constraints on the form factor of the imaging sensor depending on the application. In most applications, particularly for commercial use, size is often a constraint. Even in outer space applications where size appears to be the least constraint, size remains a problem because the imaging device needs to be launched orbitally and overcome gravity. Furthermore, any volume added by the imaging device/camera detracts from possible other functional hardware or battery capacity/life, especially in consumer electronics. Therefore, size is almost always a constraint that must be addressed in any application using an imaging sensor.

In many cases, the form factor of the imaging device is constrained. There may be a laterally or horizontally unrestricted area or real estate (real estate) relative to the pixel array, or there may be sufficient space directly behind the pixel array longitudinally. Typically, the pixel array is not the only consideration for the device, but rather also needs to accommodate the support circuitry. The support circuits may be, but are not necessarily limited to, analog-to-digital converters, power supply circuits, power harvesters, amplifier circuits, dedicated signal processors and filters, serializers for data transmission, and the like. In addition to these circuits, physical characteristic elements such as filters and lenses may be required. All of the above must be considered when deciding and designing the form factor of the imaging device, and the industry has traditionally selected either the lateral or horizontal arrangement of the support circuitry when designing today's image sensors. However, there are many applications that benefit from a longitudinal form factor rather than a transverse or horizontal form factor.

An example of an application that would benefit from an imaging device having a form factor that is relatively longitudinal (with respect to the pixel array) is a field of use that requires the use of a viewing instrument. For example, industrial viewing instruments and medical endoscopes would benefit from image sensors that can be housed within the lumens of the device. In such scope applications, an image sensor that may be disposed within a lumen of the scope may be advantageous. The inner diameter of the tube chamber (if circular) will then define the maximum diameter of the image sensor (circle). For a common lumen chamber size in the range of 3mm to 15mm, it should be appreciated that the image sensor is greatly limited in the transverse direction due to form factor considerations due to the constraint of the inner diameter. Thus, more longitudinal configurations may be advantageous.

As noted above, while size is an issue, the pixel count number continues to rise throughout the industry for whatever particular application, and often obscures the media (e.g., a computer display or television) used to actually view the image after it has been recorded. However, it should be understood that all pixels are created unequally. In the above examples, the scope configuration may be used in limited light applications. As such, a scope-based image sensor that performs well in low light conditions may be advantageous. A large pixel has the ability to collect more light than a small pixel simply due to the different sizes of the large and small pixels. However, the trend in the market is to increase the number of pixels under a given form factor. Logically, more pixels in a given area generally means a smaller pixel size. Smaller pixels suffer from the following disadvantages: work poorly in lower light and cause noise due to electronic crowding. Furthermore, more pixels correspond to more boundary space relative to the light collection space. Larger pixels tend to produce better images and higher image quality because larger pixels simply have a larger light sensing portion to edge portion ratio. Both of these problems lead to poor image quality for today's small image sensors.

As the pixel count continues to rise in a given space, the pixel pitch drops, thereby requiring greater precision for the interconnect electrical contacts. Therefore, the cost of image sensor production may increase because of the need for greater accuracy in data processing for increased pixel pitch. The prior art may be used to implement image sensors with increased capabilities, but at increased costs due to reduced yield during manufacturing.

For the ratio of pixel pitch to bump pitch, the techniques and structures disclosed herein will allow:

increased manufacturing reliability due to increased capability for alternate interconnections provided (i.e., redundancy of the interconnections);

maximizing bump pitch size in an efficient manner for cost per application or field used;

allows for a more economical CMOS process due to the ability to use larger pixel pitches;

allowing more efficient bump technology access, i.e. reading out the read data of the pixel array from multiple buses or directly;

allowing redundancy of CMOS processes to increase throughput;

use of localized ADCs in predetermined or defined pixel areas; and is

A geometry that allows the use of multiple pixel arrays, multiple bus lines, and column bump configurations.

The above identified problems describe the prior art with respect to several needs in the industry. There is a need for an image sensor with sufficient resolution by pixel count, vertical architecture and form factor, and as large a pixel size as possible, all while being constrained in a limited space. The present disclosure contemplates and will discuss embodiments and design methods that address these and potentially other issues by optimizing the size of the pixel array on a substrate/chip, and remotely placing the support circuitry on one or more support substrates/chips in a generally vertical configuration.

High performance image sensors using on-chip analog-to-digital converters (ADCs), on-chip analog-to-digital algorithms, on-chip complex timing and on-chip complex analog functions provide high quality images for the following reasons (the following list is not a complete list, but is given for exemplary purposes only):

no microphone noise due to long off-chip analog data lines (if there is no on-chip ADC, the analog signal needs to be able to be sent off-chip);

low temporal noise (no extra amplifiers, buffers to add extra noise) because the digital conversion is performed early in the data path;

local timing optimization using complex on-chip timing generators. Due to pad count limitations, only simple timing can be performed using an external system;

lower noise generated by IO. The system-on-chip allows for reduced shim counts; and is

Faster operation (more serial on-chip operation, reduced parasitic capacitance and resistance) can be achieved.

However, the detailed functions and processing used to provide such high quality images occupy a large area around the pixel array and the ratio of pixel array size to die size is significantly lower. In imaging systems using on-chip processing and circuitry (including ADCs and other detailed functions mentioned above), it is common for the ratio of pixel array size to die size to be below 25%. Thus, there is a trade-off between pixel array size to die size and on-chip functionality.

Therefore, most technical applications that require the use of an optimized pixel array size to die size ratio use custom image sensors that have no digital conversion (analog output) or reduced analog/digital functionality and low levels of analog-to-digital conversion. Even in that case, a ratio of pixel array size to die size of greater than 50% is difficult to achieve.

The present disclosure describes and contemplates systems and methods that increase the ratio of pixel array size to die size without sacrificing image quality. The present disclosure contemplates imaging applications using a given die size where a maximized pixel array size is required or imaging applications using a given pixel array size where a smaller die size is required.

One of the key issues in three-dimensional stacking technology is bump pitch. Current technology achieves a bump pitch of about 50 μm to 100 μm. In the next 3 to 10 years, it is expected that evolving technologies will allow the size of the bump pitch to be reduced to a range equal to or close to the same size as the pixel pitch.

Furthermore, the substrate/chip throughput of the stack is directly dependent on the bump pitch. The most common failure in stacked substrates/chips is an electrical short between two interconnects or bumps. As bump pitch decreases in size and becomes smaller, the planarization specifications of the wafer must be tighter. To buffer the wafer from planarization errors, the interconnects or bumps become or grow taller. However, excess metal in the taller interconnects/bumps tends to move to the sides during the bonding process of the wafer, which may short adjacent or neighboring bumps. Higher throughput and lower cost due to the relaxed wafer alignment process can be achieved by relaxing the interconnect or bump pitch.

The present disclosure presents an apparatus, system, and method that relaxes bump pitch while working on tighter pixel pitch.

The present disclosure contemplates an image sensor that may otherwise be fabricated on a separate, monolithic substrate/chip with its pixel array and supporting circuitry and separates the pixel array from all or most of the supporting circuitry. The present disclosure may use at least two substrates/chips that will be stacked together using three-dimensional stacking techniques. The first of the two substrates/chips may be processed using an image CMOS process. The first substrate/chip includes either the pixel array exclusively or the pixel array surrounded by the limiting circuitry. The processing of the second or subsequent substrate/chip may be performed using any process and need not be from an image CMOS process. The second substrate/chip may be, but is not limited to, high density digital processing to integrate various and many functions in a very limited space or area on the substrate/chip, or may be, but is not limited to, mixed mode or analog processing to integrate, for example, precise analog functions, or may be, but is not limited to, RF processing to enable wireless capability, or may be, but is not limited to, MEMS (micro electro mechanical systems) to integrate MEMS devices. The image CMOS substrate/chip may be stacked with a second or subsequent substrate/chip using any three-dimensional technology. The second substrate/chip may support most or most of the circuitry that would otherwise have been implemented in the first image CMOS chip (assuming implemented on a single substrate/chip) as peripheral circuitry and thus increase the overall system area while keeping the pixel array size constant and optimized to the fullest extent possible. Electrical connection between two substrates/chips may be carried out by interconnects, which may be wire bonds, μ bumps and/or TSVs (through silicon vias).

Referring now to fig. 1a and 1b, fig. 1a is an example of a monolithically designed imaging sensor, where a single substrate is used as the basis for chip building. As shown in fig. 1a, the substrate 100a may include a pixel array 150a, wherein the pixel array 150a is configured to receive electromagnetic energy, convert the electromagnetic energy into data, and then pass the data to the support circuitry 110a, 120a, 130a for processing, which ultimately results in a digital image or video. The support circuitry may include signal processing circuitry such as, to name a few, an analog-to-digital converter 110a, an amplifier circuit 130a, a filter circuit, a power supply and collection circuit 120a, and a serial processor. Some of the support circuits may be placed closer to the pixel array than others and connected to each pixel in the pixel array via a bus. For example, the amplification circuitry and digital conversion circuitry may preferably be placed closer to the pixel array because this architecture may increase the clarity of the data stream and introduce minimal noise to the system. As shown in fig. 1a, the image sensor 100a is a schematic illustration of those typically available in the market for image sensors. Fig. 1a shows a general lateral arrangement of support circuitry with respect to pixel array 150a, which dominates today's market due to cost and manufacturing limitations. The lateral placement on the same substrate as pixel array 150a and relative to the supporting circuitry of pixel array 150a simplifies the architecture and reduces production costs. However, the use of a single substrate has some drawbacks and limitations, such as form factor issues, because not all applications are suitable for lateral or horizontal circuit arrangements as discussed above. As shown in fig. 1b, when the support circuitry, e.g., 110a, 120a, 130a, is removed from the first substrate 160, a considerable amount of space remains for a larger pixel array 150a that can be located on the first substrate 160, meaning that more or larger pixels can be used. Allowing the same physical limitations in the electronics of the imaging sensor to be used, using the techniques and feature combinations disclosed herein allows for the ability to use increased pixel resolution or increased pixel size. In this case, the size of the image sensor substrate can be reduced, and the image sensor substrate can be used in more devices whose size is a major concern and also for which high-quality images are desired. In particular, FIG. 1b illustrates a design concept where the support circuits 110b, 120b, and 130b are remotely located relative to the pixel array.

Referring primarily to FIG. 2, the use of a support substrate for carrying support circuitry will be discussed. In an embodiment of the exemplary image sensor 200, a pixel array 205 is positioned on a surface of the first substrate 210, the pixel array 205 may include a plurality of pixels formed as a plurality of pixel columns. Each of the plurality of pixel columns on the first substrate 210 may be electrically connected to the read bus line 240. Signal processing and image enhancement may be performed by support circuitry located on the second substrate 220. The circuits may include signal processing circuits such as analog-to-digital converters 228, amplifier circuits 226, filter circuits 224, power supply and collection circuits 222, which may form a plurality of circuit columns corresponding to the plurality of pixel columns on the first substrate 210. Each circuit column may include a plurality of support circuits in electronic communication with read bus 230 or a plurality of read buses corresponding to each circuit column. In other words, the signal processing circuit may be located on the second substrate or the support substrate 220. Each of the plurality of circuit columns on the second substrate 220 may then be electrically connected to a corresponding pixel column on the first substrate 210 by an interconnect, such as a solder bump, solder ball, or via, which may be located anywhere along the physical path used to overlay or overlay the read buses 230, 240. It is also contemplated within the scope of the present disclosure to use multiple secondary substrates, where each substrate accommodates any required circuitry for the image sensor in any order or in combination with supporting circuitry depending on the desired functionality of the image sensor.

As shown in fig. 3a through 3f, the image sensor 300a may generally include a pixel array 350a and support circuitry 370a, the support circuitry 370a may include an analog-to-digital converter 317a, an amplifier 315a and a filter 314a and a clock 316a, all of which may be disposed on a monolithic substrate 310 a. In fig. 3a and 3b, a monolithic image sensor is shown in a perspective view and a top view, respectively. Pixel array 350a may include a plurality of pixel columns, wherein each pixel column of plurality of pixel columns 352a includes a plurality of individual pixels. The support circuits 370a may include a plurality of circuit columns 356a, wherein each circuit column 356a includes circuitry for supporting a corresponding pixel column 352 a. As shown in the drawing, the monolithic column 356a is one pixel wide and is locally positioned with respect to the pixel column corresponding to the monolithic column. The figure shows a pixel array of unshared pixels, where one read bus per pixel column is electrically connected to only the corresponding column circuit on one side of the image sensor. It should be appreciated that in one embodiment, the corresponding circuitry is one pixel wide, however, other configurations of the support circuitry discussed below are contemplated within the scope of the present disclosure and may be used to add image sensor design options.

Referring now to fig. 3c and 3d, a single circuit column 356a and a single pixel column 352a comprising a plurality of pixels are shown in perspective and top views, respectively. It should be understood that a single pixel column 352a and corresponding circuit column 356a are shown in the figures taken from image sensor 300a shown in fig. 3a and 3b and represent only a single pixel column 352a electrically connected to a single circuit column 356 a.

Fig. 3e and 3f show perspective and top views of an embodiment of an imaging sensor 300a fabricated on a monolithic substrate, and showing a plurality of columns including pixels and supporting circuitry. In contrast to fig. 3a and 3b, fig. 3e and 3f show support circuits with a width of two pixels. As can be seen in the figure, alternate columns of pixels 352a are read out to corresponding circuits located at opposite ends of the columns of pixels 352 a. This configuration provides for various variations in the aspect ratio of the corresponding circuit column 356a area. Because bus 330a is read out to alternating sides of pixel array 350a, circuit column 356a may be two pixels wide. In contrast to the sensors shown in fig. 3b and 3f, the pixel column 352a shown in fig. 3b has an aspect ratio (6/1) of 6 pixels (cells) long by 1 pixel (cell) wide, and the circuit column 356a has a similar aspect ratio. In contrast, the image sensor shown in fig. 3f has a pixel column 352a with an aspect ratio (6/1) of 6 pixels (cells) long by 1 pixel (cell) wide and a circuit column 356a with a width-to-length ratio (2/3) of 2 pixels wide by 3 pixels long.

In contrast, the same functionality as imaging sensor 300a (shown in fig. 3 a-3 f) built on a monolithic substrate may be provided and provided in imaging sensor 300 that is much smaller in size (at least in the lateral direction) than the monolithic substrate or chip (and has a smaller area and form factor). Referring now to fig. 3g through 3aa, an imaging sensor 300 that may include a pixel array 350a (which pixel array 350a may be disposed on a first substrate 310) is discussed, while all support circuitry 370 may be remotely located (with respect to pixel array 350 and first substrate 310) on one or more support substrates (e.g., second substrate 311 and third substrate 312).

It should be noted that the image sensor may be built and fabricated on multiple substrates. Each of the plurality of substrates may be placed with respect to each other in a stacked configuration and form, wherein all of the substrates are stacked or aligned behind the first substrate 310 comprising the pixel array 350 and with respect to the object to be imaged. Each substrate in the stack may be electrically connected by interconnects 321 (e.g., solder bumps or balls, vias, or other forms of electrical communication). It should be understood that the interconnect 321 may include any known device or method for conducting electrical signals to various circuits on the same or different substrates without departing from the scope of the present disclosure.

In fig. 3g, 3i, 3m, 3n, and 3u, each of the plurality of substrates comprising the pixel array 350 and various support circuits 370 of the image sensor 300 may be of similar size in the stack such that the plurality of substrates are substantially aligned in the stack. In one embodiment, first substrate 310 and a plurality of subsequent support substrates 311 may be stacked in substantial alignment, forming a plurality of communication columns in a multi-layer stack of substantially the same length and width.

It should be noted that in other embodiments, which will be permitted by form factor, different sized substrates having different lengths and widths may be used and are preferred in the stack. When designing a stacked configuration, several concerns such as heat dissipation, noise, and many can be addressed. For example, in one embodiment, a high thermal circuit, such as an amplifier circuit, may be located on a protruding portion of one of the support substrates in the stack (best shown in FIG. 11).

It should be noted that pixel array 350 is formed as rows of pixels and columns of pixels. Each pixel column 352 may include a plurality of pixels in a linear form factor, each pixel column being one pixel wide and "N" pixels long. It should also be noted that each pixel column 352 will have an area value that is substantially as wide as the pixel pitch and as long as a length predetermined by the sensor design.

Conversely, a circuit column 356, as referred to herein, is space allocated on a substrate that is different from the first substrate 310 that includes the pixel array 350 and that includes at least one support circuit 370 dedicated to and electrically connected to or in electrical communication with a corresponding pixel column 352. It should be understood that the space occupied by a pixel column 352 may be the same or substantially the same as the space occupied by a circuit column 356 corresponding to the pixel column 352. Thus, the second substrate or support substrate 311 may include a plurality of circuit columns 356, wherein each circuit column 356 includes substantially the same or similar area of substrate area on the second substrate 311 as the corresponding pixel column 352 has on the first substrate 310.

Further, each pixel column 352 is or can be in electrical communication with a read bus 330 on the first substrate 310, while the circuit column 356 is or can be in electrical communication with a read bus 340 on the second substrate 311. As shown in fig. 3g to 3aa, the two aforementioned buses 330, 340 may be electrically connected by at least one interconnect 321, which interconnect 321 is located anywhere along the path created by or within the superposition of or between the two buses 330, 340. In one embodiment, a plurality of interconnects 321 may be used to connect a single column of pixels 352 to a single corresponding column of circuitry 356. In such embodiments, redundancy in the number of interconnects 321 used may provide increased product yield or increased functionality.

As discussed herein, aspect ratio will be used to refer to the general shape of an area on a substrate. For example, a region defined as 4 pixel cells wide and 5 pixel cells long would have an aspect ratio of 4/5 or 5/4. The term aspect ratio may be used generally to denote: the shape of the region is considered to be an important case. For example, the concept of aspect ratio may be used to represent the difference in aspect ratio of two corresponding regions located on different substrates. It should be noted that the aspect ratios of the pixel column 352 and the circuit column 356 shown in fig. 3 g-3 aa may be the same or may be different, and the area of the footprint of the pixel column 352 and the area of the footprint of the circuit column 356 to which the pixel column corresponds may be substantially the same or equal. Fig. 3g through 3aa illustrate examples of different aspect ratios, but it should be noted that the principles of the present disclosure may be applied to any number of aspect ratio configurations. However, as shown in the figure, the footprint or real estate of the circuit column 356 is substantially the same or equal to the footprint or real estate of the pixel column 352. As manufacturing techniques improve or design parameters change, more or less area may be required for the support circuits 370 of the circuit column 356.

Referring specifically to fig. 3g and 3h, the support circuitry 370, including amplifiers, filters, clocks, or other circuitry required to support the image sensor, may be disposed on one or more support substrates (e.g., second substrate 311). However, it should be understood that the circuitry may be dispersed on one or more substrates (e.g., second substrate 311, or a third substrate). Further, the analog-to-digital converter may be remotely located on one of the support substrates. It should be understood that the order and position of the support substrate 370 may be changed and the support substrate 370 may be located on any support substrate desired.

As shown, each pixel column 352 can be associated with and electrically connected to one read bus 330 on the first substrate 310, while each circuit column 356 can be associated with and electrically connected to one read bus 340 on the support substrate 311 by one or more interconnects 321, which interconnects 321 can include bumps 321a and vias 321b (best shown in fig. 3 h). At least one interconnect 321 may be used to connect the pixel column bus 330 on the first substrate 310 to the circuit column bus 340 on the support substrate 311, as shown. The dashed arrows in fig. 3i, 3j, 3l, 3o, 3q, 3r, 3t, 3v, 3x, 3y and 3aa show that the interconnect 321 may be located anywhere along the superimposed path of the two read buses 330 and 340 of each corresponding pixel column 352 and circuit column 356.

Referring now to fig. 3i through 3m, various views of an embodiment of an imaging sensor 300 built on multiple substrates are shown. Fig. 3i and 3m show a plurality of pixel columns 352 forming a pixel array 350 on the first substrate 310 and a plurality of circuit columns 356 (representing support circuits 370) on the second substrate 311. As shown, the circuit column 356 may be one pixel wide and "N" pixels long to correspond directly to the pixel column 352 associated with the circuit column 356. The figure shows an example of the connection between each pixel column 352 and its associated circuitry 370 in the circuit column 356. The figure also shows one read bus 330 per pixel column 352 and one read bus 340 per circuit column 356. Wherein the associated circuits 370 in the circuit column 356 are one pixel column wide.

As shown herein above, each pixel column 352 may be electrically associated or connected to one pixel column bus 330, and each circuit column 356 may be electrically associated or connected to one circuit column bus 340. Fig. 3j to 3l show perspective, front and side views of a single pixel column 352 and a single circuit column 356, respectively, separate from the plurality of pixel columns 352 and the plurality of circuit columns 356 shown in fig. 3 i. Fig. 3j through 3l also illustrate electrical connections between the bus 330 of the pixel column 352 and the bus 340 of the circuit column 356 using one or more interconnects 321. Although one or more interconnects 321 may be used to electrically connect bus 330 and bus 340, the figures illustrate that interconnects 321 may be located anywhere along the superimposed path of bus 330 and bus 340 without departing from the spirit or scope of the present disclosure.

Referring now to fig. 3n through 3t, various views of an embodiment of an imaging sensor 300 built on multiple substrates are shown, wherein a plurality of pixel columns 352 for forming a pixel array 350 are located on a first substrate 310 and a plurality of circuit columns 356 are located on a second substrate 311. In this embodiment, the circuit column 356 may be two pixels wide or two pixel columns wide. In this embodiment, the connection between each pixel column 352 and its associated circuit 370 in the corresponding circuit column 356 may be one read bus 330 per pixel column 352 and one read bus 340 per circuit column 356. As shown, the area consumed by the pixel column 352 on the first substrate 310 corresponds to the area consumed by the corresponding circuit column 356. This correspondence allows for direct coverage of the substrates (e.g., 310 and 311) to directly stack the support circuits 370 in the stacked circuit column 356 with the pixel columns 352 supported by the support circuits 370.

It should also be noted that in this configuration, the aspect ratio 352 of the pixel column will be substantially equal to the aspect ratio of the circuit column 356, however, as discussed further below, this aspect ratio equality is not required. As shown in fig. 3m, the pixel column is one pixel column wide and six pixels long, so the aspect ratio is 1/6. The circuit columns also have the same aspect ratio 1/6. In contrast, fig. 3n shows a design in which the circuit column aspect ratio is twice the pixel column aspect ratio and the length of the circuit column is half the pixel column length, thereby providing a potentially more usable footprint for placement of support circuitry. In fig. 3m and 3n, although the aspect ratios are different, the areas of the footprints of both the pixel column 352 and the circuit column 356 are substantially equal to each other.

Fig. 3n also shows how different aspect ratios between substrates may allow flexibility in bus contacts. In one embodiment, the column circuit bus 340 has been designed in a general "u" shape to more evenly occupy the area of the circuit column 356, thereby providing an option for connecting the interconnects 321 throughout the entire circuit column 356. Note that the pixel column bus 330 is not generally U-shaped, but the circuit column bus 340 may be generally U-shaped, so that the same column circuit 356 may be used for the two different pixel column configurations of fig. 3o and 3 r. A first branch of the U-shaped circuit column bus 340 may be superimposed onto the read bus 330 of a first pixel column 352 (as shown in fig. 3 o), and a second branch of the U-shaped circuit column bus 340 may be superimposed onto the read bus 330 of the next, adjacent pixel column 352 (as shown in fig. 3 r). Fig. 3o and 3r show pixel columns 352 taken from the pixel array 350 of fig. 3 n. Fig. 3o and 3r show three options for the interconnect 321 to be positioned within the footprint of the circuit column 356. It should be noted that as shown in fig. 3q, the interconnect 321 location option is only a fraction of the available length for the pixel column 352, since the aspect ratio of the circuit column 356 is shown as twice as wide and half as long as the corresponding pixel column 352. Fig. 3p shows that for complex bus shapes, there may be two interconnect location path options along the bus 340 in the circuit column 356, where the width of the circuit column 356 is twice the width of the pixel column 352 supported by the circuit column 356. Fig. 3p shows a front view of a superposition of the first branch of the u-shaped circuit column bus 340 to the read bus 330 of the first pixel column 352 and the interconnect 321 is placed using the outermost part of the bus 340, as opposed to the innermost part of the bus 340 as shown in fig. 3r and 3s, in order to place the interconnect 321 to the next adjacent pixel column 352. Fig. 3r shows the next pixel column 352 to the left of and relative to the first pixel column (rightmost pixel column) shown in fig. 3n and 3 o. As shown, the bus 330 of the second pixel column 352 shown in fig. 3r may be electrically connected to a second branch of the bus 340. It should be noted that because the footprint of the circuit column 356 has an aspect ratio 2/3, the superposition of the pixel column bus 330 to the circuit column bus 340 requires that the second branch of the circuit column bus 340 be substantially U-shaped to thereby allow for a natural matching or superposition of the buses 330 and 340 with respect to the next pixel column 352 shown in fig. 3r and 3 s.

Fig. 3u shows a perspective view of an embodiment of imaging sensor 300 built on multiple substrates, wherein a plurality of pixel columns 352 for forming pixel array 350 are located on first substrate 310 and a plurality of circuit columns 356 are located on second substrate 311, wherein circuit columns 356 are four pixels wide, but are also a quarter of the length. The figure also shows a plurality of electrical connections and communication paths between a plurality of pixel columns 352 and associated or corresponding circuit columns 356.

Fig. 3v shows a perspective view of a single pixel column 352 and a single circuit column 356 taken from the rightmost column of fig. 3u to illustrate the electrical connections between the single pixel column and the single circuit column and an illustrative bus configuration to accommodate the architecture. As shown, an embodiment may include a column of pixels 352 (and associated bus 330) having minimal partial overlap with a corresponding column of circuitry 356 (and associated bus 340). In other words, a very small bus overlay is required between the substrates. However, as shown in fig. 3u, there may be a superposition at the substrate level.

Fig. 3w shows a front view of a single pixel column 352 and a single circuit column 356 taken from fig. 3v to illustrate the electrical connections between the single pixel column 352 and the single circuit column 356. As shown, only a small lateral portion of the bus stack is required to connect the pixel column 352 to the circuit column 356.

Fig. 3x shows a side view of a single pixel column 352 and a single circuit column 356 taken from fig. 3v to illustrate the electrical connections between the single pixel column 352 and the single circuit column 356. As shown, one or more interconnects 321 may be used in some embodiments, and the figure also shows that the placement of interconnect 321 may be anywhere along the superposition of buses 330 and 340.

Fig. 3y shows a perspective view of a single pixel column 352 and a single circuit column 356 taken from a column adjacent to the left of the rightmost column 356 of fig. 3u to illustrate the electrical connections between the single pixel column 352 and the single circuit column 356. Fig. 3z shows a front view of a single pixel column 352 and a single circuit column 356 taken from fig. 3y to illustrate the electrical connections between the single pixel column 352 and the single circuit column 356. Fig. 3v and 3y show pixel columns 352 taken from the pixel array 350 of fig. 3 u. Fig. 3v and 3y show two options for the interconnect 321 located within the footprint of the circuit column 356. It should be noted that as shown in fig. 3aa, the interconnect location option is only available for a portion of the length of the pixel column 352 because the aspect ratio of the circuit column is wider but shorter than the aspect ratio of the corresponding pixel column 352. Fig. 3z shows that for complex bus shapes, there may be four interconnect location path options along the bus 340 in the circuit column 356, where the circuit column 356 is four times as wide and one quarter as long as the pixel column 352 supported by the circuit column 356. Thus, it can be seen that although the aspect ratio of the circuit column 356 is different from the aspect ratio of the pixel column 352, the areas of the corresponding footprints are substantially the same or equal. As manufacturing techniques improve or design parameters change, more or less area may be required for the support circuitry of the circuit column 356.

Fig. 3v and 3w show a superposition of the first pixel column read bus 330 and the first branch of the circuit column read bus 340. Fig. 3y shows the next, adjacent pixel column relative to the pixel column shown in fig. 3 v. It should be noted that because the footprint of the circuit column 356 has an aspect ratio 4/2, superimposing the pixel column bus 330 onto the circuit column bus 340 requires a second bifurcation of the correspondingly shaped circuit column bus 340 to thereby allow for a natural matching or superimposing of the buses 330 and 340 with respect to the next pixel column 352 shown in fig. 3y and 3 z. Fig. 3aa shows a side view of a single pixel column and a single circuit column taken from fig. 3y to illustrate electrical connections between the single pixel column and the single circuit column.

It should be appreciated that each pixel column may or may not be shared with the read bus depending on existing conditions that may affect pixel design and architecture. Fig. 12 and 13 show two examples of pixel architectures. Fig. 12 shows a pixel architecture in which each pixel column does not share a read bus with another pixel column. This example shows a non-shared pixel architecture when there is only one read bus per pixel column. In contrast, fig. 13 shows horizontal bidirectional pixel sharing. In fig. 13, there is only one read bus per two pixel columns. Note that in embodiments where the pixel array 350 is optimized on a first substrate and separated from most of the support circuitry located on a second substrate or support substrate in a three-dimensional stacked embodiment as discussed herein, the number of read buses per pixel column may be an important consideration.

It should be noted that it is within the scope of the present disclosure to allow multiple columns of pixels to correspond to a set of support circuits in a circuit column. For example, multiple columns of pixels may correspond to one circuit column because the processing power of some supporting circuitry may be greater than the power required for data generated by the pixel column. Conversely, also contemplated herein, in some embodiments, the plurality of circuit columns may correspond to a single pixel column in the pixel array.

In the embodiments of the specific processes and implementations described above, the connections may be made through interconnects (e.g., bumps) located between the two substrates/chips. The metal layers of the two substrates/chips may face each other and therefore back-side illumination may be required on a CMOS image sensor chip comprising an array of pixels (the front side of the first chip may be bonded to the front side of the second chip). In one embodiment, only one interconnect may be used per column 352, 356 between the first and second substrates/chips. In one embodiment, two or more interconnects may be used per column 352, 356, and two or more interconnects may be used for redundancy purposes (process throughput). In contrast to conventional techniques (such as the monolithic CMOS image sensor shown in fig. 3a to 3 f), the read bus may be interrupted at the edge of the pixel array and may be folded in the second substrate/chip. The bumps may then connect the two buses anywhere within the column. It should be appreciated that power distribution or other signals (e.g., vertical decoders) between two or more substrates/chips may require more interconnects such as bumps.

Referring now to fig. 4, an image sensor embodiment having an image sensor pixel array and supporting circuitry built on multiple substrates using backside illumination is shown. As shown, the pixel array 450 may be disposed on a first substrate 452. The first substrate 452 may be made of silicone or another material to control light transmission characteristics. Solder balls, bumps or vias 421 may be used to electrically connect one substrate to another. Embodiments of stacked image sensors can include a pixel array 450 on a first substrate 452. The pixel array 450 can cover at least 40% of the first surface 451 of the first substrate 452. In a back-illuminated configuration, a pixel array 950 may be disposed on the back side of the first substrate 952 as best shown in fig. 9. Further, in a back-lit configuration, the substrate 452 may be thin for controlling light transmission through the substrate. In embodiments utilizing back-side illumination, the first substrate may be made primarily of silicon material, or the first substrate may be made primarily of a "high-resistance" semiconductor material (e.g., cadmium telluride), or the first substrate may be made primarily of a III-V semiconductor material (e.g., gallium arsenide).

In one embodiment, the pixel array 450 may cover a majority of the first surface 451 of the first substrate 452. In this embodiment, the pixel array 450 may be on or located on any portion of the first surface 451. The remaining space on the first surface 451 may be used for placement of secondary circuitry if desired. It may occur that the secondary circuitry may be sized such that central placement of the pixel array is not feasible.

Referring now to FIG. 5, an embodiment will be discussed in which at least some of the support circuits and components are located remotely from other support circuits and components to function for a predetermined purpose. For some applications, some secondary processors may be desired to be placed further away from the pixel array. For example, in a medical viewing instrument (e.g., an endoscope), there may not be enough space around the pixel array to contain all the required support circuitry. In this case, the substrate 510 containing the pixel array may be placed away from other supporting substrates within the image sensor 500.

In one embodiment, the substrate 510 containing the pixel array may be adjacent or proximate to a support substrate 520 positioned away from the substrate containing the pixel array. The support substrate 520 may include an amplifier circuit on the support substrate 520, while other support circuits may be located on another substrate 530 placed farther from the pixel array substrate 510 than the support substrate 520 placed farther from the pixel array substrate 510. In one embodiment, the more remotely located substrate 530 may be connected by wired vias 522 to other substrates in the image sensor 500 or may communicate wirelessly with other substrates and circuitry. Adjacent substrates may be connected to each other by bumps or solder balls 521. As pixel arrays and other circuitry become more efficient over time, it is within the scope of the present disclosure to provide an image sensor that keeps the substrate containing the pixel array farther away from all other supporting circuitry. Fig. 10 depicts the circuit wherein a substrate 1010 containing an array of pixels is placed at a greater distance from support substrates 1020, 1030, 1040, each of which includes support circuitry, such as signal processing circuitry and power supply circuitry, by vias 1022.

In one embodiment, the pixel array of the image sensor may occupy a large percentage of the available surface area of the first substrate 570. As shown in fig. 6, pixel arrays 572, 574, 576 (shown in phantom) of various sizes are contemplated by the present disclosure and are within the scope of the disclosed design. The pixel array 576 schematically presents a configuration in which the pixel array 576 covers a large percentage of the first substrate 570, but does not cover a large portion of the substrate 570. The pixel array 576, while not covering a large percentage of the area, may cover this large percentage of the available area so that at least some of the support circuitry may not be located on the first substrate 570.

Pixel array 574 schematically shows a configuration separate from pixel arrays 576 and 572 in which pixel array 574 covers approximately half of first substrate 570. Pixel array 572 schematically illustrates a separate configuration from pixel arrays 576 and 574, where pixel array 572 covers a substantial portion of first substrate 570. It should be apparent from the above discussion that the optimization process may allow for finding a pixel array size that provides the best possible image and image quality while working within constraints dictated by the application, function, or purpose. Thus, even in applications where the imaging sensor has a fixed first substrate size, the percentage of surface area occupied by the array of pixels located on the first substrate may be different from and cover many different percentages of the total surface area available on the first substrate.

It will be appreciated, therefore, that the surface area that the array of pixels may occupy may fall within the range of from about 25% to about 99% of the total surface area of one surface of the first substrate, or may fall within the range of about 40% to about 99% of the total surface area of one surface of the first substrate, or may fall within the range of about 50% to about 99% of the total surface area of one surface of the first substrate, or may fall within the range of about 60% to about 99% of the total surface area of one surface of the first substrate, or may fall within the range of about 70% to about 99% of the total surface area of one surface of the first substrate, or may fall within the range of about 80% to about 99% of the total surface area of one surface of the first substrate, or may fall within a range of about 90% to about 99% of the total surface area of one surface of the first substrate. It should be understood that all percentages falling within the claimed ranges are intended to fall within the scope of the present disclosure. It will also be appreciated that all subranges falling within the range of about 25% to about 99% of the total surface area of one surface of the first substrate are intended to fall within the scope of the present disclosure.

Due to the nature of the back-illuminated pixel array, the substrate surface discussed above may be independent of the image sensor that includes the back-illuminated pixel array. Thus, in back-side lighting applications, the substrate surface may be removed or integrated integrally with the pixel array.

The pixel array coverage or surface area may fall within a range of greater than 40% to about 70% of the total surface area of the substrate on which the pixel array is located, and in this case, certain supporting circuitry may be placed on the substrate without reducing the design of the image sensor. In one embodiment, the light emitting circuit may occupy some space on the first substrate to provide light during use. For many applications where the dimensions are extremely compact and most tightly constrained, the optimized imaging sensor may cover 90% or more up to substantially all of the surface area of the first substrate. It should be noted that pixel arrays having an integrated substrate rather than being added to the substrate are contemplated within the scope of the present disclosure.

FIG. 7 illustrates an embodiment of an imaging sensor having multiple pixel arrays. As shown, the image sensor 700 may include a first image sensor 710 and a second image sensor 711, where the first image sensor 710 and the second image sensor 711 are in electrical communication with a substrate 715 or a plurality of substrates that may be longitudinally stacked or otherwise stacked with respect to an object to be imaged. In one embodiment, the support circuitry may be remotely located on a subsequent substrate or support substrate as discussed above. This configuration may be required for three-dimensional image acquisition, which may offset the two pixel arrays during use. In another embodiment, the first pixel array and the second pixel array may be dedicated to receiving a predetermined wavelength range of electromagnetic radiation, wherein the first pixel array is dedicated to a different wavelength range of electromagnetic radiation than the second pixel array.

Fig. 14 and 15 illustrate embodiments of data for an array of pixels 1510 that have been optimized from a first substrate 1552 (see fig. 15) with support circuitry 1510 for an image sensor 1500 located on one or more second substrates or support substrates 1554 (see fig. 14), which may be configured in a stacked configuration (in conjunction with fig. 14 and 15). As shown, the pixel array 1510 may be disposed on a first substrate 1552 and may be electrically connected to support circuitry 1520, which support circuitry 1520 may be located on one or more subsequent substrates or support substrates 1554 having one or more interconnects 1521 (see fig. 14). In the embodiment illustrated in fig. 14 and 15, pixel array 1510 may include a plurality of pixel columns 1550 a-f. Each of the pixel columns 1550a-f can include a plurality of individual pixels, and the pixel columns 1550a-f can be read via a corresponding pixel column bus 1551. It should be appreciated that there may be one read bus 1551 per pixel column 1550 within the entire pixel array 1510. It should be noted that a plurality of individual pixels 1526 may be formed in columns (y-axis) and rows (x-axis) that represent or define the location of the individual pixels 1526 within the pixel array 1510.

As shown, each of the plurality of pixel column read buses 1551 can provide electrical connections to a predetermined or defined pixel column 1550 (e.g., 1550a, 1550b, 1550c, 1550d, 1550e, and 1550f in fig. 15). In this embodiment, data collected from pixels 1526 within a predetermined or defined pixel column (e.g., 1550 a) can be transmitted via a circuit column read bus 1516 (see fig. 14) and/or through one or more interconnects 1521 to support circuits 1520 located on one or more second subsequent substrates or support substrates 1554. Circuitry 1520 may be located on either side of support substrate 1554 and electrical contact may be facilitated by vias disposed in and through the substrate material. Subsequent substrate 1554 may include a plurality of circuit columns, each circuit column including a plurality of circuits 1520 and a bus 1516 for electrically connecting the various circuits 1520 within the circuit column within image sensor 1500. It should be noted that the spacing between interconnects 1521 that may be used to connect pixel column bus 1551 to circuit column bus 1516 has been increased in the figure by staggering the interconnects 1521 relative to the pixel columns 1550 a-f. The dashed lines shown on substrate 1554 illustrate areas on the substrate corresponding to areas consumed by pixel columns 1550 on first substrate 1552.

In one embodiment, it may be desirable to design an image sensor 1500 in which the support circuits 1520 for any given pixel column 1550 are placed within corresponding regions on a second substrate. It should be noted that in one embodiment, one or more dedicated support circuits 1520 may be used per pixel column or region 1550 such that each pixel region 1550a-1550f has at least one support circuit 1520 dedicated to processing only data produced by pixels 1526 within the predetermined or defined pixel column represented by the pixel column 1550a-1550f dedicated to the support circuit. For example, each pixel column area 1550a-1550f can have dedicated analog-to-digital conversion circuitry for converting analog data read from an associated pixel 1526 within the associated pixel column 1550. This close and direct association of dedicated circuitry can be used to simplify digital signal processing within the image sensor 1500, thereby greatly simplifying timing and sequencing processes within the image sensor 1500. This feature may also be used to control heat production and energy consumption within the image sensor 1500.

Referring primarily to FIG. 16, a multi-substrate image sensor 1600 having a read bus configuration is shown. As shown, substrate 1652 may include a pixel array 1610 and may be electrically connected to support substrates 1654 and 1656 by a plurality of pixel column read buses. The image sensor architecture can be greatly simplified by placing the support circuitry on one or more subsequent substrates 1654 and 1656. Subsequent base plates 1654 and 1656 may abut first base plate 1652, but be behind first base plate 1652. Support circuits 1622 and 1663 may be located on subsequent substrates 1654 and 1656 to allow stacking of the substrates in the illustrated portrait configuration. Vias through the substrate may be used to allow communication back and forth through any substrate. The second substrate 1654 in the stack can include secondary circuitry dedicated to the pixel column 1650 on the first substrate 1652 and electrically connected to the pixel column 1650. The third substrate 1654 may include additional data processing circuitry 1663 that may be dedicated to the support circuitry 1622 on the second substrate and may be used to process data from multiple support circuitry of the second substrate. It should be noted that the circuitry 1663 on the third substrate 1656 may be dedicated to a particular column of pixels 1650 on the first substrate 1652, or may be dedicated to processing data from multiple columns of pixels 1650. In other words, the circuitry 1663 on the third substrate 1656 may directly correspond to specific circuitry 1622 on the second substrate 1654 or specific columns of pixels 1650 on the first substrate 1652. It should be noted that each substrate may include at least one bus electrically connecting the circuits on all substrates. Thus, the busses 1623a-1623c of each substrate may be stacked such that the interconnections 1621 disposed between the substrates result in electrical connections between the busses 1623a-1623 c.

As shown, the pixel column 1650 on the first substrate 1652 can be electrically connected to support circuitry on one or more support substrates 1654, 1656 by direct pixel column reading through the arrangement of the pixel column 1650 or one or more strategically placed interconnects 1621 within the bus systems 1623a-1623 c. Each of the plurality of substrates 1652, 1654, 1656 that make up the image sensor 1600 may include its own bus or bus system 1623a, 1623b, and 1623c, respectively. It is therefore advantageous to connect each of the buses 1623 together to form a bus skeleton system 1630 from one substrate layer to the next. For example, a first substrate 1652 comprising an optimized pixel array 1610 as disclosed herein may be connected to support circuitry 1622 located on a second subsequent substrate 1654 by using interconnects 1621 located within predetermined or defined pixel columns 1650 and interconnects 1621 that may be located anywhere along the path of the overlying bus system 1623.

As shown, a first interconnect 1621a may be used to directly connect the first pixel column 1650 and the pixel column bus 1623a to a second bus or bus system 1623b and support circuitry 1622 located on the second substrate 1654, while a second interconnect 1621b may be used to connect the second bus or bus system 1623b located on the second substrate 1654 to a third bus 1623c located on the third substrate 1656. As also shown in fig. 16, bus skeleton system 1630 may be extended beyond first substrate 1652 and second substrate 1654, and may continue and electrically connect second substrate 1654 to third substrate 1656, and so on until all substrates have been electrically connected through bus skeleton system 1630. The bus 1623b located on the second substrate 1654 may be connected to a third bus 1623c, which may be located on the third substrate 1656, and so on until all substrates have been electrically connected together. Thus, a predetermined or defined column of pixels 1650 can be in electrical communication over respective buses 1623a-1623c on multiple substrates with supporting circuitry 1622 that can be remotely located on the second substrate 1654 or supporting circuitry 1663 that can be remotely located on the third substrate 1656.

It should be noted that because a single interconnect 1621 may be used to read a column 1650 that includes multiple pixels, the interconnect spacing or pitch may be much larger than the pixel pitch of pixel array 1610.

During use, data created by individual pixels on the pixel array must be processed by the support circuitry, and thus each pixel 1726 must be electrically connected to the support circuitry 1770 on the second substrate 1754. Ideally each pixel can be read simultaneously, thereby creating a global shutter. Referring now to fig. 17a, it should be appreciated that the ability to read data from an imaging device that is a global shutter requires the presence of one interconnect 1724 per pixel 1726, which is difficult to achieve in practice due to bump pitch in manufacturing tolerances. Fig. 17b shows the case where pixels 1726 have been grouped into columns 1728 and the bump pitch requirement remains the same in the horizontal direction. For pixels near this size, a bump pitch of about 5 μm is required, however, bump pitches of about 20 μm to about 200 μm may be allowed in practical production using three-dimensional stacking techniques and the interconnect staggering disclosed herein. Therefore, a rolling shutter of the ultra-high frame rate type, which also uses the three-dimensional stacking technique, can be considered to be a substantial improvement. In the case of a rolling shutter, only one interconnect/bump 1724 is required per pixel column 1728 instead of one interconnect/bump 1724 per pixel 1726.

Fig. 17a illustrates a bump configuration or scheme using one bump 1724 per pixel column 1726, which approximates a global shutter operation. In this configuration, the bump pitch is equal to or substantially equal to the pixel pitch in both the X and Y axes or directions.

Fig. 17b illustrates a bump configuration or scheme using one interconnect/bump 1724 per pixel column 1728. This configuration may be used in rolling shutter operation. This bump pitch or scheme is more relaxed than the bump pitch of fig. 17a in the longitudinal direction only. It should be noted, however, that in this configuration, the bump pitch is still required to be at least the same as the pixel pitch in one direction or dimension. Fig. 17b shows a plurality of columns 1728, where each column 1728 includes a plurality of pixels 1726. Each pixel column may extend a small amount in the Y-direction (Y-axis) and may be one pixel wide as shown. Each column of pixels may be read through a single connection point at one end of each column 1728. Although this configuration simplifies the chip structure, tight tolerances must still be maintained because the lateral (horizontal) distance between pixels continues to limit the bump (interconnect) pitch, because the interconnects must not contact adjacent interconnects and must be sized accordingly.

Fig. 17c shows a bump configuration that is even more relaxed than the bump configuration shown in fig. 17a or 17 b. In this figure, bump pitch is relaxed and half of the interconnects/bumps 1724 may be processed on each side of pixel array 1710 by adding or introducing a second set of interconnects 1724 at alternating ends and opposite ends of columns 1728. As shown in fig. 17c, a second set of interconnects may be used in conjunction with the first set of interconnects, and may be used to allow half of the data to be processed or read on each side of the pixel array 1710. This configuration may allow for almost double bump pitch (interconnect) size compared to pixel pitch in at least one dimension, which would greatly reduce the cost of producing image sensor 1700. In one embodiment, multiple interconnects or bumps 1724 may be used per column of pixels 1728 so that data may be read from either end of the column of pixels 1728.

Fig. 18 a-18 f illustrate embodiments and configurations of a pixel array 1810 having staggered interconnects or bumps 1824 on a substrate/chip. As indicated above, because there is one read bus per column of pixels 1828 and one read bus per column of circuitry, and because the read buses extend from the top of the column to the bottom of the column, the interconnects/bumps 1824 may be located anywhere along the superimposed path of the buses within the column. To relax the bump pitch, the bump distance may be increased from column to column by moving the next column of bumps 1824 in the next column (in the Y-direction) either up or down.

For example, it should be appreciated that the pixel pitch may be about 5 μm and the pixel columns may be any length, such as between about 2mm to about 15 mm. It should be noted that the bump pitch depends on the pixel pitch, so that the pixel pitch will determine the ideal bump pitch. For example, assuming a desired bump pitch of about 100 μm, then placing the first interconnect or bump 1824 may be done by starting at the top of the first column and moving the next column of interconnects or bumps down 100 μm. All other bumps are similarly placed until the interconnect or bump in column 20 of lines will be at the bottom of the column of pixels. At this point, the interconnect or bump in column 21 may again be at the top of the column of pixels. This same pattern can then be repeated until the end of the pixel array. The interconnects or bumps may be separated horizontally by 20 columns by 5 μm =100 μm. In this example, although the pixel pitch is about 5 μm, all the bumps will be separated by more than 100 μm later. Redundancy may then be introduced in the pixel columns for throughput purposes. For example, the bumps in all columns may be doubled (i.e., two read buses are attached by 2 interconnects or bumps). This technique will greatly increase the throughput of the stack and reduce the cost of the overall process.

As shown in fig. 18a, a first column 1828 of pixels 1826 may be electrically accessed via a first interconnect 1824 a. In one embodiment, the second pixel column 1830 may be electrically accessed through a second interconnect 1824b, wherein the second interconnect 1824b is placed in a staggered configuration relative to the first interconnect 1824a during fabrication. As shown, the location and positioning of the second interconnect 1824b may be at least two pixel widths away from the location of the first interconnect 1824b (and away from any other interconnect 1824) in both the X and Y dimensions or directions. A third interconnect 1824c may then be placed in a third pixel column in a similar manner, and so on for the N number of interconnects 1824 on the pixel array 1810. This configuration provides an interconnect pitch that is at least three times the pixel pitch. It should be appreciated that under standard conditions, the increase in interconnect pitch may be more than three times the pixel pitch. However, it should be appreciated that the increase in interconnect pitch may be at least three times the pixel pitch shown above.

Likewise, larger interconnect increases may be achieved with region-based spacing rather than column-by-column based connections (see fig. and the discussion regarding fig. 3m, 3n, and 3u, which shows pixel column aspect ratio 6/1 and circuit column aspect ratios 6/1 (for fig. 3 m) and 3/2 (for fig. 3 n), and pixel column aspect ratio 8/1 and circuit column aspect ratio 2/4 (for fig. 3 u)). This can be done with the addition of more bus structures or the use of a direct read to a subsequent substrate. In either configuration, the interconnect pitch may thus be described as follows:

where N is the number of pixels between two adjacent interconnects in the X direction, and M is the number of pixels between two adjacent interconnects in the Y direction. It should be appreciated that each interconnect of the plurality of interconnects may be a bump, wherein the bump-to-bump distance of the bump may be greater than two pixel widths or greater than four pixel widths or greater than eight pixel widths.

In many applications, the N × pixel pitch in the X direction will be equal to the M × pixel pitch in the Y direction. As shown in fig. 18 b-18 f, a larger pixel array 1810 may be accommodated or designed by the above-described process of extrapolating through additional iterations. Fig. 18b shows a stacked silicon substrate stack. In this figure, a first substrate 1852 comprising an array of pixels is shown overlying the top of a support substrate 1854 comprising support circuitry. For simplicity and discussion, the area available for placement of support circuitry for the first column of pixels 1881 is depicted and labeled in dashed line form. It should be understood that the actual area of the circuit column is not represented by dashed lines, but may be greater than, less than, or equal to the area of the pixel column. As discussed above, the support circuit regions directly correlate the pixel column regions corresponding to the support circuit regions. Each pixel column may be one pixel wide and sixty-four pixels long and may have one read bus extending from the top to the bottom of the pixel column. In fig. 18b, the area available for support circuit placement, as shown by the bold vertical lines in the figure, may be equal to one pixel unit wide by sixty-four pixel units long. Thus, the interconnect 1824 between the substrates in fig. 18c must fall somewhere within the sixty-four pixel cell area in order to read that column, because the pixel column read bus and the circuit column read bus are superimposed along the path of the sixty-four pixels, so that the interconnect 1824 can be placed anywhere along those sixty-four pixels to connect the read buses.

Furthermore, since the interconnection may occur only where the pixel column read bus and the support circuit read bus are superimposed, the interconnection range is 1 pixel wide and 64 pixels long (for this example) for reading the corresponding pixel column, which is the intersection between the pixel column and the support circuit to be connected.

It should be noted that an exemplary aspect ratio of the support circuit area in fig. 18b is shown as 1/64. Within that area there are multiple options for positioning or placing the interconnect 1824, and the final location may then be selected by the designer to allow for the desired spacing from interconnect to interconnect. For example, as best shown in fig. 18 b-18 f, it should be understood that in embodiments where the interconnects or bumps 1824 are staggered, there may be one interconnect or bump 1824 per pixel group 1826.

Further, it should be noted that various read bus architectures may be utilized depending on the desired application. As discussed above, larger dedicated support circuits may be used to process data read through each interconnect 1824. Staggering the position of each interconnect/bump 1824 may also provide even more space for support circuitry relative to each region or group of pixels within pixel array 1810.

It should also be noted that a number of optimal staggered configurations have been found for the same sensor based, with aspect ratios of the different support circuits as shown in fig. 18b to 18 f. The optimum configuration can be found by changing the position of the interconnections within the range of the intersection between the pixel column and the support circuit and the allocation pattern of the support circuit to each pixel column. It should also be noted that all interconnects shown in fig. 18b to 18f are more than 7 pixels away from each other.

In fig. 18c, the area available for support circuit placement, as shown by the bold vertical lines in the figure, may be equal to two pixel units wide by thirty-two pixel units long. Thus, the interconnection between substrate 1852 and substrate 1854 must fall somewhere in the sixty-four pixel cell area in order to read that column. It should also be noted that the aspect ratio of the support circuit area in this example is 2/32. Each pixel column is or may be one pixel wide and sixty-four pixels long and may have one read bus extending from the top to the bottom of the pixel column. The placement selection of the interconnects has multiple options in this area and may be selected so as to allow a desired spacing from interconnect to interconnect. Furthermore, because the interconnect may be located only where the pixel column read bus and the support circuit read bus overlap, the interconnect range may be one pixel wide and thirty-two pixels long (for this example) for reading the corresponding pixel column, which is the intersection between the connected pixel column and the support circuit.

In fig. 18d, the area available for support circuit placement, as shown by the bold vertical lines in the figure, may be equal to four pixel cells wide by sixteen pixel cells long. Therefore, the interconnections between the substrates must fall somewhere in the sixty-four pixel cell area in order to read the corresponding pixel columns. It should be noted that the aspect ratio of the support circuit area in this example is 4/16. Each pixel column is or may be one pixel wide and sixty-four pixels long and may have one read bus extending from the top to the bottom of the pixel column. The placement selection of the interconnects has multiple options in this area and may be selected so as to allow a desired spacing from interconnect to interconnect.

Furthermore, because the interconnect can only be located where the pixel column read bus and the support circuit read bus overlap, the interconnect range can be one pixel wide and sixteen pixels long (for this example) for reading the corresponding pixel column, which is the intersection between the connected pixel column and the support circuit.

In fig. 18e, the area available for support circuit placement, as shown by the bold vertical lines in the figure, may be equal to eight pixel units wide by eight pixel units long. Thus, the interconnection 1824 between the substrate 1852 and the substrate 1854 must fall somewhere in the sixty-four pixel cell area in order to read the corresponding pixel column. It should be noted that the aspect ratio of the support circuit area in this example is 8/8. Each pixel column is or may be one pixel wide and sixty-four pixels long and may have one read bus extending from the top to the bottom of the pixel column. The placement selection of the interconnects has multiple options in this area and may be selected so as to allow a desired spacing from interconnect to interconnect.

Furthermore, because the interconnect can only be located where the pixel column read bus and the support circuit read bus overlap, the interconnect range can be one pixel wide and eight pixels long (for this example) for reading the corresponding pixel column, which is the intersection between the connected pixel column and the support circuit.

In fig. 18f, the area available for support circuit placement, as shown by the bold vertical lines in the figure, may be equal to sixteen pixel cells wide by four pixel cells long. Therefore, the interconnections between the substrates must fall somewhere in the sixty-four pixel cell area in order to read the corresponding pixel columns. It should be noted that the aspect ratio of the support circuit region in this example is 16/4, which illustrates the flexibility that the methods and apparatus disclosed herein can provide. Each pixel column is or may be one pixel wide and sixty-four pixels long and may have one read bus extending from the top to the bottom of the pixel column. The placement selection of the interconnects has multiple options in this area and may be selected so as to allow a desired spacing from interconnect to interconnect.

Furthermore, because the interconnect can only be located where the pixel column read bus and the support circuit read bus overlap, the interconnect range can be one pixel wide and four pixels long (for this example) for reading the corresponding pixel column, which is the intersection between the connected pixel column and the support circuit.

It should also be noted that the pattern of association of support circuits to pixel columns may be different from that of fig. 18b to 18f, and that this association may ultimately provide the optimal distance of the interconnects to be far from each other. For example, the interconnects may be optimally placed at least two pixel wide apart, four pixel wide apart, eight pixel wide apart, or more wide apart from each other. The designer can best determine the distance that interconnects can be placed far from each other based on the following two degrees of freedom: (1) the number of pixels per column, and (2) the circuit aspect ratio and location. In the example shown in fig. 18 b-18 f, the interconnects 1824 may be placed approximately eight pixels apart from each other. However, it should be understood that other designs may be implemented without departing from the spirit or scope of the present disclosure.

For example, as shown in fig. 18b, each interconnect 1824 may be placed eight pixels apart in length and one pixel apart in width from each other. Because each circuit column has an aspect ratio of one pixel wide and sixty-four pixels long, each interconnect 1824 may then be placed eight pixels away from each other in adjacent columns until the bottom of the circuit 1800 is reached, as shown in fig. 18b, in which case the interconnect 1824 is then moved to the top of the next column and continues for the entire width of the pixel array 1810. Conversely, in fig. 18f, interconnects 1824 are still placed eight pixels apart in length and one pixel apart in width from each other. However, in this example, the circuit column aspect ratio is now four pixels long and sixteen pixels wide. Thus, for interconnect 1824 to be at least eight pixels away from each other, one circuit column 1856b must be skipped since the aspect ratio is only four pixels long, so that interconnect 1824 maintains the optimal spacing. Thus, for example, placing interconnect 1824 in the upper left corner of the pixel array in fig. 18f (on the first pixel of first column 1828) and then moving to the next pixel column 1830 and counting down eight pixels in length, then the next interconnect 1824 may be placed in the third circuit column 1856c, skipping, in summary, the second circuit column 1856 b. This pattern may be used throughout the pixel array. The second skipped circuit column 1856b is then connected to the pixel array by interconnect 1824a located in the ninth pixel column, and the pattern is repeated for all skipped circuit columns. Thus, as shown, optimal interconnect spacing may be achieved and various circuit designs may be accommodated without departing from the scope of the present disclosure.

Referring back to FIG. 7, in addition to first image sensor 710 and second image sensor 711, which are in electrical communication with substrate 715 or substrates, embodiments of an imaging sensor having multiple pixel arrays that may be configured with staggered interconnections as discussed herein above are also shown. This configuration may be required for three-dimensional image acquisition, which may offset the two pixel arrays during use. In another embodiment, the first pixel array and the second pixel array may be dedicated to receiving a predetermined wavelength range of electromagnetic radiation, wherein the first pixel array is dedicated to a different wavelength range of electromagnetic radiation than the second pixel array.

Fig. 19 illustrates the design and testing methodology associated with optimizing the pixel array on the first substrate. One step may be to determine the available tolerance differences for the fabrication of the imaging sensor. The design may then be processed and bump pitch may be determined for some criteria. The simulated test sensor can then be tested, read and redesigned if necessary.

Fig. 20 illustrates an embodiment having at least one dedicated support circuit for a given pixel area. A plurality of dedicated support circuits 2060a-2060f may be used in imaging device 2000 and may be stacked with pixel array 2010 in accordance with the principles of the present disclosure. Pixel array 2010 may include a plurality of pixel regions 2050. Each pixel region (e.g., 2050a-2050 f) of the plurality of pixel regions may include at least one support circuit 2060, the support circuit 2060 being dedicated to processing only data produced by the plurality of pixels 2026 within a given predetermined or defined pixel region 2050 to which the support circuit 2060 is dedicated. For example, each pixel region 2050 may have a dedicated analog-to-digital conversion circuit for converting analog data read from an associated pixel 2026 from within the associated pixel region 2050. The closely and directly associated dedicated circuitry can be used to simplify digital signal processing within the image sensor, thereby greatly simplifying timing and sequencing processes within the image sensor. This feature can also be used to control heat production and energy consumption within the image sensor.

In fig. 21, this figure schematically illustrates a scalable large image sensor for illustrating the teachings and principles of the present disclosure. Each pixel column is or may be one pixel wide and one hundred twenty eight pixels long. Note that this was chosen as an example for representing the teachings of the present disclosure, but it should be noted that any number of pixels is possible and may be used for the column length without departing from the scope of the present disclosure. It should also be noted that the number of pixels may be even or odd for the column length and need not be a power of 2. As shown, the area available for support circuit placement, as shown by the bold vertical lines in the figure, may be equal to four pixel cells wide by sixteen pixel cells long. Therefore, the interconnections between the substrates must fall somewhere in the sixty-four pixel cell area. Furthermore, because the interconnect can only be located where the pixel column read bus and the support circuit read bus overlap, the interconnect range can be one pixel wide and sixteen pixels long (for this example) for reading the corresponding pixel column, which is the intersection between the connected pixel column and the support circuit. It should be noted that the aspect ratio of the support circuit area in this example is 4/16. The placement selection of the interconnects has multiple options in this area and may be selected so as to allow a desired spacing from interconnect to interconnect. As shown in the figures, even the latest imaging sensor technology can be used for these methods by repeating the methods disclosed herein. It should also be noted that there may be multiple interconnects (2516 and 2518) for any given column of pixels, allowing more flexibility for large array configurations (e.g., parallel processing of columns of pixels).

In fig. 22, this figure schematically illustrates a scalable large image sensor for illustrating the teachings and principles of the present disclosure. Each pixel column is or may be one pixel wide and one hundred twenty eight pixels long. Note that this is chosen as an example for representing the teachings of the present disclosure, but it should be noted that any number of pixels are possible and may be used for the column length without departing from the scope of the present disclosure. It should also be noted that the number of pixels may be even or odd for the column length and need not be a power of 2. As shown, the area available for support circuit placement, as shown by the bold vertical lines in the figure, may be equal to two pixel units wide by thirty-two pixel units long. Therefore, the interconnections between the substrates must fall somewhere in the sixty-four pixel cell area. Furthermore, because the interconnect can only be located where the pixel column read bus and the support circuit read bus overlap, the interconnect range can be one pixel wide and sixteen pixels long (for this example) for reading the corresponding pixel column, which is the intersection between the connected pixel column and the support circuit. It should also be noted that the aspect ratio of the support circuit area is 2/32. The placement selection of the interconnects has multiple options in this area and may be selected so as to allow a desired spacing from interconnect to interconnect. As shown in the figures, even the latest imaging sensor technology can be used for these methods by repeating the methods disclosed herein. It should also be noted that there may be multiple interconnects (2616 and 2618) for any given pixel column, allowing more flexibility for large array configurations (e.g., pixel column parallel processing). It should be noted that fig. 21 and 22 represent the same pixel array, the only difference between the two figures being that the aspect ratio of the support circuitry has changed (i.e., aspect ratio 4/16 in fig. 21 and aspect ratio 2/32 in fig. 22).

It should be understood that the structures and devices disclosed herein are merely examples for optimizing an imaging sensor and that structures, devices, or systems for optimizing pixel arrays on image sensors using three-dimensional stacking techniques and staggering interconnections between substrates in a stack for performing the same or equivalent functions to those disclosed herein, including those structures, devices, or systems for imaging that are now known or that may become available in the future, are intended to fall within the scope of the present disclosure. Anything that is the same or equivalent in function to a device for optimizing an array of pixels on an image sensor using three-dimensional stacking techniques and the interconnections between substrates in a staggered stack is within the scope of this disclosure.

Those of ordinary skill in the relevant art will appreciate the advantages provided by the features of the present disclosure. For example, a potential feature of the present disclosure is to provide an optimized pixel array on an imaging sensor that is simple in design and manufacture. Another potential feature of the present disclosure is to provide the imaging sensor with larger pixels relative to the overall size. Another potential feature is to provide an optimized pixel array on an image sensor using three-dimensional stacking techniques and interconnections between substrates in a staggered stack.

In the foregoing detailed description, various features are disclosed which are, for brevity, combined in a single embodiment. This method of disclosure is not to be interpreted as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment, and various inventive features disclosed in separate embodiments can be combined to form their own embodiments as more fully claimed in the appended claims. Thus, the following claims are hereby incorporated into the specification by reference, with each claim standing on its own as a separate embodiment of the disclosure herein.

It is to be understood that the above-described arrangements are only illustrative of the application of the principles disclosed herein. Numerous modifications and alternative arrangements may be devised by those skilled in the art without departing from the spirit and scope of the present disclosure, and the disclosure herein is intended to cover such modifications and arrangements. Thus, while the disclosure herein has been shown in the drawings and described above with particularity and detail, it will be apparent to those of ordinary skill in the art that numerous modifications (including, but not limited to, variations in size, materials, shape, form, function and manner of extension, assembly and use) may be made without departing from the principles and concepts set forth herein.

Claims (72)

1. An imaging sensor, comprising:

a plurality of substrates including a first substrate and at least one second subsequent support substrate;

an array of pixels;

a plurality of interconnects; and

a support circuit;

wherein a first substrate of the plurality of substrates comprises a pixel array;

wherein the support circuitry is disposed on the at least one second subsequent support substrate disposed at a remote distance relative to the first substrate;

wherein the support circuitry is electrically connected and in electrical communication with the pixel array via a plurality of interconnects disposed between the first substrate and the at least one second subsequent support substrate;

wherein the second, subsequent support substrate is disposed behind the pixel array with respect to an object to be imaged;

wherein the plurality of interconnects are spaced relative to each other by a distance greater than a pixel pitch of the pixel array;

wherein the pixel array comprises a plurality of pixel columns, wherein each pixel column comprises a plurality of pixels, and the support circuitry comprises a plurality of circuit columns, each circuit column comprising circuitry for supporting a corresponding pixel column.

2. The imaging sensor of claim 1, wherein the imaging sensor is back-illuminated.

3. The imaging sensor of claim 1, wherein said plurality of substrates further comprises a plurality of second subsequent supporting substrates.

4. The imaging sensor of claim 1, wherein the pixel array covers a majority of a surface of the first substrate.

5. The imaging sensor of claim 1, wherein said pixel array covers more than twenty-five percent of the surface of said first substrate.

6. The imaging sensor of claim 1, wherein said pixel array covers more than forty percent of a surface of said first substrate.

7. The imaging sensor of claim 1, wherein said pixel array covers more than seventy percent of the surface of said first substrate.

8. The imaging sensor of claim 1, wherein said pixel array covers more than ninety percent of a surface of said first substrate.

9. The imaging sensor of claim 1, wherein one of said support circuits is an analog-to-digital converter.

10. The imaging sensor of claim 1, wherein one of the support circuits is an amplifier circuit.

11. The imaging sensor of claim 1, wherein said at least one second, subsequent support substrate is aligned in the Z-dimension with said first substrate in a stacked configuration.

12. The imaging sensor of claim 1, wherein the second, subsequent support substrate is disposed behind and laterally displaced from the first substrate.

13. The imaging sensor of claim 2, wherein the first substrate is made primarily of silicon material.

14. The imaging sensor of claim 2, wherein said first substrate is made primarily of a "high-impedance" semiconductor material.

15. The imaging sensor of claim 2, wherein the first substrate is made primarily of cadmium telluride.

16. The imaging sensor of claim 2, wherein the first substrate is made of a III-V semiconductor material.

17. The imaging sensor of claim 2, wherein the first substrate is made of gallium arsenide.

18. The imaging sensor of claim 3, wherein the first substrate and the plurality of second subsequent support substrates are stacked in alignment such that a plurality of communication columns are formed in a multi-layer stack.

19. The imaging sensor of claim 1, wherein each interconnect of the plurality of interconnects is a bump and comprises a bump-to-bump distance that is greater than two pixels wide.

20. The imaging sensor of claim 19, wherein the bump-to-bump distance is greater than four pixels wide.

21. The imaging sensor of claim 19, wherein the bump-to-bump distance is greater than eight pixels wide.

22. The imaging sensor of claim 19, wherein bump pitch is greater than

23. The imaging sensor of claim 1, wherein the pixel array comprises a plurality of pixel columns, wherein each pixel column comprises a plurality of pixels;

wherein each of the plurality of pixel columns within the pixel array is read to the bus starting with a first column read from a common origin, wherein a second column is read from a first row that is different from a previously read pixel column with respect to the second column and different from a subsequently read pixel column with respect to the second column.

24. The imaging sensor of claim 23, wherein said first row is spaced at least two row positions away from a row position of a previously read pixel column and a subsequently read pixel column.

25. An imaging sensor, comprising:

a plurality of substrates including a first substrate and at least one second subsequent support substrate;

an array of pixels;

a plurality of interconnects; and

a support circuit;

wherein a first substrate of the plurality of substrates comprises the pixel array;

wherein the support circuitry is disposed on the at least one second subsequent support substrate disposed at a remote distance relative to the first substrate;

wherein the support circuitry is electrically connected and in electrical communication with the pixel array via a plurality of interconnects disposed between the first substrate and the at least one second subsequent support substrate;

wherein the second, subsequent support substrate is disposed behind the pixel array with respect to an object to be imaged;

wherein the pixel array covers a majority of a surface of the first substrate,

wherein the plurality of interconnects are spaced relative to each other by a distance greater than a pixel pitch of the pixel array;

wherein the pixel array comprises a plurality of pixel columns, wherein each pixel column comprises a plurality of pixels, and the support circuitry comprises a plurality of circuit columns, each circuit column comprising circuitry for supporting a corresponding pixel column.

26. The imaging sensor of claim 25, wherein the imaging sensor is back-illuminated.

27. The imaging sensor of claim 25, wherein said plurality of substrates further comprises a second plurality of subsequent support substrates.

28. The imaging sensor of claim 25, wherein said pixel array covers a majority of a surface of said first substrate.

29. The imaging sensor of claim 25, wherein said pixel array covers more than fifty-five percent of the surface of said first substrate.

30. The imaging sensor of claim 25, wherein said pixel array covers more than sixty percent of the surface of said first substrate.

31. The imaging sensor of claim 25, wherein said pixel array covers more than seventy percent of the surface of said first substrate.

32. The imaging sensor of claim 25, wherein said pixel array covers more than ninety percent of a surface of said first substrate.

33. The imaging sensor of claim 25, wherein one of said support circuits is an analog-to-digital converter.

34. The imaging sensor of claim 25, wherein one of said support circuits is an amplifier circuit.

35. The imaging sensor of claim 25, wherein said at least one second, subsequent support substrate is aligned in the Z-dimension with said first substrate in a stacked configuration.

36. The imaging sensor of claim 25, wherein said at least one second, subsequent support substrate is disposed behind and laterally displaced from said first substrate.

37. The imaging sensor of claim 26, wherein said first substrate is made primarily of silicon material.

38. The imaging sensor of claim 26, wherein said first substrate is made primarily of a "high-impedance" semiconductor material.

39. The imaging sensor of claim 26, wherein said first substrate is made primarily of cadmium telluride.

40. The imaging sensor of claim 26, wherein said first substrate is made of III-V semiconductor material.

41. The imaging sensor of claim 26, wherein said first substrate is made of gallium arsenide.

42. The imaging sensor of claim 27, wherein said first substrate and said plurality of second subsequent support substrates are stacked in alignment such that a plurality of communication columns are formed in a multi-layer stack.

43. The imaging sensor of claim 25, wherein each interconnect of the plurality of interconnects is a bump and comprises a bump-to-bump distance that is greater than two pixels wide.

44. The imaging sensor of claim 43, wherein the bump-to-bump distance is greater than four pixels wide.

45. The imaging sensor of claim 43, wherein the bump-to-bump distance is greater than eight pixels wide.

46. The imaging sensor of claim 43, wherein bump pitch is greater than

47. The imaging sensor of claim 25, wherein said pixel array comprises a plurality of pixel columns, wherein each pixel column comprises a plurality of pixels;

wherein each of the plurality of pixel columns within the pixel array is read to the bus starting with a first column read from a common origin, wherein a second column is read from a first row that is different from a previously read pixel column with respect to the second column and different from a subsequently read pixel column with respect to the second column.

48. The imaging sensor of claim 47, wherein said first row is spaced at least two row positions away from a row position of a previously read pixel column and a row position of a subsequently read pixel column.

49. An imaging sensor, comprising:

a plurality of substrates;

an array of pixels; and

a support circuit;

wherein a first substrate of the plurality of substrates comprises the pixel array;

wherein the support circuitry is disposed on at least one subsequent support substrate disposed remotely with respect to the first substrate;

wherein the support circuitry is electrically connected and in electrical communication with the pixel array;

wherein the at least one subsequent support substrate is disposed behind the pixel array with respect to an object to be imaged; and is

Wherein the pixel array covers at least forty percent of the first surface of the first substrate;

wherein the pixel array of the first substrate is in electrical communication with the support circuitry disposed on the at least one subsequent support substrate through a plurality of respective read buses disposed on each of the plurality of substrates and is electrically connected through an interconnect;

wherein the pixel array comprises a plurality of pixel columns, wherein each pixel column comprises a plurality of pixels, and the support circuitry comprises a plurality of circuit columns, each circuit column comprising circuitry for supporting a corresponding pixel column.

50. The imaging sensor of claim 49, wherein said imaging sensor is back-illuminated.

51. The imaging sensor of claim 49, wherein said at least one subsequent support substrate comprises a plurality of subsequent support substrates.

52. The imaging sensor of claim 49, wherein said pixel array covers a majority of a surface of said first substrate.

53. The imaging sensor of claim 49, wherein said pixel array covers more than fifty percent of the surface of said first substrate.

54. The imaging sensor of claim 49, wherein said pixel array covers more than sixty percent of the surface of said first substrate.

55. The imaging sensor of claim 49, wherein said pixel array covers more than seventy percent of the surface of said first substrate.

56. The imaging sensor of claim 49, wherein said pixel array covers more than ninety percent of a surface of said first substrate.

57. The imaging sensor of claim 49, wherein one of said plurality of support circuits is an analog-to-digital converter.

58. The imaging sensor of claim 49, wherein one of said support circuits is an amplifier circuit.

59. The imaging sensor of claim 49, wherein said at least one subsequent support substrate is aligned with said first substrate.

60. The imaging sensor of claim 49, wherein said at least one subsequent support substrate is disposed behind and laterally displaced from said first substrate.

61. The imaging sensor of claim 50, wherein said first substrate is made primarily of silicon material.

62. The imaging sensor of claim 50, wherein said first substrate is made primarily of a "high-impedance" semiconductor material.

63. The imaging sensor of claim 50, wherein said first substrate is made primarily of cadmium telluride.

64. The imaging sensor of claim 50, wherein said first substrate is made of a III-V semiconductor material.

65. The imaging sensor of claim 50, wherein said first substrate is made of gallium arsenide.

66. The imaging sensor of claim 51, wherein said first substrate and said plurality of subsequent support substrates are stacked in alignment such that a plurality of communication columns are formed in a multi-layer stack.

67. The imaging sensor of claim 49, wherein each of said plurality of interconnects is a bump and comprises a bump-to-bump distance that is greater than two pixels wide.

68. The imaging sensor of claim 67, wherein the bump-to-bump distance is greater than four pixels wide.

69. The imaging sensor of claim 67, wherein the bump-to-bump distance is greater than eight pixels wide.

70. The imaging sensor of claim 67, wherein bump pitch is greater than

71. The imaging sensor of claim 49, wherein said pixel array comprises a plurality of pixel columns, wherein each pixel column comprises a plurality of pixels;

wherein each of the plurality of pixel columns within the pixel array is read to the bus starting with a first column read from a common origin, wherein a second column is read from a first row that is different from a previously read pixel column with respect to the second column and different from a subsequently read pixel column with respect to the second column.

72. The imaging sensor of claim 71, wherein said first row is spaced at least two row positions away from a row position of a previously read pixel column and a row position of a subsequently read pixel column.