HK1194864A - Two terminal multi-channel esd device and method therefor - Google Patents

Description

Two terminal multi-channel ESD device and method thereof

The divisional application is based on a Chinese patent application with the application number of 200910173120.0, the application date of 2009, 9, 7 and the name of 'two-terminal multi-channel ESD device and method thereof'.

Cross Reference to Related Applications

This application is related to a previously filed application having an application serial number of 200810214420.4, having common assignee, common inventor, and inventor Salih et al, entitled "MULTI-CHANNEL ESD DEVICE ands heat exchanger," which is hereby incorporated herein by reference.

Technical Field

The present invention relates generally to electronics, and more particularly to methods and structures for forming semiconductor devices.

Background

In the past, the semiconductor industry utilized various methods and structures to construct electrostatic discharge (ESD) protection devices. According to an international code, commonly referred to as the International Electrotechnical Commission (IEC) code of IEC61000-4-2 (level 2), it is desirable for ESD devices to respond to high input voltages and currents in approximately 1 nanosecond (IEC is addressed at rue de varebe, 1211Gen e20, switzerland).

Some existing ESD devices use zener diodes and P-N junction diodes in an attempt to provide ESD protection. In general, existing ESD devices must compromise low capacitance with having sharp breakdown voltage characteristics. A sharp breakdown voltage characteristic is required to provide a low clamping voltage for the ESD device. In most cases, the device structure has a high capacitance, typically greater than about 1 to 6 picofarads. The high capacitance limits the response time of the ESD device. Some existing ESD devices operate in punch-through mode, which requires the device to have a very thin and precisely controlled epitaxial layer, typically less than about 2 microns thick, and requires low doping in the epitaxial layer. These structures often make it difficult to accurately control the clamping voltage of the ESD device, particularly to control low clamping voltages, such as voltages less than about 10 volts (10V). An example of such an ESD device is disclosed in U.S. patent No. 5,880,511 issued to Bin Yu et al on 9/3 1999. Another ESD device utilizes the body region of a vertical MOS transistor to form a zener diode at the interface with the underlying epitaxial layer. The doping profile and depth used for ESD devices results in high capacitance and slow response time. Furthermore, it is difficult to control the light doping level in the thin layer, which makes it difficult to control the breakdown voltage of the ESD device. An example of such an ESD device is disclosed in us patent application No. 2007/0073807 by inventor MadhurBobde, published 3/29 2007.

It is often desirable to construct an ESD device having two terminals so that the ESD device can be assembled in a two terminal semiconductor package.

Accordingly, it is desirable to have an electrostatic discharge (ESD) device that has two terminals, has a low capacitance, has a fast response time, reacts to positive and negative ESD events, has a well controlled clamping voltage, is easy to control in manufacturing, and has a clamping voltage that can be controlled over a range from a low voltage to a high voltage.

Drawings

FIG. 1 schematically illustrates an embodiment of a portion of a circuit representation of an electrostatic discharge (ESD) protection device according to the present invention;

fig. 2 shows a cross-sectional portion of an embodiment of the ESD device of fig. 1 in accordance with the present invention;

fig. 3 through 5 show various sequential stages of some steps in a preferred method of forming the ESD device of fig. 1 in accordance with the present invention;

fig. 6 is an enlarged plan view of a portion of the embodiment of the ESD device of fig. 1-5 according to the invention;

fig. 7 is a graph showing the V-I characteristics of the ESD devices of fig. 1 through 6 according to the present invention;

fig. 8 is a graph showing some carrier concentrations of the ESD devices of fig. 1-7 according to the present invention;

fig. 9 is a graph illustrating V-I characteristics of alternative embodiments of the ESD devices of fig. 1 through 8 according to the present invention;

fig. 10 schematically illustrates an embodiment of a portion of a circuit representation of yet another electrostatic discharge (ESD) protection device, which is an alternative embodiment of the ESD device of fig. 1-8, in accordance with the present invention;

fig. 11 is a graph showing the V-I characteristic of the ESD device of fig. 10 according to the present invention;

FIG. 12 schematically illustrates an embodiment of a portion of a circuit representation of another electrostatic discharge (ESD) protection device according to the present invention; and

fig. 13 shows a cross-sectional portion of an embodiment of the ESD device of fig. 12 in accordance with the present invention.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Moreover, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, current carrying electrode means an element of a device that carries current through the device, such as a source or drain of an MOS transistor, or a collector or emitter of a bipolar transistor, or a cathode or anode of a diode; and a control electrode means an element of the device that controls the current through the device, such as the gate of a MOS transistor or the base of a bipolar transistor. Although these devices are explained herein as certain N-channel or P-channel devices, or certain N-type or P-type doped regions, one of ordinary skill in the art will recognize that complementary devices are also possible in accordance with the present invention. Those skilled in the art will recognize that the word "during.. at the same time, when.. is used" is not an exact term to indicate that an action will occur as soon as there is a start-up action, but rather that there may be some slight but reasonable delay, such as a propagation delay, between the reactions provoked by the initial action. Use of the word "about" or "substantially" means that the value of an element has a parameter that is expected to be very close to a specified value or position. However, as is well known in the art, there is always a slight variation in the blocking value or position exactly as specified. It is well established in the art that variations up to about 10% (and for semiconductor doping concentrations up to 20%) are reasonable variations from the ideal target exactly as described. For clarity of the drawings, the doped regions of the device structure are shown as having generally straight edges and precisely angled corners. However, those skilled in the art understand that the edges of the doped regions are generally not straight lines and the angles may not be precise angles due to diffusion and activation of the dopants.

Detailed Description

Fig. 1 schematically illustrates an embodiment of an electrostatic discharge (ESD) protection device or a portion of an ESD device 10, the ESD device 10 having a low capacitance, fast response time, and being easily assembled as a two terminal device within a two terminal semiconductor package. Device 10 includes two terminals, a first terminal 11 and a second terminal 12, and is configured to provide bi-directional ESD protection between terminals 11 and 12. Either one of the terminals 11 and 12 may be an input terminal or an output terminal. The output terminals are typically connected to another element (not shown) that is protected by device 10. For example, the terminals 11 and 12 may be connected between two electric wires forming a communication line or a data transmission line between two electronic devices, or the terminal 12 may be used as an output terminal and connected to a high side of a regulated power supply (e.g., a 5V power supply), and the terminal 11 is connected to a low side of the power supply. The terminals 11 and 12 may be connected to both terminals of a two-terminal semiconductor package such as a SOD323 or SOD923 package. The assembly of device 10 into a two terminal semiconductor package facilitates the use of device 10 in place of existing two terminal ESD devices. Furthermore, the configuration of device 10 allows device 10 to be assembled into a semiconductor package regardless of which of terminals 11 or 12 is connected to which terminal of the package. This advantageously eliminates assembly errors for the reverse connection, thereby reducing assembly costs and reducing the cost of the device 10. Device 10 is also configured to have a low capacitance between terminals 11 and 12. Device 10 is formed to limit the maximum voltage developed between terminals 11 and 12 to the clamping voltage of device 10. In addition, device 10 is formed with a sharp knee voltage or sharp breakdown voltage characteristic that helps to precisely control the value of the clamping voltage. The low capacitance helps provide the device 10 with a fast response time. Device 10 includes a plurality of steering diode channels, such as a first steering diode channel that includes a first steering diode 14, a second steering diode 21, and a zener diode 18. The second steering diode path includes a third steering diode 20, a fourth steering diode 15, and a zener diode 19. The device 10 also includes two back-to-back diodes shown as diodes 85 and 87. First steering diode 14 has an anode commonly connected to terminal 11 and a cathode connected to the cathode of zener diode 18. The anode of the diode 18 is connected to the anode of the second steering diode 21. The cathode of diode 21 is connected to terminal 12. Similarly, the anode of third steering diode 20 is connected to terminal 12 and the anode of back-to-back diode 85. The cathode of the diode 20 is connected to the cathode of the zener diode 19. The anode of diode 19 is connected to the anode of fourth steering diode 15 and to the anode of diode 87 of the back-to-back diode. The cathode of the diode 87 is connected to the cathode of the diode 85. The cathode of diode 15 is connected to terminal 11. Diodes 14, 15, 20, and 21 are formed as P-N junction diodes with low capacitance.

If a positive electrostatic discharge (ESD) event is received on terminal 11, terminal 11 is forced to a large positive voltage relative to terminal 12. The large positive voltage forward biases diodes 14 and 21 and reverse biases diode 18 and diodes 15, 19 and 20. When the voltage between terminals 11 and 12 reaches the positive threshold voltage of device 10 (the forward voltage of diodes 14 and 21 plus the zener voltage of diode 18), a positive current (Ip) flows from terminal 11 through diode 14 to diode 18 and through diodes 18 and 21 to terminal 12. The sharp knee voltage of diode 18 causes diode 18 to quickly fix the maximum voltage developed between terminals 11 and 12 to the zener voltage of diode 18 (plus the forward voltages of diodes 14 and 21). If a negative ESD event is received on terminal 11, terminal 11 is forced to a large negative voltage relative to terminal 12. The large negative voltage forward biases diodes 20 and 15 and reverse biases diode 19 and diodes 14, 18, and 21. When the voltage between terminals 11 and 12 reaches the negative threshold voltage of device 10 (the forward voltage of diodes 20 and 15 plus the zener voltage of diode 19), a negative current (In) flows from terminal 12 through diode 20 to diode 19 and through diodes 19 and 15 to terminal 11. The sharp knee voltage of diode 19 causes diode 19 to quickly fix the maximum voltage developed between terminals 11 and 12 to the zener voltage of diode 19 (plus the forward voltages of diodes 15 and 20).

Fig. 2 shows a cross-sectional view of a portion of an embodiment of ESD device 10. The diodes 14, 15, 18, 19, 20 and 21 are identified in a general manner by arrows. As will be seen further hereinafter, the device 10 includes a bulk semiconductor substrate 23 with an isolation layer 24 formed on the substrate 23. A conductor layer 25 is formed on the surface of layer 24 to conduct the currents Ip and In, as will be seen further below. Isolation layer 24 helps to control the flow of currents Ip and In within layer 25 and isolates diodes 14, 15, 18, 19, 20 and 21 from bulk semiconductor substrate 23. Semiconductor layer 33 is formed on layer 25 to help form diodes 14, 15, 20, and 21. Semiconductor region 29 is formed near the interface of the dopants forming layer 33 and the dopants of layer 25 to help form diodes 18 and 19.

Fig. 3 through 5 illustrate various sequential stages of some steps in a preferred method of forming device 10. Referring to fig. 3, in the preferred embodiment, the bulk semiconductor substrate 23 has a P-type conductivity, and typically has about 1X10¹⁹atoms/cm³And preferably at about 1X10¹⁹And 1X10²¹atoms/cm³With the doping concentration in between. The isolation layer 24 is preferably formed as an N-type epitaxial layer on the surface of the substrate 23. Layer 25 is formed as a P-type epitaxial layer on the surface of layer 24. The portion 75 of the surface of layer 25 that will form semiconductor region 29 is doped with a dopant that can form an N-type doped region on the surface of layer 25.

Referring to fig. 4, after portion 75 is doped, layer 33 is formed as an N-type epitaxial layer on the surface of layer 25. During the formation of layer 33, the dopants in portion 75 are typically activated to form doped semiconductor region 29 at the interface between layers 25 and 33. Region 29 may extend into layers 33 and 25 or may be formed in other locations so long as region 29 forms a P-N junction with, for example, layer 33.

Subsequently, a plurality of barrier structures, for example, isolation trenches 35, 36, 37 and 38 (fig. 2), are formed in order to isolate the portions of layer 33 where each diode 14, 15, 20 and 21 is formed from each other. These barrier structures have a perimeter (e.g., a perimeter at the surface of layer 33 and extending vertically into layer 33) that surrounds each respective diode and prevents current from flowing laterally from any of diodes 14, 15, 20, and 21 through layer 33 and forces any lateral current flowing between these diodes to appear within layer 25. To form isolation trenches 35, 36, 37, and 38, a mask 76, such as a silicon dioxide or silicon nitride layer, is formed over layer 33 and patterned to form openings 77 where trenches 35, 36, 37, and 38 will be formed. Opening 77 is used to form an opening that extends through layer 33 and into layer 25. The openings of trenches 35 and 37 also extend through region 29 into layer 25 so that trenches 35 and 37 can reduce conduction laterally through region 29 between diodes 18 and 19 and reduce conduction with either of diodes 15 or 21. In addition, trenches 35 and 37 divide region 29 into separate regions that will form separate P-N junctions between region 29 and layer 25, thereby using region 29 to form the two zener diodes 18 and 19. In some embodiments, an electrolyte liner 30, such as silicon dioxide, may be formed along the sidewalls and bottom of the openings of trenches 35, 36, 37, and 38. In other embodiments, the electrolyte lining is removed (or not formed) along the bottom of the openings of trenches 35, 36, 37, and 38. Liner 30 helps to form each of trenches 35, 36, 37 and 38 as an isolation trench. For clarity of the drawing, the liner 30 is shown as a line along the side of the opening.

Fig. 5 shows device 10 after a subsequent step in the method. After forming the openings for trenches 35, 36, 37 and 38, mask 76 is typically removed (fig. 4). Thereafter, the openings of trenches 35, 36, 37, and 38 are filled with a conductor, such as doped polysilicon, to form the openings into trenches 35, 36, 37, and 38. In some embodiments, it may be necessary to planarize the surface of layer 33 after forming the conductor material within the openings. The method of forming the trenches 35, 36, 37 and 38 is well known to those skilled in the art. Because trenches 35 and 37 extend through region 29, they also reduce alignment tolerances and make it easier to reliably manufacture device 10. Each groove 35, 36, 37 and 38 is preferably formed as a multiply-connected domain, such as a circle or closed polygon, the perimeter of which has an opening that surrounds a portion of layer 33, and thus each groove 35, 36, 37 and 38 can be considered a multiply-connected domain. In the case of a polygon, the corners of the closed polygon are preferably rounded. Trenches 35, 36, 37 and 38 each surround that portion of layer 33 where the respective diode 14, 15, 20 and 21 will be formed. Each of trenches 35, 36, 37, and 38 may be considered a blocking structure that minimizes electrical coupling between the enclosed portion and other portions of device 10.

Referring to fig. 2 and 5, conductor trenches or conductors 60 and barrier structures such as isolation trenches 57 (fig. 2) are subsequently formed. The blocking structure isolates diodes 14, 15, and 18-21 of device 10 from conductor 60 and from doped region 63. This prevents lateral current flow from any of these diodes to conductor 60 (or region 63) through any of layers 24, 25, and 33. As will be seen further hereinafter, trench 57 acts as an isolation trench that also prevents currents Ip and In, when flowing laterally through layer 25, from bypassing the diode through which the current is expected to flow. Conductor 60 facilitates forming an electrical connection from the top surface of layer 33 to substrate 23. To form the trenches 57 and the conductors 60, another mask 79 is typically applied and patterned to form openings 80 in the mask 79, where the trenches 57 and the conductors 60 will be formed. Mask 79 is generally similar to mask 76. Opening 80 is used to form an opening that extends from the surface of layer 33, through layer 33, layer 25, layer 24, and into substrate 23. An electrolyte liner 58 is formed along the sidewalls, rather than the bottom, of the opening of trench 57 to prevent trench 57 from electrically connecting with layers 24, 25 and 33. In some embodiments, the liner 58 may also be formed in the bottom of the opening. A similar electrolyte liner 61 is formed along the sidewalls of the opening of conductor 60 rather than the bottom to prevent conductor 60 from electrically connecting with layers 24, 25 and 33. Liner 61 is not formed in the bottom of the opening so that conductor 60 can make electrical contact with substrate 23. The number of conductors 60 is selected to provide the desired resistivity of the electrical connection to the substrate 23. Those skilled in the art will recognize that liners 58 and 61 are typically formed on the sidewalls and bottom by forming a dielectric such as silicon dioxide, and a separate step may be used to remove portions of the bottom.

Referring again to fig. 2, mask 79 can then be removed and a conductor, such as doped polysilicon, formed within the openings of trenches 57 and conductor 60 to form the openings into trenches 57 and conductor 60. If doped semiconductor material is used for the conductors within trenches 57 and conductors 60, the doped semiconductor material is preferably doped to the same conductivity as substrate 23 in order to form an electrical connection thereto. However, other doping types may be used. The surface of layer 33 may have to be planarized again after the conductors have been formed in the openings. The trench 57 is formed as a multiply-connected domain (e.g., a circle or a closed polygon), and its perimeter encloses the portion of the layer 33 where the diodes 14, 15, 18, 19, 20, and 21 will be formed. In the case of a polygon, the corners are preferably rounded.

Diodes 14, 15, 20, and 21 are then formed, for example, by forming doped regions on the surface and extending into layer 33. Diode 14 includes a doped region 42 formed on the surface of layer 33 having a conductivity opposite that of layer 33. Similarly, diode 20 includes a doped region 48 formed on the surface of layer 33 having an opposite conductivity to layer 33. Diodes 14 and 20 are formed by P-N junctions between layer 33 and respective regions 42 and 48. Regions 42 and 48 are formed to extend into layer 33 and overlie region 29 so that regions 42 and 48, and thus diodes 14 and 20, are electrically connected to separate portions of region 29 to form electrical connections with diodes 18 and 19. Regions 42 and 48 are generally arranged such that the perimeter of each region 42 and 48, e.g., the perimeter formed at the surface of layer 33, is completely surrounded by respective grooves 35 and 37. Preferably, each groove 35 and 37 is a continuous groove formed around the respective zones 42 and 48. Because trenches 35 and 37 extend through layer 33, they reduce the amount of layer 33 near regions 42 and 48, thereby helping to reduce the capacitance of diodes 14 and 20. The slots 35 and 37 also reduce the interaction between the diodes 14 and 20.

Diodes 15 and 21 are each formed by a P-N junction at the interface of layer 33 and layer 25 and within the region surrounded by respective trenches 36 and 38. Doped region 49 is formed in layer 33 and surrounded by trench 38, having the same conductivity as layer 33, so as to form a contact region for electrically contacting the portion of layer 33 where diode 21 is formed. Similarly, doped region 41 is formed in layer 33 and surrounded by trench 36, having the same conductivity as layer 33, so as to form a contact region for electrically contacting the portion of layer 33 where diode 15 is formed. Regions 41 and 49 are formed on the surface of layer 33 and preferably extend about the same distance into layer 33 as regions 42 and 48. However, regions 41 and 49 do not overlie region 29. Region 41 is disposed such that a perimeter of region 41, e.g., at the surface of layer 33, is completely surrounded by groove 36, and region 49 is disposed such that a perimeter of region 49, e.g., at the surface of layer 33, is completely surrounded by groove 38. Each of the grooves 37 and 38 is preferably formed as one continuous groove.

A further doped region 63 is formed on the surface of layer 33 to cover and preferably abut conductor 60 so as to form an electrical connection with conductor trench 60. Region 63 is formed with the same conductivity as substrate 23 so that region 6 forms a conductive path through trench 60 to substrate 23. Preferably, the open top of conductor trenches 60 has the electrolyte lining removed from the portion of conductor 60 within region 63 to facilitate forming a low resistance electrical connection therebetween. Regions 42, 48, and 63 may be formed together at the same time. Regions 41 and 49 may be formed together at the same time. As can be seen from fig. 2, diode 85 is formed by substrate 23 and layer 24 and the interface therebetween, while diode 87 is formed by layers 23 and 24 and the interface therebetween.

Subsequently, a dielectric 51 may be formed on the surface of layer 33. Openings are typically formed through dielectric 51 to expose portions of regions 41, 42, 48, 49, and 63. A conductor 52 is typically applied to make electrical contact to both regions 41 and 42. Conductors 53 are typically applied to make electrical contact to regions 48, 49 and 63. Those skilled in the art will recognize that region 63 may be omitted and conductor 52 may directly contact the conductor material within conductor 60. Typically conductors 52 and 53 are then connected to respective terminals 11 and 12. Since ESD current of device 10 does not pass through the bottom surface of substrate 23, a conductor is not generally applied thereto. Thus, device 10 has two terminals that are typically connected to two terminals of a semiconductor package to form a single ESD device. In other embodiments, terminals 11 and 12 of device 10 may be connected to other devices, for example, in a multiple chip semiconductor package, to form different devices.

Referring back to fig. 1 and 2, when device 10 receives a positive ESD voltage on terminal 11 relative to terminal 12, diodes 14, 18, and 21 are forward biased, while diodes 15, 19, and 20 are reverse biased. As a result, current Ip begins to flow from terminal 11 to the anode of diode 14 at region 42, through the P-N junction of diode 14 at the interface between region 42 and layer 33, and to the cathode of diode 14 in the portion of layer 33 surrounded by trench 35. Current Ip continues through layer 33 and reaches the cathode of diode 18 at region 29 and through the P-N junction of diode 18 formed at the interface of the portion of region 29 surrounded by trench 35 and the adjoining portion of layer 25. Since this adjoining portion of layer 25 forms the cathode of diode 18, a current Ip flows into layer 25. Because substrate 23 is biased by conductor 60, substrate 23 forms a reverse-biased P-N junction at the interface between layer 25 and layer 24, which prevents current Ip from flowing into layer 24 and substrate 23. Furthermore, the slot 57 constrains the current Ip to remain within the portion of the layer 25 surrounded by the slot 57. Thus, current Ip flows through layer 25 to the cathode of diode 21 formed by the portion of layer 25 that is adjacent to the portion of layer 33 surrounded by trench 38. Current Ip flows through the P-N junction of diode 21 at the interface of layer 25 and layer 33 surrounded by trench 38 and continues to flow to the anode of diode 21 formed by layer 33. Current Ip continues through layer 33 to region 49 and terminal 12. It can be seen that layer 24 forms an isolation layer that prevents current Ip from flowing to substrate 23, while layer 25 forms a conductor layer that conducts current between diodes 18 and 21. Thus, layer 25 electrically connects the anode of diode 18 to the anode of diode 21, and layer 33 connects the cathode of diode 14 to the cathode of diode 18.

Fig. 6 is an enlarged plan view of a portion of an embodiment of device 10. Fig. 6 shows device 10 without dielectric 51 and conductors 52 and 53 to illustrate the surface of layer 33. For the embodiment of fig. 6, device 10 includes two diodes 15 and two diodes 21. The plan view shows the multiple communication domain configuration slots 35, 36, 37, 38, and 57. For example, the grooves 35, 37, and 57 are formed in a closed polygon shape having rounded corners, and the grooves 36 and 38 are formed in a circle. Conductor 60 shows that conductor 60 is not formed into a closed polygon, but at one end of the structure of device 10, so as to form a contact with substrate 23. Typically, conductor 60 is formed proximate to diodes 20 and 21 so as to form conductor 53 in electrical contact with conductor 60 and all of diodes 20 and 21.

When device 10 receives a negative voltage on terminal 11 relative to terminal 12, diodes 20, 19, and 15 are forward biased, while diodes 14, 18, and 21 are reverse biased. As a result, current In begins to flow from terminal 12 to the anode of diode 20 at region 48, through the P-N junction of diode 20 at the interface between region 48 and layer 33, and to the cathode of diode 20 In the portion of layer 33 surrounded by trench 37. Current In continues through layer 33 and reaches the cathode of diode 19at region 29 and through the P-N junction of diode 19 formed at the interface of the portion of region 29 surrounded by trench 37 and the adjoining portion of layer 25. Since this adjoining portion of layer 25 forms the cathode of diode 19, a current In flows into layer 25. Substrate 23 is again biased by conductor 60 and forms a reverse biased P-N junction at the interface between layer 25 and layer 24, which prevents current In from flowing into layer 24 and substrate 23. Furthermore, the trench 57 constrains the current In to remain within the portion of the layer 25 surrounded by the trench 57. Thus, current In flows through layer 25 to the cathode of diode 15 formed by the portion of layer 25 that is adjacent to the portion of layer 33 surrounded by trench 36. Current In flows through the P-N junction of diode 15at the interface of layer 25 and the portion of layer 33 surrounded by trench 36 and continues to flow to the anode of diode 15 formed by layer 33. Current In continues through layer 33 to region 41 and terminal 11. Layer 24 forms an isolation layer that prevents current In from flowing to substrate 23, while layer 25 forms a conductor layer that conducts current between diodes 20 and 15. Thus, layer 25 electrically connects the anode of diode 15 to the anode of diode 19, and layer 33 connects the cathode of diode 20 to the cathode of diode 19. Note that for positive and negative ESD discharge events, ESD current flows into and out of the top surfaces of layers 25 and 33. ESD current does not flow or even into the substrate 23. Furthermore, it can be seen that the trench 57 limits the currents Ip and In to flow through the portion of the layer 25 surrounded by the trench 57. In addition, trench 57 prevents shorting of formation region 63 through layer 33 to layer 24. Such a short will short terminal 12 to the anodes of diodes 21 and 19.

The sheet resistivity or Gummel number of layer 24 is controlled by the carrier concentration within layer 24 and the thickness of layer 24. Controlling the sheet resistivity of layer 24 relative to the sheet resistivity of layer 25 helps prevent allowing a parasitic bipolar formation by layers 25, 24 and substrate 23A transistor. Preferably, the carrier concentration of layer 24 is about 1E15atoms/cm³And 1E17atoms/cm³And a thickness of about 2 to 20 microns. In one exemplary embodiment, layer 25 is formed with a thickness of about 2 to 10 microns and about 1E19atoms/cm³So as to facilitate efficient carrier conduction between diodes 18 and 21. Due to these doping relationships, diodes 85 and 87 generally do not conduct current in this embodiment of device 10.

Fig. 7 is a graph showing the V-I characteristic of device 10. The abscissa represents the voltage applied to terminal 11 relative to terminal 12, and the ordinate represents the current through device 10. Curve 67 shows the V-I characteristic. Because layer 24 is formed to prevent the enablement of parasitic bipolar transistors between substrate 23 and layers 24 and 25, the V-I characteristic of device 10 has a sharp knee voltage and is substantially symmetrical for positive and negative ESD discharge events, as shown by curve 68.

In addition, the structure of device 10 is formed with low capacitance. This low capacitance allows for fast data transmission on the data transmission line to which the device 10 is connected when the device 10 is not conducting, without the capacitance of the device 10 interfering with the data transmission. In normal operation, device 10 is biased to a normal operating voltage, for example, a voltage between about 1 volt (1V) and the zener voltage of diode 18 or 19, for example, by applying about 1 volt (1V) to terminal 11 and a ground reference voltage to terminal 12. Due to the characteristics of device 10 described below, the capacitance of device 10 remains low when the voltage between terminals 11 and 12 varies over this normal operating voltage. However, the capacitance of an ESD device is typically specified at zero volts applied across the device. This zero voltage condition is commonly referred to as a zero bias condition. As will be seen further hereinafter, the low capacitance feature of device 10 described below results in a very low capacitance value for diodes 14, 15, 20, and 21 in this zero bias condition. Because there are two parallel paths between terminals 11 and 12, the capacitance value of each path is the result of the addition of the capacitances in each path. The first path comprises the capacitance of the diodes 14, 18 and 21 in series. Since the capacitance of the series capacitor is less than the capacitance of the smallest capacitor, then the capacitance of the first path is less than the capacitance of any of the diodes 14, 18 or 21. The device 10 is formed such that the zero bias capacitance of the diodes 14 and 21 is very small, as will be seen further below. Similarly, the capacitance of the second path including diodes 20, 19 and 15 is also very small. The sum of the two paths forms the small zero-bias capacitance of device 10.

Fig. 8 is a graph illustrating a carrier concentration profile of a portion of one exemplary embodiment of device 10. The abscissa represents the depth from the surface of layer 33 into device 10, while the ordinate represents an increasing value of the carrier concentration. Plot 68 illustrates the carrier concentration of device 10 that results from a positive bias applied from terminal 11 to terminal 12 (e.g., via a positive ESD event). The description refers to fig. 1, 2 and 7. To facilitate formation of device 10 with sharp knee voltages, preferred embodiments of layer 25 are formed with P-type conductivity, and typically have about 1X10¹⁹atoms/cm³And preferably at about 1X10¹⁹And 1X10²¹atoms/cm³With the doping concentration in between. Semiconductor region 29 is formed as an N-type region having about 1X10 for a clamping voltage of about 2 to 10 volts¹⁹atoms/cm³And preferably at about 1X10¹⁹And 1X10²¹atoms/cm³Peak doping concentration in between. To facilitate the formation of a low zero bias voltage for device 10, the preferred embodiment of layer 24 (fig. 2) is formed with N-type conductivity and typically has about 1X10¹⁶atoms/cm³And preferably at about 1X10¹⁵And 1X10¹⁷atoms/cm³With the doping concentration in between. In addition, the thickness of region 29 is preferably between about 1 and 3 microns. Due to the high doping concentration of region 29 and layer 25, when device 10 receives a positive voltage from terminal 11 to terminal 12, the depletion region is limited to a small region within region 29 and layer 25 near the interface of layer 25. This high concentration of carriers and dopants provides the zener diodes 18 and 19 with a very sharp transition or knee voltage and allows very precise control of the breakdown voltage or zener voltage of the diodes 18 and 19. The breakdown voltage or zener voltage of diodes 18 and 19 may passThe carrier concentration or carrier distribution of region 29 and/or layer 25 is varied to adjust. This allows for precise control of the breakdown voltage for a particular application, for example for a breakdown voltage application of 5 or 12 or 24 volts.

Layer 33 is preferably formed with a lower peak doping concentration that is at least an order of magnitude less than the doping concentration of region 29, and typically at about 1E13 and 1E17atoms/cm³In the meantime.

The peak doping concentration of regions 42 and 48 is typically greater than the peak doping concentration of layer 33 and preferably about equal to the peak doping concentration of layer 25. Regions 42 and 48 are generally formed to extend a distance of no more than about 2 microns, and preferably about 0.1 to 2 microns, from the surface into layer 33. The widely different doping concentrations between region 42 and layer 33 and also between region 48 and layer 33 and the shallow depth of regions 42 and 48 help provide very little zero bias capacitance to the respective diodes 14 and 20. This very small zero bias capacitance of diodes 14 and 20 contributes to the small zero bias capacitance of device 10 as previously shown. The capacitance of each diode 14, 18, 20, and 21 at zero bias is typically less than about 0.5 picofarads, and the equivalent series capacitance of the diodes 14, 18, 20, and 21 forms the capacitance of the device 10 of about 0.2 picofarads, and preferably no greater than about 0.01 picofarads.

Because trenches 36 and 38 extend through layer 33, they reduce the area of the P-N junction formed between the portions of layers 25 and 33 located below respective regions 41 and 49, thereby helping to reduce the capacitance of respective diodes 15 and 21. In a preferred embodiment, the peak doping concentration of regions 41 and 49 is greater than the peak doping concentration of layer 33 and preferably about equal to the peak doping concentration of layer 29.

Regions 42 and 48 are typically separated from region 29 by a distance that helps to minimize the capacitance of diodes 15 and 21. The spacing is typically about 2 to 20 microns. The portions of layer 33 between regions 42 and 29 and between regions 48 and 29 form the drift regions of respective diodes 14 and 20. The drift region of layer 33 is at least about 2 microns thick to reduce the formation of parasitic transistors and to ensure that device 10 does not operate in the punch-through operating region. As can be seen, device 10 generally has no doped region that has the same conductivity as layer 25 and is located between diode 14 and region 29 and thus between regions 42 and 29.

The capacitance of device 10 at zero bias is typically less than about 0.5 picofarads and the equivalent series capacitance of device 10 is about 0.3 picofarads and preferably no greater than about 0.1 picofarads.

When device 10 receives a positive voltage on terminal 11 relative to terminal 12, diodes 20 and 15 are reverse biased, while diodes 14 and 21 are forward biased. The carrier density in layer 33 is further reduced from the zero bias condition due to the depletion region formed by the reverse bias, which helps to further reduce the equivalent series capacitance of device 10. This allows the capacitance to be low even as the bias voltage increases. In fact, device 10 has a substantially constant capacitance, unlike a single diode. Due to the symmetry of device 10, the capacitance pair is constant for both positive and negative voltages applied between terminals 11 and 12. This unchanged capacitance profile persists for voltages below the zener voltage of device 10. In contrast, a single diode has a low capacitance under reverse bias, a relatively high capacitance at zero voltage, and a capacitance that increases by the square of the forward bias.

When electrostatic discharge occurs, there are typically large voltage and current spikes that occur over a short period of time. Typically, the peak current and peak voltage occur over a period of a few nanoseconds, typically less than 2 nanoseconds (2 nsec.), and may last only about 1 nanosecond (1 nsec.). The current typically decreases to a plateau for another time interval, typically about 20 nanoseconds, and slowly decreases for another 20 to 40 nanoseconds. The peak value of the current may be between 1 and 30 amperes (amp) and the peak voltage may be between 2000 and 30000 volts. The size and response time of the elements of device 10 are preferably configured to react to voltage and conduct peak current during the time interval of peak voltage. During an ESD event between terminals 11 and 12, diodes 14 and 21 are connected in series, or diodes 15 and 20 are connected in series, the effective capacitance being the total series capacitance. Because the series capacitance results in a capacitance that is less than the minimum capacitance, the low capacitance ensures that the capacitance of device 10 is low enough for device 10 to react to ESD events and conduct current during peak ESD voltages and currents.

Fig. 9 is a graph illustrating current-voltage (I-V) characteristics of an alternative embodiment of device 10. The abscissa represents the voltage applied to terminal 12 relative to terminal 11, and the ordinate represents the current through the alternative embodiment of device 10. Curve 88 shows the I-V characteristic. In this alternative embodiment of device 10, the sheet resistivity of layer 24 is increased to facilitate the activation of parasitic bipolar transistors that may be formed between substrate 23 and layers 25 and 24. The parasitic bipolar transistor is allowed to activate to form a current flow path from layer 25 to substrate 23 and to allow current to flow from terminal 12 to the anodes of diodes 15 and 21. Enabling the parasitic bipolar transistor changes the V-I characteristic and forms the device 10 of this alternative embodiment with a snap-back and functions similarly to a thyristor. Note that at this doping concentration of layer 24, when the voltage difference between terminals 11 and 12 increases, the parasitic bipolar transistor is activated and shorts layer 25 to substrate 23, thereby allowing current to flow from layer 25 to substrate 23 and through conductor 60 to terminal 12, resulting in a snapback characteristic.

In some applications, it may be advantageous to be able to withstand large surge currents. Device 85 will provide high inrush current and ESD protection through the bipolar transistor due to the snapback characteristics. Note that the parasitic bipolar transistor is formed on the side of the terminal 12 that is shorted to the substrate 23 through the conduction groove 60. This alternative embodiment of device 10 is therefore asymmetric, since snapback is only on the positive side of the current-voltage characteristic, terminal 12 being designated as the anode. In this configuration the cathode side is still blocking.

Fig. 10 schematically illustrates an embodiment of a portion of an electrostatic discharge (ESD) protection device or ESD device 90, which is another alternative embodiment of device 10 described in fig. 1 through 9. Device 90 is similar to device 10 except that the sheet resistivity of layer 29 or layer 33 is greater in order to increase gain in the base region formed by layers 29 and 33 and to facilitate the activation of another parasitic bipolar transistor that may be formed between region 42, layer 33 (and region 29) and layer 25. Enabling the parasitic bipolar transistor changes the V-I characteristic and causes device 90 to form a snap-back direction between zener diode 18 and diode 14, causing device 10 to function similarly to a thyristor.

Fig. 11 is a graph showing the current-voltage I-V characteristics of the device 90. The abscissa represents the voltage applied to terminal 12 relative to terminal 11, and the ordinate represents the current through device 85. Curve 94 shows the I-V characteristic. Note that at this doping concentration of layer 33, when the voltage difference between terminals 11 and 12 increases, the parasitic bipolar transistor is activated and shorts layer 33 to layer 24, and thus to substrate 23, thereby allowing current to flow from terminal 12 through conductor 60 to substrate 23, and then through layers 25 and 24 to layer 33 and terminal 11. As can be seen from curve 94, device 90 is a symmetric device and has snap-reversals on both sides of the I-V characteristic.

Those skilled in the art will recognize that both layers 24 and 23 and layers 24 and 29 may be doped to implement two parasitic bipolar transistors. The pair of two current directions forms a symmetrical bi-directional device with fast reverse characteristics, similar to a bi-directional thyristor.

Fig. 12 schematically illustrates an embodiment of a portion of an electrostatic discharge (ESD) protection device or ESD device 100, which is an alternative embodiment of device 10 or 90 described in the description of fig. 9-11. Device 100 is similar to devices 10 and 90 except that device 100 has a single diode 103 instead of the back-to-back diodes 85, 87, and 91 of respective devices 10 and 90. Configuring device 100 to have diode 103 connected in parallel with diode 15 and in parallel with diode 21 improves the symmetry of the V-I characteristic of device 100.

Fig. 13 shows a cross-sectional view of a portion of ESD device 100. Device 100 is similar to devices 10 and 90 except that device 100 has a substrate 105, substrate 105 having the same doping type as layer 24. Thus, in a preferred embodiment, both substrate 105 and layer 104 are N-type. Because substrate 105 and layer 24 are of the same doping type, there is no P-N junction between substrate 105 and layer 24, and thus diode 103 is a single diode formed by the P-N junction between layer 24 and layer 25. The doping concentration of substrate 105 is substantially the same as the doping concentration of substrate 23. Forming the device 100 with a single diode 103 improves the symmetry of the device 100.

In view of all of the above, it is evident that a new device and method is disclosed. Included, among other features, is forming an ESD device having an isolation layer formed between a diode of the ESD device and a substrate on which the device is formed. The isolation layer isolates the diode from the substrate and facilitates forming the ESD device as a two terminal device. Forming the conductor layer underneath the diode facilitates forming a lateral current path to interconnect the anodes of the diode together. Furthermore, forming a blocking structure around each diode forces lateral current to appear in the conductor layer and prevents lateral current that may short the diodes together. Forming vertical conductors to facilitate forming electrical connections to the substrate facilitates configuring the device to operate from both terminals. Another blocking structure is formed to isolate the diode from the vertical conductor, helping to prevent shorting from the diode to the terminals of the ESD device. In addition, ESD devices typically have a highly doped P-type substrate, a lightly doped N-type layer forming a diode, and a highly doped N-type layer disposed adjacent to a portion of the lightly doped N-type layer to form a zener diode. Also included is a highly doped P-type layer overlying the highly doped N-type layer to form a P-N junction diode. The doping concentration and thickness result in an ESD device that can react to ESD events in less than 1 nanosecond (1 nsec.).

While the subject matter of the present invention has been described with specific preferred embodiments, it is evident that many alternatives and variations will be apparent to those skilled in the semiconductor arts. For example, all doping types may be reversed. Isolation layer 24 may be any type of layer that provides isolation between layer 25 and substrate 33, including a semiconductor dielectric, such as silicon dioxide. Although semiconductor region 29 is described as being formed by doping a portion of an epitaxial layer, region 29 may be formed by various well-known techniques. Furthermore, the doping described for isolation layer 24 may be replaced by other techniques that sufficiently suppress or reduce carrier lifetime within layer 24 to inhibit enabling the bipolar transistor. Although the device is described herein as being formed on a silicon substrate, one skilled in the art will recognize that other semiconductor materials may be used, including gallium arsenide, silicon carbide, gallium nitride, and other semiconductor materials. Moreover, the word "connected" is used throughout for clarity of description, but is intended to have the same meaning as the word "coupled". Accordingly, "connected" should be interpreted to include direct connections or indirect connections.

Claims (3)

1. A method of forming an ESD device, comprising:

forming a first semiconductor layer overlying the semiconductor substrate;

forming a plurality of diodes with at least a portion of each diode within the first semiconductor layer;

forming a plurality of first blocking structures extending through the first semiconductor layer, wherein separate blocking structures of the plurality of first blocking structures surround a perimeter of each diode of the plurality of diodes to inhibit current flow laterally through the first semiconductor layer between the plurality of diodes; and

forming a conductor extending from within the first semiconductor layer into the semiconductor substrate.

2. The method of claim 1, further comprising: forming a second barrier structure extending through the first semiconductor layer and into the semiconductor substrate, wherein a perimeter of the second barrier structure surrounds the plurality of diodes and surrounds the plurality of first barrier structures, wherein the conductor is outside the perimeter of the second barrier structure.

3. The method of claim 1, further comprising: a conductor layer formed below the first semiconductor layer, and further comprising: an isolation layer formed between the conductor layer and the semiconductor substrate; and

the semiconductor substrate, the isolation layer, and the first semiconductor layer are formed to have a first conductivity type, and the conductor layer is formed to have a second conductivity type.