HK1190834A - Apparatus and methods for envelope tracking - Google Patents

Description

Apparatus and method for envelope tracking

Technical Field

Embodiments of the present invention relate to electronic systems, and in particular, to Radio Frequency (RF) electronic devices.

Background

Power amplifiers may be used to boost the power of RF signals having relatively low power. The boosted RF signal can then be used for various purposes, including driving the antenna of the transmitter.

A power amplifier may be included in the mobile phone to amplify the RF signal for transmission. For example, in mobile phones with Time Division Multiple Access (TDMA) architectures, such as those found in the global system for mobile communications (GSM), Code Division Multiple Access (CDMA), and wideband code division multiple access (W-CDMA) systems, power amplifiers may be used for RF signal amplification. Managing the amplification of RF signals is important because the desired transmit power level may depend on how far away the user is from the base station and/or mobile environment. A power amplifier may also be employed to help adjust the power level of the RF signal over time to prevent signal interference from being transmitted during the assigned receive timeslot.

Power consumption of the power amplifier, and thus efficiency, can be an important consideration. One technique for reducing the power consumption of a power amplifier is envelope tracking, in which the voltage level of the power supply of the power amplifier is varied or controlled with respect to the envelope of the RF signal. Therefore, when the envelope of the RF signal increases, the voltage supplied to the power amplifier may be increased. Likewise, when the envelope of the RF signal decreases, the voltage supplied to the power amplifier may be decreased to reduce power consumption.

There is a need for an improved power amplifier system. Furthermore, there is a need for an improved envelope tracker for controlling the supply voltage of a power amplifier.

Disclosure of Invention

In certain embodiments, the present disclosure relates to a power amplifier system, comprising: a power amplifier configured to amplify a Radio Frequency (RF) signal; and an envelope tracker configured to generate a power amplifier supply voltage of the power amplifier using an envelope of the RF signal. The envelope tracker comprises: the apparatus includes a battery voltage generator configured to generate a battery voltage, a buck converter configured to generate a buck voltage from the battery voltage, and a digital-to-analog converter (DAC) module configured to adjust a magnitude of the buck voltage based on an envelope of an RF signal to generate a power amplifier supply voltage.

In various embodiments, the DAC module includes a push DAC and a pull DAC, the push DAC configured to increase the power amplifier supply voltage when the envelope of the RF signal increases and the pull DAC configured to decrease the power amplifier supply voltage when the envelope of the RF signal decreases.

In many embodiments, the power amplifier system further comprises a digital filter configured to receive the envelope of the RF signal and the power amplifier supply voltage and to generate a filtered envelope signal by filtering the envelope of the RF signal based at least in part on the power amplifier supply voltage.

According to several embodiments, the power amplifier system further comprises a digital shaping and delay module configured to receive the filtered envelope signal and to generate a shaped envelope signal.

In certain embodiments, the power amplifier system further comprises a thermometer decoder configured to receive the shaped envelope signal and decode the shaped envelope signal to generate a plurality of push DAC control signals and a plurality of pull DAC control signals, the plurality of push DAC control signals and the plurality of pull DAC control signals being encoded in thermometer coding.

According to many embodiments, the pull DAC comprises a plurality of NMOS current sources and the push DAC comprises a plurality of PMOS current sources. A plurality of NMOS current sources are disposed between the power amplifier supply voltage and the power low supply voltage, and a plurality of PMOS current sources are disposed between the battery voltage and the power amplifier supply voltage. The gates of the plurality of NMOS current sources and the gates of the plurality of PMOS current sources are controlled by the plurality of pull DAC control signals and the plurality of push DAC control signals, respectively.

In various embodiments, the number of the plurality of NMOS current sources and the number of the plurality of PMOS current sources is each greater than or equal to sixteen.

In some embodiments, the power amplifier system further comprises a ripple control module configured to receive the filtered envelope signal and to generate the first buck control signal and the second buck control signal using the filtered envelope signal.

In many embodiments, the buck converter includes an NMOS transistor and a PMOS transistor, each of which includes a gate, a source, and a drain. Gates of the NMOS and PMOS transistors are electrically connected to the first and second buck control signals, respectively, sources of the NMOS and PMOS transistors are electrically connected to the power low supply voltage and the battery voltage, respectively, and drains of the NMOS and PMOS transistors are electrically connected together.

According to several embodiments, the buck converter further comprises an inductor having a first end electrically connected to the supply voltage of the power amplifier and a second end electrically connected to the drains of the NMOS and PMOS transistors.

In various embodiments, the power amplifier system further comprises a transceiver for providing an envelope of the RF signal to the envelope tracker and for providing the RF signal to the power amplifier.

In some embodiments, the power amplifier includes a bipolar transistor having an emitter, a base, and a collector, the base configured to receive the RF signal, the emitter electrically connected to the power low supply voltage, and the collector configured to generate an amplified version of the RF signal.

In certain embodiments, the present disclosure relates to a method of envelope tracking in a power amplifier system. The method includes providing a power amplifier for amplifying a Radio Frequency (RF) signal and providing an envelope tracker for generating a supply voltage of the power amplifier using an envelope of the RF signal, the envelope tracker including a buck converter and a digital-to-analog (DAC) module. The method also includes generating a buck voltage from the battery voltage using a buck converter, and adjusting the buck voltage using a DAC module to generate a supply voltage, an amplitude of the adjusted voltage being based on an envelope of the RF signal.

In various embodiments, the digital-to-analog converter includes a push DAC and a pull DAC.

In some embodiments, adjusting the buck voltage using the DAC module comprises: the supply voltage is increased using a push DAC when the envelope of the RF signal increases and decreased using a pull DAC when the envelope of the RF signal decreases.

In many embodiments, the method further comprises filtering the envelope of the RF signal using a digital filter.

According to a number of embodiments, the method further comprises delaying the filtered envelope signal before providing the filtered envelope signal to the DAC module.

In some embodiments, the method further comprises delaying the filtered envelope signal prior to providing the filtered envelope signal to the DAC module, including determining a duration of the delay based on a difference in delay between the DAC module and the buck converter.

In some embodiments, the method further comprises shaping the filtered envelope signal to generate a shaped envelope signal.

In various embodiments, the method further includes converting the shaped envelope signal to a push DAC control signal and a pull DAC control signal, the push DAC control signal and the pull DAC being thermometer coded.

Drawings

Fig. 1 is a schematic diagram of a power amplifier module for amplifying a Radio Frequency (RF) signal.

Fig. 2 is a schematic block diagram of an example wireless device that may include one or more of the power amplifier modules of fig. 1.

Fig. 3A is a schematic block diagram of one example of a power amplifier system including an envelope tracking system.

Fig. 3B is a schematic block diagram of another example of a power amplifier system including an envelope tracking system.

Fig. 4A-4C show three examples of supply voltage versus time.

Fig. 5 is a schematic block diagram of another example of a power amplifier system including an envelope tracking system.

FIG. 6 is a schematic diagram of one embodiment of an envelope tracking system.

FIG. 7 is a schematic diagram of another embodiment of an envelope tracking system.

Fig. 8 is a flow chart illustrating a method for generating a power amplifier supply voltage according to one embodiment.

FIG. 9 is a schematic diagram of one embodiment of a pull-type digital-to-analog converter (DAC).

Fig. 10 is a graph of one example of input power versus efficiency for various power amplifier supply voltages.

Fig. 11 is a graph of an example of an input envelope signal versus a shaped envelope signal.

Fig. 12 is a graph of one example of power versus frequency for an envelope tracker.

Detailed Description

Headings (if any) provided herein are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.

An apparatus and method for envelope tracking is disclosed herein. In certain implementations, an envelope tracker is provided for generating a supply voltage for the power amplifier based on an envelope of an RF signal amplified by the power amplifier. The envelope tracker includes a buck converter, and a push-pull digital-to-analog converter (DAC). The buck converter may generate a buck or step-down voltage based on the low frequency component of the envelope signal, while the push-pull DAC may adjust the DC voltage based on the high frequency component of the envelope signal to generate the supply voltage. For example, the push-pull DAC may be controlled by using a digital signal generated by filtering, shaping and/or delaying the envelope signal. Employing a combination of a buck converter and a push-pull DAC may reduce design complexity and/or improve overall power efficiency of the envelope tracking system relative to schemes employing a DC-to-DC converter and a class AB amplifier, which typically require analog bandpass filters for noise reduction and/or analog delay elements for output alignment.

Overview of a Power Amplifier System

Fig. 1 is a schematic diagram of a power amplifier module for amplifying a Radio Frequency (RF) signal. The illustrated Power Amplifier Module (PAM) 10 may be configured to amplify an RF signal IN to generate an amplified RF signal OUT. As described herein, a power amplifier module may include one or more power amplifiers.

Fig. 2 is a schematic block diagram of an example wireless or mobile device 11 that may include one or more of the power amplifier modules of fig. 1. The wireless device 11 may include an envelope tracker that implements one or more features of the present disclosure.

The example wireless device 11 depicted in fig. 2 may represent a multi-band and/or multi-mode device, such as a multi-band/multi-mode mobile phone. By way of example, the global system for mobile communications (GSM) standard is a model of digital cellular communications utilized in many parts of the world. GSM mode mobile phones can operate in one or more of four frequency bands: 850MHz (approximately 824 + 849MHz for transmission, 869 + 894MHz for reception), 900MHz (approximately 880 + 915MHz for transmission, 925 + 960MHz for reception), 1800MHz (approximately 1710 + 1785MHz for transmission, 1805 + 1880MHz for reception) and 1900MHz (approximately 1850 + 1910MHz for transmission, 1930 + 1990MHz for reception). Changes in the GSM frequency band and/or regional/national implementations are also utilized in different parts of the world.

Code Division Multiple Access (CDMA) is another standard that may be implemented in mobile telephone devices. In some implementations, CDMA devices may operate in one or more of the 800MHz, 900MHz, 1800MHz, and 1900MHz bands, while some W-CDMA and Long Term Evolution (LTE) devices may operate over, for example, approximately 22 radio frequency spectrum bands.

One or more features of the present disclosure may be implemented in the above example modes and/or frequency bands and in other communication standards. For example, 3G, 4G, LTE and LTE-advanced are non-limiting examples of such standards.

In some embodiments, the wireless device 11 may include a switch 12, a transceiver component 13, an antenna 14, a power amplifier 17, a control component 18, a computer readable medium 19, a processor 20, a battery 21, and an envelope tracker 30.

The transceiver component 13 may generate RF signals for transmission via the antenna 14. In addition, the transceiver component 13 may receive incoming RF signals from the antenna 14.

It will be appreciated that various functions associated with the transmission and reception of RF signals may be carried out by one or more components collectively represented in fig. 2 as transceiver 13. For example, a single component may be configured to provide both transmit and receive functionality. In another example, the transmit and receive functions may be provided by separate components.

Similarly, it will be appreciated that various antenna functions associated with the transmission and reception of RF signals may be implemented by one or more components collectively represented in fig. 2 as antenna 14. For example, a single antenna may be configured to provide both transmit and receive functions. In another example, the transmit and receive functions may be provided by separate antennas. In yet another example, different antennas may be provided for different frequency bands associated with wireless device 11.

In fig. 2, one or more output signals from transceiver 13 are depicted as being provided to antenna 14 via one or more transmission paths 15. In the illustrated example, the different transmission paths 15 may represent output paths associated with different frequency bands and/or different power outputs. For example, the two example power amplifiers 17 shown may represent amplification associated with different power output configurations (e.g., low power output and high power output), and/or amplification associated with different frequency bands. Although fig. 2 illustrates a configuration using two transmission paths 15, the wireless device 11 may include more or fewer transmission paths 15.

In fig. 2, one or more detected signals from the antenna 14 are depicted as being provided to the transceiver 13 via one or more receive paths 16. In the illustrated example, the different receive paths 16 may represent paths associated with different frequency bands. For example, the four example paths 16 shown may represent quad-band capabilities provided to certain wireless devices. Although fig. 2 illustrates a configuration using four receive paths 16, more or fewer receive paths 16 may be employed in wireless device 11.

To facilitate switching between receive and transmit paths, the switch 12 may be configured to electrically connect the antenna 14 to a selected transmit or receive path. Thus, the switch 12 may provide a number of switching functions associated with the operation of the wireless device 11. In some embodiments, the switches 12 may include a number of switches configured to provide functionality associated with, for example, switching between different frequency bands, switching between different power modes, switching between transmit and receive modes, or some combination thereof. The switch 12 may also be configured to provide additional functionality including filtering and/or duplexing of signals.

Fig. 2 illustrates that in some embodiments, a control component 18 may be provided for controlling various control functions associated with the operation of the switch 12, the power amplifier 17, the envelope tracker 30, and/or other operational component(s). Non-limiting examples of the control assembly 18 are described in more detail herein.

In some embodiments, processor 20 may be configured to facilitate implementation of the various processes described herein. For purposes of description, embodiments of the present disclosure may also be described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the actions specified in the flowchart and/or block diagram block or blocks.

In certain embodiments, these computer program instructions may also be stored in a computer-readable memory 19 that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the action specified in the flowchart and/or block diagram block or blocks. The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operations to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the actions specified in the flowchart and/or block diagram block or blocks.

The illustrated wireless device 11 also includes an envelope tracker 30 that may be used to generate the supply voltage for the one or more power amplifiers 17. For example, the envelope tracker 30 may be configured to vary or control the supply voltage provided to the power amplifier 17 based on the envelope of the RF signal to be amplified.

The envelope tracker 30 may be electrically connected to the battery 21. The battery 21 may be any battery suitable for use in the wireless device 11, including, for example, a lithium ion battery. As will be described in more detail below, by controlling the magnitude of the supply voltage provided to the power amplifier, the power consumption of the battery 21 may be reduced, thereby improving the performance of the wireless device 11. The envelope signal may be provided from the transceiver 13 to an envelope tracker of the envelope tracker 30. However, the envelope may be determined in other ways. For example, the envelope may be determined by detecting the envelope from the RF signal using any suitable envelope detector.

Fig. 3A is a schematic block diagram of one example of a power amplifier system 25 including an envelope tracking system. The illustrated power amplifier system 25 includes a switch 12, a transceiver 13, an antenna 14, a battery 21, a delay element 29, a power amplifier or PA32, and an envelope tracker 30.

Transceiver 13 may generate an RF signal and may provide the RF signal to power amplifier 32. The power amplifier 32 may amplify the RF signal and provide the amplified RF signal to the input of the switch 12, which may be as previously described. The switch 12 may have an output electrically connected to the antenna 14. Although not shown in this figure, those of ordinary skill in the art will appreciate that additional power amplifiers may be electrically connected to the antenna 14 through the switch 12 to help provide the desired number of transmission paths.

The transceiver 13 may provide the envelope of the RF signal to the envelope tracker 30. In some implementations, a delay element 29 may be included at the input of the envelope tracker 30 to compensate for the difference in delay between the path of the RF signal through the power amplifier 32 and the path of the envelope signal through the envelope tracker 30. The envelope tracker 30 may receive the battery voltage V from the battery 21_BATTAnd may use the envelope signal to generate a power amplifier supply voltage V for power amplifier 32 that varies with respect to the envelope signal_{CC_PA}。

Although the transceiver 13 is illustrated as providing the envelope signal to the envelope tracker 30, the envelope signal may be generated in any suitable manner. For example, an envelope detector 31 may be provided, and the envelope detector 31 is used to generate an envelope signal from the RF signal.

Fig. 3B is a schematic block diagram of another example of a power amplifier system 26 that includes an envelope tracking system. The illustrated power amplifier system 26 includes a switch 12, an antenna 14, a battery 21, a directional coupler 24, an envelope tracker 30, a power amplifier 32, and a transceiver 33. The illustrated transceiver 33 includes a baseband processor 34, an envelope shaping block 35, a digital-to-analog converter (DAC) 36, an I/Q modulator 37, a mixer 38, and an analog-to-digital converter (ADC) 39.

The baseband signal processor 34 may be used to generate I and Q signals, which may be used to represent sine waves or signals of desired amplitude, frequency, and phase. For example, the I signal may be used to represent the in-phase component of a sine wave, and the Q signal may be used to represent the quadrature component of a sine wave, which may be an equivalent representation of a sine wave. In some implementations, the I and Q signals may be provided to I/Q modulator 37 in a digital format. The baseband processor 34 may be any suitable processor configured to process baseband signals. For example, baseband processor 34 may include a digital signal processor, a microprocessor, a programmable core, or any combination thereof. Further, in some implementations, two or more baseband processors 34 may be included in the electronic system 26.

I/Q modulator 37 may be configured to receive the I and Q signals from baseband processor 34 and process the I and Q signals to generate an RF signal. For example, I/Q modulator 37 may include a DAC configured to convert the I and Q signals to an analog format, a mixer for upconverting the I and Q signals to a radio frequency, and a signal combiner for combining the upconverted I and Q signals into an RF signal suitable for amplification by power amplifier 32. In some implementations, I/Q modulator 37 may include one or more filters configured to filter the frequency content of the signals processed therein.

An envelope shaping block 35 may be used to convert envelope or amplitude data associated with the I and Q signals into shaped envelope data. Shaping the envelope data from baseband processor 34 may help enhance the performance of power amplifier system 26 by, for example, adjusting the envelope signal to optimize the linearity of power amplifier 32 and/or achieve a desired gain compression of power amplifier 32. In some implementations, the envelope shaping block 35 is a digital block and the DAC36 is used to convert the shaped envelope data into an analog envelope signal suitable for use by the envelope tracker 30. However, in other implementations, DAC36 may be omitted to facilitate providing the digital envelope signal to envelope tracker 30 to assist in further processing of the envelope signal by envelope tracker 30.

The envelope tracker 30 may receive the envelope signal from the transceiver 33 and the battery voltage V from the battery 21_BATTAnd may use the envelope signal to generate a power amplifier supply voltage V for power amplifier 32 with respect to envelope changes_{CC_PA}. Power amplifier 32 may receive an RF signal from I/Q modulator 37 of transceiver 33 and may pass an RF signal through an onThe switch 12 provides the amplified RF signal to the antenna 14.

Directional coupler 24 may be located between the output of power amplifier 32 and the input of switch 12, allowing output power measurement of power amplifier 32 without including the insertion loss of switch 12. The sense output signal from the directional coupler 24 may be provided to a mixer 38, which mixer 38 may multiply the sense output signal with a reference signal of a controlled frequency to adjust the frequency of the sense output signal down. The modulated signal may be provided to ADC39 and ADC39 may convert the modulated signal to a digital format suitable for processing by baseband processor 34. By including a feedback path between the output of power amplifier 32 and baseband processor 34, baseband processor 34 may be configured to dynamically adjust the I and Q signals and/or envelope data associated with the I and Q signals to optimize operation of power amplifier system 26. Configuring power amplifier system 26 in this manner may help control the Power Added Efficiency (PAE) and/or linearity of power amplifier 32, for example.

Fig. 4A-4C show three examples of power amplifier supply voltage versus time.

In fig. 4A, a graph 47 illustrates the voltage of the RF signal 41 and the voltage of the power amplifier supply 43 versus time. The RF signal 41 has an envelope 42.

It is important that the voltage of the power amplifier supply 43 is greater than the voltage of the RF signal 41. For example, providing a supply voltage to the power amplifier having a smaller amplitude than the amplitude of the RF signal 41 may clip the RF signal, thereby creating signal distortion and/or other problems. Therefore, it is important that the power amplifier supply 43 has a voltage greater than the voltage of the envelope 42. However, because the region between the power amplifier supply 43 and the envelope 42 of the RF signal 41 in the graph 47 may represent lost energy (which may reduce battery life and increase heat generated in the mobile device), it may be desirable to reduce the difference in voltage between the power amplifier supply 43 and the envelope 42.

In fig. 4B, a graph 48 illustrates the voltage of the RF signal 41 and the voltage of the power amplifier supply 44 versus time. In contrast to the power amplifier supply 43 of fig. 4A, the power amplifier supply 44 of fig. 4B varies or changes with respect to the envelope 42 of the RF signal 41. The region between power amplifier supply 44 and envelope 42 in fig. 4B is smaller than the region between power amplifier supply 43 and envelope 42 in fig. 4A, and thus graph 48 of fig. 4B may be associated with a power amplifier system having greater energy efficiency.

Fig. 4C is a graph 49 illustrating the supply voltage 45 as a function of the envelope 42 of the RF signal 41. In contrast to the supply voltage 44 of fig. 4B, the supply voltage 45 of fig. 4C varies in discrete voltage increments. Certain implementations described herein may be used in conjunction with an envelope tracker that controls the supply voltage continuously or in discrete increments with respect to the envelope signal.

Fig. 5 is a schematic diagram of another example of a power amplifier system 60 including an envelope tracking system. The illustrated power amplifier system 60 includes an envelope tracker 30, a power amplifier 32, an inductor 62, a load capacitor 63, an impedance matching block 64, a switch 12, and an antenna 14. The illustrated envelope tracker 30 is configured to receive a battery voltage V_BATTAnd the envelope of the RF signal, and generates a power amplifier supply voltage V of the power amplifier 32_{CC_PA}。

The illustrated power amplifier 32 includes a bipolar transistor 61 having an emitter, a base, and a collector. The emitter of the bipolar transistor 61 may be electrically connected to a power low supply voltage V₁Which may be, for example, a ground node, and may provide a Radio Frequency (RF) signal to the base of bipolar transistor 61. The bipolar transistor 61 may amplify the RF signal and provide the amplified RF signal at the collector. The bipolar transistor 61 may be any suitable device. In one implementation, the bipolar transistor 61 is a Heterojunction Bipolar Transistor (HBT).

The power amplifier 32 may be configured to provide the amplified RF signal to the switch 12. An impedance matching block 64 may be used to help terminate the electrical connection between the power amplifier 32 and the switch 12. For example, the impedance matching block 64 may be used to increase power transfer and/or reduce reflections of the amplified RF signal generated by the power amplifier 32.

Inductor 62 may be included to help utilize power amplifier supply voltage V generated by envelope tracker 30_{CC_PA}The power amplifier 32 is biased. The inductor 62 may comprise a first terminal electrically connected to the envelope tracker 30 and a second terminal electrically connected to the collector of the bipolar transistor 61. Load capacitor 63 may have a first terminal electrically connected to the collector of bipolar transistor 61 and to a power low supply voltage V₁And may represent the capacitance of the power amplifier 32 as seen by the envelope tracker 30. For example, the capacitor 63 may represent a parasitic capacitance of the resistive elements of the bipolar transistor 61 and/or the matching block 64. Capacitor 63 may help provide supply voltage V generated by envelope tracker 30_{CC_PA}Filtering the noise. However, the capacitor 63 may also affect the bandwidth response of the envelope tracker 30.

Although fig. 5 illustrates one implementation of power amplifier 32, those skilled in the art will appreciate that the teachings described herein may be applied to a variety of power amplifier configurations, including, for example, multi-stage power amplifier configurations and power amplifiers employing other transistor configurations.

Overview of envelope tracking System

The envelope tracker may be used to vary or control the power amplifier supply voltage to improve the efficiency of the power amplifier system. It is important to improve the power efficiency and/or reduce the design complexity of the envelope tracker. For example, it would be desirable to provide a power amplifier system that does not require analog filters and analog delay elements that may increase the complexity of the power amplifier.

Conventional envelope tracking systems may include a DC-to-DC converter operating in parallel with a class AB amplifier. The DC-to-DC converter may have a relatively high efficiency and low bandwidth and may be used to track relatively low frequency components of the envelope signal. Class AB amplifiers may have lower efficiency than DC-to-DC converters, but may also have a wider bandwidth suitable for tracking the relatively high frequency components of the envelope signal. However, because class AB amplifiers may have a relatively large bandwidth, class AB amplifiers may require analog bandpass filters for noise reduction. Furthermore, it is difficult to align the outputs of the class AB amplifier and the DC-to-DC converter.

In certain implementations described herein, an envelope tracker is provided that includes a buck converter and a push-pull digital-to-analog converter (DAC). The buck converter may help control the supply voltage at a relatively low frequency, while the push-pull DAC may be employed to provide relatively high frequency control of the supply voltage. The push-pull DAC may be controlled using a digital signal generated by filtering, shaping and/or delaying the envelope signal. Employing a combination of a buck converter and a push-pull DAC may reduce design complexity and/or improve overall power relative to schemes employing a DC-to-DC converter and a class AB amplifier, which may require analog bandpass filters to reduce noise and analog delay blocks of the class AB amplifier to align the outputs of the DC-to-DC converter and the class AB amplifier.

Fig. 6 is a schematic diagram of one embodiment of an envelope tracking system 70. The envelope tracking system 70 includes a battery 21 and an envelope tracker 72. The envelope tracker 72 is configured to receive the envelope signal and the battery voltage V_BATTAnd generates a power amplifier supply voltage V_{CC_PA}。

The envelope tracker 72 may control the power amplifier supply voltage V with respect to the amplitude of the envelope signal_{CC_PA}Of the amplitude of (c). The illustrated envelope tracker 72 includes a buck converter 73, a control block 74, a push DAC78, a pull DAC79, and a load capacitor 77.

The buck converter 73 comprises a first switch S₁A second switch S₂And an inductor 75. First switch S₁Comprising an electrical connection to the battery voltage V_BATTAnd a first terminal electrically connected to the inductor 75 and a second switch S₂A second end of the first end of (a). A second switch S₂Further comprising an electrical connection to a power low supply voltage V₁The second end of (a). Inductor 75Comprising an electrical connection to a power amplifier supply voltage V_{CC_PA}The second end of (a).

Control block 74 is configured to receive the envelope signal and use the envelope signal to generate control signals for buck converter 73, push DAC78, and pull DAC 79. For example, control block 74 may generate a control signal for controlling first and second switches S₁、S₂And a second plurality of control signals for controlling the push and pull DACs 78, 79. In some implementations, the control signal generated by control block 74 is a digital signal. Controlling the buck converter 73 and the push and pull DACs 78, 79 using digital signals may help align the outputs of the push and pull DACs 78, 79 and the buck converter 73, thereby reducing the design complexity and/or improving the efficiency of the envelope tracker 70 relative to schemes using DC-to-DC converters operating in parallel with class AB amplifiers.

Control block 74 may receive one or more feedback signals to assist in enhancing envelope tracking control. For example, control block 74 may receive an indication of power amplifier supply voltage V_{CC_PA}Of the amplitude of (d). Furthermore, to assist in controlling the first and second switches S₁、S₂Control block 74 may be electrically connected to a first end of inductor 75. Providing feedback in this manner may help determine the direction of current through inductor 75, which may help determine when to actuate first and second switches S₁、S₂。

Push DAC78 arranged at battery voltage V_BATTAnd a power amplifier supply voltage V_{CC_PA}And controls the push DAC78 using control block 74. The pull-type DAC79 is arranged at the power amplifier supply voltage V_{CC_PA}And a low power supply voltage V₁And controls the pull DAC79 using control block 74. Control block 74 may use push DAC78 to increase power amplifier supply voltage V when the envelope signal increases_{CC_PA}When the envelope signal decreases, control block 74 may use a pull DAC79 to decrease the power amplifier supply voltage V_{CC_PA}。

As shown in fig. 6, a load capacitor 77 may be arranged at the power amplifier supply voltage V_{CC_PA}And a low power supply voltage V₁And may represent the power amplifier supply voltage V_{CC_PA}Load capacitances of various loads, e.g. with electrical connection to the power amplifier supply voltage V_{CC_PA}The parasitic load capacitance associated with the one or more power amplifiers. The illustrated load capacitor 77 includes a supply voltage V electrically connected to the power amplifier_{CC_PA}And is electrically connected to the power low supply voltage V₁The second end of (a). Load capacitor 77 may help reduce power amplifier supply voltage V_{CC_PA}But may also reduce the bandwidth response of the envelope tracker 70. In certain implementations, load capacitor 77 is configured to have a value that is small enough to avoid limiting bandwidth while being large enough to provide adequate noise filtering. The capacitance of the load capacitor 77 may be controlled in any suitable manner, such as by being electrically connected to the power amplifier supply voltage V_{CC_PA}By controlling the geometry and/or layers used to form the power amplifier supply voltage node. In some implementations, load capacitor 77 has a value selected to be in the range of about 200pF to about 4000 pF.

Fig. 7 is a schematic diagram of another embodiment of an envelope tracking system 80. The envelope tracking system 80 includes a battery 21 and an envelope tracker 82. The envelope tracker 82 is configured to receive the digital envelope signal and the battery voltage V_BATTAnd generates a power amplifier supply voltage V_{CC_PA}。

The envelope tracker 82 may vary the power amplifier supply voltage V with respect to the amplitude of the digital envelope signal_{CC_PA}Of the amplitude of (c). The illustrated envelope tracker 82 includes a buck converter 83, a push DAC88, a pull DAC89, a load capacitor 87, a digital filter 90, a ripple control block 91, a digital shaping and delay block 92, and a thermometer decoder 93. Push DAC88 and pull DAC89 collectively operate as a DAC module. The envelope tracker 82 may receive the digital envelope signal from any suitable source, such as a transceiver. In thatIn some implementations, the digital envelope signal may be generated using an analog envelope signal and an analog-to-digital converter.

The buck converter 83 includes an NMOS transistor 82, a PMOS transistor 81, and an inductor 85. PMOS transistor 81 includes a transistor electrically connected to the battery voltage V_BATTA gate configured to receive a first control signal from ripple control block 91, and a drain electrically connected to a first end of inductor 85 and a drain of NMOS transistor 82. The NMOS transistor 82 further includes a gate configured to receive a second control signal from the ripple control block 91, and is electrically connected to the power low supply voltage V₁Of the substrate. Inductor 85 includes an electrical connection to power amplifier supply voltage V_{CC_PA}The second end of (a).

Push DAC88 arranged at battery voltage V_BATTAnd a power amplifier supply voltage V_{CC_PA}And includes a plurality of PMOS current cell transistors 98a-98 c. Each PMOS current cell transistor 98a-98c includes a transistor electrically connected to the battery voltage V_BATTAnd is electrically connected to the power amplifier supply voltage V_{CC_PA}Of the substrate. The gates of the PMOS current cell transistors 98a-98c are controlled by a thermometer decoder 93, which thermometer decoder 93 may selectively activate one or more of the PMOS current cell transistors 98a-98c to increase the power amplifier supply voltage V_{CC_PA}. In some implementations, the number of PMOS current cell transistors 98a-98c is selected to be greater than or equal to about 16. For example, the number of PMOS current cell transistors 98a-98c may be selected to be in the range of about 16 to about 128.

The pull-type DAC89 is arranged at the power amplifier supply voltage V_{CC_PA}And a low power supply voltage V₁And includes a plurality of NMOS current cell transistors 99a-99 c. Each NMOS current cell transistor 99a-99c includes a transistor electrically connected to a power low supply voltage V₁And is electrically connected to the power amplifier supply voltage V_{CC_PA}Of the substrate. The gates of the NMOS current cell transistors 99a-99c are controlled by a thermometer decoder 93, which thermometer decoder 93 may be used to selectively activate NOne or more of the MOS current cell transistors 99a-99c to reduce the power amplifier supply voltage V_{CC_PA}. In some implementations, the number of NMOS current cell transistors 99a-99c is selected to be greater than or equal to about 16. For example, the number of NMOS current cell transistors 99a-99c may be selected to be in the range of about 16 to about 128.

As shown in fig. 7, a load capacitor 87 may be arranged at the power amplifier supply voltage V_{CC_PA}And a low power supply voltage V₁In the meantime. For example, the illustrated load capacitor 87 includes a supply voltage V electrically connected to the power amplifier_{CC_PA}And is electrically connected to the power low supply voltage V₁The second end of (a). Load capacitor 87 may help reduce power amplifier supply voltage V_{CC_PA}And/or may be used to supply voltage V to a power amplifier connected thereto_{CC_PA}The power amplifier of (1) provides stability. Additional details of the load capacitor may be similar to those described above with respect to load capacitor 77 of fig. 6.

The digital filter block 90 is configured to receive the envelope signal and one or more feedback signals and may filter the envelope signal using the feedback signals to generate a filtered envelope signal. For example, the digital filter block 90 may be electrically connected to the power amplifier supply voltage V_{CC_PA}And/or one or more nodes of the buck converter 83, thereby improving the operation of the digital filter block 90. The digital filter block 90 may employ various filtering techniques including, for example, finite impulse response techniques. As illustrated in fig. 7, both the digital shaping and delay block 92 and the ripple control block 91 may be configured to receive the filtered envelope signal and use the filtered envelope signal to control the DACs 88, 89 and the buck converter 83, respectively. Configuring the envelope tracker 82 in this manner may help align the outputs of the DACs 88, 89 and the buck converter 83, thereby improving the efficiency of the power amplifier system and/or reducing design complexity.

The ripple control block 91 may receive the filtered envelope signal from the digital filter block 90 and the feedback signal from the buck converter 83, and may use the filtered envelope signal and the feedback signal to generate a control signal for the buck converter 83. For example, ripple control block 91 has been configured to generate first and second switch control signals for controlling the current through NMOS transistor 81 and PMOS transistor 82, respectively.

The digital shaping and delay block 92 is configured to receive the filtered envelope signal from the digital filter 90 and shape and/or delay the filtered envelope signal to generate a shaped envelope signal. For example, the digital shaping and delay module 92 may delay the filtered envelope signal to align the output of the buck converter 83 and the push and pull DACs 88, 89 in order to compensate for differences in delay between the digital envelope and output of the buck converter 83 and the digital envelope and output of the DACs 88, 89. The digital shaping and delay block 92 may also be used to shape the envelope signal to generate signals for controlling the push and pull DACs 88, 89. For example, the digital shaping and delay block 92 may include a look-up table that maps the digital envelope signal to DAC output levels. The lookup table may be configured, for example, based on the electrical characteristics of the transistors used in the push and pull DACs 88, 89.

To help improve the output noise, the envelope tracker 82 may include a thermometer decoder 93 disposed between the digital shaping and delay block 92 and the push and pull DACs 88, 89. The thermometer decoder 93 may be used to convert the shaped envelope signal, which may be a binary coded signal, generated by the digital shaping and delay block into a thermometer coded signal. Converting the signal in this manner may help reduce switching noise generated by the push and pull DACs. For example, when using a thermometer decoder and a 16-bit push DAC, the thermometer decoder may control the gates of the PMOS transistors in the push DAC such that only one PMOS transistor switches when transitioning from a binary-coded shaped envelope signal value of "0000000011111111" to a binary-coded shaped envelope signal value of "0000000100000000".

Fig. 8 is a flow chart illustrating a method for generating a power amplifier supply voltage according to one embodiment. It will be appreciated that the method may include more or fewer operations as necessary and that the operations may be performed in any order.

The method 100 begins at block 101 where a power amplifier is provided for amplifying an RF signal. For example, a power amplifier may be provided for amplifying W-CDMA or GSM signals.

In a following block 102, an envelope tracker is provided for controlling a supply voltage of the power amplifier using an envelope of the RF signal. For example, the envelope tracker may be electrically connected to a battery, and may use an envelope received from a transmitter or other source to control the magnitude of a supply voltage provided to the power amplifier. The envelope tracker includes a buck converter and a digital-to-analog conversion (DAC) module. The buck converter may be used to track the relatively low frequency component of the envelope to generate a buck or buck voltage that is less than the battery voltage, while the DAC module may include a push DAC and a pull DAC for adjusting the output of the buck converter to correct the relatively high frequency component of the envelope. In one embodiment, the angular frequency of the buck converter is less than or equal to about 200 kHz.

The method 100 continues at block 102, where a buck converter is used to generate a buck voltage based on the envelope signal. In a subsequent block 103, the DAC module is used to adjust the buck voltage based on the envelope signal to generate the supply voltage. Using an envelope tracker comprising a buck converter and a DAC module may increase the power efficiency of the system and may avoid the need to implement an analog bandpass filter and/or an analog delay block. For example, a design using a class AB amplifier and a buck converter may require processing the envelope signal into a format suitable for controlling the buck converter and filtering the envelope signal and passing it to the class AB amplifier. As a result, a delay between the output of the buck converter and the class AB amplifier may occur, and techniques for compensating for the delay may increase design complexity and/or result in reduced power efficiency due to output misalignment.

In some implementations, the DAC module can include a push DAC having a PMOS current source array and a pull DAC having an NMOS current source array. The push-DAC may increase the voltage of the power supply using a PMOS current source when the envelope signal indicates that the output from the buck converter should be increased. Similarly, the pull-DAC may reduce the voltage of the power supply using an NMOS current source when the envelope signal indicates that the output from the buck converter should be reduced.

Fig. 9 is a schematic diagram of one embodiment of a pull DAC 120. The pull DAC120 includes a bias circuit 121 and a current source array 122. Current source array 122 includes circuitry configured to receive bias voltage V from bias circuit 121_BIASAnd is electrically connected to the power amplifier supply voltage V_{CC_PA}To output of (c). The pull-DAC 120 has been noted as being included in the power amplifier supply voltage V_{CC_PA}And a low power supply voltage V₁A load capacitor 123 and a load resistor 124 electrically connected in parallel therebetween.

The bias circuit 121 includes a current source 126 and a bias NMOS transistor 127. Current source 126 includes a current source electrically connected to a power low supply voltage V₁And a second terminal electrically connected to the source and gate of bias NMOS transistor 127. Biasing NMOS transistor 127 further includes an electrical connection to battery voltage V_BATTOf the substrate. As shown in fig. 9, the current source 126 may be configured to generate a bias current I_BIASAnd a bias current I is supplied by biasing the channel of the NMOS transistor 127_BIASSo that the gate of the bias NMOS transistor 127 is biased to a bias voltage V_BIAS。

The current source array 122 includes first to sixth switches 141 and 146 and first to sixth NMOS current source transistors 131 and 136. Each of the first through sixth NMOS current source transistors 131-136 includes a bias voltage V electrically connected thereto_BIASAnd is electrically connected to the power amplifier supply voltage V_{CC_PA}Of the substrate. The first or x1NMOS current source transistor 131 also includes a drain electrically connected to a first terminal of the first switch 141. The second or x2NMOS current source transistor 132 also includes a drain electrically connected to a first terminal of the second switch 142. The third or x4 current source transistor 133 also includes a drain electrically connected to a first terminal of the third switch 143. The fourth or x8 current source transistor 134 further includesA drain electrically connected to a first terminal of the fourth switch 144. The fifth or x16 current source transistor 135 also includes a drain electrically connected to a first terminal of the fifth switch 145. The sixth or x32 current source transistor 136 also includes a drain electrically connected to a first terminal of the sixth switch 146. Each of the first through sixth switches 141-146 further includes a voltage V electrically connected to the battery_BATTThe second end of (a).

The current source array 122 may be configured to generate an output current I in response to a digital input signal_DAC. For example, the first through sixth switches 141 and 146, respectively, may be used to convert the battery voltage V based on the value of the six-bit digital input_BATTConnected to the drains of the first through sixth NMOS current source transistors 141 and 146. In addition, the first through sixth NMOS current source transistors 141-146 may have binary weighted values such that the output currents from the sources of the first through sixth NMOS current source transistors 141-146 are summed to generate the output current I having a current magnitude that varies with respect to the digital input signal_DAC. As shown in FIG. 9, a bias voltage V may be provided to the gates of the NMOS current source transistors 131 and 136_BIASThe NMOS current source transistor 131-136 may be a replica of the bias NMOS transistor 127 such that the NMOS current source transistor 131-136 generates the bias current I_BIASA scaled output current.

The push DAC120 has been annotated to show the power amplifier supply voltage V_{CC_PA}An example of the supply voltage waveform 125. As shown in fig. 9, the supply voltage waveform 125 changes relatively gently in response to changes to the digital input of the push DAC 120. Although the push DAC120 generates an output current I that is digitized and changed in discrete increments in response to a digital input_DACThe load capacitor 123 and the load resistor 124 may be operable to supply the power amplifier with a voltage V_{CC_PA}Thereby generating a relatively flat supply voltage waveform 125.

The operation of the load capacitor 123 and the load resistor 124 as a low pass filter may reduce the supply voltage V to the power amplifier_{CC_PA}Image of quantization noise of operation of powered power amplifierAnd (6) sounding. Since the load capacitor 123 and the load resistor 124 may prevent the power amplifier from supplying the voltage V_{CC_PA}Rapidly changing in response to changes in the digital input signal of the DAC, in some implementations, it may not be necessary to include a separate explicit filter to filter the power amplifier supply voltage V_{CC_PA}。

Fig. 10 is a graph 160 of one example of input power versus efficiency for various power amplifier supply voltages. Graph 160 includes plots for a first supply voltage V, respectively_PA1A second supply voltage V_PA2A third supply voltage V_PA3And a fourth supply voltage V_PA4First to fourth curves 161-164 of input power versus efficiency, where V_PA1<V_PA2<V_PA3<V_PA4And first to fourth supply voltages V_PA1-V_PA4Each being a fixed DC supply voltage. As shown in fig. 10, the efficiency peaks at different input power levels for each of the first through fourth curves 161-164. The graph 160 further comprises a fifth curve 165 of the input power efficiency for a supply voltage that varies with respect to the input envelope signal. As shown in fig. 10, a fifth curve 165 associated with a power supply generated by an envelope tracker shows a high efficiency level over a wide range of input power levels.

Fig. 11 is a graph 170 of an example of an input envelope signal versus a shaped envelope signal. The graph 170 comprises a curve 172 of the shaped envelope signal with respect to the input envelope signal. Graph 170 also includes lines 171 associated with no envelope shaping. As shown in fig. 11, curve 172 is associated with an envelope signal that has been shaped to have a greater amplitude relative to line 171 for relatively small input envelope values. Shaping the envelope signal in this manner can help optimize the linearity of the power amplifier system over a wide range of signal power levels.

Fig. 12 is a graph 180 of one example of power versus frequency for the envelope tracker described herein. Graph 180 includes a first plot 181 of envelope tracker output power versus frequency. The graph 180 also includes a second plot 182 of buck converter output power versus frequency, and a third plot 183 of DAC output power versus frequency. As shown by the second and third curves 182, 183, the buck converter may provide a greater output power than the DAC at low envelope signal frequencies, while the DAC may provide a greater output power than the buck converter at high envelope frequencies. By configuring the buck converter to track low frequency components of the envelope signal, e.g., frequency components less than about 200kHz, and by configuring the DAC to track high frequency components of the envelope signal, e.g., frequency components greater than about 200kHz, the overall power efficiency of the envelope tracker may be increased.

Applications of

Some of the embodiments described above have provided examples in connection with mobile phones. However, the principles and advantages of the present embodiments may be applied to any other system or apparatus requiring a power amplifier system.

Such a power amplifier system may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics, portions of consumer electronics, electronic test equipment, and the like. Examples of electronic devices may also include, but are not limited to, memory chips, memory modules, circuitry of an optical network or other communication network, and disk drive circuitry. Consumer electronics products may include, but are not limited to, mobile phones, telephones, televisions, computer monitors, computers, handheld computers, Personal Digital Assistants (PDAs), microwave ovens, refrigerators, automobiles, stereos, cassette tape recorders or players, DVD players, CD players, VCRs, MP3 players, radios, camcorders, digital cameras, portable memory chips, washing machines, dryers, washer/dryers, copiers, facsimile machines, scanners, multifunction peripherals, wristwatches, clocks, and the like. Further, the electronic device may include unfinished products.

Conclusion

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, in the meaning of "including, but not limited to". As generally used herein, the term "coupled" means that two or more elements may be connected directly or through one or more intermediate elements. Further, as generally used herein, the term "coupled" means that two or more elements may be connected directly or through one or more intermediate elements. Moreover, as used in this application, the words "herein," "above," "below," and words of similar import shall refer to this application as a whole and not to any particular portions of this application. Words in the above detailed description that use the singular or plural number may also include the plural or singular number, respectively, as the context permits. The word "or" when referring to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

Furthermore, unless specifically stated otherwise, or as used within the context of otherwise understood, conditional language, such as "may," "can," "might," "meeting," "etc," "e.g.," and "such as," used herein is generally intended to convey that certain embodiments include, but other embodiments do not include, certain features, elements, and/or states, among others. Thus, such conditional language is not generally intended to imply that features, elements, and/or states are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding whether such features, elements, and/or states are included or are to be performed in any particular embodiment, whether or not input or prompted by an author.

The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a variety of different ways. Further, while processes or blocks are sometimes shown as occurring in series, these processes or blocks may alternatively occur in parallel, or may occur at different times.

The teachings of the invention provided herein may be applied to other systems, not necessarily the systems described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.

While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the present disclosure. Indeed, the novel methods and systems described herein may be embodied in various other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.

Claims (20)

1. A power amplifier system, comprising:

a power amplifier configured to amplify a Radio Frequency (RF) signal; and

an envelope tracker configured to generate a power amplifier supply voltage of the power amplifier using an envelope of the RF signal, the envelope tracker including a buck converter configured to generate a buck voltage from a battery voltage and a digital-to-analog converter (DAC) module configured to adjust a magnitude of the buck voltage based on the envelope of the RF signal to generate the power amplifier supply voltage.

2. The power amplifier system of claim 1 wherein the DAC module includes a push DAC and a pull DAC, the push DAC configured to increase the power amplifier supply voltage when the envelope of the RF signal increases and the pull DAC configured to decrease the power amplifier supply voltage when the envelope of the RF signal decreases.

3. The power amplifier system of claim 2 further comprising a digital filter configured to receive the envelope of the RF signal and the power amplifier supply voltage and to generate a filtered envelope signal by filtering the envelope of the RF signal based at least in part on the power amplifier supply voltage.

4. The power amplifier system of claim 3, further comprising a digital shaping and delay module configured to receive the filtered envelope signal and generate a shaped envelope signal.

5. The power amplifier system of claim 4 further comprising a thermometer decoder configured to receive the shaped envelope signal and decode the shaped envelope signal to generate a plurality of push DAC control signals and a plurality of pull DAC control signals, the plurality of push DAC control signals and the plurality of pull DAC control signals being thermometer coded.

6. The power amplifier system of claim 5 wherein the pull DAC includes a plurality of NMOS current sources and the push DAC includes a plurality of PMOS current sources, the plurality of NMOS current sources being disposed between the power amplifier supply voltage and a power low supply voltage and the plurality of PMOS current sources being disposed between the battery voltage and the power amplifier supply voltage, gates of the plurality of NMOS current sources and the plurality of PMOS current sources being controlled by a plurality of the pull DAC control signals and the plurality of push DAC control signals, respectively.

7. The power amplifier system of claim 6, wherein each of the number of the plurality of NMOS current sources and the number of the plurality of PMOS current sources is greater than or equal to sixteen.

8. The power amplifier system of claim 3, further comprising a ripple control module configured to receive the filtered envelope signal and to generate a first buck control signal and a second buck control signal using the filtered envelope signal.

9. The power amplifier system of claim 8, wherein the buck converter includes an NMOS transistor and a PMOS transistor, each including a gate, a source, and a drain, the gates of the NMOS and PMOS transistors being electrically connected to the first and second buck control signals, respectively, the sources of the NMOS and PMOS transistors being electrically connected to a power low supply voltage and the battery voltage, respectively, and the drains of the NMOS and PMOS transistors being electrically connected together.

10. The power amplifier system of claim 9 wherein the buck converter further comprises an inductor having a first terminal electrically connected to a supply voltage of the power amplifier and a second terminal electrically connected to the drains of the NMOS and PMOS transistors.

11. The power amplifier system of claim 1 further comprising a transceiver for providing an envelope of the RF signal to the envelope tracker and providing the RF signal to the power amplifier.

12. The power amplifier system of claim 1 wherein the power amplifier comprises a bipolar transistor having an emitter, a base, and a collector, the base configured to receive the RF signal, the emitter electrically connected to a power low supply voltage, and the collector configured to generate an amplified version of the RF signal.

13. A method of envelope tracking in a power amplifier system, the method comprising:

providing a power amplifier for amplifying a Radio Frequency (RF) signal;

providing an envelope tracker for generating a supply voltage of the power amplifier using an envelope of the RF signal, the envelope tracker including a buck converter and a digital-to-analog (DAC) module;

generating a buck voltage from a battery voltage using the buck converter; and

adjusting, using the DAC module, the buck voltage to generate the supply voltage, the adjusted voltage magnitude based on an envelope of the RF signal.

14. The method of claim 13 wherein the digital-to-analog converter includes a push DAC and a pull DAC and the buck converter includes a buck converter.

15. The method of claim 14, wherein adjusting the buck voltage using the DAC module includes increasing the supply voltage using the push DAC when an envelope of the RF signal increases and decreasing the supply voltage using the pull DAC when an envelope of the RF signal decreases.

16. The method of claim 14, further comprising filtering an envelope of the RF signal using a digital filter.

17. The method of claim 16, further comprising delaying the filtered envelope signal prior to providing the filtered envelope signal to the DAC module.

18. The method of claim 16, wherein delaying the filtered envelope signal prior to providing the filtered envelope signal to the DAC module comprises determining a duration of delay based on a difference in delay between the DAC module and the buck converter.

19. The method of claim 16, further comprising shaping the filtered envelope signal to generate a shaped envelope signal.

20. The method of claim 19 further comprising converting the shaped envelope signal to a push DAC control signal and a pull DAC control signal, the push DAC control signal and the pull DAC being thermometer coded.