HK1190230A - Method for producing a iii/v si template - Google Patents

Description

Method for manufacturing III/V Si template

Technical Field

The present invention relates to a method for manufacturing III/V Si templates or whiteboards, respectively, preferably on silicon substrates up to 300mm (diameter) and larger, to templates manufactured by such a method and to the use of such templates.

Background of the invention and Prior Art

The numerous rapid advances in computer and microchip technology, respectively, are based on the successful miniaturization of the individual components of the integrated circuit. Integrated circuits are simply electronic connections of semiconductor components and passive components for data processing, which components are fabricated in a thin crystalline layer on the surface of a silicon substrate. The number of integrated electronic components such as transistors, diodes, resistors and capacitors is very large. In order to improve the performance of microchips and at the same time reduce the manufacturing costs, the packing density of the components is significantly increased in each new generation of technology. The most important component of an integrated circuit is a silicon-based CMOS logic circuit with n-or p-MOS-FET transistors (complementary metal oxide semiconductors). In particular, the physical properties of silicon and silicon dioxide have enabled significant transistor size reduction over the past few decades. Accordingly, transistor density in microchip development can double every 24 months.

A transistor is simply a resistance controlled by an external gate voltage (the voltage at the control electrode). Key performance characteristics of these components are high clock rates and low heat dissipation in operation. Heretofore, these performance characteristics can be improved by the structure reduction of transistors. At the same time, however, the size of the individual components is so small that the fundamental physical limits are reached, and further miniaturization will not lead to improvement. At the same time, new materials, in addition to silicon and silicon dioxide, whose physical properties lead to an improvement in the functionality of the components, are used in this location for the fabrication of integrated circuits.

In particular, the use of III/V semiconductor materials in CMOS processes is discussed. The III/V semiconductor crystal group is composed of 50% each of group III and group V chemical elements. The binding properties of the respective chemical elements determine the electronic and optical properties of the III/V semiconductor compounds. Since the choice of composition is very large in the class of III/V semiconductor materials, correspondingly very different semiconductor components can be realized. The integration of the III/V semiconductor layer on a Si-based integrated circuit allows on the one hand to improve existing functionalities, such as the application of III/V channel layers for transistors. On the other hand, new device concepts can be obtained, such as the integration of III/V laser diodes for optical data processing on the microchip level.

Another key point in the application of new materials for improving integrated circuit performance is the integration process. Wherein regardless of new material and/or device concepts, it is important to keep manufacturing costs low. In contrast to hybrid integration methods (see e.g. EP0297483), monolithic growth of III/V semiconductor layers on Si substrates is a very cheap method. The III/V semiconductor hybrid crystal is here directly connected to a silicon carrier substrate (see for example only US5937274 or PCT/DE 2006/000140).

Because of the different material classes of silicon and III/V semiconductors, the following aspects must be considered for monolithic connection: the atomic bonding properties of silicon and group III/V elements are very different, and therefore the lattice constant of most III/V crystals is different from that of silicon. This difference in lattice constant will in turn lead to the formation of dislocation defects during the precipitation of III/V films on Si. Furthermore, interdiffusion at the interface between silicon and III/V crystals and/or contamination effects during crystal growth may lead to uncontrolled doping in the respective host crystal.

Another problem arises from the different crystal bases of Si and III/V crystals: if the Si surface comprises a non-atomic bi-layer stepped Si stack, reverse phase defects will form in the III/V film. From the 80 s onwards, the monolithic integration of III/V layers on silicon was investigated. The above-described difficulties of depositing III/V on small Si substrates up to 2 inches in diameter are substantially solved, but in the integration of III/V materials with lattice constants different from silicon, the formation of dislocations still complicates the realization of highly efficient components with sufficient lifetime.

Because of the different crystal bases of silicon and III/V mixed crystals, reverse defects in the III/V layer can form rapidly in the monolithic precipitation process. These defects in turn impair the operability of the component. The formation of reverse phase defects can be avoided by special preparation of the silicon surface.

If the two steps of special substrate pretreatment (one Si atomic layer prepared per step) are performed with two Si atomic layers, then III/V integration without reverse phase defects is possible. But such surface preparation is preferably possible on a slightly dislocated [ (001) deviating 2 ° -6 ° ] in the <110> direction on the substrate. In the document b.kunert, i.n. meth, s.reinhard, k.volz, w.stolz, Thin Film Solid 17(2008) 140, defect-free deposits of GaP on precisely oriented substrates are revealed for the first time, but the substrate specifications are still subject to further requirements: (001) the deviation (less) is <0.15 ° in the <110> direction.

Because the current Si-based CMOS processes are very complex and advanced, the integration of new materials must be very precisely matched to the CMOS fabrication methods. Any major intervention or variation of the current CMOS approach will significantly increase development costs. The specification for the orientation of the CMOS standard Si substrate is that (001) deviates by +/-0.5 in any direction. However, the conversion of CMOS technology to a dislocated [ (001) 2 ° -6 ° ] substrate in the <110> direction would be prohibitively expensive and uneconomical due to the readjustment of the process.

However, the above substrate specification of (001) deviating by <0.15 ° in the <110> direction will fall within the specification of the CMOS method. However, due to such small misalignments, the particular wafer sawing method is very complex and expensive and still represents a great technical challenge. At the same time, in practical CMOS processes, the Si substrate size is 300mm in diameter (some factories work with even smaller wafers). However, mass production of 300mm si wafers with <0.15 ° misalignment in the <110> direction will significantly increase the production cost and therefore the application of these substrates will be economically problematic. Therefore, non-inverting III/V integration, particularly on 300mm Si substrates, is an unsolved technical and economic problem for CMOS processes.

Another technical challenge is caused by the different thermal expansion coefficients of silicon and III/V semiconductor crystal compounds. When no system in the integration method takes into account the different dependence of the lattice constant on temperature, dislocations or cracks may form in the III/V layer. For large substrate diameters, the Si wafer can even be affected (wafer flipped) and relaxation defects formed.

Technical object of the invention

The technical aim of the present invention is therefore to propose a method for producing a monolithic III/V Si template with a minimum of dislocation defects, a minimum of reverse phase defects, and allowing the use of relatively large Si wafers with a diameter of 200mm, 300mm or more, which optionally may have a mask structure.

The essential point of the invention

In order to achieve this technical object, the invention teaches a method of manufacturing a monolithic template comprising a Si wafer on the surface of which a III/V semiconductor layer is applied epitaxially, the III/V semiconductor having a lattice constant differing by less than 10% from that of Si, said method comprising the steps of: A) optionally deoxidizing the Si wafer surface, B) optionally epitaxially growing a Si layer on the deoxidized Si wafer surface, C) optionally, subjecting the Si wafer surface or the Si layer surface to a baking step and/or an etching step, D) at a wafer temperature of 350-650 ℃, epitaxially growing a III/V semiconductor layer on the surface of the Si wafer or on the surface formed during one of the steps A) to C), at a growth rate of 0.1 to 2 μm/h and a layer thickness of 1 to 100nm, E) at a wafer temperature of 500 ℃ to 800 ℃, epitaxially growing on the layer obtained in step D) a III/V semiconductor layer which is identical to or different from the III/V semiconductor applied in step D), at a growth rate of 0.1 to 10 μm/h and with a layer thickness of 10 to 150 nm.

The invention thus includes a particular method of crystallographically precipitating group IV materials as well as III/V semiconductor compounds on Si substrates. These Si substrates have diameters of 200mm, 300mm and more and are optionally structured by means of masks. The crystal precipitation or crystal growth, respectively, is typically carried out by vapor phase epitaxy. Using this method, the integration of thin dislocation-free III/V semiconductor layers on Si substrates can also be achieved purposefully and ideally.

At the start of the process, the Si substrate may be baked in a first process step to remove silicon dioxide from the surface. In the next step, a silicon buffer layer (silicon buffer) may be deposited, if desired. Depending on the integration concept, the silicon buffer layer may be doped. The Si substrate surface with or without additional buffer layers is for example, but not necessarily, specially prepared, depending on the crystal dislocations (deviated or correctly oriented). The precipitation of steps D) and E) takes place in two process steps: first a thin III/V film is grown at low temperature (step D)), and then the reactor temperature is raised significantly for further crystal precipitation (step E)). The composition of the III/V layer is adjusted according to the layer thickness and the growth temperature, the layer thickness being such as to avoid the formation of dislocations and cracks or to reduce them as far as possible.

In contrast to most other III/V mixed crystals, monolithic integration of thin GaP layers on Si substrates without dislocation defects is possible because the two crystals have similar lattice constants. The application of GaP as the first III/V nucleation layer is therefore technically very important, since this also considerably simplifies the further integration of materials with different lattice constants. Such GaP/Si templates can thus be used for very different III/V material and (electronic) component concepts on Si microelectronics. Currently, various enterprises, associations and universities are studying specific integration concepts under application of GaP/Si templates.

The invention makes it possible for the first time to deposit virtually dislocation-free III/V semiconductor materials on silicon substrates which are precise and have dislocation diameters of up to 300 mm. In this method design, it is also contemplated that a silicon buffer layer with any doping can be implemented before the III/V material is deposited. This step is particularly helpful in order to optimize the substrate surface on the one hand to allow selective silicon overgrowth especially for mask structuring methods and to allow the deposition of a tailored Si contact layer for conventional CMOS metallization. The use of 300mm wafers corresponds to the current Si-based CMOS process, so that the integration method on the respective wafer allows maximum compatibility with the current state of the art CMOS processes.

Furthermore, by using a 300mm substrate, the ideal cost effectiveness of the manufacturing costs is ensured. In particular, since the method has been implemented in an epitaxial growth system in connection with an automated disk handler, automated substrate transfer is possible.

In addition to the application of the invention in Si micro-processes, the precipitation of III/V materials on large-area Si substrates is also advantageous for other applications. The object here is to benefit from the fact that Si substrates are much cheaper than conventional III/V substrates and that also larger substrate discs can be manufactured.

By integrating conventional III/V based components, such as LEDs, detectors or solar cells, on Si substrates, the manufacturing costs can be significantly reduced. In this regard, it is also possible to use a dislocation ((001) deviated by 2 ° -6 ° in the <110> direction) Si substrate.

In particular, the following preferred variants of the method of the invention are described.

The surface to be coated of the Si wafer is preferably a (001) Si surface with 0 to 6 °, in particular 0 to 2 °, dislocations in the direction <110 >. In addition, the Si wafer may have a mask structure. For dislocations of ≦ 1 °, the direction of the dislocations may be different from <110 >.

Step A) may be carried out by baking in an inert atmosphere to a wafer temperature of from 800 to 1200 deg.C, in particular from 900 to 1100 deg.C, for example 950-1050 deg.C, for a period of from 1s to 30min, in particular for a period of from 1 to 30min, for example from 5 to 15 min. The inert atmosphere may be nitrogen or hydrogen. The (total) gas pressure may be 50-1000mbar, preferably 100-300 mbar. The total gas flow may be 6-200l/min, in particular 6-50l/min, for example 40-50 l/min.

In step B), the Si layer may be grown at a wafer temperature of 600-1200 deg.C, in particular 725-1100 deg.C, for example 850-1050 deg.C, at a growth rate of 0.01-20 μm/h, in particular 1-10 μm/h, for example 3-10 μm/h, and a layer thickness of 0-5 μm, in particular 0.1-2 μm, for example 0.5-1.5 μm. The inert atmosphere may be nitrogen with the additional use of a gaseous Si educt (educt)Or hydrogen. Optionally, a p-or n-doping concentration of 10 is performed¹⁵-10²¹ cm^-3E.g. 10¹⁷-10²¹ cm^-3B, Ga, P, Sb and/or As. The (total) gas pressure may be 50-1000mbar, preferably 100-300 mbar. The total gas flow may be 6-200l/min, in particular 6-50l/min, for example 40-50 l/min.

In step C), an inert or protective gas (e.g. N)₂Or Ar) respectively or the reactive gas may be introduced over the surface at an etch rate of 0-5 μm/h, preferably 0-2 μm/h, at a wafer temperature of 600-1200 deg.C, in particular 725-1100 deg.C, for example 850-1050 deg.C, for a period of 0-60min, in particular 0-15min, for example 1-10 min. As the active gas, for example, HCl or hydrogen (the remainder being, for example, nitrogen) can be used. The (total) gas pressure may be 50-1000mbar, preferably 600-900 mbar. The total gas flow may be 6-200l/min, in particular 6-50l/min, for example 10-15 l/min.

In step D), Ga may be grown_xB_yAl_zP or GaN_wP_vA semiconductor, wherein x =0-1, y =0-0.1 and z =0-1, or w =0-0.1 and v =1-w, in particular x =1, y =0 and z =0, wherein for Ga_xB_yAl_zThe sum of P, x, y and z is always 1. The wafer temperature may preferably be 400-625 deg.C, in particular 420-500 deg.C. The III/V growth rate may be 0.1-2 μm/h, in particular 0.5-1.5 monolayers/second, for example 1 monolayer/second. The growth mode may be continuous, preferably by flow rate modulated epitaxial growth (FME) and by Atomic Layer Deposition (ALD), and may also be used for general or specific additional description of the layers. The layer thickness is preferably from 2 to 50nm, in particular from 2 to 8 nm. The gas ratio V/III may be from 5 to 200, in particular from 10 to 150, for example from 50 to 70. The (total) gas pressure may be 50 to 1000mbar, preferably 50 to 500mbar, in particular 50 to 150 mbar. The total gas flow may be 6-200l/min, in particular 6-60 l/min, for example 40-60 l/min. Optionally, at 10¹⁵-10²¹ cm^-3E.g. 10¹⁷-10²¹ cm^-3Is doped with Zn, Te, S, C, Mg and/or Si at a p-or n-doping concentration. But instead of the other end of the tubeThe procedure can also be carried out without doping.

In step E), Ga may be grown_xB_yAl_zP or GaN_wP_vA semiconductor, wherein x =0-1, y =0-0.1 and z =0-1, or w =0-0.1 and v =1-w, in particular x =0-1, y =0-0.06 and z =0-1, wherein for Ga_xB_yAl_zThe sum of P, x, y and z is always 1. The wafer temperature may preferably be 525-. The III/V growth rate may be 0.1-10 μm/h, in particular 0.5-5 μm/h, for example 2-2.5 μm/h. The layer thickness is preferably from 30 to 100nm, in particular from 40 to 70 nm. The gas ratio V/III may be 5 to 200, in particular 10 to 100, for example 10 to 30. The (total) gas pressure may be 50 to 1000mbar, preferably 50 to 900mbar, in particular 50 to 150 mbar. The total gas flow may be 6-200l/min, in particular 6-60 l/min, for example 40-60 l/min. Optionally, at 10¹⁵-10²¹cm^-3E.g. 10¹⁷-10²¹cm^-3Is doped with Zn, Te, S, C, Mg and/or Si at a p-or n-doping concentration. However, the procedure can also be carried out without doping.

The invention furthermore relates to a monolithic template obtainable by the method according to the invention. It also relates to the use of such a template for the monolithic integration of components of III/V-based semiconductor layers, such as transistors, laser diodes, LEDs, detectors and solar cells, on Si substrates, in particular on Si substrates having a diameter of more than 6cm, preferably more than 10cm, in particular more than 20 cm. After step E), further III/V semiconductor layers may be epitaxially grown and electronic components comprising III/V semiconductors may be formed.

In the following, the invention is explained in more detail by means of non-limiting examples which represent embodiments only.

Example 1: the device is used.

The crystal precipitation is carried out by vapor phase epitaxy. For this purpose, an epitaxial growth system is required which allows crystal growth on a 300mm (diameter) Si substrate. In addition, the temperature distribution of the susceptor in this method is varied in the radial direction to precisely adjust the temperature profile of the Si wafer. The CCS (Close Couple Shower-head) Crius system from Aixtron is preferably used.

All the described process steps can be carried out in a single epitaxial reactor. In order to minimize contamination effects or to adapt the integrated process to further process steps, two epitaxial reactors may also be used. Wherein an optional substrate transfer after process steps C) and/or D) is recommended.

Example 2: respectively, the substance or gas used.

The following educts or precursors, respectively, can be used in the process:

educts for silicon: silane, dichlorosilane, disilane, trisilane, neopentasilane (neopenta-silane), tetrachlorosilane (SiCl)₄) Di-tert-butylsilane (DitButSi).

Educts for gallium: triethylgallium (TEGa), trimethylgallium (TMGa), tri-tert-butylgallium.

Educts for boron: triethylborane (TEB), tri-tert-butylborane, diborane, borane-amine adducts, such as dimethyl-aminoborane.

Educts for aluminum: trimethylaluminum (TMAl), tri-tert-butylaluminum, amine adducts such as dimethyl-aluminum amide.

Educts for phosphorus: tert-butylphosphine (TBP), phosphine.

Educts for arsenic: tert-butyl arsine (TBA), arsine, trimethyl arsine (TMA).

Educts for antimony: triethylantimony (TESb), trimethylantimony (TMSb).

Educts for doping the III/V layer: diethyl tellurium (DETE), dimethyl zinc (DMZn), diethyl zinc (DEZn), di-tert-butylsilane, silane, di-tert-butyl sulfide (di-tert-butyl-sulfite), biscyclopentadienyl magnesium, tetraboromethane.

Cl-containing educt: HCl, dichlorosilane, SiCl₄。

Nitrogen or hydrogen is used as the carrier gas.

The following educts are preferred: silane, disilane, dichlorosilane, HCl, TEGa, TEB, TMAl and TBP. The preferred carrier gas is hydrogen.

Example 3: GaP on precision (exact) silicon (001).

As an example, the deposition of a thin GaP layer on a 300mm silicon substrate is described. In this embodiment, the Si substrate is p-doped and precisely oriented. The GaP layer is 50nm thick and is at 3 x 10¹⁸ cm^-3In the range n-doped. The following educts were used: silane, TEGa, TBP and DETe.

The Si wafers were transferred from Brooks to the CCS Crius reactor from Aixtron by means of an automated disk transfer system. Purified hydrogen gas is used as the carrier gas, while silane, TEGa, TBP and DETe can be used as educts for Si, Ga, P and Te.

In the first step, the native silica was removed from the substrate surface in a 10 minute baking step (step a). The reactor pressure was 200mbar, the total gas flow was 48 l/min and the wafer temperature was 1000 ℃.

For the deposition of a 1 μm thick Si buffer layer (step B)), the following growth parameters were adjusted: the reactor pressure was 200mbar, the total gas flow was 48 l/min and the wafer temperature was 900 ℃. Under these conditions, a silane flow of 8.9E-4mol/min will result in a growth rate of 4 μm/h.

After the buffer layer growth, a silicon surface is prepared (step C)). For this purpose, a 5min stream of 5.4E-3mol/min HCl is introduced into the reactor. The surface treatment initiates the formation of a two-layer stepped Si stack (terrace) to minimize the formation of reverse phase defects. The reactor pressure was 700mbar and the total flow was 12 l/min.

The subsequent nucleation of the GaP layer again necessitates the adjustment of the growth conditions: in step D) the wafer temperature was lowered to 450 ℃ and the reactor pressure was adjusted to 100mbar and the total gas flow was adjusted to 48 l/min. The molar flow of the III/V educts is 2.52E-4mol/min for TEGa and 1.51E-2mol/min for TBP. In the first step of III/V nucleation, TBP was fed to the reactor for 10 seconds (TBP preflow). Followed by GaP growth according to FME (flow rate modulated epitaxial growth). This means in particular that after the TBP preflow, the following educt changeover sequence for the reactor is repeated several times: 1s growth interrupted, no educts, - > 1s TEGa- > 1s growth interrupted, no educts, - > 1s TBP. This conversion cycle was repeated 22 times, thereby precipitating GaP at 6 nm. The TEGa molar flow was adjusted so that the wafer surface was covered with a single layer of Ga in one second.

In the next step (step E)), the wafer temperature is raised to 675 ℃ with TBP stabilization. Furthermore, the new molar flow for the educts was adjusted: 5.81E-4mol/min for TEGa and 1.16E-2mol/min for TBP. Thus, the V/III ratio is reduced from 60 to 20. The gas phase ratio DETE/TEGa is adjusted so that 3 x 10 is achieved at 675 DEG C¹⁸cm^-3N-doping of (2). A44 nm GaP layer was deposited at a growth rate of 2.3 μm/s. The GaP/Si template is then cooled with TBP stabilization.

These process parameters can also be used for (001) Si wafers with dislocations deviating up to 2 ° in the <110> direction.

Example 4: GaP is on (001) silicon, 2 ° off in the <110> direction of the Si wafer.

As an example, the deposition of a thin GaP layer on a 300mm silicon substrate is described. In this embodiment, the Si substrate is p-doped and has dislocations that are offset by 2 ° in the <110> direction. The thickness of the GaP layer is 50 nm. The following educts were used: silane, TEGa and TBP.

The Si wafers were transferred from Brooks to the CCS Crius reactor from Aixtron by means of an automated disk transfer system. Purified hydrogen gas is used as carrier gas, while silane, TEGa and TBP can be used as educts for Si, Ga and P.

In the first step, the native silica was removed from the substrate surface in a 10 minute baking step (step a). The reactor pressure was 200mbar, the total gas flow was 48 l/min, and the wafer temperature was 1050 ℃.

For the deposition of a 1 μm thick Si buffer layer (step B)), the following growth parameters were adjusted: the reactor pressure was 200mbar, the total gas flow was 48 l/min and the wafer temperature was 1050 ℃. Under these conditions, a silane flow of 8.9E-4mol/min will result in a growth rate of 8.3 μm/h.

Step C) is not performed in this embodiment, followed by step D).

The subsequent nucleation of the GaP layer again necessitates the adjustment of the growth conditions: in step D) the wafer temperature was lowered to 450 ℃ and the reactor pressure was adjusted to 100mbar and the total gas flow was adjusted to 48 l/min. The molar flow of the III/V educts is 2.52E-4mol/min for TEGa and 1.51E-2mol/min for TBP. In the first step of III/V nucleation, TBP was fed to the reactor for 10 seconds (TBP preflow). Followed by GaP growth according to FME (flow rate modulated epitaxial growth). This means in particular that after the TBP preflow, the following educt changeover sequence for the reactor is repeated several times: 1s growth interrupted, no educts, - > 1s TEGa- > 1s growth interrupted, no educts, - > 1s TBP. This conversion cycle was repeated 22 times, thereby precipitating GaP at 6 nm. The TEGa molar flow was adjusted so that the wafer surface was covered with a single layer of Ga in one second.

In the next step (step E)), the wafer temperature is raised to 675 ℃ with TBP stabilization. Furthermore, the new molar flow for the educts was adjusted: 5.81E-4mol/min for TEGa and 1.16E-2mol/min for TBP. Thus, the V/III ratio is reduced from 60 to 20. A44 nm GaP layer was deposited at a growth rate of 2.3 μm/s. The GaP/Si template is then cooled with TBP stabilization.

These process parameters can also be used for (001) Si wafers with dislocations deviating up to 6 ° in the <110> direction.

Claims (10)

1. A method of manufacturing a monolithic template comprising a Si wafer on the surface of which a III/V semiconductor layer is applied epitaxially, the III/V semiconductor having a lattice constant differing by less than 10% from Si, the method comprising the steps of:

A) optionally, deoxidizing the Si wafer surface,

B) optionally, epitaxially growing a Si layer on the deoxidized Si wafer surface,

C) optionally, subjecting the Si wafer surface or the Si layer surface to an etching step and/or a baking step,

D) epitaxially growing a III/V semiconductor layer on the surface of said Si wafer or on the surface formed during one of the steps A) -C) at a wafer temperature of 350-650 ℃, at a growth rate of 0.1-2 μm/h and a layer thickness of 1-100nm,

E) epitaxially growing a III/V semiconductor layer, which is identical to or different from the III/V semiconductor applied in step D), on the layer obtained in step D) at a wafer temperature of 500-800 ℃, at a growth rate of 0.1-10 μm/h and a layer thickness of 10-150 nm.

2. The method according to claim 1, wherein said surface of said Si wafer is a (001) Si surface, deviated by 0-6 ° in the direction <110>, wherein at dislocations of ≦ 1 °, the direction of said dislocations may be different from <110 >.

3. The method according to claim 1 or 2, wherein step a) is performed by baking in an inert atmosphere to a wafer temperature of 800 to 1200 ℃ for a time of 1s-30 min.

4. The method according to one of claims 1 to 3, wherein in step B) the Si layer is grown at a wafer temperature of 600-1200 ℃, a growth rate of 0.01-20 μm/h and a layer thickness of 0-5 μm.

5. The method as claimed in one of claims 1 to 4, wherein in step C) reactive gases, in particular Cl-containing gases and/or hydrogen, are led over the surface at an etch rate of 0-5 μm/h at a wafer temperature of 600-1200 ℃ for a period of 0-60min and/or inert gases are led over the surface at a wafer temperature of 600-1200 ℃ for a period of 0-60 min.

6. Method according to one of claims 1 to 5, wherein Ga is grown in step D)_xB_yAl_zP or GaN_wP_vA semiconductor, wherein x=0-1, y =0-0.1 and z =0-1, or w =0-0.1 and v =1-w, wherein for Ga_xB_yAl_zThe sum of P, x, y and z is always 1.

7. Method according to one of claims 1 to 6, wherein Ga is grown in step E)_xB_yAl_zP or GaN_wP_vA semiconductor, wherein x =0-1, y =0-0.1 and z =0-1, or w =0-0.1 and v =1-w, wherein for Ga_xB_yAl_zThe sum of P, x, y and z is always 1.

8. A monolithic template obtainable by the method according to any one of claims 1 to 7.

9. Use of a template according to claim 8 for the monolithic integration of III/V-based semiconductor components, such as transistors, laser diodes, LEDs, detectors and solar cells, on Si substrates, in particular on Si substrates optionally having mask structures with a diameter of more than 6cm, preferably more than 10cm, in particular more than 20 cm.

10. Use according to claim 9, wherein after step E) further III/V semiconductor layers are epitaxially grown and electronic components comprising III/V semiconductors are formed.