HK1188030A - Electrolytic deposition and via filling in coreless substrate processing - Google Patents

Description

Electrolytic deposition and via filling in coreless substrate processing

Background

Integrated circuits may be formed on a semiconductor wafer made of a material such as silicon. Semiconductor wafers are processed to form various electronic devices. The wafer is diced into semiconductor chips (chips are also referred to as dies) which can then be attached to a substrate using various known methods. The substrate is typically designed to couple the die to a printed circuit board, socket, or other connection. The substrate may also perform one or more other functions including, but not limited to, protecting, isolating, insulating, and/or thermally controlling the die. Traditionally, the substrate is formed by a core consisting of a laminated multilayer structure comprising layers of glass fabric impregnated with an epoxy resin material. Contact pads and conductive traces are formed on the structure to electrically couple the die to a device coupled to the package substrate.

Coreless substrates have been developed in order to reduce the thickness of the substrate. In coreless substrates, a removable core layer is typically provided, a conductive layer and a dielectric layer are deposited over the removable core, and the core is then removed. Coreless substrates typically include a plurality of vias in which interlayer electrical connections are formed.

In one type of die attach process, the die is mounted to the substrate using a conventional array of solder bumps in a flip chip configuration, with the solder bumps between the die and the substrate, by using a method known as the C4 (controlled collapse chip connection) process. In the C4 process, solder may be placed on the active side of the die, on the substrate, or on the die and pads on the substrate using, for example, stencil mask printing. The solder is then melted and allowed to flow, ensuring that each bump completely wets the pad beneath it. Next, a second reflow operation is performed and a solder connection is made between the die pad and the substrate pad. The bonded package is then allowed to cool to complete the solder bump joint. Solder bump connections may also be made between the package and a printed circuit board, such as a motherboard.

A surface treatment layer may be provided on the substrate. The surface treatment layer generally serves to protect the underlying substrate electrical connections prior to assembly. For example, if the substrate includes a copper (Cu) connection, a surface treatment layer may be disposed on the copper. The surface treatment layer may interact with the solder if the device is soldered to the substrate. Alternatively, the surface treatment layer may be removed prior to the soldering operation. Typical surface treatment layers for protecting copper include nickel/palladium/gold (Ni/Pd/Au) layers and Organic Solderability Preservative (OSP). The nickel palladium gold surface treatment comprises a layer of nickel on copper, followed by a layer of palladium on nickel, followed by a layer of gold on palladium. Nickel provides a barrier to copper migration and protects the copper surface from oxidation. Palladium acts as an oxidation barrier for the nickel layer. The gold layer serves to improve wettability during solder joint formation. The OSP surface treatment layer typically includes a water-based organic compound that selectively bonds with copper to form an organic metal layer that functions to protect the copper from oxidation.

When lead-free solder is used to couple the die to the substrate, tin-based solders including tin, silver, and copper alloys (SAC) are typically used. The surface treatment is important to ensure a strong, durable joint. For example, if the surface finish is insufficient to protect the copper, oxidation can occur and the interaction between the copper oxide and the lead-free solder can result in the formation of an unsuitable joint. In addition, depending on the materials used in the surface treatment layer, adverse reactions may occur to adversely affect the properties of the joint.

Drawings

Embodiments will be described by way of example with reference to the accompanying drawings, which are not necessarily drawn to scale, and in which:

figures 1(a) -1(U) illustrate views of processing operations for forming a coreless substrate, in accordance with certain embodiments;

figure 2 illustrates a flow diagram of process operations for forming a coreless substrate, in accordance with certain embodiments;

figure 3 illustrates a cross-sectional view of an assembly including a coreless substrate coupled to a die and a board, in accordance with certain embodiments;

fig. 4 shows an electronic system arrangement to which embodiments may be applied.

Detailed Description

Conventional methods for filling vias during fabrication of coreless substrates utilize electroless plating (electrolytic plating) to form a Cu layer as a plating bus (buss) for subsequent electrolytic plating. After patterning a photoresist layer on the electroless deposition layer to define conductive traces, the vias are filled while the traces are plated by an electrolytic Cu plating process. The electroless Cu layer (which extends to the edges of the substrate) is electrically coupled to a power source at one of the edges and acts as a plating bus to provide electrical current for the electrolytic deposition. Conventional methods for forming surface finish layers (surface finish) on high density pads also utilize electroless plating. In electroless plating, no current is used. The metal ions are reduced by chemicals in the electroplating solution and the desired metal is deposited on all surfaces. However, as via sizes decrease and dielectric layer thicknesses increase (changing via aspect ratios), void and via pocket formation can occur during conventional electroless via filling, leading to reliability issues. In addition, electroless plating generally proceeds at a slower rate than electrolytic plating. Note that the electrolytically deposited layer is crystalline and typically has a much greater density than an electroless deposited layer. Also, for surface layer formation and subsequent solder joint formation, electroless surface treatment coatings have been found to have the drawbacks of phosphorus induced solder joint quality problems, oxidation, and poor corrosion resistance.

Certain embodiments relate to the formation of coreless substrates in which an electrolytic plating process is used to fill the vias without the need for a first electroless plating operation as in conventional processes. The electrolytic plating process utilizes an electric current passing through a solution containing dissolved metal ions, which adhere to the charged metal surface to be deposited. Certain embodiments utilize a method wherein the temporary substrate core can be used as a plating bus and then the via is filled using an electrolytic process.

Figures 1(a) -1(U) illustrate operations for forming a coreless substrate, in accordance with certain embodiments. As can be seen in fig. 1(a), a temporary substrate core 10 is provided. The core 10 may be formed of, for example, a metal such as copper. Fig. 1(B) illustrates the formation of a patterned resist layer 12 having openings 14 therein that expose the core 10. Then, multiple layers may be deposited over the core 10 within the opening 14, as shown in fig. 1 (C). A first copper layer 16 can be electrolytically plated on the core. The copper layer 16 may be removed in a later process so that a recess may be formed on the surface of the substrate. A surface treatment layer 18 may then be electrolytically plated on the first copper layer 16. One example of the surface treatment layer 18 includes sublayers of gold, palladium, and nickel. Next, a second copper layer 20 may be electrolytically plated on the surface treatment layer 18. The temporary core 10 may be connected to a power source via connection 64 and used as all or a portion of a plating bus for electrolytic deposition. Plating bus bars refer to structures for transmitting current to the area to be plated. In one aspect of the various embodiments described herein, the core acts as at least a portion of a plating bus bar during an electrolytic plating operation.

Next, as can be seen in fig. 1(D), the patterned resist 12 is removed. As shown in fig. 1(E), a dielectric layer 22 is formed over the core 10 and the electrolytic plating layers 16, 18, 20. Dielectric layer 22 may be formed from a material such as a polymer using a build-up process. One example of a suitable material is a polymeric epoxy Film known as Aginomoto Build-up Film (ABF), available from Ajinomomoto Fine-Techno Company, Inc. A via 24 may be formed in the dielectric layer 22 to expose the second copper layer 22, as shown in fig. 1 (F). The vias may be formed using any suitable technique, such as laser drilling.

The via 24 may be filled with a material (e.g., copper) using an electrolytic deposition process to form a filled via 26. As shown in fig. 1(G), the temporary core 10 may be electrically coupled to a power source through a connection 64. The bottom surface defining the via is a copper layer 20, the copper layer 20 being electrically coupled to the temporary core 10 by layers 18 and 16. The via 24 may be filled with a material that is electrolytically plated onto the copper layer 20.

Once via 24 is filled, a thin metal layer 30 may be electrolessly deposited on the surface of dielectric layer 22 and the surface of filled via 24, according to some embodiments. A photoresist layer (e.g., a dry film resist) may be formed and patterned to define openings that expose areas where conductive traces will be formed. Electrolytic deposition may then be performed to form the conductive traces 30, as shown in fig. 1 (H). The traces 30 may include a thin layer of electroless deposited metal and a thicker layer of electrolytically deposited metal. The electrolytic deposition of the traces can be performed using an electroless deposition metal coupled to a power source to provide current for electrolytic plating (as described in paragraph 11 above), or can use a core 10 coupled to a power source to provide current for electrolytic plating. The photoresist layer 30 may then be removed, as shown in FIG. 1 (I). Operations such as surface roughening and flash etching (flash etch) using, for example, conventional processes known as CZ processes may also be performed to remove the underlying electroless deposition metal.

As shown in fig. 1(J), another dielectric layer 32 (e.g., ABF) may be deposited and vias 34 formed. The vias 34 can be filled using electrolytic plating as described above to form filled vias 36, with electrical connections including paths formed through the trace layer 30, the filled vias 24, the electrolytically deposited layers 20, 18, 16, and the temporary core 10 coupled to a power supply through connections 64 during the plating operation, as shown in fig. 1 (K).

Traces 40 may be formed in the same manner as traces 30 described above, including the formation of patterned photoresist 38, as shown in fig. 1 (L). Patterned photoresist 38 may be removed and other operations such as surface roughening and flash etching performed as described above to result in the structure shown in fig. 1 (M). Additional layers of dielectric material, vias, and traces can be formed in the manner described above, if desired. Fig. 1(N) shows an additional dielectric layer 42 having an electrolytically filled via 46 with a conductive trace region 50 formed over the electrolytically filled via 46.

Another layer of dielectric material 52 may be formed over the structure as shown in fig. 1 (O). In some embodiments, the dielectric material may be a solder resist material to be used on the substrate surface. When the dielectric material 52 is formed of a resist material, it may be patterned to form openings 54, as shown in FIG. 1 (O). Multiple layers may be electrolytically formed in the openings 54. These layers may include, for example, various layers or sublayers used in suitable surface treatment layers. As shown in fig. 1(P), one example includes an electrolytically deposited nickel (Ni) layer 60, palladium (Pa) layer 58, and gold (Au) layer 56. Numerous other surface treatment layer materials may also be used. In some embodiments, after the core is removed, the uppermost layer 56 is shown having an exposed surface that can be brought into direct contact with a solder connection, such as a solder bump, and then heated to reflow the solder to form a solder contact for devices including, but not limited to, semiconductor dies.

As shown in fig. 1(Q), the temporary core 10 may be removed, thereby obtaining a coreless substrate. The temporary core 10 may be removed using any suitable method, including but not limited to etching. The first copper layer 16 deposited on the temporary core 10 may also be removed, leaving a recess 76 on the lower surface, as shown in fig. 1 (R). The recessed surface may serve as a receiving space for, for example, a contact pad or a solder bump.

In some embodiments, it is useful to be able to have a surface treatment layer that differs in different regions of the substrate. This can be achieved by using a protective film compatible with the electrolytic deposition process. As shown in fig. 1(S), a protective film 62 (e.g., a polymer film including, but not limited to, a photoresist film) is formed over a portion of the substrate. As can be seen in fig. 1(S), the two openings 54 on the right side of the substrate are covered by the film 62, and the two on the left side are uncovered. Electrolytic deposition may then be performed to form layers 60, 58, and 56, as shown in FIG. 1 (T).

As shown in fig. 1(U), the temporary core 10 (which serves as a plating bus during electrodeposition) and the protective film 62 can then be removed, resulting in a substrate with different surface finish layers at different surface areas.

It has been found that electrolytic deposition of surface treatment layers (e.g., layers 56, 58, 60) provides better oxidation resistance and solder joint reliability than electroless deposition layers.

FIG. 2 illustrates a flow diagram of operations according to certain embodiments. Block 110 is forming a conductive region on the temporary core. The temporary core may comprise a metal such as copper. Block 112 is forming a dielectric layer, such as ABF, over the conductive regions and temporary core. Block 114 is forming a via by drilling through a dielectric layer (ABF) to reach the conductive region. Block 116 is via filling with a temporary core coupled to a power source to provide a current to perform electrolytic plating. Block 118 is electroless plating and Dry Film Resist (DFR) patterning. Block 120 is electrolytic plating to complete the formation of the conductive pattern (trace). Block 122 is to remove the dry film resist, surface roughening (CZ) and form another dielectric layer (ABF) using a build-up process. Block 124 is forming vias by drilling through the dielectric layer (ABF) to reach the conductive patterns. Block 126 fills the via hole with electrolytic plating as in block 116. Block 128 is electroless plating and Dry Film Resist (DFR) patterning. Block 130 is electrolytic plating to complete formation of another conductive pattern layer.

Block 132 is a determination of whether the desired number of vias and conductive pattern layers have been achieved. If not, then return to block 124 and continue to form additional layers. If so, then proceed to block 134, block 134 is dry film resist removal, surface treatment (CZ), and solder resist deposition. A solder resist may be formed and patterned to leave openings in which a surface finish metal layer may be deposited.

Block 136 is determining whether a different surface treatment layer is required in a different area of the substrate surface. For certain types of connections, such as certain C4 connections, different surface treatments in different regions are useful.

If the answer to block 136 is no, then a surface treatment layer is then deposited in the openings of the solder resist using electrolytic plating, as per block 138. Then, after completion of the electrolytic plating, the temporary core may be removed, as indicated by block 140. If the answer to block 136 is yes, then proceed to block 142 and form a protective film on the surface at the appropriate location. Block 144 is electrodepositing a surface treatment metal layer in the openings of the solder resist. Block 146 is to remove the protective film, which may be performed using a suitable heating or etching operation. Block 148 is to form an additional protective film (protective film 2), if necessary, so that the deposition of the second surface treatment layer (SF 2) can be performed using electrolytic deposition. Then, the second protective film is removed. Block 150 is to remove the temporary core. It should be appreciated that various additions and/or modifications may be made to the above operations described in connection with fig. 2 within the scope of the various embodiments. In addition, some embodiments may involve a subset of the operations specified in FIG. 2, regardless of other operations specified in FIG. 2.

Figure 3 illustrates a portion of an assembly according to some embodiments including a coreless substrate coupled to a die 74 on one side by solder connections 78 and to a board 72 on the other side by solder connections 76. The substrate includes multiple levels of vias and routing traces (patterns) within its thickness. The substrate corresponds to the substrate shown in fig. 1(R) after coupling to the die 74 and the plate 72. The vias are filled with an electrolytic plating metal (e.g., copper) formed with the core 10 (as already removed) coupled to a power source for carrying current for the plating operation. The solder connections 76, 78 may be formed using a lead-free solder, such as SAC (tin/silver/copper) solder. In this embodiment, at least a portion of the surface finish layers on the upper and lower surfaces have reacted with the solder, and thus, the areas on the substrate at and near the interfacial solder joint may comprise reaction products such as alloys and intermetallics formed from various combinations of metals including, for example, tin, silver, copper, nickel, palladium, and gold.

An assembly including components formed as described in the above embodiments may be applied to various electronic components. FIG. 4 schematically illustrates one example of an electronic system environment in which aspects of the described embodiments may be implemented. Other embodiments need not include all of the features specified in fig. 4, and may include alternative features not specified in fig. 4.

The system 201 of fig. 4 may include at least one Central Processing Unit (CPU) 203. The CPU 203, also referred to as a microprocessor, may be a die attached to an integrated circuit package substrate 205, and the integrated circuit package substrate 205 is then coupled to a printed circuit board 207, which in this embodiment may be a motherboard 207. The CPU 203 and the package substrate 205 coupled to the board 207 are examples of electronic device assemblies that may be formed according to embodiments such as those described above. Various other system components, including but not limited to memory and other components discussed below, may also include structures formed in accordance with the above-described embodiments.

The system 201 may also include a memory 209 and one or more controllers 211a, 211b … 211n also deposited on the motherboard 207. Motherboard 207 may be a single layer or multi-layer board having a plurality of wires that provide communication between the circuitry in package 205 and other components mounted to board 207. Alternatively, one or more of the CPU 203, memory 209, and controllers 211a, 211b … 211n may be deposited on other cards such as a daughter card or an expansion card. The CPU 203, memory 209, and controllers 211a, 211b … 211n may all be located in respective sockets, or may be directly connected to a printed circuit board. A display 215 may also be included.

Any suitable operating system and various applications may execute on CPU 203 and reside in memory 209. The content residing in memory 209 may be cached in accordance with known caching techniques. Programs and data in memory 209 may be swapped into storage 213 as part of memory management operations. The system 201 may include any suitable computing device, including but not limited to a mainframe computer, server, personal computer, workstation, laptop computer, handheld gaming device, handheld entertainment device (e.g., MP3 (moving picture experts group layer 3 audio) player), PDA (personal digital assistant), telephony device (wireless or wired), network appliance, virtualization device, storage controller, network controller, router, and the like.

The controllers 211a, 211b … 211n may include one or more of the following: system controllers, peripheral controllers, memory controllers, hub controllers, I/O (input/output) bus controllers, video controllers, network controllers, memory controllers, communication controllers, and the like. For example, the memory controller may control reading and writing of data from and to the memory device 213 according to a memory protocol layer. The storage protocol of this layer may be any of a number of known storage protocols. Data written to or read from the storage device 213 may be buffered according to known caching techniques. The network controller may include one or more protocol layers for transmitting/receiving network packets to/from remote devices over the network 217. Network 217 may include a Local Area Network (LAN), the Internet, a Wide Area Network (WAN), a Storage Area Network (SAN), and the like. Embodiments may be configured to transmit and receive data over a wireless network or connection. In some embodiments, the network controller and various protocol layers may employ an ethernet protocol over unshielded twisted pair cable, a token ring protocol, a fibre channel protocol, etc., or any other suitable network communication protocol.

The terms "a" and "an" as used herein mean that there is at least one of the referenced item, and not a limitation on the quantity. In addition, terms such as "first," "second," and the like, as used herein do not necessarily denote any particular order, quantity, or importance, but rather are used to distinguish one element from another.

While certain exemplary embodiments have been described above and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive, and that embodiments are not restricted to the specific constructions and arrangements shown and described since modifications may occur to those ordinarily skilled in the art.

Claims (16)

1. A method, comprising:

providing a core comprising a metal;

forming a dielectric material on the core;

forming a via in the dielectric material, the via positioned to expose a metal region;

performing an electrolytic plating of metal in the via and on the metal region, wherein the core is electrically coupled to a power source during the electrolytic plating of metal in the via and delivers current to the metal region; and

removing the metal core after electrolytically plating metal in the via.

2. The method of claim 1, further comprising: prior to forming the dielectric material on the core,

forming a patterned photoresist layer on the metal core;

performing a step of electrolytically plating at least one metal layer in the openings of the patterned photoresist layer, wherein the core is electrically coupled to a power source during the electrolytically plating the at least one metal layer in the openings and transmits an electrical current to the at least one metal layer in the openings; and

the patterned photoresist layer is removed and the patterned photoresist layer,

wherein forming a dielectric material over the core comprises positioning the dielectric material over the core and the at least one metal layer.

3. The method of claim 1, further comprising:

performing an electroless metal plating of a metal layer on the dielectric layer and on the metal in the via;

forming a patterned resist layer on the electroless metal plating layer to define conductive trace areas; and

performing an electrolytic plating of metal on the conductive trace area to form a conductive trace.

4. The method of claim 3, further comprising:

forming an additional dielectric layer on the conductive trace and the dielectric layer;

forming an additional via in the additional dielectric layer, the additional via positioned to contact underlying metal from the conductive trace; and

performing an electrolytic plating of a metal on the underlying metal in the additional via, wherein the core is electrically coupled to a power source during electrolytic plating of the metal on the underlying metal and transfers current to the underlying metal.

5. The method of claim 4, further comprising:

performing a step of additionally electroless plating an additional metal layer on the additional dielectric layer and on the electrolytically plated metal on the underlying metal in the additional via;

forming a patterned resist layer on the additional electroless metal plating layer to define additional conductive trace areas; and

performing an electrolytic plating of metal on the additional conductive trace area to form an additional conductive trace.

6. The method of claim 5, further comprising forming a patterned solder resist layer on the additional conductive traces and the additional dielectric layer, the patterned solder resist layer including openings therein.

7. The method of claim 6, wherein the opening in the patterned solder resist layer exposes a portion of the additional conductive trace, and performing the step of electrolytically plating metal on the exposed portion of the additional conductive trace to form a surface treatment layer, wherein the core is electrically coupled to a power source and transmits current to the exposed portion during the step of electrolytically plating metal on the exposed portion of the additional conductive trace.

8. The method of claim 7, wherein the core is removed after electrolytically plating metal in the opening to form the surface treatment layer.

9. A method, comprising:

providing a core comprising a metal;

forming a dielectric material on the core;

forming a via in the dielectric material, the via positioned to expose a metal region;

performing an electrolytic plating of metal on the metal region in the via;

wherein the core is coupled to a power source and transmits current during electrolytic plating of metal on the metal region in the via;

wherein the core serves as a plating bus during electrolytic plating of metal on the metal region in the via;

forming conductive traces on the dielectric material and the filled vias after electrolytically depositing the metal in the vias;

forming a solder resist layer on the conductive traces and providing openings in the solder resist layer that expose additional metal regions;

forming a metal finish layer by electrolytically plating metal on additional metal regions in openings in the solder resist layer, wherein the core is coupled to a power source and transmits current to the additional metal regions during electrolytic plating of metal on the additional metal regions in the openings; and

removing the core after electrolytically plating metal on the additional metal region.

10. The method of claim 9, further comprising: forming a protective layer on at least one of the openings in the solder resist layer prior to forming the surface treatment layer, wherein the protective layer is formed of a material that is not electroplated by a metal during an electrolytic plating process.

11. The method of claim 9, further comprising: after the surface treatment layer is formed, the protective layer is removed.

12. The method of claim 10, further comprising: after removing the protective layer, and before removing the core, an additional protective layer is formed to cover at least some of the openings in the solder resist layer that are not covered by the previously formed protective layer.

13. The method of claim 12, further comprising: electrolytically plating metal on additional metal regions in the openings of the solder resist layer that are not covered by the additional protective layer, wherein the core is coupled to a power source and transmits current to the additional metal regions during electrolytic plating of metal on additional metal regions in the openings that are not covered by the additional protective layer.

14. A method, comprising:

providing a core material comprising a metal;

forming a plurality of layers on the core material, the layers comprising a dielectric layer and conductive paths extending within the dielectric layer;

wherein at least one of the conductive paths extends from the core to an upper surface of one of the dielectric layers;

electrolytically plating at least one metal layer on the at least one conductive path extending to the upper surface of one of the dielectric layers, wherein the core is coupled to a power source and transmits current to the at least one conductive path extending to the upper surface of one of the dielectric layers during electrolytic plating of the at least one metal layer; and

removing the core after electrolytically plating the at least one metal layer to form a coreless substrate.

15. The method of claim 14, wherein the first and second light sources are selected from the group consisting of,

wherein the at least one metal layer comprises an exposed surface treatment layer metal layer;

positioning the exposed surface treatment layer metal layer in direct contact with a solder bump; and

the solder bumps are heated to form solder joints coupling the solder bumps to the coreless substrate.

16. The method of claim 15, further comprising coupling a die to the solder bump.