HK1188026B - Bumpless build-up layer and laminated core hybrid structures and methods of assembling same - Google Patents

Description

Bumpless build-up layer and laminated core hybrid structures and methods of assembling the same

The disclosed embodiments relate to semiconductor device substrates and processes for assembling them into semiconductor device devices.

Drawings

In order to understand the manner in which embodiments are obtained, a more particular description of various embodiments briefly described above will be rendered by reference to the appended drawings. The drawings depict embodiments that are not necessarily to scale and should not be considered limiting of scope. Some embodiments will be described and illustrated in more detail through the use of the accompanying drawings, in which:

fig. 1a is a cross-sectional elevation view of a semiconductor device substrate during processing according to an example embodiment;

FIG. 1b is a cross-sectional elevation view of the semiconductor device substrate shown in FIG. 1a after further processing in accordance with an embodiment;

FIG. 1c is a cross-sectional elevation view of the semiconductor device substrate shown in FIG. 1b after further processing in accordance with an embodiment;

FIG. 1d is a cross-sectional elevation view of the semiconductor device substrate shown in FIG. 1c after further processing in accordance with an embodiment;

FIG. 1e is a cross-sectional elevation view of the semiconductor device substrate shown in FIG. 1d after further processing in accordance with an embodiment;

FIG. 1f is a cross-sectional elevation view of the semiconductor device substrate shown in FIG. 1e after further processing in accordance with an embodiment;

fig. 1g is a cross-sectional elevation view of a semiconductor device apparatus including a BBUL structure and a stacked-core structure during assembly, according to an example embodiment;

fig. 1h is a cross-sectional elevation view of the semiconductor device arrangement shown in fig. 1g after further processing in accordance with an embodiment;

fig. 1j is a cross-sectional elevation view of the semiconductor device arrangement of fig. 1h after further processing in accordance with an embodiment;

FIG. 1k is a cross-sectional elevation view of the semiconductor device arrangement shown in FIG. 1j after further processing in accordance with an embodiment;

fig. 2 is a cross-sectional elevation view of a package-on-package semiconductor device apparatus according to an example embodiment;

fig. 3 is a cross-sectional elevation view of a semiconductor device arrangement according to an example embodiment;

fig. 4 is a cross-sectional elevation view of a package-stacked semiconductor device arrangement according to an example embodiment;

fig. 5 is a cross-sectional elevation view of two back-to-back semiconductor device arrangements during processing according to an example embodiment;

FIG. 6 is a process and method flow diagram in accordance with various embodiments; and

fig. 7 is a schematic diagram of a computer system, according to an embodiment.

Detailed Description

Reference will now be made to the drawings in which like structures may be provided with like subscript reference numerals. The drawings contained herein are diagrammatic representations of integrated circuit structures in order to more clearly illustrate the structure of various embodiments. Thus, the actual appearance of the fabricated integrated circuit structures (e.g., in a photomicrograph) may vary, but still include the structures of the illustrated embodiments as claimed. Furthermore, the drawings may show only structures useful for understanding the illustrated embodiments. Additional structures known in the art are not included to maintain clarity of the drawings.

Fig. 1a is a cross-sectional elevation view of a semiconductor device substrate 100 during processing according to an example embodiment. The semiconductor device substrate 100 includes a dual-foil structure of a second foil film 110, an etching stopper film 112, and a first foil film 114. In an embodiment, the foil is two copper layers separated by an etch stop layer, such as an organic film. In an embodiment, the etch stop film 112 is a solder resist material that is impermeable to copper etch chemistries.

The thickness (measured in the Z-direction) of the first foil film 114 may be dictated by a given die thickness that will be embedded within the second foil film 114 after etching the die cavity.

Fig. 1b is a cross-sectional elevation view of the semiconductor device substrate shown in fig. 1a after further processing in accordance with an embodiment. The semiconductor device substrate 101 has been processed by patterning the dry film and etching cavities 116 in the first foil film 114. Semiconductor devices such as die 118 have been placed on the etch stop film 112. In an embodiment, the die 118 is attached by coating the adhesive 120 in the cavity 116 or by pre-attaching an adhesive film 120 to the back side of the die prior to placement of the die 118. Adhesive film 120 is shown in fig. 1b, and although not shown, may also be present in selected embodiments unless explicitly excluded.

Fig. 1c is a cross-sectional elevation view of the semiconductor device substrate shown in fig. 1b after further processing in accordance with an embodiment. The semiconductor device substrate 102 has been processed by laminating the first dielectric film 122 on the entire panel constituting the semiconductor device substrate 102 when approaching from the negative Z direction. As shown, the die 118 has been encapsulated by a lamination process.

In an embodiment, the first dielectric film 122 is attached after a rough grinding is performed on the first foil film 114 to facilitate attachment of the first dielectric film 122. In an embodiment, a chemical etch that forms the recesses 116 in the first foil film 114 is performed prior to placement of the die 118. The chemical etching facilitates rough grinding of the first foil film 114. Hereinafter, the first dielectric film 122 may be referred to as a bumpless build-up layer (BBUL) first film 122 unless explicitly noted otherwise.

Fig. 1d is a cross-sectional elevation view of the semiconductor device substrate shown in fig. 1c after further processing in accordance with an embodiment. The semiconductor device substrate 103 has been processed to form die vias 124 into the BBUL first film 122 to open contacts to the die 118. Die via 124 is formed by laser drilling and subsequent desmear cleaning to clean resin smear from the bottom of the die via and roughen the surface of first dielectric film 122 for further build up processing.

Fig. 1e is a cross-sectional elevation view of the semiconductor device substrate shown in fig. 1d after further processing in accordance with an embodiment. The semiconductor device substrate 104 is processed by a semi-additive process (SAP) to fill the first contact 126 to the die via 124 (fig. 1 d) and form a first contact pad 128. After forming the contacts 126 and the first contact pads 128, a semi-additive process (SAP) is used to couple the die 118 to further build-up layers of the outside world.

Fig. 1f is a cross-sectional elevation view of the semiconductor device substrate shown in fig. 1e after further processing in accordance with an embodiment. The semiconductor device substrate 105 is processed with the second BBUL film 130 along with the second BBUL contact 132 (one of which is enumerated) and the second BBUL contact pad 134. It can also be seen that a subsequent BBUL film 136 has been formed as the last BBUL layer in the illustrated embodiment. Further, a subsequent BBUL contact 138 and a subsequent BBUL contact pad 140 are associated with the subsequent BBUL film 136. The subsequent BBUL contact pads 140 are exposed through a laminated core interface mask 142. The subsequent BBUL film 136 and the subsequent BBUL contact pads 140 form a stacked-core interface 144, as further described in this disclosure.

The BBUL third film 130 can be seen abutting a subsequent BBUL film 136. It can now be understood that there can be more BBUL films than three such BBUL films, such that a subsequent BBUL film 136 can have a BBUL film other than the second BBUL film 132 adjacent thereto. In other words, the third BBUL film, along with the dependent third BBUL contacts and third contact pads, can be located between the second BBUL film 132 and the subsequent BBUL film 136. It can now also be appreciated that there may be more films beyond the third BBUL film, followed by the subsequent BBUL film 136 and the subsequent BBUL contact pads 140, forming a stacked core interface 144, depending on the given application requirements. In an embodiment, the first BBUL film 122, the second BBUL film 130, and the subsequent BBUL film 136 are supplemented by a third BBUL film that is contiguous with each of the second BBUL film 130 and the subsequent BBUL film 136. In an embodiment, the first BBUL film 122, the second BBUL film 130, and the subsequent BBUL film 136 are disposed between and are complementary to the third and fourth BBUL films that are adjacent to the second BBUL film 130 and the subsequent BBUL film 136. More BBUL films can be fabricated in BBUL structures where useful for a given application of the effect.

Hereinafter, the BBUL structure that includes the beginning with the first BBUL film 122 and the ending with the subsequent BBUL contact pads 140 and interface mask 142 may be referred to as the BBUL structure 146.

Fig. 1g is a cross-sectional elevation view of a semiconductor device apparatus 106 including a BBUL structure 146, a die 118 embedded therein, and a stacked-core structure 148 during assembly according to an example embodiment.

The laminated core structure 148 is processed by mechanically drilling through holes 150 in the laminated core 152. As a non-limiting example embodiment, the laminated core 152 may include an organic bulk material 152 and metal interlayers 154, 156, and 158. Three metal interlayers are described, but more or fewer may be present. In an embodiment, only one metal interlayer is present. In embodiments, there are 4 to 10 metal interlayers. It is also seen that metal interlayers 154, 156 and 158 short circuit (occur twice) the two PTHs to each other. More than two PTHs may be shorted to each other by using at least one metal interlayer, depending on the given power or signaling requirements of a given die 118.

In an embodiment, the laminated core 148 is a prepreg material, such as a woven glass and epoxy (FR 4) material. Other structures may be used for the laminated core 148 depending on a given application.

In an embodiment, the width (measured in the X direction) of each through hole 150 is in a range from 100 micrometers (μm) to 350 μm. In an embodiment, the width of each through hole 150 is in a range from 100 μm to 350 μm. According to embodiments, the thickness (measured in the Z-direction) of the laminated core structure 148 as a whole may be in the range from 400 μm to 1400 μm. In an embodiment, through-hole 150 is drilled with a mechanical drill such that through-hole 150 has a substantially vertical cylindrical form factor, with width and thickness embodiments serving as dimensional descriptions. In an embodiment, the width of through-hole 150 is 100 μm and the thickness is 400 μm. In an embodiment, the width of the through-hole 150 is 100 μm and the thickness is 1400 μm. In an embodiment, the width of through-hole 150 is 350 μm and the thickness is 400 μm. In an embodiment, the width of through-hole 150 is 350 μm and the thickness is 1400 μm.

After drilling through hole 150, desmear, electroless Cu and electrolytic Cu plating are performed to form Plated Through Hole (PTH) 160, which may be referred to as first plating 160 on the PTH wall. The plated Cu on both surfaces of the laminated core structure 148 is removed by mechanical grinding.

The semiconductor device apparatus 106 is shown assembled in the Z-direction with directional arrows such that the stacked-core interface 144 of the BBUL structure 146 mates with the stacked-core 148 at several subsequent BBUL bond pads 140.

Fig. 1h is a cross-sectional elevation view of the semiconductor device arrangement shown in fig. 1g after further processing in accordance with an embodiment. The semiconductor device arrangement 107 is processed by removing the foil structure to expose the die 118 at its backside 119. The semiconductor device arrangement 107 now has an exposed die side 184. The active side 117 of the die 118 is also referred to as the active surface 117. The active surface 117 is in contact with the first contact 126 (see fig. 1 e). It may now be appreciated that cooling schemes such as heat sinks, heat spreaders, heat fins, etc. may be assembled adjacent to the die backside 119.

Further processing includes plating the PTH160 by a rapid electroless plating technique to form an electrical conductor, i.e., the enhanced plating layer 162 according to an embodiment. A reinforcement plating 162 is formed on the sidewalls of the PTH160 and on the subsequent BBUL bond pads 140. The reinforcement plating 162 can also be described as a hollow cylinder closed at one end to form a cup shape. At its closed end, the reinforcement plating 162 forms a connection with the subsequent bond pad 140. The process of forming the electrical conductor 162 results in a connection with a subsequent bond pad 140, which subsequent bond pad 140 integrates the electrical conductor 162 with the BBUL structure 146 and the laminated-core structure 148. Thus, an integrated structure is realized through the process of forming the conductive body 162.

In an embodiment, electroless copper plating techniques are used to form the enhanced plating layer 162 to form useful electrical connections between the laminated core structure 148 and the BBUL structure 146. In an example embodiment, the electroless copper plating process is performed by copper plating of the PTH160 and BBUL subsequent bond pads 140. Thus, due to the autocatalytic nature of electroless Cu plating (no catalyst need be applied if Cu is already present on existing surfaces to be plated), pre-treatment processes on these surfaces can be avoided. In an embodiment, the enhanced plating layer 162 is formed at a thickness rate of 8 μm/hr, and a useful rate range is 2-10 μm/hr. Modifications of the processing conditions to achieve different plating rates may include temperature, solution agitation, and copper chemical solution dissolved in an aqueous alkaline (e.g., NaOH) formaldehyde mixture.

In an exemplary embodiment, the fast electroless plating is performed by using a copper solution of ethylenediaminetetraacetic acid (EDTA) at a PH of 13 and a temperature of 50 ℃ using cytosine as a stabilizer. In an exemplary embodiment, the fast electroless plating is performed by using a copper solution of EDTA at PH 13 and a temperature of 50 ℃ using benzotriazole as a stabilizer. In an exemplary embodiment, the fast electroless plating is performed by using a copper solution of EDTA at pH 13 and a temperature of 50 ℃ using 2-mercaptobenzothiazole as a stabilizer. In an embodiment, the enhanced plating layer 162 is formed using electroless copper plating.

Fig. 1j is a cross-sectional elevation view of the semiconductor device shown in fig. 1h after further processing in accordance with an embodiment. The semiconductor device arrangement 108 is processed by filling the PTH160 and the enhanced plating 162 with PTH plugs 164. For example, the air-core stack 148 includes an organic material with an inorganic particulate filler. In an embodiment, the PTH plug 164 is an epoxy material with a silica particulate filler. Thus, when the PTH plug 164 is non-magnetic, it may be referred to as an "air core" PTH plug 164. The PTH plug 164 may be formed by forcing a flowing filler material 164 into the PTHs 160 and 162, curing and planarizing the bottom 166 to remove any external plug material that is not within the form factor of the PTHs 160 and 162.

Further processing may be performed to form a land interface or land-side structure, which may be implemented at the bottom 166.

Fig. 1k is a cross-sectional elevation view of the semiconductor device arrangement shown in fig. 1j after further processing in accordance with an embodiment. The semiconductor device arrangement 109 has been processed with a paddle-side film 168 formed on a stack-die paddle interface bond pad 170 along with a stack-die interface contact 172 formed in the paddle-side film 168. It is also seen that a land-side contact pad 174 is formed on the laminated core interface contact 172, which land-side contact pad 174 is further exposed through a land-side mask 176. The stacked die bond area interface bond pads 170 are formed by a blanket Cu plating process and a subtractive etching process.

After roughening the stack core land interface bonding pads 170 with a Cu etching solution, the land side film 168 is laminated. The laminated core interface contact 172 is formed by laser drilling, desmear cleaning and surface roughening of the via bottom, and semi-additive processing (SAP) for Cu fill and formation of the land side contact pad 174.

Hereinafter, the structure including the stacked core land interface bond pads 170 as the beginning and the land side contact pads 174 and the land side mask 176 as the end (in the negative Z direction) may be referred to as the land side structure 178. It can now be appreciated that the land side structures 178 can be formed by a semi-additive process.

The semiconductor device arrangement 109 may be assembled in various configurations according to given functional requirements. In an embodiment, the semiconductor device arrangement 109 is a two-level arrangement with interconnections to a ball grid array. In an embodiment, the semiconductor device arrangement 109 is a two-level arrangement with interconnects to a pin grid array. In an embodiment, the semiconductor device arrangement 109 is a two-level arrangement with interconnects to a land grid array.

In an embodiment, the semiconductor device arrangement 109 is assembled to the base substrate 190 at the electrical bumps 192. According to an embodiment, the semiconductor device arrangement 109 may be mounted to the base substrate 190 by bringing the land-side contact pads 174 into contact with the electrical bumps 192.

In an example embodiment, the semiconductor device arrangement 190 is a device holding a semiconductor device such as a macro die 118 (such asA processor), and semiconductor device arrangement 109 is assembled to or part of a server slice as one of a plurality of large die. In this embodiment, the base substrate 190 represents a connection to a server slice, and the surface 194 may represent an orientation in which the base substrate 190 obtains power and communications to service a large die 118.

In an example embodiment, the base substrate 190 is a motherboard in the case where the semiconductor device arrangement 109 is part of a handheld device (such as a smartphone embodiment or a handheld reader embodiment). In an example embodiment, where the semiconductor device apparatus 109 is part of a handheld device (such as a smartphone embodiment or a handheld reader embodiment), the base substrate 190 is a housing, such as the portion that a user touches while in use. In an example embodiment, where the semiconductor device apparatus 109 is part of a handheld device (such as a smartphone embodiment or a handheld reader embodiment), the base substrate 190 includes a motherboard and a housing (such as a portion that a user touches while in use). The semiconductor device apparatus 109 may also be referred to as a BBUL structure and stacked-core structure hybrid apparatus.

Fig. 2 is a cross-sectional elevation view of a Package On Package (POP) semiconductor device apparatus 200 according to an example embodiment. The semiconductor device arrangement 200 is similar to the semiconductor device arrangement 109 depicted in fig. 1k, but with variations in processing and structure. In an embodiment, during formation of BBUL structure 246, first film 222 is processed to have die-side contacts 280 and first contacts 226 that are directly coupled to die 218. After peeling the foil, the die-side contact 280 is connected to a die-side contact pad 282 for interfacing with an electronic device on the package die side 284.

It may now be appreciated that a package-on-package (POP) device 286 may be constructed by assembling a top package 286 to the semiconductor device 200 at the die-side contact pads 282. In an embodiment, top package 286 is a memory module that serves as a cache for semiconductor device 218. In an embodiment, top package 286 is an RF device that serves as a transceiver for semiconductor device 218. In an embodiment, the top package 286 includes active devices and a cooling scheme at the die backside 219. In an embodiment, the top package 286 includes a cooling scheme and passive devices at the die backside 219.

It may now be appreciated that a base substrate, such as the base substrate 190 depicted in fig. 1k, may be assembled to the semiconductor device arrangement 200 according to several disclosed embodiments. It can also be appreciated that the top package 286 can function as a housing similar to the base substrate, but on the opposite side of the semiconductor device arrangement 200.

Fig. 3 is a cross-sectional elevation view of a semiconductor device apparatus 300 according to an example embodiment. The semiconductor device arrangement 300 is similar to the semiconductor device arrangement 109 depicted in fig. 1k, but with variations in processing and structure. In an embodiment, during the formation of the BBUL structure 346, the plurality of dies 118 and 318 are processed into a foil structure, similar to the dual foil structure of the second foil film 110, the etch stop film 112, and the first foil film 114 shown in fig. 1 a.

In an embodiment, the first die 118 is a processor and the subsequent die 318 is also a processor, such as a dual core system in a packaged (SiP) semiconductor device apparatus 300. In an embodiment, the first die 118 is a processor and the subsequent die 318 is an integrated processor and graphics device, such asA device. In an embodiment, the first die 118 is a die such asA processor such as a processor and the subsequent die 318 are RF-intensive devices that enable the semiconductor device 300 to be mounted in a smart phone. In an embodiment, the first die 118 is a processor and the subsequent die 318 serves as a Platform Controller Hub (PCH) that contains the conventional functions of a south bridge and a north bridge. In an embodiment, the first die 118 is a processor and the subsequent die 318 acts as a discrete graphics controller.

The conventional structure of the semiconductor device 300 may be similar to those depicted in other embodiments, such as the BBUL structure 346, the stacked-core structure 318, and the land-side structure 178.

It may now be appreciated that a base substrate similar to the base substrate 190 shown in fig. 1k may be assembled to the semiconductor device arrangement 300 according to several disclosed embodiments.

It may now also be appreciated that the semiconductor device apparatus 300 may include a second die in addition to the first die 118 and the subsequent die 318. It may now also be appreciated that the semiconductor device apparatus 300 may include a plurality of dies in addition to the first die 118 and the subsequent die 318.

Fig. 4 is a cross-sectional elevation view of a semiconductor device apparatus 400 according to an example embodiment. The semiconductor device apparatus 400 is similar to the semiconductor device 200 depicted in fig. 2, but with variations in processing and structure. In an embodiment, during formation of BBUL structure 446, first film 422 is processed to have die-side contacts 480 and first contacts 226 directly coupled to first die 218 and additional first subsequent contacts 426 directly coupled to subsequent die 418. After stripping the foil, the die-side contacts 480 are connected to the die-side contact pads 482 for interfacing with the electronic device on the package die side 484. It may now be appreciated that a POP device may be constructed by assembling a top package to the semiconductor device arrangement 400 at the die-side contact pad 482. In an embodiment, the top package is a memory module that serves as a cache for semiconductor device 218. In an embodiment, the top package is an RF device that functions as a transceiver for semiconductor device 218. In an embodiment, the top package includes an active device and a cooling scheme at the backside of the die. In an embodiment, the top package includes a cooling scheme and passive devices at the backside of the die.

In an embodiment, during formation of BBUL structure 446, plurality of dies 218 and 418 are processed into a foil structure, similar to the dual foil structure of second foil film 110, etch stop film 112, and first foil film 114 shown in fig. 1 a. In an embodiment, the first die 218 is a processor and the subsequent die 418 is also a processor, such as a dual core system in a packaged (SiP) semiconductor device apparatus 400. In an embodiment, first die 218 is a processor and subsequent die 418 is an integrated processor and graphics device, such asProvided is a device. In an embodiment, the first die 218 is a die such asA processor such as a processor and the subsequent die 418 are RF-intensive devices that enable the semiconductor device 400 to be mounted in a smart phone.

Additional structures of semiconductor device 400 may be similar to those depicted in other embodiments, such as BBUL structure 446, stacked-core structure 448, and land-side structure 478. It may now be appreciated that the disclosed POP device embodiments may be constructed by assembling a top package to the semiconductor device arrangement 400 at the die-side contact pad 482.

It may now be appreciated that a base substrate similar to the base substrate 190 shown in fig. 1k may be assembled to the semiconductor device arrangement 400 according to several disclosed embodiments.

It may now also be appreciated that the semiconductor device apparatus 400 may include a second die in addition to the first die 118 and the subsequent die 418 by extending the assembly in the X-direction. It may now also be appreciated that the semiconductor device apparatus 400 may include a plurality of dies in addition to the first die 118 and the subsequent die 418.

Fig. 5 is a cross-sectional elevation view of two back-to-back semiconductor device arrangements 500 during processing according to an example embodiment. A similar process starting at fig. 1a and continuing to fig. 1f may be appreciated for the apparatus 500 and with the additional processing factor that the semiconductor device substrate 500 is processed to have a back-to-back BBUL configuration including the first die 118 and the duplicate die 518. It can now be understood that the first die 118 is positioned within a cavity in the first foil 114 and the second die 518 is positioned within a cavity in the first foil 110.

It can be seen that the semiconductor device substrate 500 has been processed with the second BBUL films 130 and 530 along with the second BBUL contacts 132 and 532 and the second BBUL contact pads 134 and 534, respectively. It is also seen that subsequent BBUL films 136 and 536 have been formed into the final BBUL layer. Further, subsequent BBUL contacts 138 and 538 and subsequent BBUL contact pads 140 and 540 are associated with subsequent BBUL films 136 and 536. Subsequent BBUL contact pads 140 and 540 are further exposed through the stacked core interface masks 142 and 542. The subsequent BBUL films 136 and 536 and subsequent BBUL contact pads 140 and 540 form stacked-core interfaces 144 and 544, as already described in this disclosure.

It can now be understood that there can be more BBUL films than the three separately described BBUL films, such that subsequent BBUL films 136 and 536 can have BBUL films other than the second BBUL films 132 and 532 adjacent thereto. In other words, the third film and the repeating third BBUL film, along with the dependent third and repeating third BBUL contacts and contact pads, can be located between the second BBUL films 132 and 532 and the subsequent BBUL films 136 and 536. It can now also be understood that there may be a third film and more BBUL films in addition to the third BBUL film repeated, followed by subsequent BBUL films 136 and 536 and subsequent BBUL contact pads 140 and 540 forming stacked core interfaces 144 and 544, depending on the requirements of a given application.

The BBUL structures that include the beginning with the first BBUL films 122 and 522 and the ending with the subsequent BBUL contact pads 140 and 540 and interface masks 142 and 542 may be referred to as respective BBUL structures 146 and 546.

It can now be seen that the process continuing at figure 1g can proceed back-to-back up to a stripped back-to-back structure such as that performed at figure 1 h. It is also understood that POP packages may be manufactured by similar back-to-back methods according to several disclosed embodiments. Also, a back-to-back plurality of first and subsequent dies, such as first die 218 and subsequent die 418 and back-to-back first die and subsequent die, may be processed, which are later separated into similar structures, such as shown in fig. 4.

Fig. 6 is a process and method flow diagram 600 in accordance with various embodiments.

At 610, the process includes embedding a semiconductor device in the BBUL structure. In a non-limiting example embodiment, the die 118 in fig. 1 a-1 k is embedded in the BBUL structure 146. It may now be appreciated that more than one semiconductor die, such as the first die 118 and the subsequent die 318, may be assembled into the BBUL structure 346. It is also appreciated that a second die may be present in addition to the first die 118 and the subsequent die 318.

At 612, the process includes assembling the BBUL structure back-to-back with a second BBUL structure. In a non-limiting exemplary embodiment, the first BBUL structure 146 is fabricated simultaneously and back-to-back with the second BBUL structure 546. In an embodiment, the throughput is substantially doubled. It can now be appreciated that warpage issues during BBUL structure fabrication can be reduced by back-to-back simultaneous processing.

At 620, the process includes assembling the BBUL structure into a stacked core to fabricate integrated electrical connections. The meaning of "integrated electrical connection" includes enhancing the chemical bonding of plating layer 162 to PTH160 and subsequent bond pad 140. By this processing embodiment, an integrated structure of the BBUL structure 146 and the stacked-core structure 148 is realized.

At 630, the process includes the definition that the integrated electrical connection is a cup-shaped cylindrical plated through hole. In a non-limiting exemplary embodiment, the enhanced plating layer 162 forms such a shape during electroless copper plating of the PTH160 and subsequent bond pad 140. It may now be appreciated that other shapes may be formed to achieve integrated electrical connections, depending on the form factor of the through holes formed in the laminated core structure.

At 640, the process includes assembling the semiconductor device arrangement into a land-side structure. In a non-limiting exemplary embodiment, the land-side structure 178 is fabricated on the laminated core structure 148 by a semi-additive processing technique. In an embodiment, the process starts at 610 and ends at 640.

At 642, a method embodiment includes assembling the top package to the BBUL structure to form a POP BBUL package. In a non-limiting example embodiment, the POP device is constructed by assembling the top package 286 to the semiconductor device arrangement 200 at the die-side contact pads 282. It is also appreciated that a cooling scheme may be included in the top package 286, particularly where the die backside 219 may abut the top package 286. In an embodiment, the method starts and ends at 642.

At 650, a method embodiment includes assembling a semiconductor device arrangement to a base substrate at a land-side structure. In a non-limiting example embodiment, the base substrate 190 is part of a server slice. It is also appreciated that the method at 650 includes assembling the first die 118 and the subsequent die 318 into a computer system.

Fig. 7 is a schematic diagram of a computer system 700, according to an embodiment. As depicted, the computer system 700 (also referred to as electronic system 700) may embody any BBUL structure and stacked-core structure hybrid device in accordance with any of the several disclosed embodiments as set forth in this disclosure and their equivalents. Computer system 700 may be part of a server slice. The computer system 700 may be a mobile device, such as a netbook computer. Computer system 700 may be a mobile device, such as a wireless smart phone. The computer system 700 may be a desktop or laptop computer. The computer system 700 may be a handheld reader. The computer system 700 may be integrated into an automobile. The computer system 700 may be integrated into a television.

In one embodiment, electronic system 700 is a computer system that includes a system bus 720 for electrically coupling various components of electronic system 700. According to various embodiments, system bus 720 is a single bus or any combination of busses. Electronic system 700 includes a voltage source 730 that provides power to integrated circuit 710. In some embodiments, the voltage source 730 provides current to the integrated circuit 710 through the system bus 720.

According to an embodiment, integrated circuit 710 is electrically coupled to system bus 720 and includes any circuit or combination of circuits. In an embodiment, the integrated circuit 710 includes any type of processor 712. As used herein, the processor 712 may represent any type of circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, the processor 712 is such as disclosed hereinA large die such as a processor. Other types of circuits that may be included in the integrated circuit 710 are custom circuits or Application Specific Integrated Circuits (ASICs), such as a communications circuit 714 for wireless devices, such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic devices. In an embodiment, the processor 710 includes on-die memory 716, such as Static Random Access Memory (SRAM). In an embodiment, the processor 710 includes embedded on-die memory 716, such as embedded dynamic random access memory (eDRAM).

In an embodiment, the integrated circuit 710 is complementary to a subsequent integrated circuit 711 coupled to the integrated circuit 710. In an embodiment, the integrated circuit 710 is complementary to a subsequent integrated circuit 711, such as a graphics processor connected to the more general process 710. Useful embodiments include dual processor 713, dual communication circuit 715, and dual on-die memory 717, such as SRAM. In an embodiment, dual integrated circuit 710 includes embedded on-die memory 717, such as eDRAM.

In an embodiment, the electronic system 700 further includes an external memory 740, which in turn may include one or more memory elements suitable to the particular application, such as a main memory 746 in the form of RAM, one or more hard drives 744, and/or one or more drives that handle removable media 746 such as floppy disks, Compact Disks (CDs), Digital Versatile Disks (DVDs), flash memory drives, and other removable media known in the art. According to an embodiment, the external memory 740 may also be an embedded memory 748. In an example embodiment, die 170 is similar to first die 118, and die 711 is similar to subsequent die 318.

In one embodiment, electronic system 700 further includes a display device 750, an audio output 760. In an embodiment, the electronic system 700 includes an input device such as a controller 770 that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system 700. In an embodiment, the input device 770 is a camera. In one embodiment, the input device 770 is a digital sound recorder. In one embodiment, the input device 770 is a camera and a digital sound recorder.

The computer system 700 may also include a passive device 780 coupled to an active device such as the integrated circuit 710. In an embodiment, the passive device 780 is an inductor for an RF circuit.

The base substrate 790 may be part of the computing system 700. In an embodiment, the base substrate 790 is part of a server slice. In an embodiment, the base substrate 790 is a motherboard that holds semiconductor devices having BBUL structure and stacked-core structure hybrid device embodiments. In the embodiment, the base substrate 790 is a board on which a semiconductor device having a BBUL structure and a stacked-core structure hybrid device is mounted. In an embodiment, the base substrate 790 contains at least one of the functions encompassed within the dashed line 790 and is a substrate such as a subscriber shell of a wireless communicator.

As shown herein, the integrated circuit 710 may be implemented in a number of different embodiments, including a single interface interconnect in a die, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly including a BBUL structure and stacked-core structure hybrid device, in accordance with any of the several disclosed embodiments as set forth in the several embodiments herein, and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can be varied to suit particular I/O coupling requirements, including the number of array contacts, array contact configurations of BBUL structure and stacked-core structure hybrid devices in accordance with any of the several BBUL structure and stacked-core structure hybrid device embodiments disclosed, and equivalents thereof.

Although the die may refer to a processor chip, an RF chip or a memory chip may be referred to in the same sentence, however this should not be understood as they have an equivalent structure. Reference throughout this disclosure to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this disclosure are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Terms such as "upper", "lower", "above" and "below" may be understood by reference to the X-Z coordinates shown, and terms such as "adjacent" may be understood by reference to X-Y or non-Z coordinates.

The abstract is provided to comply with 37c.f.r. § 1.72(b), which requires an abstract to be present to allow the reader to quickly ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the invention require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment.

It will be readily understood by those skilled in the art that various other changes in the details, materials, and arrangements of the parts and method stages which have been described and illustrated in order to explain the nature of this invention may be made without departing from the principles and scope of the invention as expressed in the subjoined claims.

Claims (15)

1. A semiconductor device, comprising:

a semiconductor die embedded in the bumpless build-up layer BBUL structure; and

a laminated-core structure abutting the BBUL structure, wherein the laminated-core structure and the BBUL structure are electrically coupled by an electrical conductor integrated into both, the electrical conductor being a hollow cylinder closed at one end, wherein the laminated-core structure includes a copper plated through hole.

2. The apparatus of claim 1, wherein the BBUL structure includes a copper subsequent bond pad, wherein the electrically conductive body is copper fused to a copper plated through hole and to a copper subsequent bond pad.

3. The apparatus of claim 1, wherein the copper plated through hole has a width in a range of 100 μ ι η to 120 μ ι η and a thickness in a range of 400 μ ι η to 1400 μ ι η, wherein the BBUL structure includes a copper subsequent bond pad, wherein the electrically conductive body is copper fused to the copper plated through hole and to the copper subsequent bond pad.

4. The apparatus of claim 1, wherein the electrical conductor is fused to a copper plated through hole in the laminated core structure and to a subsequent bond pad on the BBUL structure.

5. The apparatus of claim 1, wherein the semiconductor die is a first die, the apparatus further comprising a subsequent die embedded in the BBUL structure.

6. The apparatus of claim 1, wherein the BBUL structure includes a die side, the apparatus further including a die side contact pad.

7. The apparatus of claim 1, wherein the BBUL structure includes a die side, the apparatus further comprising:

a die-side contact pad; and

a package-on-package device mounted on the BBUL structure on the die side and electrically coupled to the die-side contact pads.

8. The apparatus of claim 1, further comprising a base substrate, wherein the laminated core structure is mounted to the base substrate.

9. A semiconductor device, comprising:

a die embedded in a bumpless build-up layer, BBUL, wherein the die includes an active surface and a backside surface, the BBUL comprising:

a first dielectric film and a first contact disposed in the first dielectric film and in contact with the die at the active surface; and

a subsequent dielectric film and a subsequent contact disposed in the subsequent dielectric film, wherein the subsequent contact is coupled to the first contact and further comprises a subsequent contact pad;

a laminated core structure assembled at the subsequent contact pad, the laminated core further comprising:

plating copper through holes;

an electrical conductor fused to the copper plated through hole and subsequent contact pad, the electrical conductor being a hollow cylinder closed at one end, wherein the laminated core structure comprises: a land side structure comprising:

land-side contact pads coupled to the copper plated through holes at the stacked-core land interface bond pads.

10. The device of claim 9, further comprising a base substrate assembled at the land-side contact pads.

11. The device of claim 9, wherein the BBUL structure includes a copper subsequent bond pad, wherein the electrically conductive body is copper fused to a copper plated through hole and fused to a copper subsequent bond pad.

12. The device of claim 9, wherein the copper plated through hole has a width in a range of 100 μ ι η to 350 μ ι η and a thickness in a range of 400 μ ι η to 1400 μ ι η, wherein the BBUL structure includes a copper subsequent bond pad, and wherein the electrically conductive body is copper fused to the copper plated through hole and to the copper subsequent bond pad.

13. The device of claim 9, wherein the semiconductor die is a first die, the device further comprising a subsequent die embedded in the BBUL structure.

14. The device of claim 9, wherein the BBUL structure includes a die side, the device further including a die side contact pad.

15. The device of claim 9, wherein the BBUL structure includes a die side, the device further comprising:

a die-side contact pad; and

a package-on-package device mounted on the BBUL structure on the die side and electrically coupled to the die-side contact pads.