HK1187161B - Method of forming a switched mode power supply controller device with an off mode and structure therefor - Google Patents

Description

Method of forming a switch mode power supply controller having an off mode and structure therefor

Technical Field

The present invention relates generally to electronic products, and more particularly to semiconductors, structures thereof, and methods of forming semiconductor devices.

Background

Current switch-mode power supply controllers seek to maintain the output voltage level within a range (e.g., within Vcc-stop and Vcc-start) and send drive signals to regulate the voltage within this range. Such adjustment can occur regardless of whether the initially applied load changes or does not change, for example, if there is a load voltage initially available on the system, the system will adjust the output voltage to provide the load voltage. However, if conditions change such that there is no longer any load for a period of time, then typical controller systems cannot provide a disconnect mode that allows the output voltage to fall outside the range while there may still be a bit of load voltage and again provide rapid adjustment when the load can be re-detected. If a disconnected mode can be provided, its implementation typically requires additional pins to the chip configuration, which prevents a simple plug-and-play implementation with existing pin connections, thus making such a solution difficult to implement in an unmodified system.

Accordingly, it would be desirable to have a method of providing an off mode in a power supply controller, wherein the semiconductor configuration does not require any additional pins to implement the off mode.

Disclosure of Invention

According to an aspect of the present invention, there is provided a semiconductor voltage controller including: a start-up mode circuit associated with a start-up mode; and an off mode circuit associated with an off mode, wherein the voltage controller can be configured to receive the feedback signal and the off mode signal from a single input and provide the output voltage, the voltage controller can be configured to be in the off mode when the feedback signal is less than the skip level and the feedback signal is less than the HV control level, and the voltage controller can be configured to be in the startup mode when the feedback signal is greater than the HV control level and Vcc is less than Vcc-start.

In one embodiment of the invention, the voltage controller can be configured to begin generating the drive signal and the voltage supply signal if the feedback signal is greater than the HV control level while in the off mode, the voltage controller can be configured to stop the voltage supply signal when Vcc is approximately equal to Vcc-start, and the voltage controller can be configured to stop the drive signal when the feedback signal is approximately less than an adjusted low value corresponding to the skip level.

In another embodiment of the invention, the voltage controller can be configured to begin generating the voltage supply signal and the drive signal if the slope of the feedback signal over time is positive and if the feedback signal is approximately equal to the HV control level when in the off mode, the voltage controller can be configured to stop the voltage supply signal when Vcc is approximately equal to Vcc-start, and the voltage controller can be configured to stop the drive signal when the slope of the feedback signal is negative and the feedback signal is approximately equal to an adjusted low value corresponding to the skip level.

In another embodiment of the invention, the voltage controller can be configured to begin generating the voltage supply signal if the slope of the feedback signal over time is positive and if the feedback signal is approximately equal to the HV control level when in the off mode, the voltage controller can be configured to stop the voltage supply signal when Vcc is approximately equal to Vcc-start, and the voltage controller can be configured to start the drive signal when Vcc is approximately equal to Vcc-start and stop the drive signal when the slope of the feedback signal is negative and the feedback signal is approximately equal to the adjusted low value corresponding to the skip level.

In another embodiment of the invention, the voltage controller can be configured to begin generating the voltage supply signal if Vcc is approximately equal to Vcc-stop when in the off mode, the voltage controller can be configured to stop the voltage supply signal when Vcc is approximately equal to Vcc-start, and the voltage controller can be configured to start the drive signal when a slope of the feedback signal over time is positive and the feedback signal is approximately equal to the HV control level, the voltage controller can be configured to stop the drive signal when the slope of the feedback signal is negative and the feedback signal is approximately equal to an adjusted low value corresponding to the skip level.

In another embodiment of the invention, the voltage controller can be configured to start generating the voltage supply signal when the slope of the feedback signal over time is positive and the feedback signal is approximately equal to the HV control level, and stop generating the voltage supply signal when Vcc is approximately equal to Vcc-start.

In another embodiment of the invention, Vcc is lower than the requested level in the OFF mode, no energy is transferred through the transformer to supply the IC, and the HV source generator is not activated when the feedback/ON/OFF control is lower than the HV start-up level above the skip level.

In another embodiment of the invention, the voltage controller can be configured to generate the drive signal during the start-up mode when Vcc equals Vcc-start.

In another embodiment of the present invention, the semiconductor voltage controller may further include: a standby circuit associated with a standby mode, wherein the voltage controller can be configured to switch to the standby mode when the feedback signal is less than the HV control level and Vcc is greater than Vcc-stop.

According to another aspect of the invention, there is provided a method of controlling a switched mode power supply, comprising: inputting a feedback signal and an off mode signal from a single input, wherein the feedback signal and the off mode signal determine whether the switched mode power supply is operating in the off mode; and when the feedback signal is less than the trip threshold, disabling the start mode.

In one embodiment of the present invention, the method may further include: generating a drive signal and a voltage supply signal if the feedback signal is greater than the HV control level; stopping the voltage supply signal when Vcc is approximately equal to Vcc-start; and stopping the driving signal when the feedback signal is less than about the adjusted low value corresponding to the skip level.

In another embodiment of the present invention, the method may further include: if the slope of the feedback signal over time is positive and if the feedback signal is approximately equal to the HV control level, then starting to generate the voltage supply signal and the drive signal; stopping generating the voltage supply signal when Vcc is approximately equal to Vcc-start; and stopping generating the drive signal when the slope of the feedback signal is negative and the feedback signal is approximately equal to the adjusted low value corresponding to the skip level.

In another embodiment of the present invention, the method may further include: if the slope of the feedback signal over time is positive and if the feedback signal is approximately equal to the HV control level, then starting to generate the voltage supply signal; stopping generating the voltage supply signal when Vcc is approximately equal to Vcc-start; starting to generate the drive signal when Vcc is approximately equal to Vcc-start; and stopping generating the drive signal when the slope of the feedback signal is negative and the feedback signal is approximately equal to the adjusted low value corresponding to the skip level.

In another embodiment of the present invention, the method may further include: if Vcc is approximately equal to Vcc-stop, then the generation of the voltage supply signal begins; stopping generating the voltage supply signal when Vcc is approximately equal to Vcc-start; beginning to generate the drive signal when the slope of the feedback signal over time is positive and the feedback signal is approximately equal to the HV control level; and stopping generating the drive signal when the slope of the feedback signal is negative and the feedback signal is approximately equal to the adjusted low value corresponding to the skip level.

According to another aspect of the invention, there is provided a switched mode power supply controller comprising a feedback node for receiving a feedback signal corresponding to an output voltage of a power supply, the controller comprising: a first comparator comprising a first input coupled to the feedback node, a second input coupled to a first reference voltage, and an output, wherein the first comparator is configured to begin starting by coupling a current to the output of the power supply; and a second comparator comprising a third input coupled to the feedback node, a fourth input coupled to the second reference voltage, and a second output for enabling energy transfer to the output of the power supply, wherein the first and second comparators are configured to support the start-up, regulation, and off mode processes by the feedback signal.

In another embodiment of the present invention, the switch mode power supply controller may further include: a first current source comprising a first electrode configured to receive a first supply voltage and a second electrode coupled to a feedback node configured to deliver a current thereto; a first switch including a third electrode configured to receive a first voltage, a control electrode coupled with an output of the first comparator, and a second terminal; and a second current source including a fourth electrode coupled to the second terminal of the first switch and a fifth electrode coupled to the output of the power supply.

In another embodiment of the present invention, the switch mode power supply controller may further include: a first zener diode comprising a cathode coupled to the feedback node and an anode coupled to the first input of the first comparator; a first resistor including a sixth electrode coupled with the first input of the first comparator and a seventh electrode configured to receive the second voltage; and a second zener diode comprising a second cathode coupled to the first input of the first comparator and a second anode configured to receive a second voltage.

In another embodiment of the present invention, the switch mode power supply controller may further include: a first diode comprising a third cathode coupled to the feedback node and a third anode coupled to a third input of the second comparator; and a second resistor comprising an eighth electrode coupled to the third input of the second comparator and a ninth electrode coupled to the output of the power supply.

In another embodiment of the present invention, the switch mode power supply controller may further include: an external pullup on the feedback node.

In another embodiment of the present invention, the switch mode power supply controller may further include: a power factor correction feedback.

Drawings

Embodiments of the present invention will become more fully understood from the detailed description and the accompanying drawings, wherein:

FIG. 1 schematically illustrates an embodiment of a portion of a system according to an embodiment of the invention;

FIG. 2 schematically illustrates an embodiment of a portion of a system according to an embodiment of the invention;

FIG. 3 schematically illustrates an embodiment of a portion of circuitry that may be part of the system of FIG. 2, in accordance with an embodiment of the present invention;

FIG. 4 schematically illustrates an embodiment of a portion of circuitry that may be part of the system of FIG. 2, in accordance with an embodiment of the present invention;

FIG. 5 schematically illustrates an embodiment of a portion of circuitry that may be part of the system of FIG. 2, in accordance with an embodiment of the present invention;

FIG. 6 illustrates a portion of a signal that may occur during a portion of the operation of a portion of a system of an embodiment of the present invention;

FIG. 7 illustrates a portion of a signal that may occur during a portion of the operation of a portion of a system of an embodiment of the present invention;

FIG. 8 schematically illustrates an embodiment of a portion of circuitry that may be part of a system according to an embodiment of the invention;

FIG. 9 schematically illustrates an embodiment of a portion of an integrated circuit that may be part of a system according to an embodiment of the invention;

FIG. 10 schematically illustrates an embodiment of a portion of circuitry that may be part of a system according to an embodiment of the invention;

FIG. 11 schematically illustrates an embodiment of a portion of circuitry that may be part of a system according to an embodiment of the present invention;

FIG. 12 schematically illustrates an embodiment of a portion of circuitry that may be part of a system according to an embodiment of the invention;

FIG. 13 schematically illustrates an embodiment of a portion of a system according to an embodiment of the invention;

FIG. 14 schematically illustrates an embodiment of a portion of a system according to an embodiment of the invention;

FIG. 15 schematically illustrates an embodiment of a portion of an integrated circuit that may be part of a system according to an embodiment of the invention;

FIG. 16 schematically illustrates an embodiment of a portion of an integrated circuit that may be part of a system according to an embodiment of the invention; and

FIG. 17 illustrates a portion of a signal that may occur during a portion of the operation of a portion of a system of an embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and are merely schematic and non-limiting, and, unless otherwise stated, like reference numerals in different figures refer to like elements. Moreover, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, current carrying electrode refers to an element of a device that carries current through the device, such as a source or drain of an MOS transistor, or an emitter or collector of a bipolar transistor, or a cathode or anode of a diode, and a control electrode refers to an element of a device that controls current flowing through the device, such as a gate of an MOS transistor or a base of a bipolar transistor. Those skilled in the art will recognize that as used herein, the words "during …," "while …," and "when …" with respect to circuit operation do not refer to the exact terms that an action occurs immediately upon initiation of the action, but rather there may be some small, reasonable delay, such as a propagation delay, between reactions that may be initiated by an initial action. Further, the term "simultaneously at …" means that a certain action occurs for at least a certain portion of the duration of the initiating action. Use of the words "about" or "substantially" means that a value of an element can have a parameter that is expected to be very close to a set value or position. However, as is well known in the art, there are always minor deviations that prevent the values or positions from being strictly as specified. It is recognized in the art that deviations of up to about ten percent (10%) (and up to twenty percent (20%) for semiconductor dopant concentrations) are considered reasonable deviations from the strict ideal target.

When used with respect to the state of a signal, the term "asserted" refers to the active state of the signal, and "inactive" refers to the inactive state of the signal. The actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic can be used. Thus, "asserted" may be high voltage or high logic or low voltage or low logic depending on whether positive or negative logic may be used, and deassertion may be low voltage or low state or high voltage or low logic depending on whether positive or negative logic may be used. Here, a positive logic agreement may be used, but it will be understood by those skilled in the art that a negative logic agreement may also be used. The terms "first," "second," "third," and the like in the detailed description of the claims and/or the drawings are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order, whether temporally, spatially, in ranking, or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments described herein are capable of operation in other sequences than described or illustrated herein.

Further, the present description describes a honeycomb design (where the body region is a plurality of honeycomb regions) in place of a single body design (where the body region may be comprised of a single region formed in an elongated pattern, typically in a serpentine pattern). However, the description should be applicable to both cellular and single base (single base) implementations.

In all of the examples illustrated and discussed herein, any specific materials such as temperature, time, energy, and material properties used for implementation of process steps or specific structures should be construed as merely illustrative and not limiting. Processes, techniques, devices and materials known to those of ordinary skill in the art may not be discussed in detail but are intended to be part of the enabling description where appropriate. It should also be noted that the word "coupled" is used herein to imply that elements may be directly coupled together or may be coupled through one or more intervening elements. Furthermore, the term "configuration" may refer to a hardware configuration that may be designed to provide a set of functions when in operation, but does not require the device to be powered on, except that the device may be "configured" to perform the functions when powered on. Thus, a claim directed to a system configured to perform a function should be able to encompass systems that can be designed to provide that function regardless of whether the system is powered on or off, and without the need for such a system to be powered on to infringe the claim.

Note that like reference numerals refer to like items in the following figures. In some instances, reference numerals from the previous description will not be placed in subsequent figures for the sake of clarity. In general, it should be assumed that structures not identified in the figures are the same as those in the previous figures.

Fig. 1 may be an illustration of a switching power supply 100 including an output terminal 102 according to an embodiment. The output terminal 102 may have a voltage Vcc that may be maintained within a predetermined voltage range during operation of the switch mode process. The predetermined voltage range may vary depending on the application and requirements of the switching power supply 100. In this example, the switching power supply 100 represents a common configuration comprising two control stages. The first stage may be a Power Factor Correction (PFC) stage 104 and the second stage may be a pulse width modulation stage 108. Note, however, that other embodiments may or may not include PFC stage 104. In general, stages 104 and 108 increase the efficiency of switching power supply 100 by effectively adjusting based on detected input and output conditions. In this example, the switching power supply 100 may be coupled to an AC voltage that may be rectified, filtered, and provided as an input voltage to the PFC stage 104. PFC stage 104 generates a regulated voltage that may be different from the output voltage of power supply 100. The PFC stage 104 may be isolated from the PWM stage 108 by a diode. The PFC stage 104 regulates by enabling and disabling the switch 106. When forward biased, the diode conducts current from the PFC stage 104, charging the storage capacitor. As shown, the switches may be transistors that may be controlled by the power factor correction stage 104, where the power factor correction stage 104 adjusts the duty cycle of the enabled switch 106 in response to a signal corresponding to the adjusted output voltage generated by the PFC stage 104. More specifically, power factor correction adjusts to maintain an input current having a time and amplitude relationship with the rectified input voltage provided thereto and with the output current flowing therefrom. Power factor correction circuitry typically keeps the power factor as close to 1 as possible.

The second stage of the switching power supply 100 may be a Pulse Width Modulation (PWM) stage 108. The PWM stage 108 includes pulse width modulation control circuitry, a switch 110, and a transformer 112. The storage capacitor may be coupled to a first terminal of the primary winding of the transformer 112. As shown, the switch 110 may be a transistor. Switch 110 may be coupled to a second terminal of the primary winding of transformer 112. The PWM stage 108 enables and disables the switch 110 based on the error signal. The error signal corresponds to the difference between the desired regulated output voltage of the switching power supply 100 and the output voltage Vout. The voltage Vout at the output of the switching power supply 100 varies with time due to variations in the load at the output terminal 102A. The load at the output 102A of the power supply 100 may vary from a no-load scenario to a load near the maximum current rating. For example, if the load on Vout increases, the PWM stage 108 detects the change and responds by raising the duty cycle to deliver power to the load more frequently and maintain or increase Vout. Conversely, with reduced load, the PWM stage 108 will reduce the duty cycle to a level that maintains regulation. In general, stages 104 and 108 will maintain the voltage at output 102A within a predetermined voltage range specified by the power supply application.

The PWM stage 108 may generate a regulated output voltage that is different from the regulated output voltage from the PFC stage 104. The regulated output voltage from the PWM stage 108 may be provided through a transformer 112 and an output rectifier 114A. The storage capacitor 116A may be coupled to the output rectifier 114A. In this example, the transformer 112 may be used to further modify the output voltage from the PWM stage 108 to the regulated output voltage Vout of the switching power supply 100. For example, the transformer 112 may step down the voltage Vout at the output by a multiple of the voltage delivered across the primary winding. As previously mentioned, the secondary transformer winding of the transformer 112 may be coupled to the output rectifier 114A. In this example, the output rectifier 114A may be a rectifier diode including an anode coupled to the secondary transformer winding and a cathode coupled to the regulated output voltage Vout. The storage capacitor 116A may be coupled to Vout to provide power to the load when the stages 104 and 108 are not delivering power. The resistor divider generates a voltage corresponding to the voltage at Vout, which can be used to monitor the change. As shown, the change in voltage across the resistive divider generates an error signal, which may be optically coupled to a feedback pin (FB) or feedback node of the on/off control + feedback circuit 118. For simplicity, the on/off control + feedback circuit 118 will be referred to hereinafter as the Feedback Control (FC) circuit 118.

In the switching power supply 100, the output rectifier 114A may have two modes of operation. In a first mode of operation, the output rectifier 114A may be in a high current path for driving a load coupled to the output terminal Vout of the switching power supply 100. The output rectifier 114A may couple the PFC stage 104 and the PWM stage 108 to a load through the transformer 112 when the output rectifier 114A is forward biased. In the second mode of operation, the output terminal Vout may be isolated from the PFC stage 104, the PWM stage 108, and the transformer 112 by the output rectifier 114A. As mentioned previously, in the second mode of operation, the storage capacitor 116A coupled to the output terminal Vout delivers power to the load. The output rectifier 114A may be turned off from significant voltage while maintaining isolation between the output terminal Vout and the regulation circuitry.

At least one embodiment includes circuits and methods for an efficient switched mode power supply including an off mode. The off mode may be integrated with additional circuitry that does not require additional pins to be added to the switch mode power supply controller integrated circuit. The different operating modes are controlled by a feedback pin or node for the regulating circuit in the switched mode power supply. In one embodiment, a switch mode power supply controller may have three different modes of operation. In the first mode, the start-up procedure may be initiated. This start-up process occurs when the power supply is first turned on or after an off mode. This start-up procedure provides current to Vcc102 of switching power supply 100, thereby moving voltage Vcc towards a predetermined voltage range so as to remain in regulation during the switching mode procedure. In the non-limiting example currently discussed, in the off mode, no feedback signal is applied. In the second mode, the switch-mode procedure may be enabled to support regulation at the output 102A of the switching power supply 100. Energy transfer occurs from transformer 112 to maintain output 102A within a predetermined voltage range. As discussed above, the duty cycle of the energy transfer is a function of the load. For example, a high duty cycle may be necessary when the switching power supply 100 is heavily loaded, requiring frequent energy transfers to maintain the voltage Vout within a predetermined voltage range. Optionally, a light load at the output terminal 102A requires a low duty cycle or infrequent energy transfer to maintain the voltage Vout within a predetermined voltage range. In this example, a feedback signal may be coupled to node 122, the magnitude of which will vary such that the switch mode power supply controller may be enabled or disabled during regulation. Disabling the switch mode power supply controller stops the switch mode process, thereby preventing energy from being transferred to the output 102A via the secondary winding of the transformer 112. As shown, a condition or status circuit 130 may be operatively coupled to the node 122 for changing the operating mode of the power supply 100 via a feedback pin or feedback node. In one embodiment, circuit 130 may be optically coupled to a transistor 132, the transistor 132 including a collector that may be coupled to node 122. The third mode may be an off mode that prevents energy from being transferred to the output terminal 102A of the switching power supply 100. The off mode will be explained in more detail below. In the off mode, the voltage Vout at the output terminal 102A of the power supply 100 may be allowed to fall outside a predetermined voltage range, e.g., a minimum voltage below the predetermined voltage range.

The off mode may be a condition or an operating mode of the switching power supply 100 in a no-load condition. Typically, a no-load condition occurs when little or no power is delivered from the switching power supply 100 to the device coupled to the output terminal 102A. Examples of no-load conditions include no device coupled to the output 102A, a device coupled to the output 102A may be disconnected, or a device coupled to the output may be placed in a power-saving mode. When a no-load condition can be detected, an off mode can be initiated and a no-load signal can be provided to node 122 that places power supply 100 in the off mode. The FC circuit 118 can be easily adapted to different switching power supply controller designs. The FC circuitry 118 generally reduces power consumption to various design levels, e.g., less than 30 milliwatts in the off mode. Further, in at least one embodiment, the circuit operates on a standard pin in a switch mode power supply controller that does not include an off mode. No additional pins are required. The startup mode, the feedback mode, and the off mode may be implemented through a feedback path of the switch mode power supply controller. Another benefit beyond low energy usage is that manufacturers do not need to redesign the interface to the power supply system (more specifically, the printed circuit board) to retrofit new controllers that include the off mode. Maintaining the form factor and pins in existing controllers reduces cost and reduces obstacles to adoption while providing substantial long-term energy savings. Another benefit is that over-voltage protection or over-current protection can be kept in place without a change in performance, thereby maintaining existing safety behavior.

The off mode improves the efficiency of the switching power supply 100 by preventing power from being delivered to the output terminal 102A for an extended period of time. The time between adjusting the power delivery of the voltage at the output terminal 102A in the off mode may be greater than the time the switched mode power supply would normally operate without the off mode capability. The switching power supply 100 dissipates a minimum power during the off mode, thereby increasing the overall efficiency of the system over time. In the off mode, the voltage at the output 102A drops over time even at a much slower rate than when power is delivered to the device. The leakage current and the feedback circuitry loading the output terminal 102A cause a slow drop in the output voltage. In one embodiment of the off mode, the voltage at the output 102A can fall below a predetermined regulated voltage range (from 30 seconds to 30 minutes) maintained during the switching mode process.

In the off mode, the voltage at the output terminal 102A continues to drop until the start-up mode occurs, whereby current can be supplied to the output terminal 102A. The startup mode is disclosed in more detail in subsequent figures below. The current supplied to Vcc102 comes from other sources besides the switch mode process. The start-up mode may then be disabled after the voltage of Vcc102 rises to a level that enables the switch-mode process, thereby transferring energy through transformer 112. It should be noted that the time elapsed from the off mode to the enabling of the switch mode process can be achieved in a very short time period (-100 ms). This may be desirable because the switched mode power supply may change rapidly from an over-power active state to provide current to the load using the regulated output voltage to enable the device (e.g., load) in the shortest possible time. During regulation, the voltage at the output terminal 102A will be maintained within a predetermined voltage range. If no load condition persists, the switch mode process will remain disabled so that no energy can be transferred by the transformer 112. As discussed above, the voltage at the output 102A will continue to drop until the start-up mode again occurs. Similar to the off mode may be standby, skip or light load mode. The difference between the off mode and the standby mode may be that the start-up mode may not be activated. The switch mode process may be periodically enabled for a minimum period of time to maintain the voltage at the output 102A within a predetermined range.

In one embodiment, the FC circuit 118 may be integrated with other circuitry of the switch mode power supply controller into a single chip. In this example, the single chip may include PFC stage 104, PWM stage 108, and FC circuit 118, as indicated by dashed line 134. The circuitry may be more or less than shown and the integration may vary depending on the power application. As shown, FC circuit 118 may have node 120, node 122, node 124, and node 126. Node 120 corresponds to a voltage HV that may be provided by FC circuit 118. A capacitor 128 may be coupled to the node 120 to store energy. In this example, the current provided during the off mode to the on mode may be provided by the source of voltage HV, capacitor 128, or both. The feedback pin or feedback node of the switch mode power supply controller corresponds to node 122 of the FC circuit 118. The circuit 130 may be coupled to the output terminal 102A of the switching power supply 100 or Vcc 102. Circuit 130 generates a signal corresponding to voltage Vout. The circuit 130 may also include circuitry for detecting the load on the output terminal 102A. The voltage Vout at the output terminal 102A may be a high voltage for the adapter, such as 19V. In one embodiment, the circuit 130 may be optically coupled to the feedback device 132. As shown, the feedback device 132 may be a transistor that generates a current corresponding to the voltage Vout, the load at the output terminal 102A, or both. The collector of feedback device 132 may be coupled to node 122. FC circuit 118 may also receive a voltage Vcc from the output 102 of the switching power supply at node 124. In addition, the FC circuit 118 may have a node 126 that may be coupled to the PFC stage 104 and the PWM stage 108. The FC circuit 118 generates a drive signal that enables or disables a switch mode process that delivers energy to the output 102A or prevents energy delivery from occurring, respectively.

It should be noted that the configuration of the switching power supply 100 may be used merely to illustrate the general operation of the switching mode process to generate the regulated voltage. Further, the above description may be an example of how the off mode affects the power efficiency of the power supply 100. There are many types of switched mode power supplies and switched mode power supply architectures that can use the off mode to improve long term power efficiency. The feedback control circuitry 118 may be adapted for different types of switch mode processes without increasing the pin count of the controller circuitry. High-capacity commercial applications include low-cost flyback circuits (flyback circuits), notebook computer power supplies, and ATX power supplies, all of which would benefit from increased efficiency. Cost and performance are factors in selecting the technology used. Generally, the initial supply cost may be selected relative to the most efficient solution, although increased efficiency may result in lower costs over the long term due to reduced energy usage. The addition of the FC circuit 118 may reduce cost while improving performance.

Thus, the FC circuit 118 may be integrated into existing switch-mode power supply controllers to improve operating efficiency, thereby facilitating proliferation of more efficient power supplies to reduce long-term power consumption. Moreover, performance and cost improvements can be achieved without adding complexity to the power supply circuitry and without introducing variations in the assembly process. In other words, performance improvements can be achieved by merely replacing the existing switch mode power supply controllers disclosed hereinafter, allowing for quick retrofit improvements to improve performance, reduce obstacles to adoption, and reduce the cost of power supply integration.

Fig. 2 is a schematic diagram of a feedback control circuit 118 according to an embodiment, the feedback control circuit 118 may provide an off mode without increasing the pin count. In this example, nodes 120, 122, 124, and 128 are pins of an integrated circuit. Nodes 120, 122, 124 and 128 correspond to the voltage input, feedback, switch mode power supply Vcc supply and controller drive, respectively, which are either common pins or internal nodes of most switch mode power controllers, thereby allowing FC circuit 118 to be integrated thereto. Alternatively, nodes 120, 122, 124, and 128 may be internal nodes of a power supply, circuit, or integrated circuit. The secondary side of the power supply 100 includes the secondary winding of the transformer 112A, the rectifier 114A, the storage capacitor 116A, error signal circuitry, and condition or status circuitry 130 coupled thereto. The condition or status circuitry 130 includes circuitry coupled to the output 102A that may be optically coupled to a transistor 132, the transistor 132 may provide a signal that controls transitions between an off mode, a start mode, and a regulation mode. The condition or status circuitry 130 may also include circuitry to detect an unloaded condition.

FC circuit 118 includes a current source portion 230, a start comparator 216, and a trim comparator 228. The voltage HV may be provided to a node 120 of the FC circuit 118. The storage capacitor 128 stores charge for delivery to the current source portion 230 in the start-up mode. The start-up mode discussed herein may be used to quickly raise the voltage at Vcc102 after the turn-off mode. The startup mode may be used in other operational sequences of the switched mode power supply 100. The voltage HV coupled to node 120 should be greater than the regulated voltage at Vcc102 of power supply 100. The voltage HV may be regulated or unregulated. The current source part 230 includes a current source 202, a current source 204, and a switch 206. In one embodiment, current source 202 may have a first terminal coupled to node 120 and a second terminal coupled to node 122. Current source 204 may have a first terminal coupled to node 120 and a second terminal. Switch 206 may have a first terminal coupled to the second terminal of current source 204, a control terminal, and a second terminal coupled to node 124. Node 124 may be coupled to Vcc102 of switch mode power supply 100.

The FC circuit 118 may be coupled to or include a current source 204, and in the startup mode, the current source 204 may provide current to the Vcc102 of the power supply 100. The start-up circuitry includes a zener diode or resistor 208, a resistor 210, a zener diode 212, and a start-up comparator 216. In general, start-up comparator 216 includes a positive input, a negative input coupled to a reference voltage, and an output coupled to a control electrode of switch 206. In this example, switch 206 is closed in a high state at the output of start comparator 216, thereby coupling current source 204 to Vcc 102. Zener diode 208 may have a cathode coupled to node 122 and an anode coupled to the positive input of start-up comparator 216. Resistor 210 may have a first terminal coupled to the positive input of start-up comparator 216 and a second terminal coupled to ground. Zener diode 212 may have a cathode coupled to the positive input of start-up comparator 216 and an anode coupled to ground. The voltage reference 214 provides a voltage Vstart to the negative input of the start comparator 216. Comparator 216 incorporates hysteresis whereby transitions from low to high states or high to low states occur at different threshold voltages.

The FC circuit 118 also includes a trim comparator 228, which trim comparator 228 may provide a drive signal that may be coupled to the switch mode power supply controller to enable and disable the switch mode process. The circuit includes a resistor 222, a diode 224, and a trim comparator 228. Generally, trim comparator 228 includes a positive input terminal, a negative input terminal coupled to a reference voltage, and an output terminal that may provide a drive signal. In this example, the power supply 100 may deliver energy to the output 102 when the switch mode power supply controller may be enabled by the drive signal from the trim comparator 228. Conversely, when the switch mode power supply controller is disabled by the drive signal from the trim comparator 228, no energy transfer at the output 102 occurs according to the switch mode process.

The resistor may have a first terminal coupled to receive the internal set voltage Vdd and a second terminal coupled to the positive input of the trim comparator 228. Diode 224 may have an anode coupled to the positive input of trim comparator 228 and a cathode coupled to node 122. The voltage reference 226 provides a voltage vresultation to the negative input of the trim comparator 228. The output of the trim comparator 228 may be coupled to the node 126. The voltage Vdd provided to the first terminal of resistor 222 corresponds to the supply voltage Vcc provided to node 124 of FC circuit 118. In one embodiment, the voltage Vdd may be converted from the voltage Vcc by a circuit. In general, the voltage Vdd may be fixed. Thus, the start up comparator 216 and trim comparator 228 support start up, trim and disconnect mode processes via signals applied to the feedback node 122.

FIG. 3 is a schematic diagram of circuitry for a startup mode according to an embodiment. As mentioned previously, the start-up mode may occur when the power supply 100 is first turned on or from an off mode. Typically, the voltage Vcc at the output terminal 102 of the power supply 100 is outside the predetermined voltage range maintained during regulation. The start-up mode may be enabled, delivering current to the output 102, thereby raising the voltage thereon. When the switched mode power supply 100 is initially energized, a different sequence of operations may be used. The startup mode described herein may be used at least when transitioning from the off mode. The current from current source 204 during the start-up mode raises the voltage Vcc at 102 to a predetermined voltage that initiates the switching mode process.

Prior to the start-up mode, the signal applied to node 122 sinks (sink) the current from current source 202, rendering zener diode 208 non-conductive. When the voltage at node 122 is insufficient to cause breakdown, zener diode 208 does not conduct. When the zener diode 208 is non-conductive, the voltage at the positive input of the start-up comparator 216 is approximately ground. The reference voltage Vstart coupled to the negative input of the start-up comparator 216 may be greater than ground, thereby generating a "0" or low state at the output of the start-up comparator 216. The low state at the output of the start-up comparator 216 maintains the switch 206 in an open state so that the current source 204 does not supply current to the Vcc102 of the power supply 100.

When the signal applied to node 122 can no longer sink current from current source 202, the voltage at node 122 will rise. Above a predetermined sinking current applied to node 122, the voltage will rise above the breakdown voltage of zener diode 208. The zener diode 208 then breaks down above a predetermined voltage, causing the resistor 210 and the zener diode 208 to conduct current. As the current conducted by resistor 210 increases, the voltage at the positive input of start-up comparator 216 will increase. The output of start-up comparator 216 switches from a low state to a "1" or high state when the voltage at the positive input of start-up comparator 216 is greater than reference voltage 214 (Vstart) coupled to the negative input of start-up comparator 216. The high state at the output of the start-up comparator 216 enables or closes the switch 206 that couples the current source 204 to the node 124 and Vcc102 of the power supply 100.

As mentioned before, during the start-up mode, the switch mode process may be in an off state. Since the voltage Vdd is less than the reference voltage 226 (Vregulation), a negative voltage difference may be generated across the +/input of the trim comparator 228 (FIG. 4). The details will be described in more detail below. The current from the current source 204 charges the storage capacitor 116, thereby increasing the voltage Vcc. The magnitude of the voltage HV and the charge stored on the storage capacitor 128 may be sufficient to quickly raise the voltage at the output terminal 102 to the start-up output voltage that initiates the switching mode process. As discussed above, boosting Vcc also increases Vdd. The zener diode 212 clamps the voltage at the positive input of the start-up comparator 216 to be no higher than the breakdown voltage of the zener diode 212.

Fig. 4 is a schematic diagram of circuitry for a switch-mode process to maintain output 102A between predetermined voltage ranges, according to an embodiment. In the example discussed above, the current from the current source 204 (fig. 3) increases the voltage Vcc at the output terminal 102. The predetermined voltage at the output 102A may be such that the optical diode of the condition and status circuitry 130 begins to conduct current. The optical signal may be coupled to a transistor 132 where it may be converted to a base current corresponding to the output voltage Vout in the transistor 132. This base current enables transistor 132 to sink the current at node 122. The base and collector currents of transistor 132 increase as the voltage Vout at output terminal 102A rises. At the predetermined voltage at output 102A, the collector current of transistor 132 may be sufficient to force the voltage at node 122 to drop until zener diode 208 is non-conductive. The predetermined voltage at which the zener diode 208 becomes non-conductive may be the voltage Vstart, as will be discussed in more detail below. When the zener diode 208 becomes non-conductive, the positive input of the start-up comparator 216 is lowered through the resistor 210 to ground. The reference voltage 214 may be greater than the ground voltage at the positive input of the start-up comparator 216, creating a transition from a "1" or high state to a "0" or low state at the output of the start-up comparator 216. The low state opens switch 206 decoupling current source 204 from Vcc supply source 102, which prevents voltage Vcc from increasing above voltage Vstart.

Generally, the switch-mode process provides power to the load coupled to the output terminal 102A and the storage capacitor 116A. The switch-mode process adjusts or maintains the voltage Vout at the output terminal 102 within a predetermined voltage range. As mentioned previously, the optical feedback to transistor 132 corresponds to the voltage Vout at the output terminal 102. The frequency or amount of energy transfer corresponds to the load at the output 102. For example, an increase in load will produce a corresponding negative rate of change at the output 102. This negative rate of change may be detected by the switch mode power supply controller, thereby increasing the frequency or amount of energy transferred over a period of time to counter this trend and maintain the voltage Vout above the minimum voltage of the predetermined voltage range. In one embodiment, an increase in the frequency or amount of energy transfer changes the rate of change from negative to positive, thereby increasing the voltage Vout at the output terminal 102A. Conversely, under light load conditions, the transfer of energy may be reduced, stopping the positive rate of change of energy transfer that would ultimately increase the voltage Vout beyond the maximum voltage of the predetermined voltage range.

The trim comparator 228 provides a drive signal to the switch mode power supply controller that enables the switch mode process to trim the voltage at the output 102A. In this example, this corresponds to a signal transition from no signal at node 122 (e.g., start-up mode) to enable optical feedback of transistor 132 (e.g., regulation mode) to sink current from node 122 when the voltage of supply 102 reaches voltage Vstart. In one embodiment, the output of the trim comparator 228 transitions from a low state to a high state after the current source 204 is decoupled from Vcc 102. The positive voltage difference from the positive input to the negative input of trim comparator 228 may be a function of the voltage at node 122 and the voltage Vdd at the first terminal of resistor 222. The voltage Vdd may be the voltage Vcc or a voltage corresponding to the voltage Vcc. For example, the voltage Vdd may be scaled from the voltage Vcc to determine the switching point using the reference voltage 226. Vdd may also be a predetermined internal reference voltage.

The voltage at node 122 during the start-up mode may be approximately the breakdown voltage of zener diode 208 and the voltage across resistor 210. Diode 224 becomes conductive when voltage Vdd is greater than the voltage at node 122 and the forward diode drop of diode 224 when conducting. Diode 224 is non-conductive prior to transitioning from the startup mode to the regulation mode. The non-conductive state of diode 224 results in the voltage at the positive input of comparator 228 being the voltage Vdd. In one embodiment, prior to the start-up mode, the voltage Vcc at the output terminal 102 of the power supply 100 is less than the minimum regulation voltage. The voltage Vdd corresponding to the voltage Vcc that is less than the minimum regulation voltage may be less than the reference voltage 226 or Vregulation. Thus, under the conditions listed above, the output of the trim comparator 228 will be in a low state. Note that during the start-up mode, the voltage Vcc at the output terminal 102 of the power supply 100 changes rapidly due to the current provided by the current source 204. Thus, a low state at the output of comparator 228 inhibits the switch mode power supply controller from delivering energy to Vcc supply 102 during the startup mode.

Diode 224 isolates node 122 from the positive input of trim comparator 228 before the switch mode process is enabled in trim mode. Diode 224 introduces an offset at the positive input of trim comparator 228 that does not affect performance. In one embodiment, the transition from the startup mode to the regulation mode occurs when the voltage Vcc at the output terminal 102 reaches Vstart. The voltage Vdd may be a voltage corresponding to Vstart. In this example, the diode 224 may conduct when the output terminal 102 is at the voltage Vstart. In other words, when the output terminal 102 is at the voltage Vstart, the voltage Vdd is greater than the voltage at the node 122 plus the forward voltage drop of the diode 224. The voltage at the positive input of comparator 228 may be approximately the voltage at node 122 plus the forward voltage drop of diode 224. Under this condition, the voltage at the positive input of the trim comparator 228 may be greater than the trim voltage 226 or Vregulation. The output of the trim comparator 228 then transitions from a "0" or low state to a "1" or high state. A high state at the output of the trim comparator 228 may be coupled to the switch mode power supply controller to enable the switch mode process.

Enabling the switch mode process allows energy to be transferred to the output terminal 102A of the power supply 100 and establishes regulation that maintains the voltage Vout within a predetermined voltage range. It should be noted that the energy transfer may be controlled by a switched mode power supply controller. As long as the output of the trim comparator 228 is in a high state, the switch-mode process may be enabled to allow energy transfer. The amount of feedback provided to node 122 and the voltage Vdd operatively determine whether the switch mode process can be enabled or disabled. In one embodiment, the output of the regulation comparator remains in a high state during the regulation mode, thereby maintaining the voltage Vout at the output 102A of the power supply 100 within the regulated voltage range.

In the case of a light load on the output 102A, an increase in power efficiency can be obtained by disabling the switch-mode process. This configuration may be referred to as a skip mode or a standby mode. The switch mode process may be enabled and disabled, respectively, transmitting energy to the output 102A and then disabling the energy transmission process. Depending on how light the load at output 102A will be, the switch mode power supply controller may be disabled for an extended period of time. In the skip mode, the voltage Vout may be maintained at the lower portion of the regulated voltage range in order to further minimize power consumption. Also, in at least one embodiment, the voltage Vout is not allowed to fall outside of the regulated voltage range while in the skip mode.

Fig. 5 is a schematic diagram of circuitry for an open mode process, according to an embodiment. In at least one embodiment, the condition or status circuitry 130 (FIG. 2) includes an automatic no-load detection circuit. The automatic no-load detection circuit detects when no load is coupled to the output 102A of the power supply 100. In this example, the no-load detection circuit enables transistor 132 to drive node 122 to approximately ground. In an alternative embodiment, the no-load detection circuit may have an output coupled to node 122 that drives node 122 to ground when no load is detected. Generally, detecting a no-load condition at output 102A of power supply 100 transitions the signal at node 122 to an off mode (e.g., ground). Upon detection of a no-load condition, the switch-mode process may be disabled, thereby stopping energy delivery to the output 102A of the power supply 100.

When a no-load condition is detected, the base current provided to transistor 132 turns on the device, causing the collector to sink a current sufficient to hold node 122 at ground. Node 122, which is at ground, renders zener diode 208 non-conductive. When the zener diode 208 is non-conductive, the voltage at the positive input of the start-up comparator 216 may be driven to ground through the resistor 210. When node 122 is grounded, the voltage at the negative input of start-up comparator 216 may be greater than the voltage at the positive input. Depending on the initial conditions for enabling comparator 216, the output of enabling comparator 216 transitions from a "1" or high state to a "0" or low state or remains in a low state.

Diode 224 (fig. 4) conducts current when node 122 is grounded. The voltage at the positive input of the trim comparator 228 is approximately the forward voltage drop of the diode 224. In this example, the voltage at the positive input of the trim comparator 228 is less than the reference voltage 226 coupled to the negative input. When the reference voltage 226 is greater than the voltage at the positive input, the output of the trim comparator 228 (e.g., the drive signal) may be in a "0" or low state. As previously mentioned, the drive signal in the low state disables or prevents energy from being transferred to the output 102A of the power supply 100 through a switch mode process. In the off mode, little or no energy is provided to the storage capacitor 116A. Due to leakage current, the storage capacitor 116A will slowly discharge over time during the off mode. Holding node 122 at ground allows voltage Vout to fall outside of regulation and below the minimum voltage of the predetermined voltage range at regulation, since the outputs of start comparator 216 and trim comparator 228 are both in a low state. The voltage Vout continues to drop until the output terminal 102A reaches a predetermined voltage that may be lower than the minimum regulated voltage of the output terminal 102A in the off mode. In one embodiment, output 102A upon reaching a predetermined voltage below the minimum adjustment voltage causes condition or state circuitry 130 to no longer provide an optical signal to transistor 132. When no optical signal is provided, transistor 132 is disabled or turned off so that the device does not conduct current. Then, a transition from the off mode to the on mode occurs. The voltage at node 122 will begin to rise due to the current provided by current source 202. As disclosed above, the start-up mode may be initiated when the zener diode 208 becomes conductive. The start-up mode may couple the current source 204 to the Vcc supply source 102, thereby stopping the discharge of the storage capacitor 116 and quickly raising the voltage Vcc to the voltage Vstart.

FIG. 6 is a timing diagram illustrating a startup mode, regulation mode, and shutdown mode duty cycle of a switch mode power supply controller, and more particularly, the operation of the FC circuit 118, according to an embodiment. When describing the circuit components, reference may be made to fig. 1 and 2. The state of the circuitry of the FC circuit 118 will be used to describe the operational changes that result in different modes being implemented through the feedback pin or node of the power supply 100. Before a, the power supply may be off and the voltage HV is not supplied to the node 120. In step a, voltage HV is provided to node 120, voltage Vcc is at ground, and transistor 132 is off. In this example, voltage HV may be greater than maximum adjustment voltage Vcc Start. The outputs of the start comparator 216 and the trim comparator 228 may both be in a low state such that the switch mode power supply controller is disabled from delivering energy to the output 102A. No feedback signal is provided to node 122. The startup mode may be initiated by the FC circuit 118 when the output of the comparator 216 transitions from a low state to a high state. The output of comparator 228 remains in a low state, thereby preventing energy transfer through the switch-mode process. The startup mode couples current source 204 to node 102 and charges the storage capacitor until the voltage Vcc at node 102 equals the voltage Vcc Start.

In step B, the adjustment mode may be initiated by the FC circuit 118. When supply 102 reaches voltage Vcc Start, the output of comparator 216 transitions from a high state to a low state. Transistor 132 may be enabled by optical feedback corresponding to the voltage at output 102A. Transistor 132 provides a feedback signal to node 122. The current source 204 may be decoupled from the node 102 of the power supply 100, thereby preventing further increases in the voltage Vcc.

The increase in the feedback signal at node 122 and the voltage Vdd produces a change in comparator 228. The output of comparator 228 transitions from a low state to a high state to provide a drive signal for enabling the switch mode power supply controller to deliver energy to output 102A through a switch mode process as needed. Although the switch mode power supply controller is enabled, no energy transfer occurs in step B. Due to the load on the supply 102 of the power supply 100, the peak voltage Vcc Start drops after step B until the switch mode process delivers energy for maintaining regulation.

From step C to step D, the power supply 100 operates in the regulation mode as a normal switching power supply. The switch mode power supply controller controls the frequency or amount of energy transfer to maintain the voltage Vout at the output terminal 102A at the requested regulation value. Supply Vcc is held between voltage Vcc Start and voltage Vcc Stop. The rate of energy transfer will vary with changes in the load. The regulation mode maintains the voltage Vout at the output terminal 102 within this range when the switching mode process is enabled. Optical feedback corresponding to the voltage Vout (more specifically, corresponding to a voltage within the regulated voltage range) may be provided during regulation. The feedback signal to node 122 and voltage Vdd enable the switch-mode process. Thus, the output of the comparator 228 stays in a high state (e.g., a drive signal) during the trimming, thereby providing a drive signal that maintains the trim mode operation of the FC circuit 118. Since the voltage Vcc at the supply source 102 is greater than Vcc Stop, the output of the start-up comparator 214 remains in a low state during regulation. The current source 204 may be decoupled from the Vcc supply 102.

At step D, a light load condition occurs, wherein keeping the switch mode process enabled will reduce power efficiency. The light load condition may also be referred to as a standby or skip mode. In the skip mode, the voltage supply Vcc drops at a much slower rate when a normal load is coupled to the output terminal 102A. When the skip or standby mode is enabled in step D, the output of comparator 228 transitions from a high state to a low state. The drive signal in the low state disables the switch mode power supply controller from delivering energy to the output 102A.

In step E, the power supply 100 may be in a skip or standby mode. The output 102A may be lightly loaded, allowing for an extended period of time before energy transfer is required to maintain regulation. In skip mode, the switch mode process may be enabled before the voltage Vcc drops below Vcc Stop. The signal to transition trim comparator 228 from a low state to a high state may be provided to node 122. The drive signal in the high state causes the switched mode power supply to participate in the switched mode process. Delivering energy to the output 102A of the power supply 100 through the enabled switch-mode process also raises the voltage Vcc, as shown in step E.

At step F, light load conditions continue to exist. Referring back to step E, energy is transferred to boost the voltage Vout. The skip mode may be resumed upon detection of a light load condition. Similar to step D, when the skip mode is enabled, the output of comparator 228 transitions from a high state to a low state. The drive signal in the low state disables the switch mode power supply controller from delivering energy to the output 102A.

At step G, the power supply 100 is in a skip or standby mode. The output 102A may be lightly loaded, allowing for an extended period of time before energy transfer may be required to maintain regulation. As disclosed in step E, the switch-mode process may be enabled before the voltage Vcc falls below Vcc Stop. The signal to transition trim comparator 228 from a low state to a high state may be provided to node 122. The drive signal in the high state causes the switched mode power supply to participate in the switched mode process. Delivering energy to the output 102A of the power supply 100 through the enabled switch-mode process raises the voltage Vout as shown in step G.

At step H, an unloaded condition may be detected at the output 102A. The detected no-load condition initiates the off mode through the FC circuit. The off mode transitions node 122 to ground. Node 122, which is at ground, holds the outputs of comparator 214 and comparator 228 in a low state. The switch mode process is disabled, thereby preventing energy transfer to the output 102A. The off mode is different from the skip mode by allowing the voltage Vcc at the supply source 102 to fall below the voltage Vcc Stop corresponding to the minimum voltage during regulation.

In step I, the voltage Vcc may have fallen below the voltage Vcc Stop. The start-up mode may be initiated when the optical feedback fails due to the voltage at output 102A or when the signal that causes transistor 132 to hold node 122 to ground is removed. In either case, the startup mode may be enabled because no signal is provided to node 122. When no signal is applied to node 122, comparator 216 is enabled to transition from a low state to a high state. The current source 204 is then coupled to the supply 102, thereby boosting the voltage Vcc. When the current source 204 raises the voltage at the Vcc supply 102 to Vcc Start, the off mode transitions to the Start mode.

The voltage Vcc Start on supply 102 enables optical feedback to transistor 132. Transistor 132 lowers the voltage on node 122 causing start comparator 216 to transition from a high state to a low state. The low state at the output of start-up comparator 216 decouples current source 204 from Vcc supply source 102, thereby preventing further increases in voltage Vcc. The voltage on node 122 causes the output of the trim comparator 228 to transition from a low state to a high state. The drive signal in the high state causes the switch mode power supply controller to deliver energy to output 102A if desired. The voltage Vcc at Vcc Start allows the SMPS to transfer energy to the output 102A as requested by the level of node 122. The voltage Vcc drops to a level corresponding to the regulation level (below Vcc Start) over an extended period of time. As discussed above, the switch mode process or regulation mode may be enabled during step I and will regulate the voltage Vout. Note that the start-up mode of startup allows the system to be powered so that the output voltage can be adjusted by delivering the requested energy to maintain the output voltage at the requested level.

At step J, the power supply 100 is changed from the regulation mode to the off mode. In one embodiment, the adjustment mode transitions through a skip mode and then transitions to a disconnect mode. A light load condition may be detected and a skip mode may be initiated. In skip mode, the signal at node 122 causes the output of trim comparator 228 to transition from a high state to a low state. In other words, the signal at node 122 may be less than the skip level that initiates the skip or standby mode. The drive signal in the low state disables the switch mode power supply controller from delivering energy to the output 102A. The voltage Vout continues to drop over an extended period of time. An unloaded condition may be detected during the skip mode prior to transitioning to the adjust mode. Detection of an unloaded condition initiates a disconnect mode that transitions node 122 to ground. The voltage Vcc may then be allowed to fall below Vcc Stop, as shown in step J. The current source 204 remains decoupled from the supply (node 102) during the skip mode and the off mode.

Similar to step I, at step K, the voltage Vcc may have dropped below the voltage Vcc Stop. Because no signal can be provided to node 122, the startup mode can begin. When no signal can be applied to node 122, comparator 216 is enabled to transition from a low state to a high state. The current source 204 is then coupled to the output terminal 102, thereby boosting the supply voltage Vcc. When current source 204 raises the voltage at node 102 to Vcc Start, the Start-up mode transitions to regulation mode.

The voltage Vcc Start on node 102 enables optical feedback to transistor 132. Transistor 132 lowers the voltage on node 122 causing start comparator 216 to transition from a high state to a low state. The low state at the output of start-up comparator 216 decouples current source 204 from node 102, thereby preventing further increases in voltage Vcc. The voltage on node 122 causes the output of the trim comparator 228 to transition from a low state to a high state. The drive signal in the high state causes the switch mode power supply controller to deliver energy to output 102A if desired. The voltage Vcc at Vcc Start powers the SMPS to allow for the transfer of energy, if desired. Since no energy is transferred to the output terminal 102A but the switch-mode process remains enabled, the voltage Vout drops over an extended period of time.

In step L, the output 102 may be loaded. The signal on node 122 does not drop to a level that can initiate the skip mode. The output of the trim comparator remains in a high state to continue the switch mode process. The drive signal in the high state keeps the switch mode power supply controller in regulation mode. Energy may be transferred to the output 102A via a switch-mode process to maintain the output at the requested regulation level while the drive signal remains in a high state.

Fig. 7 is a timing diagram illustrating a switch mode power supply controller in an off mode implemented via a feedback pin or feedback node according to an embodiment. When describing the circuit components, reference may be made to fig. 1 and 2. Prior to step l, the FC circuit 118 may be in an off mode. The outputs of the start comparator 216 and the trim comparator 228 may both be in a low state. In the off mode, the voltage Vout at the output terminal 102A of the power supply 100 drops below the minimum regulation voltage. At step l, the start-up mode may be initiated when the optical feedback fails due to the voltage Vout at the output terminal 102A or when the signal that causes the transistor 132 to hold the node 122 at ground is removed. In either case, the startup mode is initiated because no signal can be provided to node 122. The voltage on node 122 (e.g., the feedback pin or node) begins to rise by the high impedance current provided by current source 202 driving node 122.

At step l1, the voltage at node 122 rises to the voltage of the breakdown zener diode 208, thereby rendering it conductive. When the zener diode 208 conducts, the output of the start comparator 216 transitions from a low state to a high state. When zener diode 208 becomes conductive, the voltage at node 122 is shown as voltage HVcontrol. The output of start comparator 216, which is in a high state, may couple current source 204 to the Vcc supply (e.g., node 102) of power supply 100. The current from current source 204 rapidly increases the voltage Vcc at node 102. Optical feedback corresponding to voltage Vcc enables transistor 132 to be used to conduct current. Enabled transistor 132 sinks current from current source 202 and lowers the voltage at node 122. The voltage at node 122 may be reduced by optical feedback to render zener diode 208 non-conductive. When the zener diode 208 may not conduct, the output of the start-up comparator 216 transitions from a high state to a low state. The low state at the output of Start comparator 216 may decouple current source 204 from supply 102 when output 102 may be at voltage Vcc Start.

At step l2, the voltage at node 122 in combination with the supply 102 at Vcc Start produces a transition from a low state to a high state at the output of trim comparator 228. The drive signal in the high state causes the switch mode power supply controller to transfer energy via the transformer 112. Thus, the power supply 100 changes from the startup mode to the regulation mode. In one embodiment, the optical feedback may be clamped high until the regulation starts to be activated at the secondary side of the power supply 100. Generally, increasing optical feedback reduces the rate of energy transfer over a period of time. During step l2, the voltage Vcc is reduced at the output terminal 102 as little as possible or no energy transfer to the output terminal 102A occurs.

At step l3, the voltage Vcc is decreased from Vcc Start to an adjustment level corresponding to the output voltage level on 102A. Reducing optical feedback increases the rate of energy transfer over a period of time. Energy may be transferred to the output terminal 102A through a switch-mode process at a rate that increases or prevents Vout from further decreasing with the voltage Vcc. Energy transfer may be provided from the secondary side of the transformer 112.

At step J, the optical feedback continues to drop. In this example, the feedback level becomes smaller than the skip level. During step J, the secondary side no-load detection circuit in the condition and status circuit 130 (fig. 2) detects a no-load condition. The condition and state circuit 130 in the off mode enables the transistor 132 to drive the node 122 to ground. The power supply 100 changes from the regulation mode to the off mode. The low feedback level causes the output of the trim comparator to transition from a high state to a low state. The drive signal in the low state disables the switch mode power supply controller from delivering energy to the output 102A of the power supply 100. The voltage Vcc will continue to drop because no energy can be transferred to mitigate charge loss. As shown, from step J to step J1, the voltage Vcc is reduced to a voltage VccStop.

At step J1, the condition and state circuit 130 maintains the node 122 in the open mode so that the voltage Vcc at the supply 102 continues to fall below the voltage Vcc Stop. The voltage Vcc continues to drop until the optical feedback fails due to the voltage Vout at the output terminal 102A or when the signal holding the transistor 132 to ground the node 122 is removed. In this example, transistor 132 may be turned off when the optical feedback fails. The voltage at node 122 rises, changing the power supply 100 from the off mode to the start-up mode, again indicated by step l. The process continues again as discussed above.

Fig. 8 is a schematic diagram of an FC circuit 118 including an external pull-up according to an embodiment. The diode 814 may have an anode coupled to the secondary transformer winding and a cathode coupled to a storage capacitor 824, and the storage capacitor 824 may have a first terminal coupled to the cathode of the diode 814 and a second terminal coupled to ground. Voltage Vcc1 corresponds to the voltage at the cathode of diode 814. In one embodiment, the storage capacitor 824 may have a smaller capacitance than the storage capacitor 116. Voltage Vcc1 corresponds to voltage Vcc because both are generated by the auxiliary winding of the switch mode power supply.

The external pullup includes a diode 830 and a resistor 840. Diode 830 may have an anode coupled to the cathode of diode 814 and a cathode coupled to resistor 840. Resistor 840 includes a first terminal coupled to the cathode of diode 830 and a second terminal coupled to node 122. When voltage Vcc1 is greater than the forward diode drop above the voltage at node 122, current is conducted by diode 830. Thus, the current that steps up the voltage at node 122 includes the current from current source 202 and the current provided by the external pullup. An external pullup coupled to a feedback pin or feedback node (e.g., node 122) provides several benefits. First, when the power supply 100 is in the off mode, there is a reduced pull-up. Second, while the capacitor (cap) is discharged during the start-up phase, the resistor 840 is increased in pull-up in the ON mode (ON mode), but the amount of charge is limited. Third, since the capacitor is discharged between 2 cycles, in the low frequency skip mode, the storage capacitor 824, which includes a low capacitance value, provides a reduced pull-up. Finally, the need for the current optically generated by transistor 132 and the secondary drive current may be reduced. These benefits result in improved skip or standby modes. Power consumption may be reduced in both standby mode and off mode, thereby improving long-term efficiency of power supply 100. Further improvements can be incorporated by adding an internal pull-up switch controlled by a skip mode controller.

Fig. 9 schematically illustrates an embodiment of a portion of an integrated circuit that includes an open mode detection circuit 910. The off mode detection circuit 910 includes at least two comparators 940 and 942, several resistors 930, 932, a diode 962, a current source 914, an and gate 980, an inverter 960, and a reference voltage 950. The feedback signal enters through pin 920 and, when failing from the transformer, if the feedback signal is high, the HV source via pin 922 provides Vcc through current source 912. In the illustrated IC, Vcc is provided via pin 924, the drive signal is provided via pin 926, and the IC is grounded via pin 928. Another current source 912 is connected to an adjustment module 970, which adjustment module 970 is operatively connected to reference Vdd, another current source 916, and a diode 964. Diode 964 is operatively connected to resistor 934, resistor 934 being connected to node (pin) 920 and to the positive terminal of comparator 944. The opposite terminal of current source 916 is connected to the negative terminal of comparator 944 and to voltage reference 952. The comparator 944 is operatively connected to the SMPS control section to drive the power switch through pin 926.

FIG. 10 is a schematic diagram of an FC circuit 118 that may provide power factor correction feedback according to an embodiment. For brevity, only the circuitry added to the FC circuitry 118 will be discussed. The path for coupling current source 204 between node 120 and node 124 may be controlled by two switches. The added switch allows the HV voltage to be used as power factor correction feedback. The two switches also provide low off-mode consumption by turning off the current source 204 in standby mode or off mode. Switch 206A may have a first terminal coupled to node 120 and a control terminal coupled to an output of enable comparator 216. Current source 204 may have a first terminal coupled to a second terminal of switch 206A. The operation of switch 206B is similar to the operation of switch 206A by start-up comparator 216 described above. Switch 206A may be added to FC circuit 118. Switch 206B may have a first terminal coupled to the second terminal of current source 204, a control terminal coupled to the first terminal of Vcc control circuit 904, and a second terminal coupled to node 124. Vcc control circuit 904 may have a second terminal coupled to node 124.

When little or no signal is provided to node 122, switch 206B may be closed in the startup mode, thereby allowing the voltage on node 122 to rise to a level that transitions the output of startup comparator 216 from a low state to a high state. Closing switch 206B couples current source 204 for receiving voltage HV at node 120. In addition, when switch 206A is closed, the voltage HV at node 120 may be provided as power factor correction feedback to the switch mode power supply controller. Conversely, when the voltage on node 122 drops below the reference voltage 214, the switch 206B may be opened in the skip mode and the open mode. Including a switch 206B that will decouple the current source 204 from the node 124. In one embodiment, the reference voltage 214 may be reduced to a lower level than the application described above. The reduced reference voltage 214 keeps the switch 206B closed during the startup mode.

Vcc control circuit 904 controls the operation of switch 206B. Vcc control circuit 904 detects or senses the voltage Vcc at node 124. Detection circuitry in Vcc control circuit 904 provides a control signal corresponding to voltage Vcc to supply 102. When the voltage Vcc at node 124 may be greater than a predetermined value, Vcc control circuit 904 provides a control signal that opens switch 206B, thereby decoupling current source 204 from node 124. Vcc control circuit 904 provides a control signal that closes switch 206B when energy may be requested. For example, energy may be requested when the power supply 100 may be first turned on or transitioned from an off mode to a start-up mode.

FIG. 12 is a schematic diagram of an FC circuit 118 with an external voltage source according to an embodiment. An external voltage source may be coupled to node 120. In an embodiment, the external voltage supply may be a lower voltage than the voltage generated by the switched mode power supply 100 in the previously explained solution. In this example, the inclusion of an external voltage source allows for an embedded off mode. The start-up control may also be combined with feedback. The lower voltage of the external voltage source at node 120 allows for simplification of the circuitry and reduced part count of FC circuit 118. In particular, resistor 1244 replaces current source 202. Resistor 1242 also eliminates the need for resistor 210 and zener diode 208 to support high voltage operation. Resistor 1242 may have a first terminal coupled to node 120 and a second terminal coupled to node 122. In the startup mode, the FC circuit 118 operates similarly. No signal can be coupled from transistor 132 to node 122, allowing resistor 1242 to raise the voltage on node 122.

External discrete off-mode circuit 1200 may have a first terminal coupled to the collector of transistor 132 and a second terminal coupled to node 124. The discrete off-mode circuit 1200 includes resistors 1240, 1242, 1244, 1246, and 1248, a pnp transistor 1220, an npn transistor 1222, a diode 1250, and a diode 1252. Resistors 1240 and 1106 form a resistive divider for setting the voltage at the emitter of npn transistor 1222. Resistor 1242 may have a first terminal coupled to node 120 and a second terminal. Resistor 1240 may have a first terminal coupled to the second terminal of resistor 1242 and a second terminal coupled to ground. The base current to npn transistor 1222 can be provided through resistor 1246. Resistor 1246 may have a first terminal coupled to node 120 and a second terminal coupled to the base of pnp transistor 1222. Resistor 1244 may be an emitter degeneration resistor (degeneration resistor) for pnp transistor 1220. Resistor 1244 may have a first terminal coupled to node 120 and a second terminal. When the startup mode can be started, the pnp transistor 1220 supplies current to charge the storage capacitor 116 and raise the voltage Vcc on the node 102. The current output by pnp transistor 1220 corresponds to the voltage across resistor 1244. The voltage across resistor 1244 and the base-emitter junction of pnp transistor 1220 may be equal to the forward voltage drop of diodes 1250 and 1252. Diodes 1250 and 1252 are in series. pnp transistor 1220 may have an emitter coupled to the second terminal of resistor 1244, a base, and a collector coupled to the second terminal of circuit 1200. Diode 1250 may have an anode coupled to node 120, and a cathode. Diode 1252 may have an anode coupled to the cathode of diode 1250 and a cathode coupled to the base of pnp transistor 1220. When enabled in the start-up mode, npn transistor 1222 sinks the base current of pnp transistor 1220. Resistor 1112 may have a first terminal coupled to the base of pnp transistor 1220, and a second terminal. npn transistor 1222 may have a collector coupled to a second terminal of resistor 1112, a base coupled to a first terminal of circuit 1200, and an emitter coupled to a second terminal of resistor 1240. An external diode 1100 replaces the diode 224 coupled to the trim comparator 228. External diode 1100 isolates circuit 1200 from node 122 of FC circuit 118. External diode 1100 may have an anode coupled to node 122 and a cathode coupled to a first terminal of circuit 1200. In the start-up mode, the output of the trim comparator 228 is in a low state and the transistor 132 may be off. The voltage at the base of npn transistor 1222 is boosted by a current provided through resistor 1246. The enabled npn transistor 1222 provides a base current to the pnp transistor 1220, thereby enabling the device. Circuit 1200 provides current from the second terminal to Vcc supply 102 of power supply 100. Conversely, when enabled in, for example, an off mode, skip mode, or trim mode, transistor 132 sinks a current that pulls the voltage at the base of npn transistor 1222 to a voltage that turns off the device. When npn transistor 1222 is off, no base current can be provided to pnp transistor 1220 so that no current can be provided by circuit 1200 to output 102. Depending on the mode of operation, the trim comparator 228 is in a low state or a high state, as disclosed above. Even in the off mode, external discrete off mode circuit 1200 maintains Vcc for the X2 capacitor discharge function. During the off mode, the internal voltage Vdd may be cut off to reduce power consumption. The off mode may be implemented when the feedback corresponding to transistor 132 is at a low level, thereby improving the long-term power efficiency of the power supply by allowing the voltage Vcc to fall below Vcc Stop.

FIG. 13 schematically illustrates an embodiment of a portion of a system according to an embodiment of the invention. Illustrated is a schematic diagram of a disconnect control circuit configured to shut off a PFC IC. FIG. 14 schematically illustrates an embodiment of a portion of a system according to an embodiment of the invention.

Fig. 15 schematically illustrates an embodiment of a portion of an integrated circuit that may be part of a system according to an embodiment of the invention.

Fig. 16 schematically illustrates an embodiment of a portion of an integrated circuit that may be part of a system according to an embodiment of the present invention.

FIG. 17 illustrates a portion of the operation of a portion of the system of an embodiment. Various operations at specific steps will be discussed. In step AA, the HV supply is triggered by a feedback signal having a positive value of slope over time equal to about the HV control level. The HV supply is turned on until Vcc = Vcc Start, at which time the Drive signal starts at step BB and the system enters Start mode. At step BB, Vcc = Vcc Start, HV supply is turned off, and IC is started by the Start of the drive signal while Vcc falls below Vcc Start. The on mode is initiated by a constant feedback signal (FB), via step CC. At step CC, the system is in on mode, FB > skips levels, Vcc is regulated from the transformer, and the HV supply is turned off while Vcc > Vcc Stop. In the light load skip mode start of step DD, there is light load, FB < skip level, and Vcc falls but stays above VccStop. When the feedback signal exceeds the trip level, the drive signal, which is boosted to Vcc, is initiated with energy from the transformer, as illustrated in step EE. When the feedback signal falls below the skip value, the drive signal stops and Vcc begins to fall again, as illustrated in step FF. Vcc continues to drop as long as a light load is indicated. If no load is detected, such as when the feedback signal is below a lower threshold 1700 (e.g., a skip level), Vcc continues to drop without any adjustment attempts. When Vcc falls below a lower threshold level 1710 (e.g., Vcc Stop), at least one embodiment initiates a disconnect control signal 1720, which provides power from the HV supply source that increases 1710Vcc above Vcc Stop so that Vcc does not fail. In step HH, when Vcc equals or exceeds Vcc Start, the HV supply is stopped, allowing Vcc to drop. If the feedback signal is still less than the skip value, the system remains in the off mode and Vcc is stepped down. If the secondary voltage is too low, the optical device (Opto) fails or the disconnect signal disappears (1740), requesting a restart and ending the disconnect mode. In this case, the FB signal rises again due to Vcc pull-up. When FB > HV control level (1730), the off control level falls and the Vdd supply is turned on again. FB is to be clamped until the start of the adjustment mode activated from the secondary side. As illustrated in step JJ driven by the secondary regulation, FB falls < skip level, Vcc falls because the drive signal is off. After a certain time, the secondary no-load detection provides a turn-off signal, which keeps FB < skip level. The HV supply will be activated when necessary to keep Vcc above Vcc Stop. When the slope of the feedback signal over time is positive and the feedback signal exceeds the HV control level, the off signal is stopped, the Vdd signal is enabled and is a drive signal indicating the start of the on mode, as illustrated in step KK. If the feedback signal has fallen but remains stable above the HV control level, the feedback signal is greater than the skip value and Vcc is provided directly from the transformer, as illustrated in step LL.

In this context, a method of implementing an off mode, a regulation mode, and a start-up mode in a switched mode power supply via a feedback pin or feedback node of a switched mode power supply controller is disclosed in one or more embodiments. The disclosed steps may be performed in any order or combination. In a first step, no-load conditions may be detected. In one embodiment, the no-load condition is that no device requiring power is loaded at the output of the power supply. Examples of no-load conditions are that a device coupled to the output is off, that the device is in a sleep mode, that the device is in a power saving mode, or that no device is coupled to the output. In one embodiment, a circuit coupled to an output of a power supply detects a no-load condition. In a second step, the off mode signal is provided to a feedback pin or feedback node. In the embodiments disclosed above, the off mode signal may be coupled to the base of a transistor that pulls the feedback pin or feedback node to a low state or ground.

The low state at the feedback pin or feedback node may be coupled to the positive input of the start-up comparator. In a third step, a low state may be generated at the output of the start comparator when the off mode signal may be provided. A negative voltage difference may be generated from the positive input to the negative input of the start-up comparator, resulting in a low state at the output of the start-up comparator. The current source is decoupled from the output of the power supply in the low state at the output of the start comparator. Thus, no starting current is supplied to the output of the power supply to raise the voltage thereon.

The low state of the feedback pin or feedback node may also be coupled to the positive input of the trim comparator. In a fourth step, a low state may be generated at the output of the trim comparator when the off mode signal is provided. A negative voltage difference may be generated from the positive input to the negative input of the trim comparator resulting in a low state at the output of the trim comparator. The switched mode power supply controller is disabled in a low state at the output of the trim comparator. In other words, a low state at the output of the trim comparator disables the switch mode process from transferring energy to the output of the switch mode power supply. Thus, no energy transfer occurs due to the switch-mode process of the switch-mode power supply. Not providing charge to the output of the power supply will cause the voltage to drop below the minimum regulation voltage.

In a fifth step, the off mode signal is removed from the feedback pin or node when the voltage at the output of the power supply drops below the off mode output voltage. Typically, the voltage at the output is prevented from dropping below the off-mode output voltage. The off-mode output voltage may be lower than the minimum voltage when the switched-mode power supply is in regulation mode. The off mode increases power efficiency by extending the time between energy transfers when power or regulated voltage is not needed.

In a sixth step, a high state may be generated at the output of the start comparator. In one embodiment, removing the off mode signal results in no signal being provided to the feedback pin or feedback node. The absence of a signal at the feedback pin or feedback node results in a high state being generated at the feedback pin or feedback node. In this embodiment, a transistor, which may be coupled to a feedback pin or feedback node, may be turned off, thereby generating a no signal. A current source coupled to the feedback pin or feedback node generates a high state thereon. A positive voltage difference is generated from the positive input to the negative input of the start-up comparator resulting in a high state at the output of the start-up comparator.

In a seventh step, the high state at the output of the start-up comparator enables the current source to be coupled to the output of the switched-mode power supply. Due to the current provided by the current source, the voltage at the output of the switched mode power supply will rise. In this example, the trim comparator does not change state from a low state. The high state at the feedback pin or node and the output voltage of the switched mode power supply below the minimum regulation voltage maintain a negative voltage difference from the positive input to the negative input of the regulation comparator.

In an eighth step, a regulation mode signal is provided to the feedback pin or node when the voltage at the output of the power supply rises due to the current provided by the current source in the start-up mode. In one embodiment, the voltage at the output of the power supply may be rapidly charged by the current source. The adjustment mode signal may be a feedback signal corresponding to a voltage at the output of the power supply. More specifically, a signal corresponding to a voltage at an output of the power supply may be optically generated and coupled to a base of a transistor that includes a collector coupled to a feedback pin or feedback node. The signal provided to the base of the transistor generates a collector current which may be a regulated mode signal. As mentioned earlier, the regulation mode signal will vary with the voltage at the output of the power supply.

In a ninth step, a low state may be generated at the output of the start-up comparator when the trim-mode signal may be provided to the feedback pin or feedback node. The trim mode signal reduces the voltage at the feedback pin or node so that a negative voltage difference can be generated from the positive input to the negative input of the start-up comparator. The low state at the output of the start-up comparator can decouple the current source from the output of the power supply, thereby preventing a further increase in voltage. The current source may be stopped or prevented from supplying current to the output of the power supply. In one embodiment, the current source may be decoupled from the output of the power supply at about the time or before the voltage reaches the maximum regulated voltage.

In a tenth step, a high state may be generated at the output of the trim comparator. In this example, there are two conditions in the adjustment mode. First, the voltage at the output of the power supply may be greater than the minimum regulation voltage. Second, the voltage at the feedback pin or feedback node may have transitioned from a high state to a low state in the startup mode due to the trim mode signal. These two conditions combine to generate a positive voltage difference from the positive input to the negative input of the trim comparator. The positive voltage difference causes the output to transition from a low state to a high state. The switch mode power supply controller is enabled in a high state at the output of the trim comparator.

In a tenth step, energy may be transferred via a switch mode process to maintain the voltage at the output of the power supply between the minimum regulation voltage and the maximum regulation voltage. The switch mode process monitors the voltage at the output of the power supply and maintains the voltage between a minimum regulation voltage and a maximum regulation voltage. The frequency and amount of energy transfer may vary with the load on the output of the power supply. As disclosed herein, transitions between different operating modes can be achieved without adding pins to the switch mode power supply controller. Thus, the disconnect mode can be implemented on existing designs without requiring redesign of the printed circuit board or major component changes, thereby allowing for rapid adoption of more power efficient power supplies.

In at least one embodiment, no energy is transferred through the transformer to supply the IC despite Vcc being less than the requested level in the OFF mode, wherein the HV source generator will not be activated when the feedback/ON/OFF control level is below the HV control level, wherein the HV control level is above the feedback skip level.

Although embodiments have been described with reference to particular embodiments, those skilled in the art will recognize that many changes may be made thereto without departing from the spirit and scope of the described embodiments. Each of these embodiments and obvious variations thereof is contemplated as falling within the spirit and scope of the present invention.

Claims (19)

1. A semiconductor voltage controller comprising:

a start-up mode circuit associated with a start-up mode;

an off mode circuit associated with an off mode, wherein the voltage controller can be configured to receive a feedback signal and an off mode signal from a single input and provide an output voltage, the voltage controller can be configured to be in the off mode when the feedback signal is less than a skip level and the feedback signal is less than a HV control level, and the voltage controller can be configured to be in a start mode when the feedback signal is greater than the HV control level and the voltage Vcc is less than a voltage Vcc-start; and wherein the voltage controller is configurable to:

while in the off mode, when the slope of the feedback signal over time is positive and when the feedback signal is approximately equal to the HV control level, then starting to generate the voltage supply signal and the drive signal; or

When in the off mode, when the slope of the feedback signal over time is positive and when the feedback signal is approximately equal to the HV control level, then generation of the voltage supply signal is initiated.

2. The voltage controller of claim 1, wherein the voltage controller is configurable to begin generating the drive signal and the voltage supply signal if the feedback signal is greater than the HV control level while in the off mode, the voltage controller is configurable to stop the voltage supply signal when the voltage Vcc is approximately equal to the voltage Vcc-start, and the voltage controller is configurable to stop the drive signal when the feedback signal is approximately less than the adjusted low value corresponding to the skip level.

3. The voltage controller of claim 1, wherein the voltage controller is configurable, when in the off mode, to begin generating the voltage supply signal and the drive signal when a slope of the feedback signal over time is positive and when the feedback signal is approximately equal to the HV control level, the voltage controller is further configurable to stop the voltage supply signal when the voltage Vcc is approximately equal to the voltage Vcc-start, and the voltage controller is configurable to stop the drive signal when the slope of the feedback signal is negative and the feedback signal is approximately equal to an adjusted low value corresponding to the skip level.

4. The voltage controller of claim 1, wherein the voltage controller is configurable, when in the off mode, to begin generating the voltage supply signal when a slope of the feedback signal over time is positive and when the feedback signal is approximately equal to the HV control level, the voltage controller is further configurable to stop the voltage supply signal when the voltage Vcc is approximately equal to the voltage Vcc-start, and the voltage controller is configurable to start the drive signal when the voltage Vcc is approximately equal to the voltage Vcc-start and to stop the drive signal when the slope of the feedback signal is negative and the feedback signal is approximately equal to the adjusted low value corresponding to the skip level.

5. The voltage controller of claim 1, wherein the voltage controller is configurable to start generating the voltage supply signal when a slope of the feedback signal over time is positive and the feedback signal is approximately equal to the HV control level, and to stop generating the voltage supply signal when the voltage Vcc is approximately equal to the voltage Vcc-start.

6. The voltage controller of claim 1, wherein in the off mode the voltage Vcc is less than the requested level, no energy is transferred through a transformer driven by the PMW control circuit enabled by the voltage controller to supply the voltage controller, and wherein the HV source generator providing the HV voltage is not activated when the feedback signal is below a HV start level, wherein the HV start level is above the skip level.

7. A voltage controller according to claim 5, wherein the voltage controller is configurable to generate the drive signal during the start-up mode when the voltage Vcc is equal to the voltage Vcc-start.

8. The voltage controller of claim 7, further comprising:

a standby circuit associated with a standby mode, wherein the voltage controller can be configured to switch to the standby mode when the feedback signal is less than the HV control level and the voltage Vcc is greater than the voltage Vcc-stop.

9. A voltage controller, comprising:

a start-up mode circuit associated with a start-up mode;

an off mode circuit associated with an off mode, wherein the voltage controller can be configured to receive a feedback signal and an off mode signal from a single input and provide an output voltage, the voltage controller can be configured to be in the off mode when the feedback signal is less than a skip level and the feedback signal is less than a HV control level, and the voltage controller can be configured to be in a start mode when the feedback signal is greater than the HV control level and the voltage Vcc is less than a voltage Vcc-start; and wherein the voltage controller can be configured to, while in the off mode, begin generating the voltage supply signal if the voltage Vcc is approximately equal to the voltage Vcc-stop, the voltage controller can be configured to stop the voltage supply signal when the voltage Vcc is approximately equal to the voltage Vcc-start, and the voltage controller can be configured to start the drive signal when a slope of the feedback signal over time is positive and the feedback signal is approximately equal to the HV control level, the voltage controller can be configured to stop the drive signal when the slope of the feedback signal is negative and the feedback signal is approximately equal to an adjusted low value corresponding to the skip level.

10. A method of controlling a switched mode power supply, comprising:

inputting a feedback signal and a disconnect mode signal from a single input;

configuring the switch mode power supply to operate in an off mode in response to the feedback signal being less than the HV control level and the off mode signal being less than the skip level, and configuring the switch mode power supply to operate in a start mode in response to the feedback signal being greater than the HV control level and the voltage Vcc being less than the voltage Vcc-start;

disabling the start-up mode when the feedback signal is less than the skip level;

starting to generate the voltage supply signal and the drive signal when the slope of the feedback signal over time is positive and the feedback signal is approximately equal to the HV control level; or

The generation of the voltage supply signal begins when the voltage Vcc is approximately equal to the voltage Vcc-stop.

11. The method of claim 10, wherein when the voltage supply signal and the drive signal are generated when the slope of the feedback signal over time is positive and the feedback signal is approximately equal to the HV control level, the method further comprises:

stopping generating the voltage supply signal when the voltage Vcc is approximately equal to the voltage Vcc-start; and

the generation of the drive signal is stopped when the slope of the feedback signal is negative and the feedback signal is approximately equal to the adjusted low value corresponding to the skip level.

12. The method of claim 10, wherein when generating the voltage supply signal when the voltage Vcc is approximately equal to the voltage Vcc-stop, the method further comprises:

if voltage Vcc is approximately equal to voltage Vcc-stop, then the generation of the voltage supply signal begins;

stopping generating the voltage supply signal when the voltage Vcc is approximately equal to the voltage Vcc-start;

beginning to generate the drive signal when the slope of the feedback signal over time is positive and the feedback signal is approximately equal to the HV control level;

stopping generating the drive signal when the slope of the feedback signal is negative and the feedback signal is approximately equal to the adjusted low value corresponding to the skip level.

13. A method of controlling a switched mode power supply, comprising:

inputting a feedback signal and a disconnect mode signal from a single input;

configuring the switch mode power supply to operate in an off mode in response to the feedback signal being less than the HV control level and the off mode signal being less than the skip level, and configuring the switch mode power supply to operate in a start mode in response to the feedback signal being greater than the HV control level and the voltage Vcc being less than the voltage Vcc-start;

disabling the start-up mode when the feedback signal is less than the skip level;

starting to generate the voltage supply signal and the drive signal when the slope of the feedback signal over time is positive and the feedback signal is approximately equal to the HV control level; and

the method further comprises the following steps:

generating a drive signal and a voltage supply signal if the feedback signal is greater than the HV control level;

stopping the voltage supply signal when the voltage Vcc is approximately equal to the voltage Vcc-start; and

the drive signal is stopped when the feedback signal is less than about the adjusted low value corresponding to the skip level.

14. A method of controlling a switched mode power supply, comprising:

inputting a feedback signal and a disconnect mode signal from a single input;

configuring the switch mode power supply to operate in an off mode in response to the feedback signal being less than the HV control level and the off mode signal being less than the skip level, and configuring the switch mode power supply to operate in a start mode in response to the feedback signal being greater than the HV control level and the voltage Vcc being less than the voltage Vcc-start;

disabling the start-up mode when the feedback signal is less than the skip level;

starting to generate the voltage supply signal and the drive signal when the slope of the feedback signal over time is positive and the feedback signal is approximately equal to the HV control level;

stopping generating the voltage supply signal when the voltage Vcc is approximately equal to the voltage Vcc-start;

starting to generate a drive signal when the voltage Vcc is approximately equal to the voltage Vcc-start; and

the generation of the drive signal is stopped when the slope of the feedback signal is negative and the feedback signal is approximately equal to the adjusted low value corresponding to the skip level.

15. A switched mode power supply controller including a feedback node for receiving a feedback signal corresponding to an output voltage of a power supply, the controller comprising:

a first comparator comprising a first input coupled to the feedback node, a second input coupled to a first reference voltage, and a first output, wherein the first comparator is configured to begin starting by coupling a current to the output of the power supply; and

a second comparator comprising a third input coupled to the feedback node, a fourth input coupled to a second reference voltage, and a second output for enabling energy transfer to the output of the power supply, wherein the first and second comparators are configured to support start-up, regulation, and disconnect mode processes by the feedback signal;

a first current source comprising a first electrode configured to receive a first supply voltage and a second electrode configured to deliver a current thereto coupled with a feedback node;

a first switch including a third electrode configured to receive a first voltage, a control electrode coupled with an output of the first comparator, and a second terminal; and

a second current source including a fourth electrode coupled to the second terminal of the first switch and a fifth electrode coupled to the output of the power supply.

16. The switch mode power supply controller of claim 15, further comprising:

a first zener diode comprising a cathode coupled to the feedback node and an anode coupled to the first input of the first comparator;

a first resistor including a sixth electrode coupled with the first input of the first comparator and a seventh electrode configured to receive the second voltage; and

a second zener diode comprising a second cathode coupled to the first input of the first comparator and a second anode configured to receive a second voltage.

17. The switch mode power supply controller of claim 16, further comprising:

a first diode comprising a third cathode coupled to the feedback node and a third anode coupled to a third input of the second comparator; and

a second resistor comprising an eighth electrode coupled to the third input of the second comparator and a ninth electrode coupled to the output of the power supply.

18. The switch mode power supply controller of claim 17, further comprising:

an external pullup on the feedback node.

19. The switch mode power supply controller of claim 18, further comprising:

a power factor correction feedback.