HK1187150B - Isolation structures for integrated circuits and modular methods of forming the same - Google Patents

Description

Isolation structure for integrated circuit and modular method for forming the same

The present application is a divisional application of patent applications with application number 200780027883.3, international application date 2007/5/30, applicant's advanced analog technology corporation, entitled "isolation structure of integrated circuit and module method for forming the same".

Cross Reference to Related Applications

This application is related to application No.10/262,567 filed on 29/9/2002, now U.S. patent No.6,855,985, which is incorporated herein by reference in its entirety.

Technical Field

The present invention relates to semiconductor chip fabrication, and more particularly to a method of monolithically fabricating and electrically isolating bipolar, CMOS and DMOS transistors and passive devices in a semiconductor chip at high density without the need for epitaxial layers or high temperature fabrication process steps.

Background

In the fabrication of semiconductor Integrated Circuit (IC) chips, it is often desirable to electrically isolate devices formed on the surface of the chip. There are various ways to do this. One approach is by using the well-known LOCOS (local oxidation of silicon) process, in which the surface of the chip is masked with a relatively hard material such as silicon nitride and a thick oxide layer is thermally grown in the openings of the mask. Another approach is to etch a trench in the silicon and then fill the trench with a dielectric material such as silicon oxide, also known as trench isolation. While both LOCOS and trench isolation can avoid surface conduction between devices, they do not facilitate complete electrical isolation.

Complete electrical isolation is required to integrate certain types of transistors including bipolar junction transistors and various Metal Oxide Semiconductor (MOS) transistors including power DMOS transistors. Complete electrical isolation is also required to allow the CMOS control circuitry to float to a potential well above the substrate potential during operation. Complete isolation is particularly important in the fabrication of analog, power, and mixed signal integrated circuits.

Non-isolated CMOS fabrication and structure

Conventional CMOS wafer fabrication, while providing high density transistor integration, does not facilitate complete electrical isolation of the devices it manufactures. For example, fig. 1A shows a simplified cross-sectional view of a prior art double well CMOS. Fig. 1A shows N-well (NW) regions 4A and 4B and P-well (PW) regions 3A and 3B formed in a P-type substrate 2 prior to transistor fabrication.

Fig. 1B shows CMOS structure 10 after transistor formation, which includes N-channel MOSFETs fabricated within P-well 3A, P-channel MOSFETs formed within N-well 4B, isolated by intervening LOCOS field oxide layer 11. The combination of P-channel and N-channel MOSFETs, together, form a complementary MOS transistor, also known as a CMOS.

Within PW region 3A, an N-channel MOSFET is formed, which includes a shallow N + source-drain implant region 14 with a Lightly Doped Drain (LDD) 15, a polysilicon gate 19, and P + to PW contact regions 13. Within NW region 4B, a P-channel MOSFET is formed comprising shallow P + source-drain implant region 17 with LDD18, polysilicon gate 19, and N + to NW contact region 12. The NW and PW regions are ion implanted, typically with a subsequent high temperature diffusion to drive the dopants into the substrate to a greater depth than the implant. The depth of the well is typically greater for higher voltage devices, such as 12V, than for lower voltages, especially 3.3V or lower.

The transistor packing density of the CMOS structure 10 is limited to a large extent by the area wasted by the LOCOS oxide 11, which cannot be reduced to deep sub-micron dimensions without encountering numerous problems. Another limitation of the CMOS structure 10 is that it includes a gate structure of doped polysilicon 19 without any overlying shunt metal. As transistors are scaled to smaller sizes, the gate resistance contributes to slower switching speeds and increased propagation delay. The effect of this gate resistance practically limits CMOS scaling to gate sizes in the 0.8 to 0.6 micron range.

Another major limitation of CMOS10 in analog circuits is its lack of complete electrical isolation. As shown, PW region 3A is shorted to substrate 2. Since the P-well 3A electrically forms the body (or back-gate) of the NMOS transistor, and since the P-type substrate 2 needs to be biased to the most negative on-chip potential (referred to herein as "ground"), the body connection of each N-channel transistor is biased to ground, limiting its useful operating voltage range and subjecting the N-channel MOSFET to undesirable substrate noise.

The structure 80 shown in fig. 2A represents a general prior art CMOS implementation for CMOS transistors having gate lengths of 0.35 microns or less. In this structure, LOCOS field oxide layer 11 is replaced by a dielectric-filled shallow trench 81 having a size of half or less of the minimum LOCOS size. The polysilicon gate includes a metal silicide (e.g., platinum silicide) to reduce gate resistance. The metal sandwich polysilicon stack is sometimes referred to as a polycide (polycide) layer, a connection of polysilicon and silicide. Note that in CMOS structure 80, P-well 3A is electrically shorted to P-type substrate 2 despite its smaller devices and capability for high integration density.

N-channel MOSFET25, shown in cross-section in fig. 1C, is a non-isolated N-channel device of LOCOS-type CMOS structure 10, which includes P-well 27 formed in P-type substrate 26, N + implant region 33, gate oxide 36 located over PW channel region 35, topped with polysilicon gate 38 and gate silicide 39. Lightly doped drain extension 34 is self-aligned to gate 38 and N + region 33 is self-aligned to sidewall spacer 37. Also in MOSFET25, a single layer of metal interconnect 41 is also included for illustrative purposes, although integrated circuits may use from 2 to 10 layers of metal interconnects. Metal interconnect 41, typically aluminum copper or an aluminum copper silicon alloy, contacts N + region 33 through a contact opening in interlayer dielectric (ILD) 32 and through thin barrier metal 40. A barrier metal, typically comprising titanium, platinum or tungsten, is introduced to avoid metal burrs (i.e., filaments) from alloying through the N + to P-well junctions and shorting the transistor junctions during the process.

Note that the uniquely shaped oxide 31 has the appearance of a bird's head and an extended beak where the oxide thickness is graded over a distance of tens of microns. This shape results from the stress present between the silicon and the overlying nitride layer used to locally avoid oxidation in the active device region. As the field oxidation progresses, oxygen under the nitride mask diffuses, raising its edges to create unique feature shapes. The bird's beak has several adverse effects on smaller transistors, affecting the threshold and gain of the transistor, and wasting usable area (real estate). In some processes, P-type field dopant PFD29 is introduced prior to LOCOS field oxidation in order to increase the threshold and suppress surface leakage between any two adjacent N-type regions. N-type field dopant NFD30 may also be introduced into the field region above N-well region 28 to avoid parasitic leakage between adjacent P regions. A problem with both NFD and PFD regions is that they diffuse too deeply during field oxidation and can adversely affect the electrical characteristics of the transistor, particularly for deep submicron devices.

Another characteristic of the P-well 27 is its non-Gaussian (Gaussian) doping profile, particularly in the channel region 35. One possible doping profile along the vertical section line a-a' is shown in the dopant concentration diagram 50 of fig. 1D. As shown, the dopant concentration of PW27, as shown by curve 52, follows a gaussian profile that intersects the constant dopant concentration of substrate 26, shown as horizontal line 51. Since PW27 and substrate 26 are both P-type, there is no PN junction where they meet, and the P-well is not isolated from the substrate. Peaks 53, 54, and 55 represent implanted P-type dopants located in the trench region to avoid body punch-through breakdown, to avoid subsurface leakage, and to set the threshold voltage of the device, respectively. However, the graph shown represents an ideal one-dimensional doping profile and ignores the effects of lateral encroachment under the gate caused by field dopants or field oxides, both of which often alter the two-dimensional and even three-dimensional doping profiles in an adverse manner. Tuning the LOCOS to a smaller size of a thinner final thickness is problematic as the beak shape becomes sensitive to slight process variations.

N-channel MOSFET100, shown in cross-section in fig. 2B, avoids the aforementioned LOCOS problem by replacing the field oxidation process with a dielectric filled trench 104. Methods of Forming dielectric-filled trench Isolation regions are discussed in related application No.11/298,075 filed by Richard k.williams at 2005, 12/9 entitled "Isolation Structures for Semiconductor Integrated Circuit Substrates and methods of Forming the same," which is incorporated herein by reference in its entirety. Without LOCOS, no bird's beak is present to encroach on polysilicon gate 113 or affect the doping of channel region 112, and device 100 can be scaled to smaller dimensions. Similar to its predecessor, N-channel MOSFET100 is formed in P-well 102, which P-well 102 is electrically shorted to P-substrate 101 and does not provide electrical isolation.

Figure 3A shows several typical prior art process flows for fabricating non-isolated CMOS using LOCOS or trench isolation. Shown as a series of cards, these cards with squared corners are the process steps that must be followed while cards with clipped corners (e.g., NFD injection) represent optional process steps.

Fig. 3B shows a schematic representation of a CMOS pair 130 that includes a P-channel MOSFET132 and an N-channel MOSFET131 and is fabricated using either of the described prior art fabrication procedures. Each transistor includes four terminals-a source S, a drain D, a gate G, and a bulk or back gate B. In the case of P-channel MOSFET132, its source-to-body junction is shown by PN diode 137. The resistance of the N-well region is shown as a lumped-circuit-element resistance 138, but is actually spatially distributed across the device, especially for large area power devices.

One weakness of P-channel 132 is that it inherently includes a substrate PNP139 that is parasitic to the construction of the device. As shown, in the case of an emitter that injects holes into the N-well base from the source, some of these holes may penetrate the N-well base without recombining and may eventually be collected by the substrate as a flow of holes. If the gain of the parasitic PNP139 is too high, especially in the case of lightly doped shallow N-wells, bipolar fast reverse breakdown (also known as BVceo or BVcer breakdown) may result and the device may be damaged or destroyed. Without isolation, it is difficult to control the characteristics of the parasitic PNP139 without affecting other characteristics of MOSFET132, such as its threshold voltage.

The body of N-channel MOSFET131 is shorted to the substrate and thus not isolated, and the source-to-body junction of N-channel MOSFET131 is schematically represented by PN diode 133; and the drain-to-body junction of N-channel MOSFET131 is represented by PN diode 134, the body being represented here by the ground symbol. The resistance of the P-well and surrounding P-type substrate region is shown as lumped circuit element resistance 135, which is actually spatially distributed across the device and substrate, especially for large area power devices. In addition to the circuit meaning of the body-connected connection to ground, the forward bias of the drain diode 134 injects electrons into the P-type substrate, which can travel a significant distance across the integrated circuit (chip) before recombining or being collected. Such parasitic ground currents can adversely affect other devices and impair proper circuit operation.

Since most CMOS pairs are used as logic gates in digital circuits (e.g., inverter 150 in fig. 3C), parasitic diodes 154 and 153 remain reverse biased for all operating conditions normally encountered by N-channel 151 and P-channel 152. However, if the same inverter is used to drive the inductor in a Buck switching regulator, the diode 153 will become forward biased as long as the P-channel 152 is off, injecting current into the substrate and potentially causing undesirable phenomena to occur.

A similar problem arises when non-isolated CMOS is used to implement the cascode clamped output driver 160 shown in fig. 3D. In this circuit, the output voltage of the inverter including the N-channel 161 and P-channel 163 is clamped to some maximum positive voltage by the N-channel follower 162, and the N-channel follower 162 limits the output voltage to its gate bias V_biasA threshold voltage V below_TN(162). By its cascode action, the inverter can reduce, i.e., "level shift," its output to a smaller voltage range than the supply voltage Vcc. Diodes 164, 165, 166, 167 remain reverse biased during normal operation. The problem is that since diode 166 is reverse biased to a voltage equal to Vout, the threshold of N-channel 162 increases in proportion to the output voltage and thereby limits the maximum output voltage of the circuit. If N-channel MOSFET162 is isolated, its source and body can be shorted to the output so that diode 166 is never reverse biased and its threshold voltage remains constant.

Junction isolated CMOS fabrication and structure

The need for electrically isolated CMOS is further illustrated in the circuit 150 of fig. 4A, where pairs of N-channel MOSFETs 151 and 152 are connected in a totem pole configuration and driven out of phase by a break-before-make (BBM) circuit 155. To achieve low on-resistance independent of its operating conditions, high-side N-channel MOSFET152 requires a source-body short (so that at all times V_SB0). The floating bootstrap capacitor 157 powers the floating gate drive circuit 156 to provide the appropriate gate bias voltage V for the MOSFET152_GSEven when the high side device is on and Vout is substantially equal to Vcc. To implement bootstrap driving, the floating circuit 156 and the high side MOSFET152 must both be electrically isolated from the IC substrate (i.e., ground).

Another situation where isolation is required is shown in the Buck converter 170 of fig. 4B, where a push-pull CMOS pair, comprising a low-side MOSFET171 and a high-side MOSFET172, controls the current in the inductor 177 and regulates a steady voltage across the output capacitor 178 in closed-circuit operation. Diode 173, which is anti-parallel to high-side MOSFET172, remains reverse biased during normal operation, whereas drain-to-body diode 174 of low-side MOSFET171 does not remain reverse biased. Inductor 177 drives converter output voltage Vx below ground forward-biased diode 174 each time high-side MOSFET172 is turned off. If the conduction current in the body of the MOSFET is sufficient to exhibit a voltage drop across the resistor 175, electrons can be injected deep into the substrate via the action of the parasitic NPN176 bipolar transistor and can be collected by any other N region 179. The resulting substrate current can adversely affect efficiency and cause circuit failure. If the low side MOSFET175 is isolated, the diode current can be collected without becoming an undesirable substrate current.

The most common form of complete electrical isolation is junction isolation. Although not ideal for dielectric isolation where oxide surrounds each device or circuit, junction isolation has heretofore given the best compromise between manufacturing cost and isolation performance. As shown in fig. 5A, prior art CMOS isolation requirements include a deep P-type isolation P grown atop P-type substrate 201 and electrically connected to the P-type substrate_ISO204 to completely isolate the N-type epitaxial island by the underlying and all sides of the P-type material. The growth of epitaxial layer 203 is also slow and time consuming, representing the most expensive step in semiconductor wafer fabrication. Isolation diffusion is also expensive, and is formed over an extended period (up to 18 hours) using high temperature diffusion. In order to be able to suppress parasitic devices, the heavily doped N-buried layer NBL202 also needs to be masked and selectively introduced before epitaxial growth.

To minimize the upward diffusion during the isolation diffusion and epitaxial growth, a slow diffuser such As arsenic (As) or antimony (Sb) is selected to form NBL 202. But prior to epitaxial growth, the NBL layer must be diffused deep enough to reduce its surface concentration or otherwise the concentration control of the epitaxial growth will be adversely affected. Since the NBL layer is composed of a slow diffuser, the pre-epitaxial diffusion process can take more than 10 hours.

Once isolation is complete, CMOS fabrication may begin in a manner similar to that discussed previously. Referring again to fig. 5A, P-well 205 and N-well 206 are implanted and diffused to facilitate N-channel and P-channel fabrication. But they are advantageously completely isolated from the substrate since they are formed in the isolated epitaxial pocket of N-type silicon.

Since junction isolation fabrication methods rely on high temperature processes for forming deep diffused junctions and growing epitaxial layers, these high temperature processes are expensive and difficult to fabricate, and are incompatible with large diameter wafer fabrication, exhibit significant variation in device electrical performance and avoid high transistor integration densities. The complexity of junction isolation is illustrated in the flow chart 220 of fig. 5B. After all the steps shown have been performed, the wafer must continue with the formation of the field oxide layer, and only then begins with the large scale CMOS fabrication portion where the flow can begin.

Another disadvantage of junction isolation is the area wasted by the isolation structures and otherwise available for the fabrication of active transistors or circuits. In fig. 5C, the area required to meet certain minimum design criteria is shown for buried layer 212, P-type diffusion junction isolation 213, and diffused heavily doped N-type sinker (sinker) 214 (overlying NBL 212B). As a further complicating factor, in the case of junction isolation, the design criteria (and wasted area) depend on the maximum voltage of the device being isolated. For growth to thickness x_epiSupporting the actual thickness x of the voltage_netSmaller, the depth of the up-diffusion due to P + junction 216 and NBL212A must be subtracted from the total thickness to determine the voltage capability of the isolated device.

Typical epitaxial thicknesses range from 4 microns to 12 microns. The opening required for isolation region implantation depends on the epitaxial thickness being isolated. P_ISOThe mask openings must be large enough to avoid the lack of diffusion (starveddiffusion) effect. The lack of diffusion occurs when two-dimensional (or three-dimensional) diffusion reduces the dopant concentration gradient and slows the vertical diffusion rate. Practically unless P_ISOThe opening is enough, the isolation is even possibleThe substrate is not reached. As a general rule of thumb to avoid starved diffusion, the opening of the isolation implant should have a thickness approximately equal to the epitaxial thickness x_epiAnd an invalid dimension y 1.

Neglecting the two-dimensional effect, lateral diffusion occurs at a rate of approximately 80% of the vertical diffusion (per side) during the isolation drive cycle. The actual surface width of diffused partition y2 is approximately equal to x_epi+2·(0.8·x_epi)]=2.6·x_epi. Using this criterion, an 18 micron wide isolation ring is required to isolate the 7 micron epitaxial layer. It is desirable to include a further spacing y6 in order to avoid avalanche breakdown between the bottom of isolation 213 and NBL 212A.

Similar design criteria must be considered for fabricating the low resistance sinker 214 connecting the NBL layer 212B to the surface. N is a radical of_sinkerThe mask opening must have a depth x substantially equal to it_netDimension y 3. This results in a sinker surface width y4 equal to [ x ]_net+2·(0.8·x_net)]=2.6·x_net. Suppose x_net=5 microns (for an epitaxial layer of 7 microns), the sinker ring has a width of 13 microns. Allowing a spacing y5 of 2 microns between isolation and sinker rings means that the surface area required for the sinker and adjacent isolation is [ y ]₂+y₅+y₄]=[18+2＋13]Or 33 microns. Obviously, conventional epitaxial junction isolation, despite its electrical benefits, is too area-wasteful to be a viable technology option for mixed-signal and power integrated circuits.

BCD process without epitaxial full isolation using contour implantation (Contouring Implants)

As shown in the multi-voltage CMOS250 of FIG. 6, the principles of the previously disclosed Modular BCD process rely on high energy (MeV) ion implantation through a contoured (budgeted) oxide to produce a self-forming isolation structure with substantially no need for high temperature processes.

In the illustrated structure, deep N-type layers (DN) 253A and 253B, implanted through LOCOS field oxide layer 255, form a conformal isolation structure surrounding the multi-voltage CMOS. For example, DN layer 253A contains a 5V CMOS well comprising a surface P-well 255 (PW 1) with a higher concentration of buried P-wells 254 (PW 1B), and a surface N-well 253 (NW 1) with a higher concentration of buried N-wells 252 (NW 1B), with doping profiles optimized for 5V N channel and P-channel MOSFETs. In another region of the same chip, DN layer 253B contains a 12V CMOS well comprising a surface P-well 259 (PW 2) with a higher concentration of buried P-well 258 (PW 2B), and a surface N-well 257 (NW 2) with a higher concentration of buried N-well 256 (NW 2B), with doping profiles optimized for 12V N channel and P-channel MOSFETs. The same process can integrate bipolar transistors, and various power devices, all tuned using conformal and chained ion implantations of different doses and energies. (Note: As used herein, the term "conformal" means that a region or layer of dopant (a) is formed by implantation of a layer (often an oxide layer) at the surface of the semiconductor material, and (b) has a vertical thickness and/or depth in the semiconductor material that varies depending on the thickness and/or other characteristics of the surface layer, including any openings formed in the surface layer.)

Although this "epi-free" low thermal budget technique has many advantages over non-isolation and epitaxial junction isolation processes, its reliance on LOCOS places certain limitations on its scaling to smaller dimensions and higher transistor densities. The principle of conformal ion implantation in a LOCOS-based modular BCD process is that by the concept of implantation through a thicker oxide layer, the dopant atoms will be closer to the silicon surface, and by implantation through a thinner oxide layer, the implanted atoms will be located deeper in the silicon, away from the surface.

The scaling problem for conformal implantation is shown in fig. 7. In the case of LOCOS282 as shown in fig. 7A, the natural slope of the beak region produces a smooth continuous gradient of oxide thickness, i.e., mirrored (mirrored) by the smooth continuous gradient 285 in the depth of the implanted DN layer. The bottom isolation regions 284 set the one-dimensional device characteristics, but the isolation sidewalls are self-formed, sloping toward the surface to the right of the line as the oxide thickness 286 increases. No implant is introduced through the photoresist mask layer 283.

However, to improve CMOS transistor integration density, the bird's beak taper must be reduced to a more vertical structure so that devices can be placed closer together for higher cluster density. For example, in FIG. 7B, the beak region 296 on the right side of line 297 is much steeper. The result is that more of the implant uniformly contacts the bottom of LOCOS292 and the transition 295 between deep portion 294 and field region 298 is more vertical and steeper. As a result, the width of the isolation of the sidewall portion 295 is narrowed and isolation quality is sacrificed.

To make this point more extreme, fig. 7C shows a near vertical oxide profile of LOCOS302, where the graded portion (graded portion)306 to the right of line 307 is very short. The resulting implant profile shows a very thin abrupt transition 305 between the deep isolation 304 and the surface doping 308. Thus, there is a conflict. More transistors can be clustered into the same region simply by making the oxide steeper, but the region 305 is too narrow to provide good isolation.

What is needed is a new isolation structure that provides complete electrical isolation and high density integration without the use of epitaxial layers or long high temperature processes.

Disclosure of Invention

According to the present invention, various isolation structures overcome the referenced problems. These new isolation structures are formed in a substrate without an epitaxial layer and comprise a deep bottom isolation layer formed by high energy implantation of a dopant of the opposite conductivity type to the substrate. In one set of embodiments, a dielectric-filled trench is used as a sidewall of at least a portion of an isolation structure. The dielectric-filled trench may extend into the deep bottom isolation region. The dielectric-filled trench may extend through and a distance below the deep floor isolation region.

In an alternative embodiment, the dielectric-filled trench extends only part of the distance to the deep-bottom isolation region, and a doped sidewall region of opposite conductivity type to the substrate extends between the bottom of the trench and the deep-bottom isolation region. Advantageously, the doped sidewall regions are formed by implanting dopants through the bottom surface of the trench before the trench is filled with the dielectric.

In another embodiment, a stack of chain-implanted sidewall dopant regions extends from a surface of the substrate to the deep floor isolation region, and a dielectric-filled trench is formed within or adjacent to the sidewall dopant regions.

In most embodiments described above, the trenches may be filled with a conductive material, such as doped polysilicon, and lined with a dielectric layer, such as oxide. This allows electrical contact to be made to the deep bottom isolation regions from the surface of the substrate, either directly via the trenches or via the trenches and doped sidewall regions.

The trench and the doped sidewall region may be in the shape of a ring such that they surround the pocket of the isolated substrate. (Note: As used herein, the term "ring-shaped" refers to a structure that laterally surrounds or surrounds a region of a substrate, regardless of the shape of the structure. in various embodiments, the ring-shaped structure may be, for example, circular, rectangular, polygonal, or some other shape.)

In yet another set of embodiments, a mask layer is formed on a surface of a substrate and an opening is formed in the mask layer. The edges of the mask layer surrounding the opening are sloped. Dopants are implanted through the openings in the mask layer to form a disk shaped isolation region having sidewalls below the sloped edges of the mask layer. The isolation region surrounds the isolated pocket of the substrate.

When isolated pocket regions are formed in accordance with the present invention, shallow dielectric-filled trenches may also be formed within the pocket regions to provide surface isolation between multiple devices in the same pocket region. Furthermore, additional dielectric-filled trenches may extend to a height below the deep-bottom isolation regions, which may be formed between the isolated pockets to provide additional isolation between the pockets. Shallow trenches inside the isolated pockets and trenches between the isolated pockets may also be used with conventional isolation structures, such as structures having chain implanted sidewalls and deep implanted bottom regions.

The invention also includes implanting regions of the same conductivity type as the substrate between the isolated pocket regions to help avoid punch-through between adjacent pocket regions.

The invention also comprises a manufacturing method of the isolation structure. The method is generally modular in the sense that many process steps can be performed at different stages of the overall process sequence without significantly affecting the properties of the resulting isolation structure. Furthermore, the process typically does not involve the growth of epitaxial layers or other processes with significant thermal cycling, meaning that the dopant regions remain in an "as-implanted" configuration with minimal lateral and vertical expansion. This allows increasing the cluster density of the semiconductor devices and preserving valuable real estate (real estate) on the surface of the semiconductor chip. The method also includes techniques that share process steps in the formation of various trenches incorporated into the isolation structure, including deep trenches, shallow trenches, dielectric-filled trenches, and trenches filled with conductive material.

Drawings

Fig. 1A and 1B are prior art non-isolated complementary well CMOS processes with LOCOS field oxidation. Fig. 1A shows the structure after complementary well formation. Figure 1B shows the structure after device fabrication and before metallization and interconnection.

Fig. 1C is a detailed cross-sectional view of a sidewall spacer N-channel MOSFET surrounded by LOCOS field oxide.

Fig. 1D shows the doping profile of the P-well region under the gate of the N-channel MOSFET.

Fig. 2A and 2B are prior art non-isolated complementary well CMOS processes with shallow oxide filled trenches. Figure 2A shows the structure after device formation and before metallization and interconnection. Fig. 2B is a detailed cross-sectional view of a sidewall spacer N-channel MOSFET surrounded by an oxide-filled trench.

Figure 3A shows a prior art process flow for fabricating a prior art trench and LOCOS field oxide complementary well CMOS. Fig. 3B is a schematic representation of a CMOS device. Figure 3C is a schematic representation of a CMOS push-pull driver or inverter. Fig. 3D is a schematic representation of a CMOS cascode clamped push-pull driver.

Fig. 4A and 4B illustrate several circuits that may benefit from electrical isolation. Fig. 4A is a schematic representation of a push-pull driver implemented using a push-pull output circuit N-channel MOSFET. Fig. 4B is a schematic representation of a Buck topology switching regulator.

Fig. 5A is a cross-sectional view of a prior art high temperature junction isolated CMOS including an epitaxial layer prior to metallization and interconnection.

Fig. 5B shows a process flow for the CMOS of fig. 5A.

Fig. 5C illustrates several design criteria related to isolation and sinker diffusion.

Figure 6 is a cross-sectional view of a non-epitaxial low thermal budget, fully isolated CMOS using a LOCOS oxide layer and a profile isolation implant.

Fig. 7A-7C illustrate the limits imposed by the distribution of LOCOS according to the profile isolation implant.

Fig. 8 is a cross-sectional view of a type II trench isolation process with implanted floor and trench bottom isolation enabling fully isolated device integration.

Fig. 9 is a cross-sectional view of a type I trench isolation process with implanted bottom isolation capable of fully isolated device integration.

Figure 10 is a cross-sectional view of a type III process for a device capable of complete isolation using implanted bottom and sidewall isolation and a non-implanted trench region.

Fig. 11A-11C illustrate a fabrication process for a bottom isolation implanted prior to a trench isolation fabrication process.

Figures 12A-12E illustrate a type II trench isolation process with implanted bottom and trench bottom isolation.

Figures 13A-13D illustrate a type III trench isolation process with implanted bottom and sidewall isolation.

Fig. 14A and 14B illustrate a type II trench isolation process with implanted deep P-regions.

Fig. 14C and 14D show design criteria for the device shown in fig. 14A and 14B with and without deep P-regions.

Fig. 15A-15F illustrate an alternative type III trench isolation process.

Fig. 16 illustrates various trench isolation processes.

Fig. 17 is a cross-sectional view of a structure produced using a type III trench isolation process, the structure having implanted bottom isolation, implanted sidewall isolation, shallow and deep dielectric trench isolation.

Figure 18 is a cross-sectional view of a structure produced using a type I trench isolation process having implant bottom isolation, dielectric trench sidewall isolation, including shallow and deep dielectric trench isolation.

Fig. 19 is a cross-sectional view of a structure produced using a type VI trench isolation process, the structure having implanted bottom isolation, and conformal implanted sidewall isolation, in combination with shallow and deep dielectric trench isolation.

Fig. 20 is a cross-sectional view of a structure produced using a type IV trench isolation process, the structure having implanted bottom isolation, and conductive/dielectric sidewall isolation, including shallow trench isolation.

Figure 21 is a cross-sectional view of a structure produced using a type V trench isolation process having implanted bottom isolation, conductive/dielectric trench plus implanted sidewall isolation, including deep and shallow trench isolation.

Fig. 22A-22C illustrate a type I trench isolation process including shallow and deep dielectric trench isolation.

Fig. 23A-23C illustrate a type VI trench isolation process that includes a conformal implant isolation layer.

Fig. 24A-24F illustrate another type IV trench isolation process.

Fig. 25A-25E illustrate a type V trench isolation process.

Detailed Description

The low temperature isolation process used to fabricate the device shown in fig. 6 utilizes a high energy implant that is contoured by the LOCOS field oxide layer to achieve sidewall and bottom isolation around each isolated pocket and device. The scaling limitations and maximum transistor density of such techniques are limited by how small the LOCOS field oxide region can be implemented. The practical implementation of the LOCOS process becomes apparent at dimensions much larger than the lithographic limit. Such adverse effects include distorted field oxide shape, excessive oxide thinning, high stress, high surface state charge, poor quality gate dielectric, and others. Furthermore, as discussed with reference to fig. 7, the small LOCOS dimensions result in thinning of the implanted sidewall isolation regions and corresponding degradation of device isolation quality.

To eliminate the LOCOS size limitation in scaling ICs, an alternative is to replace LOCOS with an alternative process manufacturing flow to accommodate shallow or medium depth trench isolation regions (referred to as "STI"). These dielectric filled trenches can then be combined with high energy and chain ion implantation to form bottom isolation and potentially improve voltage capability for sidewall isolation.

The combination of new sidewall isolated STI and high energy implanted bottom isolation is expressed in various forms, a new method and apparatus for integrating and isolating devices at high density without the need for long high temperature diffusion or expensive epitaxial deposition. The isolation structures produced in this manner can be divided into six categories or "types", defined herein as follows:

● type I isolation: the combination of deep high energy ion implantation bottom isolation and dielectric filled trench sidewall isolation has the option that deep and/or shallow trench isolation is not associated with sidewall isolation.

● type II isolation: the combination of the deep high energy ion implant bottom isolation and the dielectric filled trench sidewall isolation has an additional isolation implant connecting the bottom of the trench to the bottom isolation.

● type III isolation: the combination of deep high energy ion implanted bottom isolation and chain implanted junction sidewall isolation has the option that deep and/or shallow trench isolation is not associated with sidewall isolation.

● type IV isolation: the combination of deep high energy ion implantation bottom isolation and conductive/dielectric filled trench sidewall isolation has the option that deep and/or shallow trench isolation is not associated with sidewall isolation.

● type V isolation: the combination of the deep high energy ion implant bottom isolation and the conductive/dielectric filled trench sidewall isolation has an additional isolation implant connecting the bottom of the trench to the bottom isolation.

● type V isolation: the combination of deep high energy ion implantation bottom isolation and conductive/dielectric filled trench sidewall isolation, with the additional isolation implant connecting the bottom of the trench to the bottom isolation, has the option that deep and/or shallow trench isolation is not associated with sidewall isolation.

● type VI isolation: the combination of deep high energy ion implanted bottom isolation and conformal implanted junction sidewall isolation has the option that deep and/or shallow trench isolation is not associated with sidewall isolation.

Type II epitaxy-free isolation

The type II non-epitaxial isolated device structure 350 shown in cross-section in fig. 8 includes deep N-shaped (DN) bottom isolation regions 352A and 352B formed in a P-shaped substrate 351, the deep N-shaped (DN) bottom isolation regions 352A and 352B having dielectric filled trenches 355A-355F and N-type doped sidewall isolation regions 354A-354F formed at the bottoms of the dielectric filled trenches. An optional deep P-type region (DP) 353 is formed in P-type substrate 351 at a depth shallower than, deeper than, or equal to DN regions 352A and 352B. The result is the formation of electrically isolated P-type pocket regions P1-P4, also designated as regions 356A, 356B, 356D, and 356E, pocket regions P1-P4 being electrically isolated from P-type substrate 351 by a combination of junction isolation at the bottom of the pocket regions and dielectric-filled trenches along the sidewalls of the pocket regions.

In a preferred embodiment of the present invention, deep N-regions 352A and 352B are formed by high energy implantation of phosphorus without any significant high temperature process after implantation. Here, we refer to such deep N-type regions by the term "DN", an acronym for deep N-type regions. Since P-type substrate 351 does not have an epitaxial layer grown on top of it, DN layers 352A and 352B differ from buried layers formed using high temperature processes in conventional epitaxial processes (e.g., region 202 in prior art device 200 shown in fig. 5A), although they are similar in appearance.

The peak concentration and the total vertical width of conventional buried layers are affected by significant diffusion that inevitably occurs in high temperature fabrication before, during and after epitaxial growth. The problem of diffusion and variations in the epitaxial process due to slight variations in temperature can cause large deviations in the doping profile as a result of the temperature-index dependent diffusivity.

In contrast, in all of the low temperature processes disclosed herein, implanted DN regions 352A and 352B are affected only by the implant energy (or energy in the case of multiple implants). The resulting distribution is "as-implanted" and is not subject to the changes associated with thermal processing. In a relative sense, the DN region formation should generally include the implantation of the highest energy in the process, at 1MeV (one million electron volts) to a range above 3 MeV. Specifically, energies of 1.5MeV to 2.3MeV allow deep implants to be achieved in a reasonable time using mono-and di-ionized dopants. A tri-ionized dopant species with a high state of charge may be implanted to a greater depth, but at a correspondingly lower beam current. The result is a slower implant. The phosphorus implant dose for the DN region can be from 1E12cm^-2To 1E14cm^-2But typically includes 1-5E 13cm-²The dosage of the range.

The deep P-type region 353, having the acronym "DP," may be formed at any depth in the preferred embodiment using a high energy implant of boron, but is typically formed at a depth equal to or shallower than the DA regions 352A and 352B. Implanting boron to any given depth requires a lower energy than phosphorus, e.g., from 0.8MeV to 1.5MeV, since boron is a smaller, lower mass atom than phosphorus. The boron implant dose for DP region 353 may also be from 1E12cm^-2To 1E14cm^-2But may typically include 5E12cm^-2To 1E13cm^-2Dose of range, slightly less than DN implant of phosphorous.

The formation of N-type isolation (NI) regions 354A-354F is also accomplished using implanting medium to high energy ions into the bottom of trenches 355A-355F, before the trenches are filled with any dielectric material. NI regions 354A-354F overlap DN regions 352A and 352B, completing isolation in the regions below the trenches and above DN regions 352A and 352B, allowing shallower trenches to be used for sidewall isolation. Shallower trenches are easier to fabricate, i.e., etch and fill.

In device structure 350, 4 pocket regions P1, P2, P3, and P4 (i.e., 356A, 356B, 356D, and 356E, respectively) are formed using 2 DN floor isolation regions 352A and 352B. Although the DN regions may be electrically floating, typically they are biased to a more positive potential than the substrate and thus form a permanent reverse-biased PN junction around them. The reverse bias present on each DN region may be the same or different and may be a fixed potential or vary over time. E.g., pocket regions P1 and P2, are isolated from the substrate by a common bottom isolation 352A and trenches 355A and 355C; and are isolated from each other by trench 355B, pocket regions P1 and P2 may contain 5V circuits. The adjacent pocket regions P3 and P4, which are isolated from the substrate by the common bottom isolation 352B and the trenches 355D and 355F, and which are isolated from each other by the trench 355E, may contain 12V circuits, which operate without regard to the 5V circuits sharing the same P-type substrate 351.

In the isolation regions, each isolated P-type pocket may contain devices biased at any potential equal to or more negative than the DN bias potential corresponding to the pocket. For example, if DN region 352A is biased to 5V, the devices inside isolated pocket regions P1 and P2 may operate at up to 5V, and the junction breakdown of the isolated devices may allow a negative potential, potentially even more negative than the potential of P-type substrate 351 itself. The isolated pocket region may similarly include additional P-type or N-type doped regions introduced before and after isolation formation. Each pocket may also include one or more shallow isolation trenches, such as shallow isolation trench 357, shown in pocket 1, to provide surface isolation between devices in the same pocket. The shallow trenches 357 may be formed by a second trench etch and backfill, or preferably may share the same etch and backfill steps as the trenches 355A-355F, employing an additional mask during the implantation of the NI regions 354A-354F, so as to avoid the NI regions 354A-354F from being implanted underneath the shallow trenches 357.

Type I non-epitaxial isolation

The type I device structure shown in fig. 9 without epitaxial isolation includes DN floor isolation regions 372A and 372B formed in a P-type substrate 371 with dielectric-filled trenches 375A-375F overlapping the floor isolation regions 372. An optional DP region 373 is formed in P-type substrate 371 at a depth that may be shallower, deeper, or equal to DN regions 372A and 372B. The P-type pocket regions P1 through P4, i.e., regions 376A, 376B, 376D and 376E, are electrically isolated from the P-type substrate 371 by the combination of dielectric-filled trenches 375A-375F surrounding the regions 376A, 376B, 376D and 376E and overlapping the underlying isolation regions 372A and 372B. The P-type surface region 376C located between trenches 375C and 375D is not isolated because there is no DN layer in this region and is thus electrically shorted to substrate 371.

In a preferred embodiment of the present invention, DN regions 372A and 372B are formed by high energy implantation of phosphorus without any significant high temperature process after implantation. Similarly, DP region 373 may be formed using a high energy implant of boron.

Unlike type II isolation, type I isolation does not have N-type dopants implanted into the bottom of the trench. By eliminating the N-type material at the bottom of the trench, wafer fabrication requires fewer steps and this can reduce fabrication costs. Furthermore, without NI injection, the electrical interaction between the isolated device and the electrical operation of the NI layer can be neglected. In type I isolation, the trench must be etched deep enough to overlap directly over the DN floor isolation region for sidewall isolation. As a result, the trench depth required for type I isolation using any given DN region depth is deeper than that required for type II isolation. Deeper trenches, however, can be more difficult to fabricate, especially for etching, filling, and planarization. In addition, etching deeper trenches may require a wider trench width in order to allow the etchant and byproduct gases to flow uniformly during the etching process. Wider trenches, if desired, will result in lower device cluster density than narrower, shallower trenches.

One way to avoid the tradeoff of trench width and depth is to utilize trenches with two different depths that are separately masked and etched, as shown in structure 800 of fig. 18. For dense device integration, the trenches 584A and 584B are relatively shallow and narrow. These shallow trenches are preferably the same or similar to existing STI used in a given CMOS technology node and are used to provide surface isolation, i.e., field threshold control, but do not provide complete isolation between devices in a given isolated P-type pocket. The deeper trenches 585A, 585B, 585C, and 585D are at least as deep as the DN floor isolation regions 582A and 582B (or deeper as shown in fig. 18) to provide complete electrical isolation between P-type pockets 586A and 586B and substrate 581. The dual trench process is somewhat more complex than the single trench process of fig. 9, but it may share backfill and planarization steps, as described more fully below.

Type III no-epitaxial isolation

Type III isolation combines a DN region and a chain implanted sidewall isolation region, which may optionally be used in combination with a dielectric filled trench to improve isolation capability. For example, the device structure of fig. 10 shows two isolated P-pocket regions P formed using two high-energy implanted DN floor isolation regions 402A and 402B in combination with chain implanted sidewall isolation regions (NI) 408A, 408B, 408C, and 408D₁And P₂(i.e., 406A and 406B, respectively). These implanted sidewall isolation regions are formed using a series of implants of different energies so as to vary the depth of each particular implant, the deepest of which overlaps the DN floor isolation regions 402A and 402B and the shallowest of which reaches the surface of the P-type substrate 401. Dielectric filled trenches 405A, 405C, 405D, and 405F may optionally be included within or adjacent to the implanted sidewall isolation regions 408A, 408B, 408C, and 408D in order to improve isolation. Optional DP region 403 may be used to suppress punch-through between adjacent DN regions 402A and 402B.

Sequential formation of a series of phosphorus implants results in a continuous N-type sidewall isolation region as shown. For example, NI regions 408A and 408B may have a ring or other closed geometry and overlap onto DN region 402A to create P-type region 406A that is electrically isolated from substrate 401. Similarly, NI regions 408C and 408D may have a ring or other closed geometry and overlap onto DN region 402B to create P-type region 408B that is electrically isolated from substrate 401 and region 406A. In type III isolation, the implant used to form the sidewall isolation is independent of the process of trench formation, such that the trench may be formed inside an NI sidewall isolation region, such as trench 405A, 405C, 408D, or 405F, or may be formed inside an isolated pocket, such as 405B and 405E. Since the trench in type II isolation need not be deep enough to overlap the DN layer, its use in floating pockets 406A and 406B does not subdivide the pockets into mutually isolated regions, i.e., all devices in pocket P1 share the common potential of P-type region 406A. These shallow trenches are preferably the same or similar to existing STI used in a given CMOS technology node and are used to provide surface isolation, i.e., field threshold control, but do not provide complete isolation between devices in a given isolated P-type pocket.

An alternative embodiment of type III isolation is shown in the device structure 560 of fig. 17. Trenches 564A and 564B are equivalent to trenches 405B and 405E in fig. 10. The deep trenches 565A, 565B, and 565C replace the shallow trenches 405A, 405C, 405D, and 405F of fig. 10. Deep trenches 565A, 565B, and 565C are placed between adjacent DN regions 562A and 562B in order to avoid punch-through, instead of DP region 403 of fig. 10. The dual trench process is somewhat more complex than the single trench process of fig. 10, but may share a backfill and planarization process, as described more fully below.

Type IV non-epitaxial isolation

An example of type IV no-epitaxial isolation is shown in device structure 620 of fig. 20. DN floor isolation regions 622A and 622B are formed in the P-type substrate 621. Trenches 625A-625D overlap DN regions 622A and 622B. An optional DP region 623 is formed between adjacent DN regions 622A and 622B. The P-type pockets 626A and 626B are electrically isolated from the substrate 621 by the combination of trenches 625A-625D surrounding pockets 626A and 626B and overlapping on the bottom isolation regions 622A and 622B. The optional trenches 624A and 624B are preferably the same as and similar to existing STI used in a given CMOS technology node. Trenches 624A and 624B are used to provide surface isolation between devices in a given isolated P-type pocket. Trenches 625A-625D are generally wider and deeper than trenches 624A and 624B.

Unlike type I isolation, where the trenches are completely filled with dielectric, type IV isolated trenches 625 include a conductive material 628, such as doped polysilicon, i.e., for providing an electrical connection to DN region 622. The conductive material 628 in each trench 625A-625D is surrounded by a dielectric material 627, such as a deposited oxide, that isolates the conductive material 628 from the P-type pockets 626A and 626B and the substrate 621. In type IV isolation, trenches 625A-625B are etched to a suitable depth to provide good electrical contact between conductive layer 628 and DN 622. Although the conductive/dielectric trench fill of type IV isolation is somewhat more complex than the dielectric-only process of type I isolation, it provides a very dense and low resistance connection to the DN region. In addition, some of the backfill and planarization processes may be shared with the shallow trenches, as described more fully below.

Type V non-epitaxial isolation

An example of type V no-epitaxial isolation is shown in the device structure 640 of fig. 21. DN floor isolation regions 642A and 642B are formed in P-type substrate 641. Trenches 645A to 645D are etched on portions above DN regions 642A and 642B. Unlike type IV isolation, trenches 645A-645D are not deep enough to directly contact DN regions 642A and 642B. Instead, NI regions 643A through 643D are used to connect trenches 645A-645D to DN regions 642A and 642B. Thus, isolated P-type pocket regions 646A and 646B are isolated by the combination of the underlying DN floor isolation regions 642A and 642B and the on-side trenches 645A-645D and NI regions 643A-643D.

Type V isolated trenches 645A-645D include conductive material 648, e.g., doped polysilicon, for providing electrical connection to DN regions 642A and 642B. The conductive material 648 in each trench 645A-645D is surrounded by a dielectric material 647, such as a deposited oxide, that isolates the conductive material 648 from the P-type pocket regions 646A and 646B and the substrate 641. Conductive material 648 forms an electrical contact through NI regions 643A-643D to DN regions 642A and 642B. The NI regions 643A-643D are preferably formed by implanting ions into the bottom of the trenches 645A-645D before the trench backfill is complete, such that the NI regions 643A-643D are self-aligned to the trenches 645A-645D. The trenches 645A-645D are shallower than used in type IV isolation and may preferably be formed by the same etching step used for the optional shallow trenches 644A and 644B. An optional deep trench 649 may be formed between adjacent DN regions 642A and 642B. The trench 649 may share some backfill and planarization steps with the shallow trenches 644A, 644B, and 645A-645D, as described more fully below.

Type VI epitaxy-free isolation

An example of type VI no epitaxial isolation is shown in the device structure 600 of fig. 19. DN floor isolation regions 602A and 602B are formed in P-type substrate 601. The DN region includes sidewall portions 603A-603D, which sidewall portions 603A-603D are formed by high energy DN regions 602A and 602B implanted through a suitable mask to bring the implant range up to the substrate surface at a suitable distance. This may be accomplished, for example, by forming a mask layer over the substrate with relatively shallow sidewalls, e.g., 45-75 degrees. This is similar to the prior art isolation technique shown in fig. 6, which uses a LOCOS field oxide layer as a masking layer, but in the present invention the masking layer does not remain on the wafer, but is removed. The sacrificial mask layer may be an etched oxide, photoresist, or other material. After implantation of DN regions 602A and 602B through the sacrificial mask layer, P-type pocket regions 606A and 606B are completely isolated by DN regions 602A and 602B and sidewall portions 603A-603D. Sidewall portions 603A-603D also provide electrical contact to DN areas 602A and 602B. Optional shallow trenches 604A and 604B may be formed within P-type pocket regions 606A and 606B to provide surface isolation between devices therein, and optional deep trenches 605A-605C may be formed between adjacent DN regions 602A and 602B to mitigate punch-through.

Isolation manufacturing and process sequence

In principle, because there is no high temperature required to achieve electrical isolation using the techniques of the present disclosure, the formation of the NI sidewall isolation region, the dielectric-filled trench, and the DN floor isolation region may be formed in any order without adversely affecting the electrical isolation of the integrated device. In practice, however, some manufacturing sequence is preferred as it simplifies wafer processing. It is easier to implant the bottom of the etched trench, for example, before filling the trench, because only a low energy implant is needed and the implant can be self-aligned to the trench. The implant after the trench fill process requires high energy to penetrate the same depth.

Fig. 11A-11C illustrate one method of forming the DN floor isolation region using high energy ion implantation without the need for high temperature processing or epitaxy. In fig. 11A, mask layer 412 is formed thick enough to block the high-energy DN implant. The mask material is preferably a photoresist, but may also be an oxide or other suitable material. In FIG. 11B, the crystalThe tile is patterned by removing the mask layer 412 in the areas where the DN region is to be implanted. The pre-implant oxide layer 413 may be thermally grown or deposited before or after the masking step, or the etching of the masking layer 412 may be interrupted before it is completely removed, leaving the oxide layer 413 in the regions to be implanted. In FIG. 11C, the high energy implant is preferably in the range of 1.5MeV to 4.5MeV, preferably 1 to 5E13cm^-3Is used to form DN isolation regions 414 in the P-type substrate 411 below the thin oxide layer 413 but not below the mask layer 412. In a preferred embodiment, no trenches are present in the substrate at this time.

Fig. 12A-12E illustrate the formation of type II isolation structures. As shown in the cross-sectional view of fig. 12A, P-type substrate 421 containing DN region 424 has a mask layer 425 formed and patterned to form an opening 426. Mask 425 is preferably a deposited oxide hard mask,thick ranges, but alternative materials such as photoresist may also be used. An optional second layer 433 can be formed and patterned between the mask layer 425 and the substrate 421. This layer may be, for example, silicon nitride or other suitable material that serves as an etch stop for subsequent planarization.

In fig. 12B, trench 427 is etched into substrate 421 to a depth less than the depth of DN region 424, and preferably to the same depth as used to form STI in a given CMOS technology. Fig. 12C shows the formation of an electrically isolated NI region 428 by implanting the bottom of trench 427, thereby completing floating P-type region 430. A masking layer 425 for the trench etch is preferably used for this implant, advantageously providing self-alignment of the NI region 428 to the trench 427. An optional second mask layer 432 may be deposited and patterned to avoid NI implants formed in trenches 427 that would provide surface isolation between devices within floating P-type region 430. Fig. 12D shows the structure after the mask layer 425 is removed and the trenches 427 are filled with a dielectric material 431, such as a deposited oxide. The structure is planarized by CMP or other technique that results in the planarized structure 420 shown in fig. 12E, which includes filled trenches 429, DN floor isolation regions 424, and NI isolation regions 428 that together isolate floating P-type region 430 from P-type substrate 421.

Fig. 22A-22C illustrate the formation of type I isolation structures. Fig. 22A shows the isolation structure after formation of DN floor isolation regions 662, formation of mask layers 663 and 664, and etching of shallow trenches 665, using the same processes as described above in fig. 12. Fig. 22B shows the structure after deposition and patterning of optional second mask layer 666. In a preferred embodiment, mask layer 664 is nitride or other layer suitable for etch stop during planarization, mask layer 663 is a hard mask material such as deposited oxide, and mask layer 666 is photoresist or similar material. A deeper trench 667 is etched through an opening in mask layer 666. After removing mask layers 663, 664, and 666, the deep trenches 667 and the optional shallow trenches 665 are simultaneously backfilled by dielectric deposition. The structure is then planarized by CMP or other techniques, resulting in the planarized structure shown in fig. 22C, which includes dielectric-filled deep trench 669 and DN floor isolation 662 regions, which together isolate floating P-type region 670 from P-type substrate 661. Optional dielectric-filled shallow trenches 668 provide surface isolation between devices formed in P-type region 670.

The fabrication of type III isolation is shown in fig. 13A-13D. Fig. 13A shows isolation structure 450 after the formation of DN region 452, DN region 452 being implanted at high energy through first masking layer 453, first masking layer 453 preferably being a deposited and etched hard mask material such as an oxide. A second mask layer 455, preferably a photoresist, is then deposited and patterned. Chain implantation of phosphorus is then used to form sidewall junction isolation regions 456 that extend from the surface and overlap onto the DN floor isolation regions 452. With type III isolation, the floating pocket region 451B is completely surrounded on all sides by N-type junction isolation, isolating it from the surrounding P-type substrate 451A.

In the preferred embodiment, a mask layer 453, which is used to define the lateral extent of DN region 452, is also used to define the outer edges of sidewall isolation region 456, thus providing self-alignment between regions 452 and 456. To accomplish this, a mask layer 455 is defined atop the mask layer 453 (but not overlapping the edges of the mask layer 453) and also atop the exposed surface of the substrate 451A, which may be covered with a thin oxide 454. The phosphorus chain implant may not penetrate the mask layer 455 or the mask layer 453. The pre-implant oxide 454 may be a remnant of a previous process step or may be grown prior to implanting the sidewall isolation regions 456. Using a process sequence such as that shown in fig. 11A-11C, oxide layer 453 defines the outer edges of both DN floor isolation region 452 and sidewall isolation region 456.

In subsequent processes shown in fig. 13B, surface oxide layers 453 and 454 and mask layer 455 are removed and a new mask layer 457 is defined using a low temperature technique to avoid diffusion of DN region 452. Windows 458A and 458C are defined in the mask layer 457 on top of or adjacent to the sidewall isolation regions 456. Optional window 458B may also be formed that does not overlap isolation region 456.

In fig. 13C, trenches 460A, 460B, and 460C are etched through windows in mask layer 457. After mask layer 457 is removed, trenches 460A, 460B, and 460C are filled with a dielectric material and planarized. The resulting isolation structure 450 is shown in fig. 13D. Regions 456 and 452 provide isolation of P-type region 451B from substrate 451A. Filled layers 461A and 461C within sidewall isolation regions 456 or adjacent to side isolation regions 456 are optional but improve the isolation capability of the structure by completely eliminating the conduction of majority carriers or minority carriers near the surface. Filled trench 461B provides surface isolation between devices within region 451B. By combining these process steps with the deep trench steps described above in fig. 22, the structure of fig. 17 can be produced that provides deep trench isolation between adjacent DN regions 562A and 562B. Since the deep and shallow trenches can share the same dielectric backfill and planarization steps, the added process complexity is minimal.

Fig. 23 illustrates the formation of a type VI isolation structure that includes a conformally implanted DN region. FIG. 23A illustrates forming a combOne method of forming DN region 682. The mask layer 683 is deposited and patterned using a hard mask layer, such as oxide, or a soft mask layer, such as photoresist. The opening in the mask layer 683 is formed with an intentionally sloped sidewall 686. Several possible techniques for this process step are described below. Total thickness t of mask layer 683₁Enough to avoid injection of the DN layer completely. The sidewall 686 has a continuously decreasing thickness so that the DN implant penetrates into the substrate 681 at a continuously varying depth to conform to the thickness profile of the sidewall 686. When the thickness of the side wall is t₂At this time, the DN implant is only transmitted through the sidewalls so that it is localized to the surface substrate. The depth of the DN implant reaches its maximum at the end of the sidewall where the implant is directly into the substrate. The conformal DN regions 682A, 682B completely isolate the P-type pocket region 690 from the P-type substrate 681.

Fig. 23B illustrates another method of forming the conformal region 702. The mask layer 703 is deposited and patterned using a hard mask layer, such as an oxide. A second mask layer 704, such as a photoresist, is defined over portions of mask layer 703. The opening in the mask layer 703 is formed with an intentionally sloped sidewall 706. The combined thickness of mask layers 703 and 704 is sufficient to completely avoid N-type dopants used to form DN region 702 from penetrating through mask layers 703 and 704 to substrate 701. However, the total thickness t of the mask layer 703₃Is designed to allow N-type dopants to penetrate just below the surface of substrate 701 so that a surface portion 702C of DN region 702 is formed, where the full thickness of mask layer 703 is exposed. In the region under sidewall 706, mask layer 703 has a tapered thickness such that the N-type dopants used to form DN region 702 penetrate into substrate 701 at a continuously varying depth, conforming to the profile of sidewall 706 to form sloped portion 702B of DN region 702. In the opening of mask layer 703 between sidewalls 706, the N-type dopant used to form DN region 702 penetrates into substrate 701, forming bottom 702A of DN region 702. The conformal DN region 702 completely isolates the P-type pocket 710 from the P-type substrate 701.

Fig. 23C shows the type VI isolation structure of fig. 23A after removal of the mask layer. The conformal DN region 682 is dished and forms both bottom and sidewall isolations such that the isolated P-type region 690 is completely isolated from the P-substrate 681 junction. Subsequent processes may include the formation of shallow trenches to provide surface isolation within each P-type pocket, and/or deep trenches between adjacent DN regions to avoid punch-through. These process steps may be, for example, the same as described in fig. 22C. An example of the resulting type VI isolation structure is shown in fig. 19. In its simplest form (i.e., fig. 23C), type VI isolation requires only one masking step and a single implant in order to form a complete junction isolation without epitaxy or high temperature diffusion. However, it requires the development of a masking process that provides a controlled sidewall angle to facilitate conformal implantation.

One method of forming a mask layer with a controlled sidewall angle includes deposition of an oxide layer, masking with a photoresist, and etching the oxide layer with one or more etch processes that etch the oxide layer laterally as well as vertically. For example, a single Reactive Ion Etch (RIE) process may be optimized to provide such controlled sidewall angles. The RIE process may include a sequence of sub-processes with various lateral and vertical etch rates. Alternatively, a sequence of wet etch steps and RIE steps may be employed to etch the oxide. Instead of oxide, a metal layer or a polysilicon layer may be used as a mask layer, or a stack of different materials and a different etching process may be employed. In addition, a thick photoresist mask may be formed using a sequence of development and baking processes in order to produce a controlled sidewall angle.

Fig. 24A-24F illustrate the formation of a type IV isolation structure that includes an implanted DN region contacted by a conductive trench backfill region. Fig. 24A shows the structure after the formation of DN region 742 as described above, and the deposition and patterning of an optional planarization stop layer 744 of silicon nitride or other suitable material, and the formation of a mask layer 743, preferably a hard mask of deposited oxide or other suitable material. Shallow trenches 745 are etched into the P substrate 741 through openings in mask 743. The trench 745 is preferably compatible with standard STI for a given CMOS technology.

Fig. 24B shows the structure after patterning and etching trenches 746. These trenches are deeper than trench 745 and extend into DN region 742. The trench 746 is also wider than the trench 745 to allow for the formation of dielectric backfill in the trench 745 and the backfill of conductive/dielectric in the trench 746 as described below. For example, trench 745 may be approximately 0.5 microns wide and 0.5 microns deep, while trench 746 may be approximately 1 micron wide and 1.5 microns deep.

Fig. 24C shows the structure after deposition of a dielectric layer 747. Dielectric layer 747 preferably has good conformality, for example, an oxide can be deposited using TEOS. The deposition thickness is designed so as to completely backfill the narrow trenches 745, but only cover the sidewalls of the wide trenches 746. In the example given here, a thickness of 0.3 microns can be used to completely backfill the 0.5 μm wide shallow trenches 745 and form a 0.3 micron layer over each deep trench 746, leaving a 0.4 micron wide space in the deep trenches 746.

Figure 24D shows the type IV structure after the dielectric layer 747 has been etched back. Etch back, preferably accomplished by well known reactive ion etching techniques, should completely remove the dielectric 747 from the bottom of the deep trench 746. By doing so, it will also be possible for dielectric 747 to be completely removed from the surface, and underlying mask layer 743 can also be etched, depending on the materials used and their relative etch rates. After this etch-back step, sidewall dielectric layers 748B, 748C, 748D and 748E remain in the deep trenches 746, while the shallow trenches 745, which should extend above the initial surface of the substrate 741, are completely filled with dielectric regions 748A.

Fig. 24E shows the structure after deposition of conductive layer 749, which is preferably highly conductive and conformal, e.g., in-situ doped polysilicon. The deposition thickness of the layer 749 is designed to provide complete backfill of the deep trenches 746.

Figure 24F shows a type IV isolation structure after planarization. In this example, the structure has been planarized back to the original surface of the substrate 741. This is preferably done by a CMP and/or etch back process. The final structure includes P-type regions 751 separated by DN742 on the bottom and backfilled trenches 746 on the sides. Trench 746 is filled with conductive materials 750A and 750B, conductive materials 750A and 750B providing electrical contact to DN region 742. Conductive backfill 750 is surrounded by dielectric 748 such that it is isolated from P-type region 751 and substrate 741.

Type IV isolation advantageously provides a very compact electrical connection to the DN layer through deep trenches backfilled with a conductive material. Furthermore, the formation of these trenches shares many steps in common with the formation of standard STI isolation within each isolated P-type region, including dielectric deposition and planarization steps, so there is little additional process complexity to achieve the DN layer contact.

Fig. 25A-25E illustrate the formation of a type V isolation structure that includes an implanted DN region contacted by a conductive trench backfill region via implanted sidewall extensions. Fig. 25A shows the structure after formation of DN region 762, and the deposition and patterning of an optional planarization stop layer 764 of nitride or other suitable material, and the formation of a mask layer 763 that is preferably a hard mask of deposited oxide or other suitable material, as described above. A shallow trench 765 is etched into the P substrate 761 through an opening in the mask 763. The trench 765 is preferably compatible with standard STI for a given CMOS technology. Trench 766 is etched at the same time as trench 765. These trenches are wider than trench 765 to allow dielectric backfill in trench 765 and the formation of a conductive/dielectric backfill in trench 766, as described below. For example, trench 765 may be approximately 0.5 microns wide and 0.5 microns deep, while trench 766 may be approximately 1 micron wide and 0.5 microns deep. Type V has the advantage over the type IV isolation described above that only a single trench mask and etch is required to form the STI and sidewall isolation trenches.

Fig. 25B shows the structure after deposition of dielectric layer 767. The dielectric layer preferably has good conformality, for example, TEOS may be used to deposit the oxide. The deposition thickness is designed so as to completely backfill the narrow trench 765, but only cover the sidewalls of the wide trench 766. In the example given here, a thickness of 0.3 microns can be used to completely backfill 0.5 μm wide shallow trenches 765 and form a 0.3 micron layer on the sidewalls of each deep trench 766, leaving a 0.4 micron wide space in the deep trenches 766.

Figure 25C shows the type V structure after dielectric layer 767 etch back. The etch back, preferably done by well-known reactive ion etching techniques, should completely remove the dielectric layer 767 from the bottom of the wide trench 766. By doing so, dielectric layer 767 will likely also be removed from the surface, and underlying mask layer 763 can also be etched, depending on the materials used and their relative etch rates. After this etch-back step, sidewall dielectric layers 768B, 768C, 768D, and 768E remain in deep trench 766, while shallow trench 765 is completely filled by dielectric region 768A, which should extend above the initial surface of substrate 761. The implantation of NI regions 772A and 772B is preferably done in this case so that these implants are self-aligned to trench 766 and extend directly under trench 766 without the need for additional masking steps. One or more implants are performed to provide a continuous region of N-type doping connecting the bottom of trench 766 to DN region 762. Since these implants are performed directly in the trench bottom, the required energy is minimized, which provides the further benefit that high flow (high dose) implants can be used to provide heavily doped NI regions. Since these NI regions are very narrow, heavy doping is promising in avoiding punch-through. In an alternative embodiment, the NI region implant can be performed at a different stage of the process, e.g., before the etch back of dielectric layer 767 (as in fig. 25B), and still maintain its self-alignment.

Fig. 25D shows the structure after deposition of a conductive layer 769, which is preferably highly conductive and conformal, such as in-situ doped polysilicon. The deposition thickness of layer 769 is designed to provide a complete backfill of deep trench 766.

Figure 25E shows a type V isolation structure after planarization. In this example, the structure has been planarized back to the original surface of the substrate 761. This is preferably done by a CMP and/or etch back process. The final structure includes P-type region 771, which is isolated from the combination of NI regions 772A and 772B by DN region 762 on the bottom and backfill trench 766 on the sides. Trench 766 is filled with conductive materials 770A and 770B, which conductive materials 770A and 770B provide electrical contact to DN region 762 via conductive NI regions 772A and 772B. Conductive backfill 770A and 770B is surrounded by dielectrics 768B, 768C, 768D, and 768E such that it is isolated from P-type region 771 and substrate 761.

Type V isolation advantageously provides a very compact electrical connection to the DN layer, via deep trenches with conductive backfill. Furthermore, the formation of these trenches shares many of the same steps as the formation of standard STI isolation within the P-type region of each isolation, including trench masking and etching, dielectric deposition, and planarization steps, so there is little additional process complexity to achieve the DN layer contact. A further benefit of this isolation structure is the self-alignment of the NI region to the conductive trench fill, which minimizes the consumed area by eliminating misalignment issues, and also ensures that the conductive layer is isolated from the substrate and the isolated P-type region.

The formation of the deep P-type region DP, similar to many of the process operations described in this disclosure, may be performed before or after any other isolation process. As shown in fig. 14A, the formation of the deep P-type region 483 uses a high-energy ion implantation similar to the formation of the DN region 482. The P-type substrate 481 containing the high-energy implanted DN floor isolation regions 482 is masked with photoresist 488 and implanted with boron at high energy to form DP regions 483.

DP processes may use photoresist to define the implant, or the etched thick oxide, or a combination of both. For example, in fig. 14A, oxide layers 485A, 485B, 485C, and 483 represent the oxide layers remaining in the previous process steps used in forming DN region 482. Photoresist layer 488 is first used as a mask and etched through thick oxide layer 485 to form layers 485B and 485C. The photoresist must remain during implantation in order to avoid unwanted boron penetration through the thin oxide layer 483 over the CN region 482. Alternatively, the oxide layer from the previous process may be removed and regrown prior to masking and implantation of DP region 483. If the regrown oxide layer is thin, e.g., a few hundred angstroms, the photoresist layer may need to be present during implantation. If the regrown oxide layer is thick, e.g., a few microns, the oxide layer may be masked and etched and the optional photoresist layer may be removed prior to implantation.

The resulting deep P-type region may be used to reduce the risk of punch-through breakdown between adjacent isolation regions. For example, type II isolation structure 490 in fig. 14B includes DN regions 492A and 492B formed in P-type substrate 491A. Bottom isolated DN region 492A is overlapped by NI sidewall isolation region 484A and NI sidewall isolation 484A is overlapped by trench sidewall isolation 495A to form floating P-type region 491B. Similarly, bottom isolated DN region 492B is overlapped by NI sidewall isolation 484B and trench sidewall isolation 495B to form floating P-type region 491C. In this example, DN layers 492A and 492B may potentially be biased to different potentials during operation. Their minimum spacing is reduced by the introduction of a DP region 493, which is sandwiched between two DN layers 492A and 492B. To understand this benefit, the effect of punch-through breakdown must be considered.

In the cross-sectional view of FIG. 14C, two DN regions 502A and 502B are separated by a distance Δ x by a P-type substrate 501_DNAnd (4) separating. Assume that both DN layer 502A and P-type substrate 501 are grounded. In the zero-bias case, only a small depletion region 503A develops around the P-N junction formed between DN region 502A and substrate 501. However, DN region 502B is biased to a potential + V, and thus forms a much wider depletion region 503B that extends into the lightly doped substrate side x of the junction, depending on the doping concentration of P-type substrate 501 and the applied voltage V_DDistance. As long as the depletion region does not extend over the entire distance, Δ x_DN>x_DThen no current flows between the two DN regions 502A and 502B. Thus, the two DN regions 502A and 502B may be considered to be isolated from each other. However, if two DN regions 502A and 502B are placed too close to each other, then only Δ x is needed_DN＝x_DPunch-through breakdown will occur and an undesirable current will flow between the two DN regions 502A and 502B. Punch-through breakdown is not actually a breakdown mechanism, but rather represents a barrier lowering phenomenon of the N-I-N junction and exhibits an increase in leakage with "soft breakdown" current-voltage characteristics.

In FIG. 14D, grounded DN region 513A and P-type substrate 511 are separated by a distance Δ x from DN region 513B, which is biased at potential + V_DNAnd (5) separating. Has a ratio ofA heavily doped P-type implant into DP region 515 of substrate 511 at a distance ax from DN layer 513B that is biased_DPFormed between two DN regions 513A and 513B. The voltage extending to the edge of the DP region 515 in the depletion region 514B, i.e., Δ x_DP≈x_DThe depletion region is pinned to a fixed size. Beyond this condition, the electric field continues to increase with increasing potential, concentrating between the DP and DN regions, until avalanche breakdown occurs at some voltage. Since this P-I-P type junction appears in the bulk through avalanche, the electric field at breakdown occurs in the range of 25MV/cm to 35 MV/cm-an avalanche exhibiting a much higher voltage than the onset of punch-through that would occur if DP region 515 were absent.

The DP region thus suppresses punch-through breakdown and allows the adjacent DN floor isolation regions 513A and 513B to be more tightly clustered without suffering high leakage and punch-through. This technique can be applied generally to all isolation structures described herein. Alternatively, deep trenches may be formed between adjacent DN regions in order to allow them to be tightly clustered without suffering from high leakage and punch-through, as shown, for example, in fig. 17 and 18.

Fig. 15A-15F illustrate that the order of the implants in the methods described herein can be rearranged without significantly altering the resulting isolation structure. For example, in fig. 15A, an oxide layer 522 is grown on top of a P-type substrate 521 and is subsequently masked by a photoresist layer 523 and etched to form an opening 524, as shown in fig. 15B. A phosphorus chain implant comprising an implant sequence of varying dose and energy is then implanted through the opening 524 to form NI sidewall isolation regions 525, as shown in fig. 15C.

In fig. 15D, oxide layer 522 is masked by photoresist layer 526 and its center portion is removed, allowing a high energy implant to penetrate deep into substrate 521 to form DN floor isolation regions 527, DN floor isolation regions 527 self-aligned to and overlapped by NI sidewall isolation regions 525, thereby isolating P-type regions 528 from substrate 521. As shown in fig. 15E, substrate 521 is then covered with oxide layer 529, which is patterned to form openings 530A, 530B, and 530C. The substrate 521 is etched to form trenches 531A-531C. The trenches 531A-531C are filled with a dielectric material and planarized as shown in fig. 15F. The resulting structure includes dielectric-filled trenches 531A and 531C in NI sidewall isolation region 525 and dielectric-filled trench 531B in isolation region 528. It should be appreciated that other trenches, similar to 531B, may be readily formed in other regions of the substrate 521 during the same process. The resulting structure 520 is nearly identical to the structure shown in fig. 13D, although the order of fabrication is different.

Although the resulting structure shown in fig. 15F illustrates a type III isolation structure, one skilled in the art may change the fabrication sequence of other isolation processes in a similar manner with minimal electrical impact. This flexibility is exemplified by the various process sequences shown in the flow diagram 540 shown in fig. 16. In flow chart 540, the cards shown with cut angles represent optional process steps. The process flow 541 can implement either type I or type II isolation depending on whether the NI implant step is performed or skipped. Process flows 542 and 543 represent two different methods of implementing type III isolation.

It should be understood that not all possible process flows are expressed in flow chart 540. For example, the DP region may be introduced after or before the DN bottom isolation implant and also before or after the NI isolation sidewall chain implant step. In other options, a deep trench step may be included, a second shallow trench may be included, and some trenches may be filled with a combination of conductive and dielectric materials.

While specific embodiments of the present invention have been described, it is to be understood that these embodiments are illustrative only and not restrictive. Numerous additional or alternative embodiments in accordance with the broad principles of the present invention will be apparent to those skilled in the art.

Claims (18)

1. An isolation structure formed in a semiconductor substrate of a first conductivity type, the substrate having a planarized top surface and not including an epitaxial layer, the structure comprising:

a region of a second conductivity type opposite the first conductivity type, the region of the second conductivity type being dished and having a bottom parallel to the planarized top surface of the substrate and a sloped sidewall portion extending downwardly from the planarized top surface of the substrate at an oblique angle and merging with the bottom, the bottom and sidewall portions together forming an isolated pocket region of the substrate; and

a dielectric-filled trench located in the isolated pocket, a bottom of the dielectric-filled trench being located above the bottom of the region of the second conductivity type.

2. The isolation structure of claim 1, further comprising:

a second region of the second conductivity type outside of the isolated pocket, the second region of the second conductivity type comprising a second bottom portion parallel to the planarized top surface of the substrate and a second annular sidewall portion extending downwardly from the planarized top surface of the substrate at an oblique angle and merging with the second bottom portion, the second bottom portion and the second annular sidewall portion together forming a second isolated pocket of the substrate; and

a second dielectric-filled trench extending downward from the planarized top surface of the substrate, the second dielectric-filled trench being located between the region of the second conductivity type and the second region of the second conductivity type.

3. The isolation structure of claim 2, wherein said second dielectric filled trench extends into said substrate to a level below the level of said bottom and said second bottom.

4. The isolation structure of claim 1, further comprising a second dielectric-filled trench extending downward from a top surface of the substrate, the second dielectric-filled trench located outside of an isolation pocket of the substrate and proximate to the first side of the isolation structure.

5. The isolation structure of claim 4, wherein the second dielectric-filled trench extends into the substrate to a level below the level of the bottom.

6. The isolation structure of claim 4, further comprising a third dielectric-filled trench extending downward from the planarized top surface of the substrate, the third dielectric-filled trench located outside of the isolation pocket of the substrate and proximate a second side of the isolation structure opposite the first side of the isolation structure.

7. The isolation structure of claim 6, wherein the third dielectric-filled trench extends into the substrate to a level below the level of the bottom.

8. The isolation structure of claim 1, further comprising a surface portion of the second conductivity type extending radially outward from a sidewall portion of the ramp at the surface of the substrate.

9. The isolation structure of claim 2, further comprising a third dielectric-filled trench located in the second isolated pocket.

10. The isolation structure of claim 9, wherein the third dielectric-filled trench comprises a bottom portion located above the second bottom portion.

11. The isolation structure of claim 2, further comprising a third dielectric filled trench located on an opposite side of the region of the second conductivity type from the second dielectric filled trench.

12. The isolation structure of claim 11, wherein the third dielectric-filled trench extends into the substrate to a level below the level of the second bottom.

13. The isolation structure of claim 11, further comprising a fourth dielectric filled trench located on an opposite side of the second region of the second conductivity type from the second dielectric filled trench.

14. The isolation structure of claim 13, wherein the fourth dielectric-filled trench extends into the substrate to a level below the level of the second bottom.

15. The isolation structure of claim 1, further comprising

A second region of the second conductivity type outside of the isolated pocket region, the second region of the second conductivity type comprising a second bottom portion parallel to the planarized top surface of the substrate and a second annular sidewall portion extending downward from the planarized top surface of the substrate at an oblique angle and merging with the second bottom portion, the second bottom portion and the second annular sidewall portion together forming a second isolated pocket region of the substrate; and

a deep implanted region of the first conductivity type disposed between the region of the second conductivity type and the second region of the second conductivity type.

16. A method of forming the isolation structure of claim 1, the method comprising

Depositing a mask layer on the planarized top surface of the substrate;

forming an opening in the mask layer, the opening having sloped sidewalls;

implanting dopants of the second conductivity type into the substrate through the opening in the mask layer and the sidewall of the slope in the mask layer to form a region of the second conductivity type; and

forming the dielectric-filled trench in the isolated pocket region.

17. The method of claim 16, wherein the mask layer is formed with sidewalls of a ramp inclined at an angle between 45 degrees and 75 degrees.

18. The method of claim 16, wherein the mask layer is a first mask layer, and the method further comprises depositing a second mask layer on regions of the first mask layer where the first mask layer is radially displaced from sidewalls of the ramp.