HK1186890B - Circuit configuration and method for time of flight sensor - Google Patents

Abstract

The subject application relates to circuit configuration and method for time of flight sensor. An apparatus includes a photodiode, a first and second storage transistor, a first and second transfer transistor, and a first and second output transistor. The first transfer transistor selectively transfers a first portion of the image charge from the photodiode to the first storage transistor for storing over multiple accumulation periods. The first output transistor selectively transfers a first sum of the first portion of the image charge to a readout node. The second transfer transistor selectively transfers a second portion of the image charge from the photodiode to the second storage transistor for storing over the multiple accumulation periods. The second output transistor selectively transfers a second sum of the second portion of the image charge to the readout node.

Description

Circuit arrangement and method for a time-of-flight sensor

Technical Field

The present invention relates generally to sensors and particularly, but not exclusively, to image sensors capable of three-dimensional imaging.

Background

As the popularity of three-dimensional (3D) applications continues to grow in applications such as imaging, movies, games, computers, user interfaces, etc., interest in image sensors capable of 3D imaging is increasing. A typical passive way of creating 3D images is to use multiple cameras to capture stereo or multiple images. Using stereo images, objects in the images can be triangulated to create a 3D image. One drawback of this triangulation technique is that it is difficult to create 3D images using small devices because there must be a minimum separation distance between each camera (ideally, close to the human eye separation) in order to create a three-dimensional image. In addition, this technique is complex and therefore requires considerable computer processing power in order to create the 3D image in real time.

For applications requiring real-time acquisition of 3D images, active depth imaging systems based on optical time-of-flight measurements are sometimes utilized. These time-of-flight systems typically use: a light source that directs light toward an object; a sensor that detects light reflected from an object; and a processing unit that calculates a distance to the object based on round trip times taken for the light to travel to and return from the object. In a typical time-of-flight sensor, a photodiode is typically used because the transfer efficiency from the light detection region to the sensing node is high. Some known time-of-flight sensors require a large pixel size to collect an acceptable signal level from light reflected off an object, which is typically low intensity and short duration light. Some known time-of-flight sensors accumulate and store charge by multiple accumulations of light from a light source to obtain a higher signal level. However, leakage current may draw stored charge during multiple accumulations of light, leaving a poor signal-to-noise ratio.

Disclosure of Invention

In one aspect, the present application relates to an apparatus comprising: a photodiode configured to accumulate image charge over an accumulation period in response to each pulse of non-visible light emitted from a light source, the pulse of non-visible light becoming incident on the photodiode; a first storage transistor configured to store a first sum of a first portion of the image charge over a plurality of accumulation periods, wherein the accumulation periods are among the plurality of accumulation periods; a first transfer transistor coupled between the photodiode and the first storage transistor to selectively transfer the first portion of the image charge from the photodiode to the first storage transistor for storage over the plurality of accumulation periods; a first output transistor coupled to the first storage transistor to selectively transfer the first sum of the first portion of the image charge to a readout node; a second storage transistor configured to store a second sum of a second portion of the image charge over the plurality of accumulation periods; a second transfer transistor coupled between the photodiode and the second storage transistor to selectively transfer the second portion of the image charge from the photodiode to the second storage transistor for storage over the plurality of accumulation periods; and a second output transistor coupled to the second storage transistor to selectively transfer the second sum of the second portion of the image charge to the readout node.

In another aspect, the present application relates to a time-of-flight ("TOF") imaging system comprising: a light source coupled to emit light pulses in response to a first modulation signal; and an imaging pixel array having the imaging pixels arranged in rows and columns, wherein each imaging pixel includes: a photodiode to accumulate image charge; a first storage transistor to store a first portion of the image charge; a first transfer transistor coupled between the photodiode and the first storage transistor to selectively transfer the first portion of the image charge from the photodiode to the first storage transistor in response to the first modulation signal; a first output transistor coupled to the first storage transistor to selectively transfer the first portion of the image charge to a readout node; a second storage transistor to store a second portion of the image charge; a second transfer transistor coupled between the photodiode and the second storage transistor to selectively transfer the second portion of the image charge from the photodiode to the second storage transistor; and a second output transistor coupled to the second storage transistor to selectively transfer the second portion of the image charge to the readout node.

In yet another aspect, the present application relates to a method of determining time of flight using pixels, the method comprising: initializing a first storage transistor and a second storage transistor for storing image charges generated in the photodiode during a plurality of accumulation periods; emitting light pulses from a light source, wherein each of the light pulses is emitted from the light source in response to each of first on-time pulse widths of a first modulation signal; activating a first transfer transistor in response to each of the first on-time pulse widths to transfer a temporally first portion of accumulated image charge to the first storage transistor, wherein the accumulated image charge is generated in the photodiode each time one of the light pulses reflects off an object and illuminates the photodiode during one of the plurality of accumulation periods; activating a second transfer transistor in response to each of a second on-time pulse width of a second modulation signal, wherein activating the second transfer transistor transfers a temporally second portion of the accumulated image charge to the second storage transistor; and determining a time of flight of the light pulse using a first sum of each of the temporally first portions of the accumulated image charge transferred to the first storage transistor and a second sum of each of the temporally second portions of the accumulated image charge transferred to the second storage transistor.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

FIG. 1A is a block diagram showing one example of a time-of-flight sensing system according to the teachings of this disclosure.

FIG. 1B is a timing diagram showing an example of receiving a light pulse emitted from a light source relative to a reflected light pulse in an example time-of-flight imaging system, according to teachings of this disclosure.

Figure 2 is a schematic diagram illustrating one example of a time-of-flight pixel circuit according to the teachings of this disclosure.

Figure 3A is a line graph illustrating a negative gate voltage applied to the gate of a storage transistor during operation of a time-of-flight pixel according to the teachings of this disclosure.

Figure 3B is a line graph illustrating hole accumulation under the gate of a storage transistor during operation of a time-of-flight pixel, according to the teachings of this disclosure.

Figure 4A is a timing diagram showing an example of transmitted and reflected light pulses relative to the switching of first and second transistors in an example time-of-flight imaging system, according to the teachings of this disclosure.

Figure 4B is a timing diagram showing another example of transmitted and reflected light pulses relative to the switching of first and second transistors in an example time-of-flight imaging system, according to the teachings of this disclosure.

FIG. 5 is a timing diagram illustrating an example operation of a time-of-flight pixel according to the teachings of this disclosure.

FIG. 6 is a flow diagram illustrating an example process for determining time of flight using pixels according to the teachings of this disclosure.

FIG. 7 is a block diagram showing a portion of an example time-of-flight sensing system including a time-of-flight pixel array with corresponding readout circuitry, control circuitry, and functional logic, according to the teachings of this disclosure.

Detailed Description

Methods and apparatus for acquiring time-of-flight and depth information using a 3D time-of-flight sensor are disclosed. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Throughout this specification, several technical terms are used. These terms take their ordinary meaning in the art from which they come, unless the context of their use or the specific definitions herein will clearly imply otherwise. For example, the term "or" is used in an inclusive sense (e.g., as in "and/or") unless the context clearly dictates otherwise.

As will be shown, examples of time-of-flight sensors having circuit designs that allow for storage of charge with less leakage are disclosed. By allowing charge to be stored with less leakage, charge can be stored for longer periods of time and still achieve an acceptable signal-to-noise ratio. A longer storage time may allow for smaller pixels that may capture time-of-flight image signals over a longer time period, rather than using larger pixels to capture time-of-flight image signals over a shorter time period.

To illustrate, FIG. 1A is a block diagram showing one example of a time-of-flight sensing system 100, according to the teachings of this disclosure. As shown, time-of-flight sensing system 100 includes a light source 103 that emits modulated pulses, illustrated as emitted light 105 in FIG. 1A. As shown, the emitted light 105 is directed at an object 107. In one example, the emitted light 105 includes pulses of light of Infrared (IR) light. It is understood that in other examples, emitted light 105 may have a wavelength other than infrared, such as visible light, near infrared light, and the like, in accordance with the teachings of this disclosure. The emitted light 105 then reflects back from the object 107, which is shown in FIG. 1A as back reflected light 109. As shown, reflected light 109 is directed from object 107 through lens 111 and then focused onto time-of-flight pixel array 113. In one example, the time-of-flight pixel array 113 includes a plurality of time-of-flight pixels arranged in a two-dimensional array. As will be discussed, in one example, the synchronization signal 115 is generated by the control circuit 121 and sent to the light source 103 to synchronize the light pulses of the emitted light 105 with the corresponding modulation signals that control the plurality of pixels in the time-of-flight pixel array 113 in accordance with the teachings of this disclosure. The synchronization signal 115 may be a clock signal that directs the light source 103 to emit one or more light pulses for a predetermined duration known to the light source 103. In one example, the synchronization signal 115 contains the duration of one or more light pulses emitted by the light source 103.

In the example depicted in FIG. 1A, the time-of-flight pixel array 113 is positioned at a focal length f from the lens 111_{Lens and lens assembly}To (3). As shown in the example, the light source 103 and the lens 111 are positioned at a distance L from the object. The lens 111 may be a microlens among a plurality of microlenses disposed on a time-of-flight pixel array 113. The lens 111 may be a fixed field lens, or an assembly containing microlenses and fixed field lenses. It should be understood, of course, that FIG. 1A is not to scale, and that in one example, the focal length f_{Lens and lens assembly}Substantially smaller than the distance L between the lens 111 and the object 107. Thus, it should be appreciated that for purposes of the present invention, the distance L and the distance L + the focal length f are for purposes of time-of-flight measurement in accordance with the teachings of the present invention_{Lens and lens assembly}Are substantially equal.

FIG. 1B is an illustration according to the teachings of the present disclosureA timing diagram of the timing relationship between the receipt of an example light pulse emitted from a light source relative to a back-reflected light pulse in an example time-of-flight imaging system. Specifically, FIG. 1B shows emitted light 105, which represents a modulated light pulse emitted from light source 103 toward object 107. FIG. 1B also shows reflected light 109, which represents reflected light pulses reflected back from object 107 and received by time-of-flight pixel array 113. In one example, the light source 103 emits a light pulse of the emitted light 105 having a duty cycle of less than 10%. In one example, the pulse width T of the light pulse_PW147 have a duration in the range of 20 nanoseconds to 100 nanoseconds. It should of course be understood that other duty cycles and pulse widths of the emitted light 105 may also be utilized in accordance with the teachings of the present disclosure. As shown, the light pulses of the emitted light 105 and the reflected light 109 all have the same pulse width T_PW147。

As shown in the depicted example, due to the amount of time it takes for a light pulse to travel the distance L from the light source 103 to the object 107, and then the additional time it takes for a reflected light pulse to travel the distance L from the object 107 back to the time-of-flight pixel array 113, there is a delay time T between the emission of a light pulse of the emitted light 105 and the receipt of the light pulse of the reflected light 109_TOF117. Time difference T between emitted light 105 and reflected light 109_TOF117 represents the time of flight of the light pulse to and from the light source 103 and the object 107. Once the time of flight T is known_TOF117, the distance L from the light source 103 to the object 107 may be determined using the following relationship in equations (1) and (2) below:

where c is the speed of light, which is approximately equal to 3 × 10⁸m/s, and T_TOFThe amount of time it takes for the light pulse to travel to and return from the object, as shown in fig. 1A.

Figure 2 is a schematic diagram illustrating one example of a time-of-flight pixel circuit according to the teachings of this disclosure. It should be appreciated that time-of-flight pixel circuit 200 may be implemented in one of a plurality of pixels included in the example time-of-flight pixel array 113 illustrated in FIG. 1A. As shown in the example depicted in fig. 2, time-of-flight pixel circuit 200 includes a photodiode 205 that accumulates charge in response to light incident on photodiode 205. In one example, the light incident on the photodiode 205 includes reflected light 109, as discussed above with respect to fig. 1A and 1B. Ambient light 208 may also be incident on the photodiode 205. A filter may be used to control the light reaching the photodiode 205. A calibration process (mentioned below in connection with fig. 4B) may be used to calculate the difference between the image signal from the photodiode 205 generated by the ambient light 208 and the image signal from the photodiode 205 generated by the reflected light 109.

The time-of-flight pixel circuit 200 illustrated in fig. 2 includes a storage transistor 235 (controlled by control signal SG1) coupled between the transfer transistor 225 (controlled by control signal TX 1) and the output transistor 245 (controlled by control signal OG 1). The pass transistor 225 is coupled to the photodiode 205 and the output transistor 245 is coupled to the readout node 240. The illustrated time-of-flight pixel circuit 200 also includes a storage transistor 239 (controlled by a control signal SG2) coupled between the transfer transistor 229 (controlled by a control signal TX 2) and the output transistor 249 (controlled by a control signal OG 2). The transfer transistor 229 is coupled to the photodiode 205 and the output transistor 249 is coupled to the readout node 240. The storage transistors 235 and 239 may have buried channels or surface channels. The illustrated time-of-flight pixel circuit 200 also includes a reset transistor 255, an amplifier transistor 260, and a select transistor 265.

In the illustrated example, the reset transistor 255 is coupled to a voltage source VDD 257. The photodiode 205 may be reset by selectively activating (turning on) the reset transistor 255 while simultaneously activating the transfer transistor 225, the storage transistor 235, and the output transistor 245. In one example, the photodiode 205 can be reset by selectively activating the reset transistor 255 while simultaneously activating the transfer transistor 229, the storage transistor 239, and the output transistor 249. The transistors of time-of-flight pixel circuit 200 can be controlled using a controller, such as control circuit 121. After the photodiode 205 is reset, the storage transistors 235 and 239 may be initialized for storing image charge over a plurality of accumulation periods. In one example, control circuit 121 may generate a negative voltage to be applied to the gates of memory transistors 235 and 239 before the memory transistors are activated.

Figures 3A and 3B are line graphs illustrating the negative gate voltage applied to the gate of a storage transistor and the corresponding holes accumulated under the gate during operation of a time-of-flight pixel according to the teachings of this disclosure. In one example, control circuit 121 sends control signals having a negative bias (e.g., negative bias 305) to storage transistors (e.g., storage transistors 235 and 239). The control signal may be lower than the threshold voltage of the memory transistor (e.g., SG threshold voltage 307) by more than 0.5V. In one example, the control signal has a voltage of-1.2V. Pre-biasing the gate of the memory transistor with a negative voltage "accumulates" holes in a surface state in the substrate below the memory transistor (see fig. 3B). The positively charged accumulated holes may physically exclude electrons from surface states and thus minimize electron interactions with surface states. Thus, leakage current from surface states may be reduced, which reduces leakage current that draws accumulated image charge from within the storage transistor. This may allow the storage gate to accumulate charge over a longer period of time (e.g., multiple accumulation periods), which achieves an improved signal-to-noise ratio.

When the memory transistor is pre-biased with a negative voltage, the memory transistor may need to be isolated from the transistors coupled to its source and drain. Control circuit 121 may be used to deactivate (turn off) adjacent transistors to achieve isolation. For example, the control circuit 121 may deactivate the pass transistor 225 and the output transistor 245 when pre-biasing the storage transistor 235. Similarly, the control circuit 121 may deactivate the transfer transistor 229 and the output transistor 249 while pre-biasing the memory transistor 239.

Fig. 4A and 4B are example timing diagrams that may be used to help describe the operation of time-of-flight pixel circuit 200 to acquire image charge in conjunction with the time-of-flight imaging system and time-of-flight pixel circuit in fig. 1-2 above. Specifically, fig. 4A is a timing diagram showing an example of modulated pulses of emitted light 405 and corresponding pulses of reflected light 409 in relation to switching modulation signals TX1425 and TX2429 in an example time-of-flight imaging system, according to the teachings of this disclosure.

Fig. 4A illustrates that image charge can accumulate in photodiode 205 whenever a pulse of light from emitted light 405 reflects off of object 107 and becomes reflected light 409. In the illustrated example, the emitted light 405 has a modulation frequency, and may have a duty cycle of less than 10%. As shown in the example, reflected light 409 has the same modulation frequency as emitted light 405, as well as the same duty cycle and pulse width T_PW447. Pulse width T of emitted light 405_PW447 may be in the range of 20 nanoseconds to 100 nanoseconds. Due to the time of flight of the light pulses to and from the object 107, at time of flight T_TOFFollowing 417, the light pulses of reflected light 409 are received by pixels in time-of-flight pixel array 113.

The image charge accumulated in photodiode 205 from a single light pulse is the sum of Q1449 and Q2451. Q1449 is accumulated by the photodiode 205 during the time that the transfer transistor 225 is activatedAnd Q2451 is accumulated by the photodiode 205 during the time that the transfer transistor 229 is activated. Transfer transistor 225 selectively transfers Q1449 (the temporally first portion of the image charge accumulated by photodiode 205) to storage transistor 235 when transfer transistor 225 is activated by control circuit 121. First modulation signal TX1425 activates transfer transistor 225 for the same duration (T) while the light pulses making up emitted light 405 are being emitted from light source 103_PW447). Thus, the first modulation signal TX1425 may be said to be "in phase" with the emitted light 405.

When transfer transistor 229 is activated by control circuit 121, transfer transistor 229 selectively transfers Q2451 (the temporally second portion of the image charge accumulated by photodiode 205) to storage transistor 239. As shown in fig. 4A, second modulation signal TX2429 activates transfer transistor 229 immediately after deactivation of transfer transistor 225 (corresponding to first modulation signal TX 1425). It should be appreciated that the transfer transistor 229 is activated for the same duration (T) as the light pulse that makes up the emitted light 405_PW447) And the same duration (T) that the pass transistor 225 is activated_PW447). Given the relationship between the second modulation signal TX2429 and the emitted light 405, the second modulation signal TX2429 may be said to be "out of phase" with the emitted light 405. Each pulse of second modulation signal TX2429 immediately follows each pulse of first modulation signal TX1425 and does not overlap each pulse of first modulation signal TX 1425. Thus, as shown in fig. 4A, each on-time pulse of reflected light 409 is received by photodiode 205 immediately after the end portion of each pulse of first modulation signal TX1425, and during the beginning portion of each pulse of second modulation signal TX2429, in accordance with the teachings of this disclosure.

As mentioned above, pass transistor 225 is switched in response to first modulation signal TX1425 and pass transistor 229 is switched in response to second modulation signal TX 2429. Thus, during each on-time pulse of first modulation signal TX1425, the photo-generated charge accumulated in photodiode 205 is transferred to storage transistor 235. In the example, this photo-generated charge transferred from photodiode 205 to storage transistor 235 in response to first modulation signal TX1425 is represented in FIG. 4A as Q1449. Similarly, during each on-time pulse of second modulation signal TX2429, the photo-generated charge accumulated in photodiode 205 is transferred to storage transistor 239. In the example, the photo-generated charge transferred from the photodiode 205 to the storage transistor 239 in response to the second modulation signal TX2429 is represented as Q2451 in fig. 4A.

In one example, the time of flight T taken for light emitted from the light source 103 to travel to the object 107 and return from the object 107 may be determined according to the following relationship in equation (3) below_TOF417：

Wherein T is_TOFRepresenting time of flight T_TOF417，T_PWRepresents the pulse width T_PW447, ∑ Q2 represents the total amount of charge Q2 accumulated in the storage transistor 239 and ∑ (Q1+ Q2) represents the sum of the total amounts of charge accumulated in the storage transistors 235 and 239_TOF417, T may then be added_TOFThe result is substituted into equation (2) outlined above to determine the distance L.

FIG. 4B is a block diagram showing an embodiment according to the teachings of the present inventionA timing diagram of another example of the transmitted and reflected light pulses relative to the switching of transfer transistors 225 and 229 in a time-of-flight imaging system. It should be appreciated that fig. 4B is similar to fig. 4A, but the time scale along the x-axis of fig. 4B has a lower resolution than the time scale of fig. 4A. Thus, fig. 4B illustrates an example in which charge is allowed to accumulate in storage transistors 235 and 239 over multiple cycles of reflected light 409. In the example shown in fig. 4B, charge information is read out of time-of-flight pixel circuit 200 during the period in which the light source is on 453 at the time indicated by RO 457. The time between ROs 457 is the frame time. Each frame may be in tens of milliseconds. During one frame, hundreds of thousands of integration/accumulation periods may occur corresponding to hundreds of thousands of light pulses emitted by the light source 103. Thus, RO457 may occur after multiple (e.g., hundreds of thousands) reflected light pulses illuminate photodiode 205 and charges Q1449 and Q2451 are transferred to storage transistors 235 and 239, respectively, multiple times. In doing so, charge is allowed to accumulate within storage transistors 235 and 239 over multiple cycles, which provides an improved signal-to-noise ratio compared to time-of-flight calculations based on only a single light pulse, because of the pulse width T_PW447 are so small due to the very short illumination pulses in the range of 20 ns to 100 ns.

Fig. 4B also illustrates an example in which the light source 103 is turned off 455 for one or more periods to allow for background signal measurements 459 to be made. In this example, the background signal from storage transistors 235 and 239 is periodically measured while photodiode 205 is not illuminated with reflected light 409. This measurement may be made at the end of the light off 455 period, as shown. In one example, such a measurement may represent ambient light and/or dark current in the pixel, which would add noise to the time of flight calculation. In one example, according to the teachings of this disclosure, this background signal measurement 459 may be stored as calibration information and may be subtracted from measurements made during the light on 453 periods to compensate for determining the time of flight T_TOFBackground noise at 417.

FIG. 5 is a timing diagram illustrating an example operation of a time-of-flight pixel according to the teachings of this disclosure. As shown in fig. 5, the control signal (SG1) that controls the gate of the memory transistor 235 is driven to the first negative voltage 501 before the pass transistor 225 passes the first Q1449 to the memory transistor 235. Fig. 5 shows a mini-chart labeled as "Σ Q1 within SG 1511" which gives a visual representation of the accumulated image charge stored within storage transistor 235 corresponding to the timing of first modulation signal TX 1425. The mini-plot 511 shows that there is negligible (or no) image charge stored in the storage transistor 235 when it is pre-biased with the first negative voltage 501. Also shown in fig. 5, before pass transistor 229 passes first Q2451 to storage transistor 239, the control signal (SG2) controlling the gate of storage transistor 239 is driven to a second negative voltage 503. Fig. 5 shows a mini-chart labeled as "Σ Q2 within SG 2513" which gives a visual representation of the accumulated image charge stored within storage transistor 239 corresponding to the timing of second modulation signal TX 2429. The mini-graph 513 shows that there is negligible (or no) image charge stored in the storage transistor 239 when it is pre-biased with the second negative voltage 503. It should be appreciated that both negative voltages 501 and 503 are lower than the threshold voltage (VTH507) of storage transistors 235 and 239, respectively. For example, the negative voltages 501 and 503 may be-1.2V, and the actuation voltage (applied to the gate) of the transistor may be approximately 2.8-3.2V.

Fig. 5 also shows example control signals RST, SEL, OG1, and OG2 that control reset transistor 255, select transistor 265, and output transistors 245 and 249, respectively, for readout of Σ Q1 and Σ Q2. These control signals may be generated by control circuitry 121. Referring back to fig. 2, the reset transistor 255 is coupled between a voltage source VDD257 and the sense node 240. The sense node 240 is coupled to output transistors 245 and 249 and to an amplifier transistor 260. Amplifier transistor 260 has a gate coupled to sense node 240 and operates as a source follower that amplifies an input signal at the gate terminal of amplifier transistor 260 to an output signal at the source terminal of amplifier transistor 260. The drain terminal of amplifier transistor 260 may be coupled to a voltage source VDD 257. The select transistor 265 is coupled between the source terminal of the amplifier transistor 260 and a bit line (BITLINE) 267. The select transistor 265 is configured to selectively couple the output signal of the amplifier transistor 260 to the bit line 267 for sensing.

Referring back to fig. 5, after the storage transistor finishes collecting the image charge, the image charge will be read out. It should be understood that fig. 5 shows only three accumulation cycles before readout for illustration purposes, but that hundreds or thousands of accumulation cycles may exist between readouts. In the illustrated example, reset transistor 255 is activated (via control signal RST) a first time when a read occurs (e.g., RO 457). When the reset transistor 255 is activated for the first time, a known voltage (e.g., voltage source VDD257) is coupled to the sense node 240 to precharge the sense node 240 to the known voltage for the first time. The output transistor 245 is then activated (via control signal OG1), which transfers the image charge (SIG Q1) stored within the storage transistor 235 to the readout node 240. The mini-graph 511 shows that ∑ Q1 within the storage transistor 235 decreases when the output transistor 245 is activated. When Σ Q1 flows into the sense node 240, it biases the gate of amplifier transistor 260, which places a corresponding amplified voltage representing Σ Q1 onto the source terminal of amplifier transistor 260. Select transistor 265 is then activated for the first time (via control signal SEL), which couples the amplified voltage to bit line 267 for sensing.

In the illustrated example, reading out Σ Q2 after reading out Σ Q1 functions similarly to reading out Σ Q1. The reset transistor 255 is activated a second time to precharge the sense node 240 to a known voltage. The output transistor 249 is then activated (via control signal OG2), which transfers the image charge (SIG Q2) stored within the storage transistor 239 to the sense node 240. The mini-graph 513 shows that Σ Q2 within the storage transistor 239 decreases when the output transistor 249 is activated. When Σ Q2 flows into the sense node 240, it biases the gate of amplifier transistor 260, which places a corresponding amplified voltage representing Σ Q2 onto the source terminal of amplifier transistor 260. The select transistor 265 is then activated a second time, which couples the amplified voltage to the bit line 267 for sensing.

In one example, for double correlated sampling purposes, the control circuit 121 may initiate a readout sequence (not shown) of the readout node 240 after resetting the reset transistor 255 and the absence of Σ Q1 or Σ Q2 in the readout node 240.

In one example of a readout sequence (not shown), the readout node 240 is reset, and then the OG2 is activated and the ∑ q2 is read out, in the case where ∑ Q2 is still in the readout node 240, the OG1 is activated, which allows ∑ Q1 to flow into the readout node 240 and join ∑ q2, then, in the case where ∑ Q1+ ∑ Q2 is in the readout node 240, reading out the readout node 240 first ∑ Q2 and second readout ∑ Q1+ ∑ Q2 can reduce the computation of T3 according to equation 3 of this disclosure_TOFThe amount of processing required. Those skilled in the art will appreciate that other readout sequences may be utilized to readout the image charge stored within storage transistors 235 and 239.

Referring again to FIG. 2, the example shows an optional transistor set 299 including a transfer transistor 269 (controlled with a control signal TX3), a storage transistor 279 (controlled with a control signal SG 3), and an output transistor 289 (controlled with a control signal OG 3). Storage transistor 279 is coupled between transfer transistor 269 and output transistor 289. Optionally, in the illustrated example, transfer transistor 269 is coupled to photodiode 205 and output transistor 289 is coupled to readout node 240. In one example, optional transistor set 299 can optionally be used as a way to correct for possible aliasing of emitted light 105. In this example, transfer transistor 269 may be activated (via control signal TX3) after transfer transistor 229 is deactivated, but before transfer transistor 225 is activated to transfer image charge to storage transistor 279. An optional transistor set 299 may be used to capture luminance images during the off 455 period to provide a calibration reference for counteracting background illumination (e.g., ambient light 208) and obtaining a true reading of the emitted light 105.

FIG. 6 is a flow diagram illustrating an example process 600 for determining time of flight using pixels according to the teachings of this disclosure. The order in which some or all of the process blocks appear in process 600 should not be considered limiting. Rather, those skilled in the art, having the benefit of this disclosure, will appreciate that some of the process blocks may be executed out of order or even in parallel.

In process block 605, first and second storage transistors (e.g., storage transistors 235 and 239) are initialized to store image charge over a plurality of accumulation periods. The initialization may include pre-biasing the gate of the memory transistor with a negative voltage such that holes accumulate in a surface state in anticipation of acquiring image charge. As discussed in connection with fig. 1-5, surface state holes may reduce leakage current drawn from the storage gate as the storage gate acquires image charge over multiple accumulation periods. The photodiode receiving the light pulse (e.g., photodiode 205) may be reset prior to process block 605.

In a process block 610, a light pulse (e.g., emitted light 105) is emitted from a light source (e.g., light source 103) in response to a first modulation signal (e.g., TX 1425). In process block 615, a first transfer transistor (e.g., transfer transistor 225) is activated in response to the pulse width from the first modulation signal to transfer image charge (e.g., Q1449) generated by the light pulses to a first storage transistor (e.g., storage transistor 235). Image charges are generated in the photodiodes in response to incident light from the light pulses. In a process block 620, a second transfer transistor (e.g., transfer transistor 229) is activated in response to the pulse width from a second modulation signal (e.g., TX2429) to transfer image charge (e.g., Q2451) generated by the light pulses to a second storage transistor (e.g., storage transistor 239).

If multiple accumulation cycles are over, then Σ Q1 is read out from within the first storage transistor and Σ Q2 is read out from within the second storage transistor (process block 625). Process block 625 may correspond to RO457 in fig. 4B. In one example discussed above, Σ Q2 is first transferred into a sense node (e.g., sense node 240), and then Σ Q2 is read out. Then, Σ Q1 is transferred into the readout node, so that the readout node holds Σ Q1+ ∑ Q2, and reads out Σ Q1+ ∑ Q2. If Σ Q1 and Σ Q2 are not read out in process block 625, the process returns to process block 610 for another accumulation period. If Σ Q1 and Σ Q2 are read out in process block 625, the ratio between the sums is used to determine the time of flight of the optical pulse, as discussed above (process block 630). Once the time of flight has been determined in process block 630, the process may end or return to process block 605 to prepare the storage transistor to store image charge within a subsequent frame of the plurality of accumulation periods.

FIG. 7 is a block diagram showing a portion of an example time-of-flight sensing system 700 in greater detail according to teachings of this disclosure. As shown, the illustrated example of a time-of-flight sensing system 700 includes a time-of-flight pixel array 713, readout circuitry 753, functional logic 755, and control circuitry 721. It should be appreciated that time-of-flight pixel array 713 corresponds to time-of-flight pixel array 113 of FIG. 1A, and control circuitry 721 corresponds to control circuitry 121.

In the example illustrated in fig. 7, time-of-flight pixel array 713 is a two-dimensional (2D) array of time-of-flight pixels (e.g., pixels P1, P2, …, Pn). In one example, each of the time-of-flight pixels P1, P2, …, Pn may be substantially similar to the system or time-of-flight pixel circuits discussed above in fig. 1-6. As illustrated, each pixel is arranged into rows (e.g., rows R1-Ry) and columns (e.g., columns C1-Cx) to acquire time-of-flight data for an image of an object focused onto time-of-flight pixel array 713. Thus, according to the teachings of this disclosure, the time-of-flight data may then be used to determine distance to an object or depth information.

In one example, after each pixel has accumulated its Σ Q1 and Σ Q2 charge information in the respective storage transistor, as discussed above, the Σ Q1 and Σ Q2 signals are readout by readout circuit 753 and transferred to functional logic 755 for processing. The readout circuit 753 may include an amplification circuit, an analog-to-digital (ADC) conversion circuit, or other circuits. In one example, function logic 755 may determine time-of-flight and distance information for each pixel. In one example, the functional logic may also store time-of-flight information and/or even manipulate the time-of-flight information (e.g., crop, rotate, adjust for background noise, etc.). In one example, readout circuitry 753 may readout a row of image data at a time along readout column lines (illustrated), or may readout the image data using a variety of other techniques (not illustrated), such as a serial readout or a full parallel readout of all pixels at once.

In the illustrated example, control circuitry 721 is coupled to time-of-flight pixel array 713 to control the operation of time-of-flight pixel array 713. For example, control circuitry 721 may generate first and second modulation signals TX1425 and TX2429 to control respective transfer transistors (e.g., transfer transistors 225 and 229) in each pixel of time-of-flight pixel array 713. Thus, the control circuit 721 may control the transfer of charge from the respective photodetectors to the respective storage transistors (e.g., storage transistors 235 and 239), as described above with respect to fig. 1-6. In one example, the control circuit 721 may also control the light source (e.g., light source 103) that emits the light pulses to the object (e.g., object 107) with the synchronization signal 715 to synchronize the emission of the modulated light to the object to determine time-of-flight information, in accordance with the teachings of this disclosure.

The processes explained above are described in terms of computer software and hardware. The described techniques may constitute machine-executable instructions embodied within a tangible or non-transitory machine (e.g., computer) readable storage medium, that when executed by a machine will cause the machine to perform the operations described. Additionally, the process may be included within hardware, such as an application specific integrated circuit ("ASIC") or other hardware.

A tangible, non-transitory machine-readable storage medium includes any mechanism that provides (i.e., stores) information in a form accessible by a machine (e.g., a computer, network device, personal digital assistant, manufacturing tool, any device with a set of one or more processors, etc.). For example, a machine-readable storage medium includes recordable/non-recordable media (e.g., Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.).

The above description of illustrated embodiments of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (27)

1. A time-of-flight "TOF" imaging apparatus comprising:

a photodiode configured to accumulate image charge over an accumulation period in response to each pulse of non-visible light emitted from a light source, the pulse of non-visible light becoming incident on the photodiode;

a first storage transistor configured to store a first sum of a first portion of the image charge over a plurality of accumulation periods, wherein the accumulation periods are among the plurality of accumulation periods;

a first transfer transistor coupled between the photodiode and the first storage transistor to selectively transfer the first portion of the image charge from the photodiode to the first storage transistor for storage over the plurality of accumulation periods;

a first output transistor coupled to the first storage transistor to selectively transfer the first sum of the first portion of the image charge to a readout node;

a second storage transistor configured to store a second sum of a second portion of the image charge over the plurality of accumulation periods;

a second transfer transistor coupled between the photodiode and the second storage transistor to selectively transfer the second portion of the image charge from the photodiode to the second storage transistor for storage over the plurality of accumulation periods; and

a second output transistor coupled to the second storage transistor to selectively transfer the second sum of the second portion of the image charge to the readout node.

2. The apparatus of claim 1, further comprising control circuitry configured to apply a first negative voltage to a first gate of the first storage transistor and a second negative voltage to a second gate of the second storage transistor, wherein the first negative voltage is applied to the first gate before selectively transferring the first portion of the image charge to the first storage transistor, and wherein the second negative voltage is applied to the second gate before selectively transferring the second portion of the image charge to the second storage transistor.

3. The apparatus of claim 1, further comprising a reset transistor coupled to the readout node to selectively reset charge accumulated in the readout node.

4. The apparatus of claim 1, further comprising:

an amplifier transistor coupled to the readout node to amplify an image voltage corresponding to the charge in the readout node; and

a row select transistor coupled between the amplifier transistor and a bit line.

5. The apparatus of claim 1, wherein the first portion of the image charge is generated within the photodiode for a first time period in the accumulation period, and the second portion of the image charge is generated within the photodiode for a second time period immediately after the first time period in the accumulation period.

6. The apparatus of claim 1, wherein the photodiode is a pinned photodiode.

7. The apparatus of claim 1, further comprising a control circuit configured to send a first modulation signal having a first on-time pulse width to activate the first transfer transistor to transfer the first portion of the image charge, wherein the control circuit is configured to activate the first transfer transistor in synchronization with each pulse of non-visible light emitted from the light source, and wherein a duration of the pulse of non-visible light is the same as the first on-time pulse width of the first modulation signal.

8. The apparatus of claim 7, wherein the control circuit is further configured to activate the second transfer transistor to transfer the second portion of the image charge in response to a second modulation signal having a second on-time pulse width immediately after the first on-time pulse width and having the duration of the non-visible light pulse, and wherein the light source does not emit light when the second transfer transistor is activated.

9. The apparatus of claim 1, further comprising:

a third storage transistor that stores visible light image charges;

a third transfer transistor coupled between the photodiode and the third storage transistor to selectively transfer the visible light image charge from the photodiode to the third storage transistor; and

a third output transistor coupled to the third storage transistor to selectively transfer the visible light image charges to the readout node.

10. A time-of-flight "TOF" imaging system comprising:

a light source coupled to emit light pulses in response to a first modulation signal; and

an imaging pixel array having the imaging pixels arranged in rows and columns, wherein each imaging pixel includes:

a photodiode configured to accumulate image charge over an accumulation period in response to each pulse of non-visible light emitted from a light source, the pulse of non-visible light becoming incident on the photodiode;

a first storage transistor configured to store a first sum of a first portion of the image charge over a plurality of accumulation periods, wherein the accumulation periods are among the plurality of accumulation periods;

a first transfer transistor coupled between the photodiode and the first storage transistor to selectively transfer the first portion of the image charge from the photodiode to the first storage transistor for storage over the plurality of accumulation periods;

a first output transistor coupled to the first storage transistor to selectively transfer the first sum of the first portion of the image charge to a readout node;

a second storage transistor configured to store a second sum of a second portion of the image charge over the plurality of accumulation periods;

a second transfer transistor coupled between the photodiode and the second storage transistor to selectively transfer the second portion of the image charge from the photodiode to the second storage transistor for storage over the plurality of accumulation periods; and

a second output transistor coupled to the second storage transistor to selectively transfer the second sum of the second portion of the image charge to the readout node.

11. The imaging system of claim 10, further comprising a control circuit configured to apply a first negative voltage to a first gate of the first storage transistor and a second negative voltage to a second gate of the second storage transistor, wherein the first negative voltage is applied to the first gate before selectively transferring the first portion of the image charge to the first storage transistor, and wherein the second negative voltage is applied to the second gate before selectively transferring the second portion of the image charge to the second storage transistor.

12. The imaging system of claim 10, further comprising a reset transistor coupled to the readout node to selectively reset charge accumulated in the readout node.

13. The imaging system of claim 10, further comprising:

an amplifier transistor coupled to the readout node to amplify an image voltage corresponding to the charge in the readout node; and

a row select transistor coupled between the amplifier transistor and a bit line.

14. The imaging system of claim 10, wherein the first portion of the image charge is generated over a first time period and the second portion of the image charge is generated over a second time period immediately following the first time period.

15. The imaging system of claim 10, further comprising control circuitry configured to send the first modulation signal having a first on-time pulse width to activate the first transfer transistor to transfer the first portion of the image charge, wherein the control circuitry is configured to activate the first transfer transistor in synchronization with a light pulse among the light pulses emitted from the light source, and wherein a duration of the light pulse is the same as the first on-time pulse width of the first modulation signal.

16. The imaging system of claim 15, wherein the control circuitry is further configured to activate the second transfer transistor to transfer the second portion of the image charge in response to a second modulation signal having a second on-time pulse width immediately after the first on-time pulse width and having the duration of the light pulse, and wherein the light source does not emit light when the second transfer transistor is activated.

17. A method of determining time of flight using pixels, the method comprising:

initializing a first storage transistor and a second storage transistor for storing image charges generated in the photodiode during a plurality of accumulation periods;

emitting light pulses from a light source, wherein each of the light pulses is emitted from the light source in response to each of first on-time pulse widths of a first modulation signal;

activating a first transfer transistor in response to each of the first on-time pulse widths to transfer a temporally first portion of accumulated image charge to the first storage transistor, wherein the accumulated image charge is generated in the photodiode each time one of the light pulses reflects off an object and illuminates the photodiode during one of the plurality of accumulation periods;

activating a second transfer transistor in response to each of a second on-time pulse width of a second modulation signal, wherein activating the second transfer transistor transfers a temporally second portion of the accumulated image charge to the second storage transistor; and

determining a time of flight of the light pulse using a first sum of each of the temporally first portions of the accumulated image charge transferred to the first storage transistor and a second sum of each of the temporally second portions of the accumulated image charge transferred to the second storage transistor.

18. The method of claim 17, wherein the second on-time pulse width is immediately subsequent to the first on-time pulse width and has the same duration as the first on-time pulse width.

19. The method of claim 17, wherein determining a time of flight of the light pulse comprises:

activating a first output transistor coupled between the first storage transistor and a sense node to transfer the first sum to the sense node;

activating a second output transistor coupled between the second storage transistor and the sense node to transfer the second sum to the sense node; and

a reset transistor coupled to the sense node is reset.

20. The method of claim 17, wherein determining the time of flight of the light pulses comprises multiplying a pulse width time of each of the light pulses by the second sum divided by a third sum of the first sum and the second sum.

21. The method of claim 17, wherein initializing the first storage transistor and the second storage transistor comprises:

negatively biasing a first gate of the first storage transistor prior to activating the first pass transistor in response to each of the first on-time pulse widths; and

a second gate of the second storage transistor is negatively biased prior to activating the second pass transistor in response to each of the second on-time pulse widths.

22. The method of claim 21, wherein negatively biasing the first gate of the first storage transistor and the second gate of the second storage transistor reduces leakage current.

23. The method of claim 21, wherein the first gate is negatively biased at least 0.5 volts below a first threshold voltage of the first storage transistor and the second gate is negatively biased at least 0.5 volts below a second threshold voltage of the second storage transistor.

24. The method of claim 17, wherein the first storage transistor is coupled between the first pass transistor and a first output transistor coupled to a sense node, and wherein the second storage transistor is coupled between the second pass transistor and a second output transistor coupled to the sense node.

25. The method of claim 17, wherein the plurality of accumulation periods number up to more than one thousand accumulation periods, and wherein the determining the time of flight of the light pulse occurs after the plurality of accumulation periods.

26. The method of claim 17, further comprising:

activating a third transfer transistor to transfer visible light image charge from the photodiode to a third storage transistor between the plurality of accumulation periods, wherein activating the third transfer transistor is at an image time when the first transfer transistor and the second transfer transistor are not activated.

27. The method of claim 17, wherein the light pulse is substantially near-infrared light centered between 800nm and 900 nm.