HK1186572B - An image sensor pixel and method for operating the same, and an image sensor - Google Patents

Abstract

The subject application relates to an image sensor pixel and method for operating the same, and an image sensor. An image sensor pixel suitable for use in a back-side-illuminated or a front-side-illuminated sensor arrangement is provided. The image sensor pixel may be a small size pixel that includes a source follower implemented using a vertical junction field effect (JFET) transistor. The vertical JFET source follower may be integrated directly into the floating diffusion node, thereby eliminating excess metal routing and pixel area typically allocated for the source follower in conventional pixel configurations. Pixel area may instead be allocated for increasing the charge storage capacity of the photodiode or can be used to reduce pixel size while maintaining pixel performance. Using a vertical junction field effect transistor in this way simplifies pixel addressing operations and minimizes random telegraph signal (RTS) noise associated with small size metal-oxide-semiconductor (MOS) transistors.

Description

Image sensor pixel, operation method thereof and image sensor

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of united states patent application No. 13/476,784, filed on day 5, month 21, 2012 and united states provisional patent application No. 61/569,734, filed on day 12, month 12, 2011, which are hereby incorporated by reference in their entirety.

Technical Field

The present invention relates to solid state image sensors, and more particularly, to front or backside illuminated image sensors having small sized pixels. The small pixel size helps to reduce the cost of the image sensor array. However, sensor performance should not be affected as pixel size decreases.

Background

Conventional image sensors detect light by converting impinging photons into electrons that are integrated (collected) within the sensor pixel. Upon completion of each integration cycle, the collected charge is converted to a voltage signal, which is then supplied to a respective output terminal associated with the image sensor. Typically, the charge-to-voltage conversion is performed directly within the pixel, and the resulting analog pixel voltage signal is transferred to the output terminals through various pixel addressing and scanning schemes. Analog signals can sometimes be converted to equivalent numbers on-chip before being transferred off-chip. Each pixel includes a buffer amplifier, commonly referred to as a Source Follower (SF), for driving an output sense line connected to the pixel via a respective address transistor.

After the charge-to-voltage conversion is completed and after the resulting signal is transferred out of the pixel, the pixel is reset before the beginning of a subsequent integration cycle. Within a pixel having a Floating Diffusion (FD) acting as a charge detection node, this reset operation is accomplished by temporarily turning on a reset transistor that connects the FD node to a fixed voltage reference for draining (or removing) any charge remaining at the FD node.

However, as is well known in the art, removing charge from the floating diffusion node using a reset transistor generates kTC reset noise. To achieve the desired low noise performance, kTC noise must be removed using Correlated Double Sampling (CDS) signal processing techniques. Image sensors utilizing CDS typically require three transistors (3T) or four transistors (4T) per pixel. An example of a 4T pixel circuit with pinned photodiodes can be found in Lee (U.S. patent No. 5,625,210, which is incorporated herein by reference).

Fig. 1 is a simplified representation of a cross-sectional side view of a conventional image sensor pixel 100. As shown in fig. 1, a conventional image sensor pixel 100 includes a photodiode 107 configured to collect photo-generated carriers, a charge transfer transistor gate 108, an N + doped floating diffusion region 111, a reset transistor gate 109, and a source follower transistor gate 110. The reset transistor and the source follower transistor share an N + drain region 112 that is biased to a fixed positive supply voltage Vdd. The source follower transistor has an N + source region 113 that is connected to a column sense line Vout (i.e., the output line to which each pixel in a given column is connected) via a metal via 115.

Note that the floating diffusion region 111 is connected to the source follower gate 110 via a connection 116. This connection supplies the signal collected at the floating diffusion region to the source follower transistor gate. Pixel 100 may include an address transistor interposed between region 113 and sense line Vout that is common to all pixels in a given column of image sensor pixels. For simplicity, the address transistors are not shown in FIG. 1.

The pixel 100 is fabricated in an epitaxial substrate 101. If the sensor is a backside illuminated image sensor, a P + doped layer 102 is deposited on the backside surface of the sensor. The substrate 101 may also be deposited on a substantially thicker P + substrate (relative to layer 102) for a front side illuminated image sensor. Epitaxial layer 101 is covered by oxide layer 103, which oxide layer 103 provides electrical isolation for gates 108, 109 and 110. The oxide material 103 generally extends into the Shallow Trench Isolation (STI) region 114 and fills the Shallow Trench Isolation (STI) region 114. An additional oxide layer 104 is deposited over the gate and serves as isolation for metal wiring formed over the pixel 100. Additional oxide isolation layers and metal wiring layers are typically deposited (not shown) over the top of the pixel 100.

Photodiode 107 includes P + layer 105, which is formed directly under layer 103 and connected to ground. This P + doped layer reduces dark current by filling the silicon-to-silicon dioxide interface state with holes. The photo-generated electrons accumulate within the N-type doped region 106. When the transfer gate 108 is turned on, the accumulated charges are transferred to the N + floating diffusion region 111. The floating diffusion region 111 needs to be reset by a pulse modulated signal supplied to the gate 109 of the reset transistor before the charge transfer gate 108 is turned on.

An additional bottom P implant (BTP) layer 117 extends from the P + layer 105 formed under the STI region 114 to the region under the reset transistor gate 109 and the source follower transistor gate 110 (see fig. 1). Layer 117 is connected to ground and functions to block photogenerated electrons from entering regions 111, 112 and 113.

As is apparent from fig. 1, most of the useful pixel area is occupied by transistor gates 108, 109 and 110. It may be disadvantageous to form the transistors side-by-side on the surface of the substrate 101 using this arrangement. Accordingly, it may be desirable to provide an image sensor having a reduced pixel area, where a smaller portion of the pixel area is occupied by a transistor and a larger portion of the pixel area is occupied by a photodiode.

Disclosure of Invention

Various embodiments have been described illustrating small size pixel designs showing improved storage well capacity and low dark current. The pixel may include a photodiode (e.g., a pinned photodiode), a charge transfer transistor (sometimes referred to as a charge transfer gate), a reset transistor (sometimes referred to as a reset gate), and a source follower transistor. The small-sized pixels may include vertical Junction Field Effect Transistors (JFETs) that act as source followers.

Small size pixels can include a floating diffusion region shared between the source to drain of the charge transfer gate, the source to drain of the reset gate, and the gate of the vertical JFET source follower. A floating diffusion region may be formed using a plurality of vertically stacked N-type doped regions, as an example. A P + doped region may be formed in one of the stack regions to act as a source for the vertical SF, however, a P-type doped region may be formed in the remaining stack region to act as a channel for the vertical JFET source follower. A bottom P + implant layer may be formed under the stacked floating diffusion region to act as a drain for the vertical JFET source follower.

The use of a vertical JFET source follower may provide reduced Random Telegraph Signal (RTS) noise, which is typically associated with small metal oxide semiconductor source follower transistors. Additional address transistors need not be used if desired. Selected pixels may be reset to a reduced bias level to distinguish from unselected pixels along columns of pixels that may have SF gates held at a higher bias level.

Drawings

Fig. 1 is a simplified cross-sectional side view of a conventional image sensor pixel.

FIG. 2 is a simplified schematic diagram of an illustrative image sensor pixel having a vertical junction gate source follower in accordance with an embodiment of the invention.

FIG. 3 is a simplified cross-sectional side view of an illustrative image sensor pixel of the type shown in FIG. 2, according to an embodiment of the invention.

FIG. 4 is an example of a timing diagram illustrating how an image sensor pixel of the type shown in FIG. 2 may be operated according to an embodiment of the invention.

Detailed Description

Fig. 2 is a simplified circuit diagram showing one suitable circuit arrangement for an image sensor pixel, such as pixel 200. As shown in fig. 2, the pixel 200 may include a pinned photodiode 207, a charge transfer transistor 208, a reset transistor 209, and a source follower transistor 300. The charge generated from the impinging photons can be collected using a photodiode 207. The reset transistor 209 may be used to reset the floating diffusion node 302 associated with the pixel 200 (e.g., by temporarily pulsing the reset gate control signal Rx). After the reset operation, the collected charge may be transferred to the floating diffusion node 302 via the gate of the charge transfer transistor 208 (e.g., by temporarily pulsing the charge transfer gate control signal Tx). The source follower transistor 300 may be used to buffer signals generated from transferred charge present on the floating diffusion node, and to drive a respective column output line Vout.

The photodiode 207 may have a P-type doped region coupled to a ground power supply terminal 312 (e.g., a power supply line on which a ground power supply signal Vss is provided) and an N-type doped region coupled to the floating diffusion node 302 via the charge transfer transistor 208. The reset transistor 209 may have a drain region coupled to an adjustable power supply terminal 310 (e.g., an adjustable power supply terminal on which an adjustable power supply voltage Vddx is provided), and a source region coupled to the floating diffusion node 302.

According to an embodiment of the present invention, the source follower transistor 300 may be a Junction Field Effect Transistor (JFET), however, the transistors 208 and 209 may be N-channel metal oxide semiconductor (NMOS) transistors. The source follower transistor 300 may have a source coupled to the output sense line Vout, a drain coupled to ground 312, and a gate coupled to the floating diffusion region 302. As shown in fig. 2, an address transistor 304 (e.g., a transistor selectively turned on using an address signal Addr) may optionally be inserted in the output path between the source of the transistor 300 and the output line Vout.

Fig. 3 shows a simplified cross-sectional side view of an image sensor pixel 200. As shown in fig. 3, the pixel 200 may be formed within an epitaxial substrate 201. If the pixel 200 is to be used in a backside illumination arrangement, a P + doped layer 202 may be deposited on the backside of the substrate 201. If pixel 200 is to be used in a front-side lighting configuration, epitaxial substrate 201 may be deposited on a thicker P + silicon carrier (i.e., a silicon carrier having a thickness substantially greater than the thickness of layer 202). Layer 202 may function to reduce dark current by filling the silicon interface state with holes and thus quenching dark current generation. The silicon to silicon dioxide interface on the front side of the substrate 201 within the pinned photodiode region 207 is also lined with a P + doped layer 201 to help reduce dark current generation. Layer 205 may extend into substrate 201 beneath shallow trench isolation regions 250.

The pinned photodiode 207 may be formed from a P + doped region 205 and an N-doped region 206. The impinging photons may generate charges (e.g., electrons) that are temporarily stored in N-type region 206. The epitaxial substrate 201 may be covered by a dielectric layer (e.g., a silicon dioxide layer 203). Layer 203 can be formed between the gate conductors (e.g., gate conductors 208 'and 209') of pixel 200 and substrate 201.

The N + region 218 may serve as a drain for the reset transistor 209. The N + region 218 may be coupled to an adjustable supply voltage Vddx via a conductive via 219. The voltage bias Vddx may be used as a reference voltage level to which the pixel 200 may be reset. The reset transistor 209 has a gate 209' configured to receive a signal Rx through a respective control routing path formed over the top of the interlayer oxide layer 204. Similarly, charge transfer transistor 208 has a gate 208' configured to receive signal Tx via a respective control routing path formed over the top of layer 204.

For simplicity, the detailed routing of the control paths on which the signals Tx, Vout, Rx, and Vddx are provided is not shown in FIG. 2. A dielectric stack, also comprising alternating layers of conductive via layers and metal routing layers, may be formed over the top of pixel 200 over layer 204.

As shown in fig. 3, the pixel 200 may include N-type doped regions 210, 212, and 213, which collectively function as a floating diffusion region 302 for the pixel 200. The floating diffusion region 302 formed in this manner serves as both a source-drain for the charge transfer transistor 208, a source for the reset transistor 209, and a gate for the source follower transistor 300 (e.g., the transistor 300 may have a gate integrated into the floating diffusion region 302).

A P + doped region 211, which serves as a source for SF transistor 300, may be formed within region 210. P-type doped regions 214 and 215, which serve as channels for transistor 300, may be formed within regions 212 and 213, respectively. Transistor 300 having a p-type channel may sometimes be referred to as a p-channel JFET. A P + doped region 217 may be formed under and adjacent to regions 214 and 215 to act as a drain for transistor 300. Region 217 may serve as a photo-blocking layer for preventing pixel cross-talk and may sometimes be referred to as a bottom P implant (BTP) layer. The BTP layer 217 may be continuous with the region 205 and may be coupled to ground 312 (e.g., see fig. 2).

When charge from the region 206 within the photodiode 207 is transferred onto the floating diffusion 302 (i.e., regions 210, 212, and 213), a voltage change may occur at the floating diffusion node 302. This voltage change can result in a change in the source voltage of JFET transistor 300 when a constant current (or holes) flows from region 211 to region 216, as indicated by arrows 216.

In the example of fig. 3, the layers 212 and 213 can function to define a channel length Lch for the transistor 300 extending vertically into the substrate 201. The transistor 300 formed vertically within the surface of the substrate 201 may therefore sometimes be referred to as a vertical JFET. If Lch is too short, SF transistor 300 may exhibit reduced gain due to Drain Induced Barrier Lowering (DIBL) effects. Accordingly, it may be desirable to form multiple regions (e.g., regions 212 and 213 between P + regions 211 and 217) so that Lch is greater than a predetermined minimum length. For example, at least three N-type regions, at least four N-type regions, or at least five N-type regions each including a P-type doped channel region can be formed between the source and drain regions of the vertical JFET source follower 300. Optimizing the source follower channel length in this manner does not introduce any undesirable pixel area overhead.

The arrangement as described in connection with fig. 3, where pixel 200 uses a P-doped epitaxial substrate and an N-type PD layer 206 to collect photo-generated electrons, is merely illustrative and does not serve to limit the scope of the invention. In some cases, it may be advantageous to create a pixel that accumulates holes rather than electrons. Thus, the same vertical JFET transistor concepts described in connection with fig. 2 and 3 can also be used for such pixels. The type of doping of the substrate, the type of doping of the source-drain regions and the type of carrier collection should not be construed as limiting aspects of the invention.

For example, the doping types of each region within pixel 200 may be switched so that pixel 200 collects photo-generated holes rather than electrons using an N-doped epitaxial substrate and a P-type PD layer 206. The vertical source follower transistor 300 may be an N-channel JFET with the P + doped BTP layer 217 replaced by an N + bottom implanted (BTN) layer. The floating diffusion region 302 may include P-type doped implants 210, 212, and 213, however, region 211 becomes an N + doped region and regions 214 and 215 become N-type regions. Likewise, the region 218 associated with the reset transistor 209 may also become a P + doped region.

The biasing scheme for this type of pixel 200 would also be reversed. For example, the charge transfer gate 208 and the reset gate 209 may be turned on to negative voltage levels by respective pulsed gate control signals Tx and Rx. The pixel 200 may instead be reset to an adjustable negative power supply level instead of Vddx.

As previously discussed in connection with FIG. 2, it is not necessary to form additional transistors for addressing the pixel 200 (e.g., it is not necessary to use an address transistor that connects the source terminal of the transistor 300 to the column sense line Vout). For example, the pixel reset bias level applied to region 218 may be modulated for pixel addressing purposes. Fig. 4 shows one suitable addressing scheme for pixel 200. During integration, Vddx and Rx are held high to drain any existing overflowing charge from the overexposed photodiode. This technique of discharging the overflowing electric charge is sometimes referred to as shading (blooming) control. At the beginning of the readout operation (at time t 1), the reset signal Rx on the unselected lines is driven low, thereby keeping the floating diffusion nodes associated with the unselected pixels at the nominal positive supply voltage Vdd1 throughout the current readout operation. This effectively ensures that the p-channel JFETs associated with the unselected pixels are off.

At time t2, Vddx may drop from Vdd1 to a reduced positive power supply voltage level Vdd 2. The bias level Vdd1 may be equal to 3.3V, however, Vdd2 may be equal to 2V (as an example). Doing so will cause the reset level of the addressed floating diffusion region to decrease, which turns on the p-channel JFET within the selected pixel. At time t3, the signal Rx associated with the selected line is driven low. When all reset lines are deactivated, all floating diffusions are now floating.

At time t4, the source follower output is sampled to obtain a reference sample level, which is stored in the CDS reference storage node. At time t5, the transfer signal Tx associated with the selected pixel is pulsed high to transfer the photo-generated charge into the floating diffusion region. At time t6, the source follower output is sampled to obtain a signal sample level. The CDS may then subtract the signal sample levels from the stored reference sample levels to obtain respective output signal levels. Subsequently, Vddx and Rx may be driven high so that the overflowing charge from the photodiode may be drained once again to Vdd1 in preparation for another integration or readout cycle.

Having thus described preferred embodiments of a novel pixel for backside illumination or for front side illumination image sensor arrays having small pixel size, high well capacity, low dark current, and a vertical JFET transistor acting as a source follower (which are intended to be illustrative and not limiting), it is noted that principles and various modifications of the invention may be made by persons skilled in the art without departing from the scope and spirit of the invention.

According to an embodiment, an image sensor pixel may be provided, comprising: a photosensitive element; a floating diffusion region; a charge transfer transistor coupled between the photosensitive element and the floating diffusion region; and a vertical Junction Field Effect Transistor (JFET) source follower coupled to the photosensitive element via the charge transfer transistor, wherein the vertical junction field effect transistor source follower has a gate integrated into the floating diffusion region.

According to a further embodiment, the photosensitive element comprises a pinned photodiode configured to collect and store photo-generated electrons.

According to a further embodiment, the charge transfer transistor comprises an n-channel metal oxide semiconductor (NMOS) transistor.

According to a further embodiment, the image sensor pixel further comprises an n-channel metal oxide semiconductor reset transistor.

According to another embodiment, the vertical junction field effect transistor source follower comprises a p-channel junction field effect transistor.

According to a further embodiment, the image sensor pixel further comprises a semiconductor substrate within which the image sensor pixel is formed, wherein the floating diffusion region comprises at least two N-type doped regions formed at respective depths within the semiconductor substrate.

According to a further embodiment, the vertical junction field effect transistor source follower further comprises a channel formed by at least two P-type doped regions implanted within the at least two N-type doped regions associated with the floating diffusion region, respectively.

According to a further embodiment, the vertical junction field effect transistor source follower further comprises a drain formed from a P + doped layer implanted below the at least two N-type doped regions associated with the floating diffusion region, and the P + doped layer is coupled to a ground power supply terminal.

According to a further embodiment, the photosensitive element comprises a pinned photodiode configured to collect and store photo-generated holes.

According to a further embodiment, the charge transfer transistor comprises a p-channel metal oxide semiconductor (PMOS) transistor.

According to a further embodiment, the image sensor pixel further comprises a p-channel metal oxide semiconductor reset transistor.

According to another embodiment, the vertical junction field effect transistor source follower comprises an n-channel junction field effect transistor.

According to a further embodiment, the image sensor pixel further comprises a semiconductor substrate within which the image sensor pixel is formed, wherein the floating diffusion region comprises at least two P-type doped regions formed at respective depths within the semiconductor substrate.

According to a further embodiment, the vertical junction field effect transistor source follower further comprises a channel formed by at least two N-type doped regions implanted within at least two P-type doped regions associated with the floating diffusion region, respectively.

According to a further embodiment, the vertical junction field effect transistor source follower further comprises a drain formed from an N + doped layer implanted under at least two P-type doped regions associated with the floating diffusion region, and the N + doped layer is coupled to a positive power terminal.

According to an embodiment, an image sensor may be provided, comprising an array of image sensor pixels, wherein each image sensor pixel in the array of image sensor pixels comprises: a photosensitive element; a charge transfer transistor coupled to the photosensitive element; and a vertical Junction Field Effect Transistor (JFET) source follower coupled to the photosensitive element via the charge transfer transistor.

According to a further embodiment, wherein each image sensor pixel in the array of image sensor pixels further comprises a floating diffusion region, wherein the charge transfer transistor is coupled between the floating diffusion region and the photosensitive element, and wherein the vertical junction field effect transistor source follower has a gate integrated within the floating diffusion region.

According to a further embodiment, wherein each image sensor pixel within the array of image sensor pixels further comprises a reset transistor coupled between an adjustable power supply terminal and a floating diffusion region, wherein the reset transistor and charge transfer transistor comprise n-channel metal oxide semiconductor (NMOS) transistors.

According to an embodiment, a method for operating an image sensor pixel may be provided, the method comprising: collecting photo-generated charges with a photosensor; transferring the collected charge to a floating diffusion region with a charge transfer transistor; and converting the collected charge at the floating diffusion region to a corresponding voltage signal with a vertical Junction Field Effect Transistor (JFET) source follower.

According to a further embodiment, the method further comprises resetting the floating diffusion node to a reduced voltage level with a reset transistor for selectively addressing image sensor pixels for readout.

According to a further embodiment, the charge transfer transistor and the reset transistor comprise Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).

The foregoing merely illustrates the principles of the invention, which may be practiced in other embodiments. The above embodiments may be implemented individually or in any combination.

Claims (15)

1. An image sensor pixel, comprising:

a semiconductor substrate;

a photosensitive element formed within the semiconductor substrate;

a floating diffusion region comprising at least two N-type doped regions formed at respective different depths within the semiconductor substrate;

a charge transfer transistor coupled between the photosensitive element and the floating diffusion region; and

a vertical Junction Field Effect Transistor (JFET) source follower coupled to the photosensitive element via the charge transfer transistor, wherein the vertical junction field effect transistor source follower has a gate integrated into the floating diffusion region, and wherein the vertical junction field effect transistor source follower further includes a channel formed by at least two P-type doped regions implanted within the at least two N-type doped regions associated with the floating diffusion region, respectively.

2. The image sensor pixel of claim 1, wherein the photosensitive element comprises a pinned photodiode configured to collect and store photo-generated electrons.

3. The image sensor pixel of claim 2, wherein the charge transfer transistor comprises an n-channel metal oxide semiconductor (NMOS) transistor.

4. The image sensor pixel of claim 3, further comprising:

an n-channel metal oxide semiconductor reset transistor.

5. The image sensor pixel of claim 1, wherein the vertical junction field effect transistor source follower further comprises a drain formed from a P + doped layer implanted below the at least two N-type doped regions associated with the floating diffusion region, and wherein the P + doped layer is coupled to a ground power terminal.

6. The image sensor pixel of claim 1, wherein the charge transfer transistor comprises a p-channel metal oxide semiconductor (PMOS) transistor.

7. The image sensor pixel of claim 6, further comprising:

a p-channel metal oxide semiconductor reset transistor.

8. An image sensor, comprising:

an image sensor pixel array, wherein each image sensor pixel in the image sensor pixel array comprises:

a semiconductor substrate;

a photosensitive element formed within the semiconductor substrate;

a floating diffusion region comprising at least two P-type doped regions formed at respective different depths within the semiconductor substrate; a charge transfer transistor coupled between the photosensitive element and the floating diffusion region; and

a vertical Junction Field Effect Transistor (JFET) source follower coupled to the photosensitive element via the charge transfer transistor, wherein the vertical junction field effect transistor source follower has a gate integrated into the floating diffusion region, and wherein the vertical junction field effect transistor source follower further comprises a channel formed from at least two N-type doped regions implanted within the at least two P-type doped regions associated with the floating diffusion region, respectively.

9. The image sensor of claim 8, wherein each image sensor pixel within the array of image sensor pixels further comprises:

a reset transistor coupled between an adjustable power supply terminal and the floating diffusion region, wherein the reset transistor and the charge transfer transistor comprise n-channel metal oxide semiconductor (NMOS) transistors.

10. The image sensor pixel of claim 8, wherein the photosensitive element comprises a pinned photodiode configured to collect and store photo-generated holes.

11. The image sensor pixel of claim 8, wherein the charge transfer transistor comprises an n-channel metal oxide semiconductor (NMOS) transistor.

12. The image sensor pixel of claim 9, wherein the reset transistor comprises an n-channel metal oxide semiconductor (NMOS) transistor.

13. The image sensor pixel of claim 8, wherein the vertical junction field effect transistor source follower further comprises a drain formed from an N + doped layer implanted below the at least two P-type doped regions associated with the floating diffusion region, and wherein the N + doped layer is coupled to a power supply terminal.

14. A method for operating an image sensor pixel, the method comprising:

collecting photo-generated charges with a photosensor;

transferring the collected charge to a floating diffusion region with a charge transfer transistor; and

converting the collected charge at the floating diffusion region into a respective voltage signal with a vertical Junction Field Effect Transistor (JFET) source follower;

deselecting a portion of the image sensor with a reset transistor by resetting a floating diffusion node to a first voltage level; and

selecting, with the reset transistor, another portion of the image sensor for readout by resetting the floating diffusion node to a second voltage level that is less than the first voltage level.

15. The method of claim 14, wherein the charge transfer transistor and the reset transistor comprise Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).