HK1186284A - Dual function compatible non-volatile memory device - Google Patents

Description

Dual function compatible non-volatile memory device

The present application is a divisional application entitled "dual-function compatible non-volatile memory device" having application number 200880114400.8 and application date 2008, 12/11.

Cross Reference to Related Applications

This application claims priority to U.S. provisional patent application No.61/015366, filed on 20.12.2007, the contents of which are incorporated herein by reference in their entirety.

Technical Field

The present invention relates generally to non-volatile memories, and more particularly to flash memory systems.

Background

The disclosed technology relates to a nonvolatile semiconductor memory device capable of multi-mode operation and multi-connection mode operation. The nonvolatile semiconductor memory device capable of both multi-mode operation and multi-connection mode operation is suitable for use in a system having a memory controller in communication with the nonvolatile semiconductor memory device.

Electronic devices use semiconductor devices such as volatile and non-volatile memory devices. These memory devices may include Random Access Memory (RAM) and flash memory (e.g., NAND flash devices, NOR flash devices) for storing data or information.

Memory systems on system boards are designed to introduce higher density and faster operation due to the needs of applications running on the system board. Two design techniques that can introduce higher density memory systems onto the system board include: 1) memory devices configured in a serial connection such as a cascade; and 2) memory devices configured in parallel interconnects such as multi-dropping. These design techniques may be used to overcome the density issues that determine the cost and operating efficiency of memory swapping between a hard disk and a memory system.

Disclosure of Invention

According to a first aspect, a method for setting an operating mode of a memory device is provided. The method comprises the following steps: powering up the memory device; providing a response in response to a voltage of the port after the memory device has completed powering up; and in response to the response, setting an operating mode of circuitry of the memory device. In a first embodiment, the setting step includes: based on the response, a signal corresponding to the operating mode is selected for use by circuitry in the memory device. The step of selecting comprises: detecting the absence of the voltage to provide a voltage response as the response, the voltage response corresponding to a complement of the response in the event that the absence of the voltage is not detected. The setting step further includes: the operating mode of the circuit is set to another operating mode in response to the complement of the response. The memory device has at least one other port and the step of setting further comprises: receiving a signal containing information at the at least one other port; and in response to one of the response and the complement of the response, configure the at least one other port to receive the information contained in the signal, the circuitry operating in response to the information. The receiving step includes: receiving the signal containing information at least one other port, the information corresponding to at least one of control information and data information.

In another embodiment of this aspect, powering up the memory device includes detecting whether a supply voltage reaches a predetermined level, where the voltage is the supply voltage. The voltage of the port is detected when the power supply voltage reaches a predetermined level and the port comprises an existing port used in the first mode of operation and not used in the second mode of operation. In this embodiment, the low logic level of the existing port is latched when the supply voltage has reached a predetermined level. After latching the low logic level, the existing port may switch between high and low logic levels. In yet another embodiment of this aspect, the existing port may switch between high and low logic levels after latching a low logic level. The step of setting includes driving the mode signal to a first logic level when the voltage is detected at the port and driving the mode signal to a second logic level when the voltage is not detected at the port. The setting step includes coupling the control and data ports of the memory device to the asynchronous circuitry in response to a first logic level of a mode signal and coupling the control and data ports of the memory device to the synchronous circuitry in response to a second logic level of the mode signal. Optionally, the supply voltage is disconnected from the synchronous circuit in response to a first logic level of the mode signal and the supply voltage is disconnected from the asynchronous circuit in response to a second logic level of the mode signal. In this embodiment, the asynchronous circuit includes an asynchronous command decoder for providing a decoded asynchronous command signal, and a synchronous command decoder for providing a decoded synchronous command signal. The setting step further includes: one of the decoded asynchronous command signal and the decoded synchronous command signal is passed to control logic in response to the mode signal. The decoded asynchronous command signal and the decoded synchronous command signal are identical to each other.

In a second aspect, a memory device configurable to operate in a first mode and a second mode is provided. The memory device includes a port, an interface and control circuit, and a mode detector. The port receives one of a first allocation of functions corresponding to a first mode and a second allocation of functions corresponding to a second mode. The interface and control circuitry receives a command from at least one of the ports and is configurable for decoding the command within one of a first mode and a second mode. The command is decoded to control the core circuitry of the memory device. A mode detector is connected to a selected one of the ports for configuring the interface and control circuitry to decode the command in a first mode when a voltage source is detected and to decode the command in a second mode when a voltage source is not detected. In this embodiment, the interface and control circuit includes: synchronous circuits, asynchronous circuits, control logic, and selectors. A synchronization circuit is coupled to the port for receiving the command when the voltage source is not detected by the pattern detector and for generating a decoded synchronization command signal. An asynchronous circuit is coupled to the port for receiving the command when the mode detector detects a voltage source and for generating a decoded asynchronous command signal. The control logic generates the same internal control signals in response to the decoded synchronous command signal and the decoded asynchronous command signal. The selector selectively passes one of the decoded asynchronous command signal and the decoded synchronous command signal to the selector of the control logic in response to the detected state of the voltage source.

In this embodiment, the mode detector includes a voltage detector and mode logic. The voltage detector provides a status signal when the voltage source has reached a predetermined level. Mode logic is coupled to the selected port for driving the mode signal from the first logic level to the second logic level in response to the status signal when the selected port is biased to a voltage level different than the voltage source. The synchronous circuit includes a synchronous command decoder and a synchronous buffer coupled to each port, and the asynchronous circuit includes an asynchronous buffer coupled to the asynchronous command decoder and to each port. Each port in the first functional allocation and the second functional allocation having the same type has a common buffer that serves as the synchronous buffer and the asynchronous buffer, where the type may be one of an input type and an output type. The interface and control circuit further includes a signal path switch for selectively coupling each port to the synchronous command decoder through the synchronous buffer in response to a first logic level of the mode signal and for selectively coupling each port to the asynchronous command decoder through the asynchronous buffer in response to a second logic level of the mode signal. The interface and control circuit further comprises: a first power switch and a second power switch. The first power switch decouples the voltage source from the synchronous circuit in response to the second logic level of the mode signal, and the second power switch decouples the voltage source from the asynchronous circuit in response to the first logic level of the mode signal. In another alternative embodiment, the mode logic includes a latch for maintaining the second logic level of the mode signal in response to the status signal. The selected port is a functional port used during normal operation in one of the first mode and the second mode. The selected port is a dedicated port that is not used during normal operation in both the first mode and the second mode.

In a third aspect, a memory system is provided that includes a memory controller and a plurality of memory devices. The memory controller provides a control signal having a first signal function assignment and a second signal function assignment. Each of the plurality of memory devices is configured to receive one of a first signal function assignment and a second signal function assignment responsive to the port being biased to a supply voltage during a power-up sequence. Each of the plurality of memory devices is configured to receive the other of the first signal function assignment and the second signal function assignment when the port is biased to the other supply voltage during a power-up sequence. There are several further embodiments of the third aspect. The port is part of the first signal function assignment and is not used in a second function assignment. The port is unused in both the first signal function assignment and the second signal function assignment. The port is physically connected to a supply voltage. The port is statically held at the supply voltage by the circuit.

Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.

Drawings

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1A is a block diagram of a non-volatile memory system;

FIG. 1B is a schematic diagram of the flash memory device used in FIG. 1A;

FIG. 2A is a block diagram of a serial memory system;

FIG. 2B is a schematic diagram of the serial interface flash memory device used in FIG. 2A;

FIG. 3 is a block diagram of an asynchronous memory device;

FIG. 4A is a block diagram of a synchronous serial memory;

FIG. 4B is a block diagram of the input serial-to-parallel register block of FIG. 4A;

FIG. 5 is a block diagram of a dual function memory device, according to an embodiment of the invention;

FIG. 6A is a schematic diagram showing an example of the interconnection of a dual function memory device with a synchronous flash memory controller;

FIG. 6B is a schematic diagram illustrating another example of an interconnection of a dual function memory device with an asynchronous flash memory controller;

FIG. 7 is a block diagram of an embodiment of the mode detector and interface and control circuit blocks shown in FIG. 5;

FIG. 8 is an example of a circuit principle of the pattern detector of FIG. 7;

FIG. 9A is a timing diagram illustrating detection of an asynchronous mode of operation by the mode detector of FIG. 7;

FIG. 9B is a timing diagram illustrating the detection of a synchronous mode of operation by the mode detector of FIG. 7;

FIG. 10 is a block diagram of another embodiment of the mode detector and interface and control circuit blocks shown in FIG. 5;

FIG. 11 is a block diagram of the arrangement of signal paths between a controller and a command decoder in the interface and control circuit blocks shown in the embodiments of FIGS. 7 and 10;

FIG. 12 is a circuit schematic of a buffer circuit for a clock port CK of a dual function memory device;

FIG. 13 is a circuit schematic of a buffer for an input data port Dn and an output data port Qn in a dual function memory device;

FIG. 14 is a flow chart illustrating a method for operating a memory system having a dual function memory device.

Detailed Description

In general, the present invention provides a dual function memory device architecture that is compatible with two different operating modes, such as an asynchronous mode of operation and a synchronous mode of operation.

Flash memory is a common type of non-volatile memory that is widely used as mass storage for consumer electronic devices such as digital cameras and portable digital music players. The density of currently available flash memory devices comprising 2 stacked dies (die) can reach 32 gbits (4 GB), which is suitable for use in popular USB flash drives since the size of one flash device is typically very small.

The advent of eight million pixel digital cameras and portable digital entertainment devices with music and video capabilities has fueled the demand for ultra-high capacity for storing large amounts of data that a single flash memory device cannot meet. Therefore, multiple flash memory devices are combined together in a system to effectively increase the available storage capacity. For example, such applications may require a flash memory density of 20 GB.

FIG. 1A is a block diagram of a non-volatile memory system 10 integrated with a host system 12. The system 10 includes a memory controller 14 in communication with a host system 12 and a plurality of non-volatile memory devices 16-1, 16-2, 16-3, and 16-4. For example, the non-volatile memory devices 16-1 through 16-4 may be asynchronous flash memory devices. The host system 12 includes a processing device such as a microcontroller, microprocessor, or computer system. The system 10 of FIG. 1A is organized to include one channel 18, with memory devices 16-1 through 16-4 connected in parallel to the channel 18. It should be understood by one of ordinary skill in the art that the system 10 may have more or less than four memory devices connected thereto. In the presently illustrated embodiment, memory devices 16-1 through 16-4 are asynchronous and connected in parallel with each other.

The channel 18 includes a common set of buses that include data and control lines connected to all of its corresponding memory devices. Each memory device may be enabled or disabled by a respective chip select (enable) signal CE #1, CE #2, CE #3, and CE #4 provided by memory controller 14. In the present and following embodiments, "#" indicates that the signal is an active low logic level signal. In this scheme, one of the chip select signals is typically selected at a time to enable one of the corresponding non-volatile memory devices 16-1 through 16-4. The memory controller 14 is responsible for issuing commands and data to selected memory devices via the channel 18 in response to operation of the host system 12. The read data output from the memory device is transferred back to the memory controller 14 and the host system 12 via the channel 18. The system 10 is generally considered to include a multi-drop bus in which the memory devices 16-1 through 16-4 are connected in parallel for a channel 18.

FIG. 1B is a block diagram of one of the flash memory devices 16-1 through 16-4 that may be used in the memory system of FIG. 1A. The flash memory device includes a plurality of input and output ports including, for example, a power pin, a control pin, and a data pin. The power supply pins include VCC and VSS for applying power to all circuits of the flash memory device. Additional power pins are provided for application only to the input and output buffers, as is known in the art. The list provided in table 1 below includes control and data pins, corresponding description, definitions and example logic states. Note that these pins are one example physical representation of a port used to interconnect signals or voltages of the packaged device to the board. These ports may include other types of connections, such as terminals and contact points for embedded and system-in-package (SIP) systems.

TABLE 1

Except for the chip enable CE #, all other pins are coupled to respective global lines that make up lane 18. A respective slice enable signal is provided to each flash memory device by memory controller 14.

A problem with the memory system 10 of fig. 1A is that each non-volatile memory device has a dedicated data interface for receiving and providing data. In the example of FIG. 1A, this is a parallel data interface common in asynchronous flash memory devices. It is known that standard parallel data interfaces providing multiple bits of data in parallel are subject to well-known communication degradation effects such as crosstalk, signal skew and signal attenuation which would impair signal quality if, for example, they were operated above their nominal operating frequency.

To increase data throughput (throughput), a memory device having a serial data interface has been disclosed in commonly owned U.S. patent publication No.20070076479, which receives and provides data serially at a frequency of, for example, 200 MHz. The memory device described in U.S. patent publication No.20070076479 may be used in a system of memory devices connected in series with each other, as described in a commonly owned U.S. provisional patent application filed on 16/2/2007, the contents of which are incorporated herein by reference in their entirety.

Fig. 2A is a block diagram illustrating the conceptual principle of a serial memory system. In fig. 2A, a memory system 20 of a serial ring topology includes a memory controller 22 having at least one output port Sout and an input port Sin, and memory devices 24, 26, 28, and 30 connected in series. The memory device may be, for example, a serial interface flash memory device. Although not shown in fig. 2A, each memory device has a Sin input port and a Sout output port. The input and output ports include one or more physical pins or connections that couple the memory device to the system of which the memory device is a part. In one embodiment, the memory device may be a flash memory device. Alternatively, the memory device may be a DRAM, SRAM, or any other type of memory device as long as it has an input/output interface compatible with a particular command structure for executing commands or for passing commands and data through to the next memory device. The current example of fig. 2A includes 4 memory devices, but alternative embodiments may include a single memory device, or any suitable number of memory devices. Thus, if memory device 24 is the first device of system 20 because it is connected to Sout, and memory device 30 is the nth or last device because it is connected to Sin, where N is an integer greater than zero. Memory devices 26 through 28 are memory devices that are connected in series intermediate between the first and last memory devices. In the example of FIG. 2A, memory devices 26 through 28 are synchronized and serially connected to each other with memory controller 22.

FIG. 2B is a schematic diagram of a serial interface flash memory device (e.g., 24-28) that may be used in the memory system of FIG. 2A. The serial interface flash memory device of this example includes a power pin, a control pin, and a data pin. The power supply pins include VCC and VSS for applying power to all circuits of the flash memory device. Additional power pins may be provided for application only to the input and output buffers, as is known in the art. The list provided in table 2 below includes control and data pins, corresponding descriptions, and example logic states.

TABLE 2

In the example configuration shown in FIG. 2A, all signals are passed from memory controller 22 to each memory device in series, except for CE # which is provided to all memory devices in parallel.

Further details of the serial memory system of FIG. 2 are disclosed in commonly owned U.S. patent application No.12/032249, filed on 15/2/2008, which describes a serial memory system in which each memory device receives a parallel clock signal, and a serial memory system in which each memory device receives a source synchronous clock signal.

Both the asynchronous flash memory device of FIG. 1B and the recently introduced serial interface flash memory device of FIG. 2B are generally available, which allows memory system manufacturers to offer both types of memory systems. However, this results in higher costs to the memory system manufacturer since two different types of memory devices must be provided and purchased. One of ordinary skill in the art will appreciate that when purchased in large quantities, the unit price of the memory device may be reduced, thereby minimizing the cost of the memory system through the large quantities of purchases. Thus, when a manufacturer can provide two types of memory systems, there is a risk that: the market demand for one memory device is so high that the market demand for another memory device is reduced or even no longer needed. This may render the purchased memory device unusable.

As shown in fig. 1B and 2B, the functional pin assignments or definitions of the asynchronous and serial interface flash memory devices are substantially different from each other and, therefore, are incompatible with each other. This means that the serial interface flash memory device of fig. 2B cannot be used in a multi-drop memory system, nor the asynchronous flash memory device of the corresponding fig. 1B can be used in a serial ring topology memory system.

In accordance with the present invention, a dual function memory device is provided that can be used in two different operating modes, such as a synchronous mode and an asynchronous mode. More specifically, dual function memory devices are compatible with both asynchronous and synchronous functions or operations. For the purpose of illustrating the differences between the asynchronous and synchronous modes of operation, the following embodiments illustrate an asynchronous flash memory device connected in parallel with a corresponding memory controller, and a synchronous flash memory device for serial connection with a corresponding memory controller. The architecture and circuit embodiments shown herein are applicable to other memory devices without limiting parallel or serial interconnection to another device.

Embodiments of the present invention provide a dual function memory device architecture compatible with asynchronous operation as well as synchronous serial operation. A dual function memory device architecture includes a set of ports having two different pin distribution definitions or functions. Coupled between these ports and the core circuitry of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal path includes shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a converter network, and a pattern detector. The mode detector determines an operation mode of the dual function memory device according to one port and provides an appropriate switching selection signal. The converter network transmits the input or output signal through an asynchronous or synchronous circuit in response to a conversion selection signal. A suitable command decoder interprets the input signals and provides the necessary signals for the common control logic to initiate the corresponding operation.

The differences and similarities between typical asynchronous memory devices and synchronous memory devices are described below. FIG. 3 is a block diagram of an asynchronous memory device, while FIG. 4 is a block diagram of a synchronous serial memory device.

The asynchronous flash memory device of fig. 3 includes two main circuit blocks. The first main circuit block is an interface and control circuit block including I/O buffers 42, 44 and 46, registers 48, 50 and 52 and control circuit 54. Those skilled in the art will understand the function of the circuitry of the interface and control circuit blocks and will not show much detail in order to simplify the schematic. For example, the circuitry interconnecting the circuit blocks merely shows the functional relationship between the connected blocks and does not describe in detail the particular signals used. Output buffer 42 drives the R/B # output port, control buffer 44 includes input buffers each connected to a corresponding input control port, and data buffer 46 includes a bi-directional buffer for receiving and driving data into a corresponding I/O port. In this example, the control buffers 44 include input buffers for the CE #, CLE, ALE, WE #, RE #, and WP # input control ports. In this example there are eight data I/O ports and thus eight bidirectional buffers. Asynchronous input buffer and output buffer circuits are well known in the art and need not be described in further detail.

To perform operations such as erase, program, and read in the asynchronous flash memory device 40, commands are provided via the data I/O port. Based on the operation performed, the command may include an operation code (OP code), an address signal, and data corresponding to the particular operation. Note that since the address and write (program) data can be more than 8 bits in length, multiple input iterations or loops are required before all address and write data bits are latched in the correct registers. OP code data is latched in the command register 48 and address information for read and program operations is latched in the address register 50. The OP code data is provided to a control circuit 54, which control circuit 54 includes logic for decoding the OP code, such as a command decoder or interpreter. The control circuit 54 also includes control logic that generates internal control signals with the required timing for operating the circuitry of the interface and control circuit block and the circuitry of the second main circuit block.

The second main circuit block is a block including a high voltage generator 56, a row pre-decoder 58, a row decoder 60, a column pre-decoder 62, a column decoder 64, a page buffer 66 and a memory array 68. These circuits are well known to those familiar with flash memory. The high voltage generator 56 may be used for program and erase operations. The following circuit description relates to a read operation. The row pre-decoder 58 receives a row address from the address register 50 and the column pre-decoder 62 receives a column address from the address register 50. The pre-decoded row signals are used by row decoder 60 to drive word lines of memory array 68 for accessing a page of data. Data held in memory cells connected to the selected word line is sensed via the bit lines and held in the page buffer 66. The pre-decoded column signals are used by column decoder 64 to select a set of 8-bit data from page buffer 66 for output to data buffer 46. It should be noted that the sequence and timing of the asserted control signals are derived from control circuit 54 in response to the received OP code.

Similarly, the synchronous serial memory 100 of FIG. 4A includes two main circuit blocks. The first main circuit block is an interface and control circuit block that includes a control interface 102, a serial interface 104, an input serial-to-parallel register block 106, and an output parallel-to-serial register block 108. The control interface 102 includes an input buffer circuit, and generates an internal chip select signal chip _ sel, an internal clock signal sclki, and an internal reset signal reset corresponding to CS #, SCLK, and RST #, respectively. While the signal chip _ sel is primarily used by the serial interface 104, reset and sclki are used by multiple circuits throughout the memory 100. The second main circuit block is a core circuit including a memory array 110, sense amplifier and page buffer circuits 112, a row decoder 114, a column decoder 116, and a high voltage generator 118. In general, the circuitry of the core circuits may be the same as that shown in asynchronous flash memory device 40 of FIG. 3, meaning that they are responsive to the same address, data, and control signals received from the interface and control circuit blocks of synchronous serial memory 100. The main difference between the asynchronous flash memory device 40 and the synchronous serial memory 100 is how these control signals are received and provided to the core circuitry. Although the interface and control circuit blocks of asynchronous flash memory device 40 of fig. 3 are well known, there are significant differences in the identically named circuit blocks in synchronous serial memory 100.

The serial interface 104 includes input buffers for receiving serial input data D [ n ], command strobe input CSI, and data strobe input DSI, and output buffers for providing serial output data Q [ n ], command strobe output CSO (response to CSI), and data strobe output DSO (response to DSI). These signals are received and provided at corresponding input/output ports, which as previously described may be physical pins, terminals, or connectors. The input and output buffers of the serial interface 104 may be implemented using circuitry known in the art for buffering input signals and for driving output signals. Note, however, that the input buffer performs functions other than passing the received data to the input serial-to-parallel register block 106. More specifically, each input buffer of the serial interface 104 may pass its received input signal to a corresponding output buffer to provide a fully functional data stream. For example, an input buffer for CSI passes the received CSI signal to an output buffer for CSO. Similarly, an input buffer for D [ n ] passes received data signals to an output buffer for Q [ n ], and an input buffer for DSI passes received DSI signals to an output buffer for DSO. This interface allows multiple memory devices with compatible serial interfaces to be serially connected to each other as shown in the memory system of FIG. 2A.

It should be clear to those of ordinary skill in the art that the primary difference between the memory device 100 and the memory device 40 of FIG. 3 is that all command, data, and address information is received via a serial bit stream in the memory device 100. A serial input D [ n ] receives the serial data stream, where there may be "n" serial inputs and a corresponding number of "n" serial outputs to achieve higher throughput loading and data output. Thus, the integer n may be an integer greater than zero, but for the purpose of simplifying the description of the present invention, it is assumed that n = 1.

The serial interface 104 provides buffered serial input data SER _ IN and receives serial output data SER _ OUT from the output parallel to serial register block 108. The input serial-to-parallel register block 106 receives SER _ IN and converts it to a set of parallel signals PAR _ IN. As described in detail below, the input serial-to-parallel register block 106 includes serial-to-parallel registers for converting OP code command, data, and address bit information into a parallel format, and command decode logic for generating internal control signals required for controlling the core logic. Thus, PAR _ IN includes input data DIN, column addresses C _ ADDR, row addresses R _ ADDR, and other control signals (not shown) for activating the core circuitry IN a particular sequence and/or timing. The output parallel-to-serial register block 108 receives a set of parallel output data DOUT and converts it to serial output data SER _ OUT, which is then provided as a data stream Q n through the serial interface 104. The details of the input serial-to-parallel register block 106 shown IN fig. 4B are used to illustrate how the SER _ IN bit stream is converted to parallel address, command and data signals.

Fig. 4B is a schematic diagram illustrating an example configuration of the input serial-to-parallel register block 106 shown in fig. 4A. As mentioned before, the circuit receives an input data stream SER _ IN and converts SER _ IN to parallel data sets. More specifically, the SER _ IN may be converted to provide a command CMD, a column address C _ ADD, a row address R _ ADD, and input DATA _ IN. The input serial-to-parallel register block 106 includes a command register 130, a temporary register 132, and a serial data register 134. Since the data structure of the serial input data stream is predetermined, a certain number of bits of the input data stream are allocated into the aforementioned register. For example, bits corresponding to a command may be stored in the command register 130, bits corresponding to a row and column address may be stored in the temporary register 132, and bits corresponding to input data may be stored in the serial data register 134. The allocation of bits of the serial input data stream may also be controlled by other circuits in a manner unrelated to embodiments of the present invention.

The input serial-to-parallel register block 106 includes a command interpreter 136 that receives command signals from the command register 130 and generates decoded commands CMD. The command interpreter 136 is a standard circuit implemented using interconnected logic gates or firmware that can decode received commands. Although not shown in fig. 4A or 4B, the decoded command CMD is received by control logic responsible for enabling certain circuits of the core circuit in a certain sequence and/or with a certain timing depending on the operation performed.

The conversion controller 138 receives one or more signals from the CMD to control a simple conversion circuit 140. Translation circuit 140 receives all of the data held in temporary registers 132 in parallel and will load the data into one or both of column address register 142 and row/bank register 144 in accordance with the decoded command CMD. This decode operation is preferably performed because the temporary registers do not always include column and row/bank address data. For example, a serial input data stream with a block erase command would use only the row address, in which case only the relevant bits saved in the temporary register 132 would be loaded into the row/bank register 144. The data register 146 receives the converted parallel data directly from the serial data register 134 under the control of the command interpreter 136. Note that all of the circuitry shown in fig. 4B may be controlled by command interpreter 136, but these signals are not shown in order to maintain clarity of the schematic. Column address register 142 provides parallel signals C _ ADDR, row/bank address register 144 provides parallel signals R _ ADDR, and data register 146 provides parallel signals DIN for programming operations. CMD, C _ ADDR, R _ ADDR, and DIN are brought together to form a parallel signal set PAR _ IN. Since the desired bit width for a particular design or architecture is a design parameter that can be customized or tailored, the bit width for each of the parallel signals has not been specified.

As can be seen from the previous discussion, the interface and control circuit blocks of the asynchronous flash memory 40 and the synchronous serial memory 100 are inherently different from each other. This difference is due to the fact that the input control signals received at the pins of the two memory devices are different, each set of signals following a particular signaling protocol in order to properly operate the respective memory device. However, since both memory devices use the same core circuitry, the resulting signals used to control the core circuitry of each memory device are functionally identical. Thus, a dual function memory device may be formed based on an understanding of the input and output signal path differences between the core circuitry and the ports of each memory device.

FIG. 5 is an architecture schematic of a dual function memory device according to an embodiment of the invention. Dual function memory device 200 selectively operates in one of two modes, where each mode is responsive to a particular set of external signals. In the example of the presently described embodiment, one mode is an asynchronous mode corresponding to operation of the asynchronous flash memory device 40, and the second mode is a synchronous serial mode corresponding to operation of the synchronous serial memory 100.

The dual function memory device 200 has a plurality of dedicated input, output and bidirectional I/O ports 202, only one of which is shown to represent a collective (collective) set of pins formed in the packaging of the memory. A particular single port 202 is designed to receive two different signals, meaning, for example, that a physical package of dual function memory device 200 includes a set of pins that can be coupled to two different sets of signals originating from a memory controller. Thus, the memory device 200 includes at least all ports corresponding to a class of memory devices having a greater number of ports. The dual function memory device 200 includes three main circuit blocks, the first of which is a core circuit 204, the second of which is an interface and control circuit block 206, and the third of which is a mode detector 208. The core circuitry 204 may be, for example, the same as the core circuitry shown in fig. 3 and 4A. The interface and control circuit block 206 includes two signal paths between the core circuitry 204 and the port 202, where only one signal path is active for the selected mode of operation. The mode detector 208 detects the voltage level of one of the ports 202 and enables a signal path corresponding to the set of external signals applied to the port 202.

In the present embodiment, the interface and control circuit block 206 includes an interface circuit 210, a selector 212, and control logic 214. Interface circuit 210 includes a synchronous circuit 218 and an asynchronous circuit 220 selectively coupled to port 202, each corresponding to a synchronous signal path and an asynchronous signal path. Generally, the synchronous serial signal path includes a synchronization circuit 218 and a selector 212. The synchronization circuit 218 includes input/output buffers, data registers, address registers, and any other circuitry necessary to condition (condition) input or output signals provided to or received from the core circuitry 204. For example, the synchronization circuit 218 may include all of the elements of the input serial-to-parallel register block 106 of FIG. 4A, including the synchronous command interpreter.

The asynchronous signal path includes an asynchronous circuit 220 and a selector 212. Asynchronous circuit 220 may include buffers 42, 44, 46 and registers 48, 50, 52 shown in fig. 3 for conditioning input or output signals provided to or received from core circuitry 204. Each of synchronous circuit 218 and asynchronous circuit 220 provides decoded command signals and core circuitry signals, and may receive read data from the memory array. The decoded command signal S _ DEC is provided by a command decoder of the synchronous circuit 218, and the decoded command signal a _ DEC is provided by a command decoder of the asynchronous circuit 220. Both S _ DEC and a _ DEC are provided to selector 212, and selector 212 passes only one to control logic 214. Control logic 214 generates signals necessary to operate core circuitry 204 for all operations, including read, program, and erase operations. Core circuitry signals include input data, memory address information, or data to be written to the memory array, as well as other control signals used by the core circuitry 204. These signals are collectively shown as signals DATA/CTRL in FIG. 5. These signals are not used by control logic and are therefore provided directly to core circuitry 204. DATA/CTRL also includes read DATA from the memory array that is provided to the output buffer of synchronous circuit 218 or asynchronous circuit 220.

The switching signal MODE is provided by a MODE detector 208 which monitors one of the ports 202. The signal MODE is provided to the interface circuit 210 for selectively transmitting an external input signal or an output signal through the synchronous circuit 218 or the asynchronous circuit 220. As described below, some ports 202 that receive two different external signals share the same circuitry, and the buffered signals are then transmitted over either an asynchronous or synchronous signal path in response to MODE. Other ports 202 have different dedicated circuitry in order to accommodate different external signals, so that port 202 is directly coupled to a selected buffer circuit in response to MODE. The shared buffer circuit thus serves as both a synchronous and an asynchronous buffer circuit.

Note that fig. 5 is intended to illustrate a general signal path for the synchronous serial signal path and the asynchronous signal path. It should be appreciated that some of the signals provided by synchronous circuitry 218 and asynchronous circuitry 220 are passed directly to selector 212 or may be passed directly to core circuitry 204, such as data and address signals, or any other signals not required by the corresponding control logic for generating other downstream signals. Accordingly, the read data provided by the core circuitry 204 may be passed directly to or via the selector 212 to the circuitry 218 and 220. Both the synchronous serial signal path and the asynchronous signal path may include unidirectional and bidirectional signals. The unidirectional signals include address signals and control signals provided from the port 202 to control logic 214, which control logic 214 is used to control the core circuitry 204. The bidirectional signals include data lines or data buses carrying read data and program data.

MODE detector 208 provides a switching signal MODE that is used by interface circuit 210 to control the switching device, which sends a signal through either synchronous circuit 218 or asynchronous circuit 220. MODE detector 208 statically sets MODE to a particular logic level in response to a static voltage level detected on one of ports 202. More specifically, the mode detector 208 monitors the voltage level of a particular port 202 during a power-up sequence and determines whether the particular port is electrically biased to a particular voltage level, such as a voltage source level. If a particular port 202 is biased to a particular voltage source level, MODE is set to a particular logic level. Otherwise, MODE is set to a different logic level. Thus, the voltage level applied to a particular port 202 corresponds to the set of external signals applied to the other ports 202.

FIG. 6A is a schematic diagram illustrating the interconnections of a flash memory controller with the dual-function memory device embodiment of FIG. 5 in an example memory system 300. In FIG. 6A, a memory system 300 includes a synchronous flash memory controller 302 connected to a dual function memory device 304, where the dual function memory device 304 may have the architecture shown in FIG. 5. The dual function memory device 304 includes by default the input/output ports previously listed in table 2. The VCC and VSS power supplies are physically connected to the synchronous flash memory controller 302 and the corresponding VCC and VSS ports of the dual function memory device 304. In the example of FIG. 6A, the RST # port is monitored by the pattern detector 208 of FIG. 5, which is connected to the corresponding RST # port of the synchronous flash memory controller 302. The RST # port of the dual function memory device 304 may be a join option to determine the operating mode of the dual function memory device 304. In this example, RST # is held at the VSS voltage level during power-up to configure the dual function memory device 304 to operate in a synchronous serial mode. Such that the port is coupled to the synchronous serial signal path.

FIG. 6B is a schematic diagram illustrating the interconnections of a flash memory controller with the dual-function memory device of FIG. 5 in an example memory system 310. In FIG. 6B, the memory system 310 includes an asynchronous flash memory device 312 connected to the same dual function memory device 304 of FIG. 6A. The asynchronous flash memory controller 312 includes ports for providing and receiving the signals previously listed in table 1. The VCC and VSS power supplies are physically connected to the asynchronous flash memory controller 312 and the corresponding VCC and VSS ports of the dual function memory device 304. FIG. 6B illustrates an example distribution of signals provided by the asynchronous flash memory controller 312 to ports of the dual function memory device 304. As shown in the example of FIG. 6A, the RST # port is monitored by the mode detector 208 of FIG. 5, which is currently physically connected to the VCC supply. In addition, RST # may be held statically at VCC level by another circuit, rather than being physically connected to VCC. Note that the data input port D [ n ] of the dual function memory device 304 is not connected to any of the ports of the asynchronous flash memory controller 312 and may alternatively be connected to VSS. In this example, RST # is connected to the VCC power supply during the power-up signal, causing the dual function memory device 304 to operate in an asynchronous serial mode. Thus, these ports may be coupled to asynchronous serial signal paths. In an alternative configuration to the example memory systems 300 and 310, there may be any number of dual function memory devices connected in series to the memory device 304, with the output of the last dual function memory device connected to a corresponding input of the memory controller 302 or 312.

Fig. 7 is a block diagram of an embodiment of the mode detector 208 and the interface and control circuit block 206 shown in fig. 5. The lines interconnecting the circuit blocks are merely illustrative of the functional relationship between the connected blocks and do not describe in detail the specific signals used. The mode detector 208 includes a power supply detector, such as a VCC detector 400, and mode logic 402. The VCC detector 400 provides a status signal VCC _ OK indicating that the power supply VCC has reached the correct level. The MODE logic 402 generates the switching signal MODE in response to VCC _ OK and the buffered reset signal RST #. In this example, the buffered reset signal RST # and the external reset signal RST # are related and are low logic level active signals indicated by a "#" symbol appended to the signal name. According to the present embodiment, once VCC _ OK is asserted, if RST # remains at VCC, the logic level of MODE has one logic level; while RST # remains at VSS, it has another logic level. This means that when VCC _ OK is at a logic level indicating that the power supply is at the correct level, the logic state of MODE is sensed and therefore determined by the voltage applied to the external port RST #. More specifically, for the specific example, if RST # is connected to VCC, MODE is at a logic level corresponding to the asynchronous MODE of operation. Otherwise, MODE is at a logic level corresponding to the synchronous serial MODE of operation. Although two specific modes of operation are discussed, one of ordinary skill in the art will appreciate that the techniques may be used to determine any two different modes of operation.

The interface and control circuit block 206 includes a RST # input buffer 404, a set of control signal buffers, shown as a control buffer block 406, a set of data input and output buffers, shown as a data buffer block 408, a global command decoder 410, and control logic 412. The RST # input buffer 404 is a dedicated input buffer for the external signal RST # and the RST # input buffer 404 is considered part of the synchronization circuit 218 of FIG. 5 due to the change in logic level in response to the signal RST # during the synchronous mode of operation of the dual function memory device 200. Control buffer block 406 includes a single input buffer for synchronous serial mode signals CE #, CK #, CSI, DSI and a single output buffer for synchronous serial mode signals CSO and DSO. For the present embodiment, these synchronous serial mode row signals, including RST #, are considered the default signals assigned to the ports coupled to the interface and control circuit block 206. As shown in fig. 7, particular ports have secondary signals assigned to them, which appear in parentheses. For example, in a synchronous serial mode of operation, the port receiving CK receives WE # in an asynchronous mode of operation.

The secondary signal can be arbitrarily assigned to the port already assigned to the existing default signal. However, to minimize additional buffer circuitry in the control buffer block 406 and the data buffer block 408, secondary signals may be assigned to existing default signals of the same type. The port may be an input type port or an output type port. Thus, the secondary input signal is assigned to the default input signal port and the secondary output signal is assigned to the default output signal port. This means that the same input or output buffer circuit is shared for both synchronous serial and asynchronous modes of operation. However, in some circumstances, when asynchronous and synchronous serial modes of operation each use a different number of input and output signals, it may not be possible to have the default signal port share a buffer circuit with all secondary signals. In this example, an additional input buffer is coupled to the CSO port, since the port assigned to the default output signal CSO is assigned to the secondary input signal WP #. Similarly, the port assigned to the default data output signal Q [ n ] is assigned to the secondary data input/output signal I/O [ n ]. Thus, at least one additional input buffer is coupled to each Q [ n ] port to enable data input functionality in an asynchronous mode of operation.

Thus, while some of the secondary signals applied during asynchronous mode are transmitted through the shared buffer, other secondary signals are transmitted through dedicated additional buffers. In addition to the example of fig. 5, the shared buffer is considered to be part of both the synchronous circuit 218 and the asynchronous circuit 220, while the dedicated buffer for the default signal is part of the synchronous circuit 218 and the dedicated buffer for the secondary signal is part of the asynchronous circuit 220. As shown below and according to the present embodiment, the control buffer block 406 and the data buffer block 408 include path switching circuitry for transmitting buffered signals through either a synchronous serial signal path including the synchronous circuit 218 or through an asynchronous signal path including the asynchronous circuit 220.

The global command decoder 410 is responsible for decoding commands received from the data input port via the data cache block 408, including read, program, and erase OP code commands during synchronous serial and asynchronous modes of operation. While both modes of operation may share the same type of command, there are some commands that are excluded from one mode. Thus, the global command decoder 410 includes dedicated decoders, one being a synchronous command decoder 414 and the other being an asynchronous command decoder 416. According to the present embodiment, each of the two command decoders 414 and 416 includes logic and circuitry for decoding all valid commands for the corresponding mode of operation. To minimize circuit duplication, the two command decoders 414 and 416 may share common logic and circuitry for decoding the same bit pattern used in both modes of operation to represent the same command. Once a command is decoded by one of command decoders 414 and 416, global command decoder 410 provides a corresponding command signal to control logic 412, which then activates the circuitry necessary to take charge of executing the command. Note that both command decoders 414 and 416 receive different signals from the ports corresponding to the same operation, but provide the same command signals to control logic 412. For example, the commands for a program operation are not the same for synchronous and asynchronous modes of operation, but command decoders 414 and 416 generate the same command signals that are used to enable control logic 412 to perform the program operation.

The control logic 412 is responsible for providing internal control signals for activating certain circuits of the dual function memory device 200 in response to the command signal corresponding to the decoded command and one or more external control signals provided by the RST # buffer 404 and the control buffer 406. In the programming operation example, control logic 412 ensures that the word lines and bit lines are driven with the appropriate voltage levels and in the correct sequence.

In the embodiments and examples shown in fig. 5, 6A, 6B and 7, the operation mode of the dual function memory device is set by coupling the reset port RST # to a power supply voltage such as VSS or VCC, or statically holding RST # at VSS or VCC. In the embodiment of fig. 7, the mode detector 208 evaluates the voltage level of the RST # port during VCC detection for setting the operating mode, which may be coupled to the supply voltage or controlled as a reset signal. Fig. 8 is an exemplary circuit schematic of the pattern detector 208 of fig. 7.

Fig. 8 illustrates an example circuit for the VCC detector 400 and the pattern detector 402 of the pattern detector 208 of fig. 7. The VCC detector 400 is connected to VCC and VSS power supplies for driving the intermediate output signal VCC _ OK to a high logic level after VCC reaches a predetermined voltage level. The VCC detector 400 includes a capacitor 450 connected in series with the drain of a PMOS transistor 452, the source of which is connected to the supply voltage VCC, and the gate of which is grounded (VSS). A pair of cross-coupled inverters 454 and 456 are connected to a common terminal of capacitor 450 and transistor 452 and to an input of an inverter 458. Capacitor 460 is connected between VCC and the input of inverter 458. The output of inverter 458 drives the output signal VCC _ OK. Alternatively, the circuitry of VCC decoder 400 may be modified to detect the predetermined voltage instead of VCC. For example, the circuit may detect a reference voltage that is below VCC. Those skilled in the art will appreciate that there are well known circuit techniques for detecting a predetermined voltage below VCC.

In operation, during power up, as the voltage at node a rises, current from VCC passes through transistor 452. Capacitor 460 draws current from VCC as VCC rises. However, due to the PMOS threshold voltage of transistor 452, the voltage at node B is higher than the voltage at node a. The cross-coupled inverters 454 and 456 amplify the potential difference in voltage between node a and node B and latch the logic state. At this time, node B is at a high logic level, and VCC _ OK is at a low logic level due to the inversion of the inverter 458. As VCC continues to increase, transistor 452 conducts current. Since transistor 452 is typically sized such that when it conducts current, it forces cross-coupled inverters 454 and 456 to flip (flip) logic states. Node a then rises to VCC and node B falls to VSS, and as a result VCC _ OK rises to a high logic level.

The mode detector 402 in this example includes a pair of cross-coupled NAND logic gates 462 and 464 and an inverter 466. NAND logic gate 462 has a first input receiving VCC _ OK from VCC detector 402 and a second input receiving the output of NAND logic gate 464. NAND logic gate 464 has a first input receiving the output of NAND logic gate 462 and a second input receiving the buffered reset signal RST #. The cross-coupled NAND logic gates 462 and 464 function as a set-reset latch for latching RST # at a low logic level during VCC detection. The output of the inverter 466 is a switching signal MODE. Depending on the logic level of RST #, MODE can have two different logic levels. In one logic level, MODE signals internal circuitry that the dual function memory device is operating in an asynchronous MODE. In the other and opposite logic levels, MODE signals internal circuitry that the dual function memory device is operating in a synchronous serial MODE. These internal circuits include, for example, the interface and control circuit block 206 of fig. 7. The operation of mode detector 402 is described with reference to the timing diagrams of fig. 9A and 9B.

In the example operation of fig. 9A and 9B, it is assumed that the reset port RST # can be coupled to the supply voltage VCC or dynamically controlled by an external circuit such as a memory controller. Fig. 9A is a timing diagram showing how the synchronous serial operation mode is detected. During power up, the RST # signal remains at a low logic level while the voltage applied to the VCC port rises from ground to VCC. Finally, after VCC reaches a predetermined target level, the output signal VCC _ OK is driven to a high logic level by the VCC detector 400. Mode logic 402 then compares VCC _ OK to the output signal RSTf #, where the level of RSTf # follows the level of RST #. Since RSTf # is at a low logic level when VCC _ OK reaches a high logic level, MODE rises to a high logic level to set the interface and control circuit block 206 of FIG. 7 to operate in a synchronous serial MODE. Since the output of the NAND logic gate 462 is at a low logic level, the logic level of MODE is latched, allowing RST # to rise to an inactive high logic level to allow normal operation of the memory device.

Fig. 9B is a timing diagram showing how an asynchronous operation mode is detected. During power up, RST # is maintained at the VCC power supply level. This can be achieved by physically coupling RST # to VCC or by statically holding RST # at a high logic level corresponding to VCC. In each case, RST # and RSTf # follow VCC, since the circuitry that maintains RST # at VCC is assumed to receive the same global supply voltage. The voltage applied to the VCC port rises from ground to VCC, and after VCC reaches a predetermined target level, the output signal VCC _ OK is finally driven to a high logic level by the VCC detector 400. Mode logic 402 then compares VCC _ OK to the output signal RSTf #. Since RSTf # is at a high logic level when VCC _ OK reaches a high logic level, MODE remains at a low logic level to set the interface and control circuit block 206 of fig. 7 to operate in an asynchronous MODE. In both fig. 9a and 9b, during power up, the chip enable port may be statically held at VCC, in which case its signal trace follows a dashed line that follows the change in VCC. Otherwise, CE # can be driven high after VCC _ OK rises to a high logic level.

In the previously described examples and embodiments, the operating mode of the dual function memory device is set using an existing port, such as the reset port RST #. Thereby eliminating the need for additional new ports. The benefit of using the RST # port is that it is the signal used by only one of the two modes of operation. Thus, the previously described embodiments are not limited to using the RST # port, but may be any port used in only one of the two modes of operation. However, a dedicated port for selecting an operation mode may also be added to the dual function memory device for setting the operation mode.

FIG. 10 is a block diagram illustrating an alternative embodiment of the MODE detector 208 and the interface and control circuit block 206 of FIG. 7, in which a dedicated port MODE is used to select between synchronous serial and asynchronous MODEs of operation. In the presently illustrated alternative embodiment, the MODE detector 208 includes a MODE input buffer 480 coupled to the MODE port for providing the internal MODE signal MODE and an interface and control circuit block 206 that is substantially the same as the interface and control circuit block 206 having the same reference numerals as fig. 7. The main difference is that control buffer block 482 of fig. 10 includes an input buffer circuit for resetting port RST #. As described previously with respect to fig. 7, each port may have a shared buffer or a dedicated buffer. In fig. 10, the RST # port is used because it can be normally used in the synchronous serial mode of operation but it cannot be used in the asynchronous mode of operation. MODE buffer 480 includes standard input signal conditioning circuits similar to or the same as those used in control buffer block 482 for other input signals. The function of MODE in fig. 10 is the same as that of fig. 7, wherein the logic levels of MODE set the interface and control circuitry of circuit block 260 to operate in either asynchronous MODE or synchronous serial MODE. As with the reset port RST # in FIG. 7, the MODE port may be physically coupled to VDD or VSS, or statically held at VDD or VSS, for setting the operating MODE of the dual function memory device. Using both techniques, MODE can be set to VDD or VSS.

In the embodiments of fig. 7 and 10, the global command decoder 410 includes two different control signal paths. In connection with the embodiment of FIG. 5, a synchronous command decoder 414 is included in the synchronization circuit 218. Similarly, an asynchronous command decoder 416 is included in the asynchronous circuit 220. Although not shown in fig. 7 and 10, the global command decoder 410 may include the selector 212 of fig. 5 integrated therein such that an appropriate set of command signals is coupled to the control logic 412.

Fig. 11 is a block diagram showing circuit blocks in the aforementioned synchronous signal path and asynchronous signal path. The synchronous control signal path includes a synchronous command decoder 414 and a selector 216, and the asynchronous control signal path includes an asynchronous command decoder 416 and a selector 216. The synchronous command decoder 414 receives a set of signals S _ CMD from the data buffer block 408 corresponding to a synchronous mode command, also referred to as an OP code. The decoded command signal S _ DEC is provided to one input of the selector 212.

Similarly, asynchronous command decoder 416 receives a set of signals A _ CMD from data buffer block 408 corresponding to asynchronous mode commands, also referred to as OP codes. The decoded command signal a DEC is provided to a second input of the selector 212. The selector 212 couples either a _ DEC or S _ DEC to the control logic 412 in response to the switching signal MODE. The control logic 412 generates the necessary internal control signals, collectively referred to as CORE _ CTRL in fig. 11, which are used by particular circuitry in the CORE circuitry 204. The set of signals CORE _ CTRL may be a set of arbitrarily activated signals required for performing a specific operation. It will be appreciated by those skilled in the art that, for example, a programming operation requires a different internal control signal than a sensing operation.

As previously described, control buffer block 406/482 and data buffer block 408 of FIGS. 7 and 10 have ports with shared buffer circuits or dedicated buffer circuits. The input or output buffer circuit for the default signal may be shared when the secondary signal assigned to that port is the same type of signal. For example, the default and secondary signals are both input type or both output type.

FIG. 12 is a circuit schematic of a buffer circuit of a clock port CK used by the dual function memory device in a synchronous serial mode of operation. In this example, the secondary signal WE # for the asynchronous operation mode is assigned to the CK port. The buffer for CK includes a well-known input buffer 500 and a signal path switch including transmission gates 502 and 504. The input buffer 50 receives the signal received at port 506 and provides a corresponding buffered signal at its output. The inputs of transmission gates 502 and 504 receive the buffered signals in parallel and selectively pass them as either an internal clock signal CKf or an internal WEf # signal in response to the logic level of MODE and its complement MODE #. According to the previously described example, MODE is at a high logic level to set the dual function memory device to operate in a synchronous serial MODE. Thus, signal CK is connected to port 506 and transmission gate 502 is on, while transmission gate 504 is off. The internal signal CKf is then passed to other circuits, such as the synchronization control logic of fig. 7 and 10. On the other hand, if MODE is at a low logic level, the dual function memory device is set to operate in an asynchronous MODE. Thus, signal WE # is connected to CK port 506 and transmission gate 502 is off and transmission gate 504 is on. Internal signal WEf # is then passed to other circuitry, such as asynchronous control logic 420 in fig. 7 and 10. As can be seen in fig. 12, the input buffer 500 is shared by the signals CK and WE #.

There may be some type of secondary signal that may be assigned to another type of default signal. In such a case, the port may include dedicated buffers for accommodating synchronous and asynchronous mode signals. Fig. 13 is a circuit schematic of buffers for the input data port Dn and the output data port Qn. In this example, the asynchronous secondary signal is not assigned to the Dn port, but the asynchronous data input/output signal I/On is assigned to the Qn port. The Dn buffer includes a serial input block 510 and optional power saving devices, including a power switch 512. The serial input block 510 includes other circuitry, such as an input buffer connected from the serial interface 105 of FIG. 4A to the Dn port and used to provide serial input data SER _ IN, and an input serial-to-parallel register block 106 of FIG. 4A for receiving SER _ IN and providing a parallel signal group PAR _ IN. As shown IN fig. 4B, PAR _ IN includes command information CMD, which is provided to the synchronous command decoder 414 of fig. 7 and 10. In a synchronous mode of operation, the dual function memory device passes data received at its Dn input port to a subsequent device through its Qn output port. Thus, the serial input block 510 provides through (flow) DATA F _ DATA received by the buffer of the Qn port.

The Qn buffer includes a unidirectional data output path and a bidirectional data path. The unidirectional data output path is enabled during a synchronous serial mode of operation and the bidirectional data path is enabled during an asynchronous mode of operation. The unidirectional data output path includes serial output block 516, transmission gate 518, transmission gate 520, and power switch 522. Transmission gate 518, serial output block 516, and transmission gate 520 are connected in series for coupling the sense data DOUT provided by the core circuitry of the dual function memory device to the Qn port 524 during the synchronous serial mode of operation. In this example, DOUT is provided as a parallel signal group, and serial output block 516 may include the outputs of fig. 4 in parallel to the pass register block and output buffer. As previously described, the output parallel-to-serial register block 108 converts DOUT and converts to serial output data SER _ OUT. In the synchronous serial mode of operation, Qn corresponds to F _ DATA provided from the serial input block 510 or read DATA DOUT provided from the core circuitry. The synchronization control logic 418 of fig. 7 and 10 controls which data source is selected for output based on the operations performed.

Because the Qn port 524 defaults to a unidirectional output port, a bidirectional data path is provided to accommodate the secondary allocation of the input/output data signal I/On. The bi-directional data path includes transmission gate 526, I/O buffer 528, transmission gate 530, and power switch 532. Transmission gate 526, I/O buffer 528 and transmission gate 530 are connected in series for bi-directionally coupling input/output data DI/O to Qn port 524. I/O buffer 528 includes an output buffer for driving read data to Qn port 524 and an input buffer for receiving data applied to Qn port 524. For example, the I/O buffer 528 may include the same circuitry as the data buffer 46 in FIG. 3. In this example, the DI/O may be read data from the core circuit or command information including an OP code, a read address, a write address, and optionally write data. The OP code portion of the DI/O is provided to asynchronous command decoder 416

The power switches 512, 522, and 532 couple VCC power to all circuits in the serial input block 510, the serial output block 516, and the I/O buffer 528. In the synchronous serial MODE of operation, MODE is a high logic level to turn off the power switch 532 and transmission gates 526 and 530. By turning these devices off, the I/O buffer 528 is isolated from DI/O and Qn port 524 and disabled because it is no longer receiving VCC. In other words, the bidirectional data path is disabled during the synchronous serial mode of operation and power savings are achieved because there is no longer power drain due to logic gate switching. In the asynchronous MODE of operation, MODE is at a low logic level. Thus, the power switches 512 and 522 and the transmission gates 518 and 520 are turned off to disable the serial input block 510 and the unidirectional data output path. Thus, serial output block 516 is isolated from DOUT and Qn port 524.

Although not shown in fig. 11, the asynchronous command decoder 416 and the asynchronous control logic 420 may be powered by VCC through at least one power switch similar to the power switches shown in fig. 12 and 13, such that they only receive VCC power when the dual function memory device is set to operate in an asynchronous mode. Similarly, the synchronous command decoder 414 and the synchronous control logic 418 may be powered from VCC through at least one power switch. Thus, circuits that are not used in one mode may be turned off to reduce power consumption.

FIG. 14 is a flowchart outlining a method for setting an operating mode of a dual function memory device in accordance with an embodiment of the present invention. It is assumed that the memory system includes a memory controller serially connected in a ring topology with at least one dual function memory device including the previously described embodiments. For example, the memory system may be configured as described in fig. 6A or 6B. The method begins at step 600 with the memory system powered up, meaning that VCC power is applied to the VCC terminal for feeding all dual function memory devices and the memory controller. The designated MODE port of each dual function memory device, which may be an existing port such as RST # or a dedicated port such as MODE, is monitored by its corresponding MODE detector. The pattern detector may be, for example, the pattern detector 208 of fig. 7 or fig. 10. In step 604, the mode detector of each dual function memory device determines whether its mode port is biased to a supply voltage. The presently described example assumes that the mode port can be biased to VCC for setting the asynchronous mode of operation. If the MODE port is biased to VCC, its internal switching signal MODE is set to VSS, indicating that the dual function memory device is operating in an asynchronous MODE of operation. Thus, the method proceeds to step 606 and the interface and control circuit block 206 of each dual function memory device is dynamically configured to receive asynchronous signals at its ports and operate the internal circuitry using internal control signals generated from the received asynchronous signals.

Returning to step 604, if the memory controller maintains the MODE port at VSS during power-up, MODE is set to VCC. Thus, the method proceeds to step 608 and the interface and control circuit block 206 of each dual function memory device is dynamically configured to receive a synchronization signal at its port and to operate the internal circuitry using internal control signals generated from the received synchronization signal.

The previously described embodiments enable a memory device, such as a flash memory device, to operate in a synchronous serial mode and in a more well-known asynchronous mode by biasing a port of the memory device package to a particular voltage level during power-up. The particular voltage level may be a power supply voltage or any predetermined voltage level that the memory device may detect and, when detected, provide an internal switching signal having a corresponding logic level. Since different signals are assigned to the ports of the memory device according to the set operation mode, the path switching circuit ensures that a signal corresponding to each operation mode is supplied to the corresponding controller circuit in response to the internal switching signal. The controller circuit provides a set of control signals with appropriate timing parameters for proper control of the core circuitry of the memory device according to the set mode of operation.

In the previous description, for purposes of explanation, numerous details were set forth in order to provide a thorough understanding of the embodiments of the invention. However, it will be apparent to one of ordinary skill in the art that these specific details are not required in order to practice the present invention. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the present invention. For example, specific details are not provided as to whether the embodiments of the invention described herein are implemented as a software program, hardware circuitry, firmware, or a combination thereof.

In the embodiments and examples described above, the device elements are shown interconnected for simplicity. In practical applications of the present invention to apparatuses, devices, elements, circuits, etc. may be directly connected to each other. Also, devices, elements, circuits, etc. may be connected indirectly to each other through other devices, elements, circuits, etc., necessary for operation of the apparatus. Thus, in actual configuration, circuit elements, devices, etc. are directly or indirectly coupled or connected to each other.

The above-described embodiments of the invention are intended to be examples only, and alterations, modifications and variations may be effected to the particular embodiments by those of skill in the art without departing from the scope of the invention, which is defined solely by the claims appended hereto.

Claims (15)

1. A memory device configurable to operate in a first mode and a second mode, comprising:

a port for receiving one of a first allocation of functions corresponding to a first mode and a second allocation of functions corresponding to a second mode;

interface and control circuitry for receiving commands from at least one of said ports and configurable for decoding the commands in one of a first mode and a second mode, the commands being decoded to control core circuitry of the memory device; and

a mode detector connected to a selected one of the ports for configuring the interface and control circuitry to decode the command in a first mode when a voltage source is detected and to decode the command in a second mode when a voltage source is not detected.

2. The memory device of claim 1, wherein the interface and control circuitry comprises:

a synchronization circuit coupled to the port for receiving the command when the voltage source is not detected by the pattern detector and for generating a decoded synchronization command signal;

an asynchronous circuit coupled to the port for receiving the command when the mode detector detects a voltage source and for generating a decoded asynchronous command signal;

control logic responsive to the decoded asynchronous command signal and the decoded synchronous command signal to generate the same internal control signal; and

one of the decoded asynchronous command signal and the decoded synchronous command signal is selectively passed to a selector of the control logic in response to a detected state of the voltage source.

3. The memory device of claim 2, wherein the pattern detector comprises:

a voltage detector for providing a status signal when the voltage source has reached a predetermined level; and

mode logic coupled to the selected port for driving the mode signal from the first logic level to a second logic level in response to the status signal when the selected port is biased to a voltage level different from the voltage source.

4. The memory device of claim 3, wherein the synchronous circuit includes a synchronous command decoder and a synchronous buffer coupled to each port, and the asynchronous circuit includes an asynchronous buffer coupled to the asynchronous command decoder and to each port.

5. The memory device of claim 4, wherein each port in the first functional allocation and the second functional allocation having the same type, which is one of an input type and an output type, has a common buffer that serves as the synchronous buffer and the asynchronous buffer.

6. The memory device of claim 5, wherein the interface and control circuit further comprises a signal path switch for selectively coupling each port to the synchronous command decoder through the synchronous buffer in response to a first logic level of the mode signal, and for selectively coupling each port to the asynchronous command decoder through the asynchronous buffer in response to a second logic level of the mode signal.

7. The memory device of claim 6, wherein the interface and control circuitry further comprises:

a first power switch for decoupling the voltage source from the synchronization circuit in response to a second logic level of the mode signal, an

A second power switch to decouple the voltage source and the asynchronous circuit in response to the first logic level of the mode signal.

8. The memory device of claim 3, wherein the mode logic includes a latch to maintain the second logic level of the mode signal in response to the status signal.

9. The memory device of claim 1, wherein the selected port is a functional port used during normal operation in one of the first mode and the second mode.

10. The memory device of claim 1, wherein the selected port is a dedicated port that is not used during normal operation in both the first mode and the second mode.

11. A memory system, comprising:

a memory controller for providing a control signal having a first signal function assignment and a second signal function assignment; and

a plurality of memory devices, each configured to receive one of a first signal function assignment and a second signal function assignment responsive to a port biased to a supply voltage during a power-up sequence, each of the plurality of memory devices configured to receive the other of the first signal function assignment and the second signal function assignment when the port is biased to the other supply voltage during the power-up sequence.

12. The system of claim 11, wherein said port is part of said first signal function assignment and is not used in a second function assignment.

13. The system of claim 11, wherein the port is unused in both the first signal function assignment and the second signal function assignment.

14. The system of claim 11, wherein the port is physically connected to a supply voltage.

15. The system of claim 11, wherein the port is statically held at a supply voltage by a circuit.