HK1182842B - Mosfet gate drive with reduced power loss - Google Patents

Description

MOSFET gate driver with reduced power consumption

The present application is a divisional application of an invention patent application having an application date of 2008/04/30, an application number of 200880025666.5, and an invention name of "MOSFET gate driver for reducing power consumption".

Cross Reference to Related Applications

This application claims priority from provisional application No. 60/931,097 filed on 21/5/2007, which is hereby incorporated by reference in its entirety.

Technical Field

The present invention relates to the driving of discrete or integrated power MOSFETs in switching applications such as DC/DC conversion, and in particular to the driving of discrete or integrated power MOSFETs which switch at high frequencies.

Background

Switching regulators are used to regulate and convert one DC voltage to another by stepping up or down the voltage, or with the ability to step up or down the voltage depending on changing conditions. The quality of a DC/DC switching converter and regulator is measured by its ability to regulate a range of input voltages, output voltages, load currents and temperatures. During voltage and current transients, as well as during steady state operation, the DC/DC switching converter and regulator should react fast enough to ensure good regulation. In some applications, electrical isolation should also be provided to prevent high input voltages from coupling to the output, eliminating the risk of electrical shock and fire.

Most switching regulators utilize an inductor or coil as an energy storage device because inductors tend to generate a range of output voltages that are different from the input voltage driving the inductor (i.e., different from the magnetizing inductor). One or more power switches, typically power MOSFETs, are used with a diode rectifier to control the current in the inductor and the output voltage of the regulator is controlled by using negative feedback, wherein the switching and conduction of the one or more power switches is controlled by a Pulse Width Modulation (PWM) controller. Some examples of DC/DC converter regulators well known in the prior art are illustrated in fig. 1A-1F.

Common DC/DC converter topologies: in fig. 1A, a Buck (Buck) converter 1 controls the current in inductor 4 by pulse width modulation, with a high side power MOSFET2 responsive to PWM controller 7, thereby providing regulation that steps down the voltage. The capacitor 5 filters the voltage ripple at the output of the converter 1. When high side MOSFET2 is turned off, the current in inductor 4 remains unchanged because of voltage V_xDropping below ground, forward biasing the rectifier 3 and freewheeling the inductor current until the MOSFET2 turns on again (turn on). The diode 6 remains reverse biased under normal operation. As shown, MOSFET2 is a P-channel device, but a high side N-channel MOSFET can replace the P-channel device with appropriate changes to the gate drive circuitry.

Fig. 1B illustrates a synchronous buck converter 10 having a PWM controller 17, a high side P-channel MOSFET11 with an intrinsic PN junction diode 15, an inductor 13, and a capacitor 14. The synchronous rectifier includes an N-channel MOSFET12 with an intrinsic PN junction diode 16. The synchronous buck converter 10 includes a break-before-make (BBM) circuit 18 to prevent the high side P-channel MOSFET11 and the low side N-channel synchronous rectifier MOSFET12 from turning on simultaneously. The operation of synchronous buck converter 10 employs the same control and feedback techniques as described for non-synchronous buck converter 1, except that MOSFET12 is turned on during a portion of the time diode 16 is turned on, i.e., when MOSFET11 is turned off.

While synchronous buck converter 10 employs a complementary half-bridge with P-channel MOSFET11 and N-channel MOSFET12, non-synchronous buck converter 20 of fig. 1C utilizes an N-channel totem pole arrangement including an N-channel high-side MOSFET21 and an N-channel low-side synchronous rectifier MOSFET 22.

Boost converter 30 shown in fig. 1D includes MOSFET31 and PWM controller 36, Boost converter 30 controlling the current in inductor 32 by pulse width modulation or by controlling the on-time of MOSFET31 in a variable frequency operation. Whenever MOSFET31 is turned off and inductor 32 is not magnetized, voltage V_xIt rises quickly and forward biases the rectifier diode 33 and will supply current to the filter capacitor 34 and the output. Via a feedback voltage V_FBUsing the output voltage V_outTo control the on-time of MOSFET31, the current in inductor 33, and V_out. Synchronous boost regulator, a modification of boost converter 30 includes placing an N-channel or P-channel synchronous rectifier MOSFET in parallel with diode 33 to shunt current from diode 33 during a portion of the time when diode 33 is forward biased, i.e., low side MOSFET31 is off.

Typically, the buck or synchronous buck converters shown in fig. 1A-1C may be used only for step-down voltage conversion, i.e., reducing the input voltage to a lower and well-regulated output voltage, using a single inductor instead of a transformer or coupled inductor for the switching regulator. The flyback (reverse) converter of the buck converter, the boost converter shown in fig. 1D and the corresponding synchronous boost converter can be used only for step-by-step conversion of the boosted voltage, i.e. to increase the input voltage to a higher and well-regulated output voltage.

Obtaining a single regulator with the ability to step up or down the input voltage requires a more complex solution, using a doubled number of power MOSFETs to combine the buck and boost converters into a single circuit, or by employing a multi-winding inductor and transformer. For example, in the converter 40 shown in fig. 1E, the high side MOSFET41 drives a coupled inductor 42 with a turns ratio of "n", and the secondary side of the coupled inductor 42 is rectified by one, two, or four rectifying diodes or synchronous rectifier MOSFETs to output a voltage across the capacitor 44. To regulate the output voltage, it is necessary to pass through a feedback voltage V across an isolation gate (barrier)46_FBWill output a voltage V_outFeedback to PWM controller 47, isolation gate 46 may comprise a transformer or an optocoupler.

Although the converter 40 utilizes a positive input voltage V_ccA P-channel power MOSFET is connected, but the converter 50 shown in fig. 1F uses a grounded N-channel MOSFET51 to control the current in the coupling inductor 52, with the secondary winding of the coupling inductor 52 rectified by a diode or MOSFET rectifier circuit 53 and filtered by a capacitor 54. The output voltage across the capacitor 54 is fed back to the primary side PWM controller 57 through an isolation transformer or optocoupler 56. Converter 50 may operate as a forward converter or a flyback converter depending on whether energy is delivered to the load in phase when MOSFET51 is on or out of phase when the MOSFET is off.

In all of the regulators shown in fig. 1A-1F, power MOSFETs and rectifier diodes are used to control the flow of energy in the converter and regulation circuitry. In a synchronous rectifier converter, uniform (even) diodes are shunted by conducting mosfets to reduce conduction losses.

Switching power MOSFETs at frequencies in excess of one megahertz, however, introduces (involving) switching and gate drive power losses, not just power losses due to conduction.

Conduction and switching losses in power MOSFETs: even though power MOSFETs provide excellent electrical performance to other semiconductor devices, they are not ideal power switches especially for operation below 100 volts-indeed they consume power and reduce the efficiency of the circuits in which they are employed. In the conducting or on state, the voltage across the drain-source terminal is multiplied by the current, or P ═ I_D·V_DSThe power consumed is determined. Since the device is not always on, the time for turning on and on by the device is a percentage of the clock period T (i.e., T_onT) determining the average power.

In a main switch such as a DC/DC switching regulator, this fraction is also referred to as the converter duty cycle D. It is well known to those skilled in the art that if a circuit is not operating at a fixed frequency f ≡ 1/T, its average power changes from cycle to cycle and a more careful time integration must be performed to calculate the average power loss of the device over a longer duration, for example, during discharge of a lithium battery.

The power loss in a conducting, "on" state power MOSFET depends on its terminal voltage. The terms "on" and "switch" should not be understood to imply or imply exclusively digital operation. The power MOSFET may operate as a programmable current source or as a variable resistance. As used herein, the term "switch" follows the definitions of the IEEE and Webster dictionaries, such as referring to a device that makes (completes) or breaks an electrical circuit (i.e., allows or prevents current flow regardless of the magnitude of the current).

In its saturation region of operation, is dependent on the gate voltage and relatively independent of its drain voltage V_DSOf (3), the "on" power MOSFET behaves like a constant current source I_sat. Then, the average power loss is given by:

when operating as a controlled current source, the magnitude of the current of the power MOSFET must be kept low or else the device will overheat. Care must be taken in circuit design to minimize the effect of variations in the input voltage on the gate bias of the device. With gate control, a power MOSFET can be operated as a switched current source, alternating between a fixed drain current and an off condition in which no current flows except for the device leakage current.

When the power MOSFET is used as a low resistance switch, the device operates in its "linear" region, characterized in that there is a linear relationship between its drain voltage and its drain current, the slope of the line defining the variable resistance R_DS(on)The variable resistor R_DS(on)The magnitude of (c) varies with the MOSFET gate bias. Since V ═ I · R according to ohm's law, the power loss of a MOSFET in its linear region follows the following relationship:

the term R_DS(on)It is assumed that the device operates in its linear region, acting as a variable resistance dependent on the gate voltage.

Switching power MOSFETs on and off at high frequencies also has power losses. Fig. 2A-2D illustrate power losses in a MOSFET caused by the gate capacitance of the MOSFET. As shown in FIG. 2A, the transient gate current I required to charge and discharge the capacitive gate of the MOSFET61_g(t) Supplied by the gate buffer 63 and lost in the gate buffer 63, first charges the gate of the MOSFET to turn it on, and then subsequently drains (dump) the charge stored on the gate of the MOSFET to ground. The equivalent power loss caused by the driving capacitor is given by the well-known formula P ═ C_eq·V²It is given. Use the term C_eqBecause MOSFETs exhibit multiple voltage-variable capacitances inherent in their structure, simple power calculations are performed, at best, using unknown (probastic) capacitances. FIG. 2B illustrates the inclusion of a gate-source capacitance 70 (C)_GS) Gate-drain capacitance 69 (C)_DG) And a drain-source capacitance 72 (C) associated with the PN junction diode 71_DS) The MOSFET 66.

In addition to being voltage variable, the gate-drain capacitance 69 forms a feedback path from the "output" of the MOSFET drain to the input of its gate. Whenever the circuit shows a voltage gain, the capacitor is also amplified and will be larger than the small signal capacitor C_DGA capacitance many times larger in magnitude is loaded on the input terminal. This phenomenon, known as the Miller effect, complicates the calculation of power loss using capacitance extremely because during switching transients MOSFET66 goes from off to saturation and into its linear region, changing voltage gain and capacitance in tandem.

FIG. 2C illustrates a power-on-power MOSFET_D-V_DSSuch switching transients on a family of curves. Specifically, the "load" represents a switching regulator such as the buck converter 1 of fig. 1A that drives both the rectifying diode 3 and the inductor 4 during diode recovery, i.e., when the diode stops conducting and the MOSFET starts.

Starting with the "off" device with no current at point 78, the switching transient is shown traversing path 71 at a relatively constant drain voltage. The drain-source voltage cannot be changed immediately because the diode 3 must deplete any stored charge before the drain voltage can rise. For large V_DSDrain voltage, V_DS>V_GSAnd the MOSFET operates in its saturation region. As controlled by gate voltage 74Current and V in saturated MOSFET_GSThe value ramps up proportionally. Under such conditions and circuits, saturated MOSFETs exhibit voltage gain, making it increasingly difficult for the gate buffer to drive the MOSFET gate smoothly during the transition period by amplifying the gate-drain feedback capacitance by constantly changing and increasing amounts.

At gate bias V_GS5In this regard, the device enters an operating condition 72 where both current and drain voltage change rapidly. Point 75 corresponds to a bias condition in the transition region between linear and saturated, sometimes referred to as a saturation edge or quasi-saturation. The instantaneous power loss in the device peaks and starts with V_DSAnd decreases as it decreases. From gate bias V_GS6And a higher gate bias, the MOSFET operates in its linear region 76.

Further increase in gate voltage 73 causes the resistance R of the MOSFET to increase_DSFurther down to point 79 but with a diminished improvement in conduction losses. In the example shown, the current becomes semi-constant during this short interval, because the load is inductive and the current is not allowed to change immediately. Due to I_D、V_DSAnd V_GSAnd at the same time, it is difficult to meter all intra-device currents.

Although in practice the gate buffer used to drive the gate of the MOSFET appears as a fixed voltage source, a clearer device operation can be obtained with current source gate drive. As shown in fig. 2D, a constant current I is supplied to the gate of the MOSFET driving the load_GCurrent source of (2) generating V_DSSwitching transient, voltage V from cut-off region 83_ccBegins to fall over time, passes through saturation region 87, and enters its linear region 88. During the same time period, V_GSThe gate voltage starts at zero voltage at point 90, increases linearly 81 during the off period, reaches a plateau 82 at saturation when the drain voltage 87 slew, and increases again 83 as the device enters its linear operating region. At time t_onAt the end of the transient, the MOSFET is fully on and the drain voltage is nowIs I_D·R_DS. Since the gate current is constant throughout the transition, and since Q ═ I_G·t_onSo the x-axis can be redrawn as the gate charge Q_G。

Since the charge is always conserved, the amount of charge required to reach point 84 is independent of the gate drive circuit. In other words, the gate charge Q required to achieve a given gate and drain bias condition_GIs path independent and does vary with the drive circuit. As shown in the graph 100 of fig. 3A, may be at V_GSRedrawing Q on the x-axis_GAnd V_GSHaving a cut-off region, a saturation region, and a linear region 104, 105, and 106, respectively. The drain voltage plotted on the same axis is expressed as rapidly dropping to the linear region 102 at the saturation edge 101, eventually settling at a minimum value R at point 108_DSThe resistance of (c).

The power loss to the gate charge 107 and drain voltage 108 can then be expressed as:

P_drive＝Q_G·V_GS·f。

this equation takes into account the Miller effect and all voltage-dependent capacitances, but the equation is a function of the drain bias V_DSIs driven by a grid_GSAnd varies from technology to technology. Then, the total loss for the power MOSFET in the switching regulator can be calculated by the following equation:

P_loss＝P_cond(lin)+P_cond(sat)+P_drive+P_other。

in conventional switching regulators, MOSFET operation is never intentionally in saturation, but is only subject to saturation during switching transients and diode recovery. In such a case, P can be ignored provided that the frequency of the converter is not too high_cond(sat)And only the linear region P needs to be considered_cond(lin)Internal conduction losses. At low voltage, the parasitic loss P can be ignored_otherAnd the power loss equation is simplified to:

given Q in graph 100_GAnd R_DSCurve for t at a constant value_onOperation of the/T ratio, the overall power loss calculated using the above equation is shown in graph 120 of FIG. 3B. As shown, curves 121, 122, and 123 illustrate power loss versus frequency f₁、f₂And f₃Proportionally increasing, frequency f₁、f₂And f₃May be, for example, 300kHz, 1MHz and 2 MHz.

The power loss curve has a U-shape with a minimum at a certain gate voltage, and the loss increases for any gate drive above or below that value. At higher gate drive voltage P_lossThe gradual increase is due to the gate drive loss P increasing in line with curve 106 in graph 100_driveAnd (4) causing. For low gate voltage, P_lossThe steep dependence on gate voltage is a result of MOSFET operation at the saturation edge corresponding to curve 101 in graph 100. With frequencyThe ratio increases from curve 121 to 123, the minimum power loss increases, i.e. the converter exhibits reduced efficiency, and exhibits a larger concavity (concavity), i.e. its minimum occurs over a narrower range of gate voltages. In other words, gate drive loss becomes more and more critical at higher frequency operation.

In normal applications using constant voltage drive rather than constant current drive, according to V_GSInspection of the switching waveforms shows that gate drive losses are not significant because they occur too quickly to be seen. For example, in FIG. 4A, P-channel MOSFET142 and N-channel MOSFET143 are included and supplied with voltage V_ccThe gate buffer 141 supplied by the voltage source 146 is driven rapidly at V_ccThe gate of power MOSFET144 between ground and ground. During turn-on, V shown in FIG. 4B_GSThe switching waveform 150 shows a slight change 153 in slope in different smooth upward progresses (progressions) 151 and 154, and again shows a change 157 in slope in smooth decays 156 and 158 of the final gate voltage 159 to zero voltage during turn-off.

A clearer mechanistic picture of actual drive loss is also shown in graph 170 in fig. 4B, where the gate charge increases linearly from a start value 171 of zero coulomb, rises with slope 172, reaches a final value 173, and at time t₃The push 174 decays to a final value 175 of zero coulombs at the end of the switching transient. Therefore, even if the gate driving uses the constant voltage driving, the power loss is the same as shown using the current source driving condition. The total charge stored on the gate during charging is lost to ground during turn-off.

Such rail-to-rail (rail-to-rail) driving is lossy because no gate charge is recovered or conserved from one cycle to the next, and because the gates are driven to a voltage V that may not correspond to the minimum power loss condition shown in fig. 3B_cc. As a result, power is wasted by discarding charge and overdriving the MOSFET gate, both factors reducing the efficiency of the converter.

What is needed in any MOSFET that switches at various frequencies, particularly in DC/DC switching regulators, is a way to charge and discharge the gate of the power MOSFET so that a portion of the gate charge is preserved and reused on a cycle-by-cycle basis in order to increase the overall efficiency of the converter or other circuit.

Disclosure of Invention

These needs are met in a MOSFET operated in accordance with the present invention, wherein the switching MOSFET is not fully turned off, but alternates between a fully turned on condition and a low current condition. The low current condition of the MOSFET replaces the full off condition used in conventional switching sequences. Switching the MOSFET between the fully on condition and the low current condition reduces the amount of charge that must be moved into and out of the gate of the MOSFET during each switching cycle, thereby reducing power losses in charging and discharging the gate. In many cases, this power savings more than compensates for the additional power loss from the drain current that continues to flow into the MOSFET under low current conditions of the MOSFET. Thus, the overall efficiency of the MOSFET is improved.

The above-described method of driving the gate of the MOSFET can be implemented using various gate drive circuits, all of which are within the scope of the present invention.

In one set of embodiments, the gate is driven using a two-state gate driver that is functionally configured as a single pole double throw switch and has a first input connected to a first voltage sufficient to fully turn on the MOSFET and a second input connected to a second voltage typically near the threshold voltage of the MOSFET. An output of a gate driver connected to the gate of the MOSFET is switched between the first and second inputs to drive the MOSFET between a fully on and low current condition. The gate driver may be constructed using a pair of complementary MOSFETs and a pass transistor connected to a reference voltage suitable for driving the MOSFETs to a low current condition. The voltage delivered to the gate of the MOSFET may be generated using a plurality of pass transistors connected as a multiplexer, or a voltage divider circuit including resistors and/or diodes. The gate driver is capable of delivering more than two voltages to ensure that a voltage suitable for the low current condition of the MOSFET is available.

Feedback may be employed to ensure that the proper drain current is allowed to flow through the MOSFET under low current conditions. The feedback circuit measures the current through the MOSFET and then compares the measured value to a reference value representing the desired current value. If there is a difference, an error signal is generated and, if necessary, causes the gate driver to increase or decrease the gate voltage of the MOSFET in a low current condition until the correct value of the drain current in the MOSFET is reached. The feedback circuit may include an amplifier, a sense resistor, and/or a current mirror.

Alternatively, since the threshold voltage of a MOSFET is the most dominant process parameter affecting its saturation current, manufacturing variations in its threshold voltage can be corrected by trimming to obtain the correct value of the low current in the MOSFET. When the gate of the MOSFET is biased for a low current condition, the trim circuit can measure the drain current in the MOSFET and adjust the reference voltage delivered by the gate driver to the gate of the MOSFET until the correct value of the drain current is achieved. For example, the trimming circuit may include a one-time programmable (OTP) MOSFET in parallel with a resistor in series in the voltage divider network. The individual MOSFETs are programmed, i.e. permanently switched on, to short out a sufficient number of resistors until a gate voltage is obtained that provides the correct value of the drain current in the MOSFET.

Alternatively, the MOSFET may be monolithically fabricated with a second threshold-connected (threshold-connected) current mirror MOSFET. Since any change in threshold voltage will affect both MOSFETs, supplying a fixed current to the current mirror MOSFET will cause the current to be mirrored in the main MOSFET by the ratio (n) of the respective gate widths of the MOSFETs. Thus, if a current equal to the target current in the main MOSFET divided by n is supplied to the current mirror MOSFET, the correct magnitude of current will flow through the main MOSFET. The current supplied to the current mirror MOSFET can be regulated by a D/a converter under the control of digital logic, a digital signal processor, or a microprocessor, and, if desired, can be regulated dynamically and in real time. Alternatively, the gate of the current mirror MOSFET may be switched between a first position connected to the drain of the current mirror MOSFET and the current source, and a second position connected to ground, turning off the current mirror MOSFET, and connecting the gate of the main MOSFET to a high voltage driving the main MOSFET into a high current state.

In another set of embodiments, the gate driver is functionally configured as a three-pole switch with the third input connected to the source of the MOSFET. By connecting the output of the gate driver to the third input, the MOSFET is turned off or put into a sleep or off mode, in which case there is no power loss either driving the gate of the MOSFET or allowing current to flow through the drain of the MOSFET. In some embodiments, the gate driver may have an enable input that, in an on condition, causes the gate driver to switch the MOSFET between high and low current states, and, in an off condition, causes the gate driver to connect the gate of the MOSFET with the source, turning off the MOSFET or causing it to enter its sleep mode.

The invention also includes a method of driving a MOSFET by switching a gate between a first voltage at which the MOSFET is fully turned on and a second voltage, typically close to a threshold voltage, at which the MOSFET is in a low current or partially turned on condition.

The above-described method and circuit for driving a power MOSFET with low gate drive loss may be applied to a low-side, high-side, or push-pull configuration power MOSFET of an N-channel or P-channel conduction type.

Drawings

Fig. 1A is a circuit diagram of a buck converter.

Fig. 1B is a circuit diagram of a synchronous buck converter with complementary power MOSFETs.

Fig. 1C is a circuit diagram of a synchronous buck converter with totem pole N-channel power MOSFETs.

Fig. 1D is a circuit diagram of a non-synchronous boost converter.

Fig. 1E is a circuit diagram of a flyback or forward converter with P-channel power MOSFETs.

Fig. 1F is a circuit diagram of a flyback or forward converter with an N-channel power MOSFET.

Fig. 2A is a circuit diagram illustrating an operation of the gate driver.

Fig. 2B is a graph illustrating the inherent capacitance in a MOSFET.

FIG. 2C is a schematic view showing the superposition at I_D-V_DSGraph of switching transients on a family of curves.

Fig. 2D is a graph showing the change in drain-source voltage and gate charge as the MOSFET goes from an off condition to an on condition.

FIG. 3A is a graph showing gate charge and R as a function of gate voltage_DSA graph of the variation of (c).

Fig. 3B is a graph of power loss as a function of gate bias.

Fig. 4A is a circuit diagram of a CMOS gate driver.

Fig. 4B shows a graph of gate charge and gate voltage in the gate driver during switching.

Fig. 5 is a conceptual circuit diagram of a gate charge reduced power MOSFET gate driver in accordance with the present invention.

Fig. 6 shows voltage and current switching waveforms in the gate driver of the present invention.

Fig. 7 is a graph of gate voltage and drain voltage as a function of gate charge illustrating a limited gate voltage swing (swing) in the gate driver of the present invention.

Fig. 8 is a graph showing the limited drain current swing in a MOSFET driven by the gate driver of the present invention.

Fig. 9 is a graph showing limited gate charge swing in a MOSFET driven by the gate driver of the present invention.

Fig. 10 is a conceptual circuit diagram of a tri-state gate driver according to the present invention.

11A-11F are graphs and circuit diagrams illustrating operating conditions of a tri-state gate driver of the present invention, including a low resistance condition, a low current or controlled current condition, and an off state condition.

Fig. 12A shows a graph of voltage and current switching waveforms for a tri-state gate driver of the present invention.

Fig. 12B is a graph of gate voltage in the gate driver of the present invention alternating between low current and conventional gate drive techniques.

Fig. 12C is a graph of gate voltage in the gate driver of the present invention having a soft-on (turn-on) feature.

Fig. 13A is a circuit diagram of a gate driver including a pass transistor.

Fig. 13B is a circuit diagram of a gate driver including a D/a converter.

Fig. 13C is a circuit diagram of a gate driver including a multiplexing pass transistor.

Fig. 13D is a circuit diagram of a gate driver including a multiplexed resistor divider.

Fig. 13E is a circuit diagram of a gate driver including a multiplexed resistor/diode divider.

Fig. 14A is a circuit diagram of an open-loop gate driver without feedback.

Fig. 14B is a circuit diagram of a gate driver with a current sensing feedback system.

Fig. 14C is a graph comparing stability of drain current in open loop gate driver and feedback gate driver.

Fig. 14D is an I-V graph illustrating control of drain current in a gate driver with feedback.

Fig. 15A is a circuit diagram of a gate driver with a feedback system utilizing a current sense resistor.

Fig. 15B is a circuit diagram of a gate driver with a feedback system utilizing current mirror sensing techniques.

Fig. 15C is a circuit diagram of a gate driver with a feedback system using cascode current sensing technique.

Fig. 16A is a conceptual circuit diagram of a trimming (trimming) circuit of the gate driver of the present invention.

Fig. 16B is a circuit diagram of a trimming circuit of the gate driver of the present invention including a one-time programmable MOSFET.

Fig. 16C is a graph of the bias programming code of the gate driver of fig. 16B.

FIG. 16D is a flow chart of a calibration algorithm for the trim circuit.

FIG. 16E is a graph of a programming sequence for a trim circuit.

Fig. 17A is a circuit diagram of a gate driver utilizing a current mirror to control current in a MOSFET in a low current condition.

Fig. 17B is a circuit diagram showing a trimming circuit that adjusts the magnitude of the mirror current.

Fig. 18 is a circuit diagram of a gate driver including a P-channel current mirror.

Fig. 19 is a circuit diagram of a gate driver including a circuit for converting a reference voltage into a reference current to control the magnitude of a current in a MOSFET in a low current state.

Fig. 20 is a circuit diagram of a gate driver including a circuit to obtain a variable reference current to control the magnitude of current in a MOSFET in a low current state.

Fig. 21A is a circuit diagram of another gate driver including a circuit that obtains a variable reference current to control the magnitude of current in a MOSFET in a low current state.

Fig. 21B is a circuit diagram of a gate driver including a digital-to-analog converter that generates a variable reference current to control the magnitude of current in a MOSFET in a low current state.

Fig. 22A is a graph showing gate drive current as a function of drain current.

Fig. 22B is a graph showing gate drive current as a function of on-time.

Fig. 23A is a conceptual circuit diagram of a gate driver switching the gate of a MOSFET mirror between ground voltage and bias supply current.

Fig. 23B is a more detailed circuit diagram of the gate driver shown in fig. 23A.

Fig. 24A is a circuit diagram showing a gate driver using the present invention with an N-channel low-side MOSFET connected to a load.

Fig. 24B is a circuit diagram showing a gate driver of the present invention used with an N-channel high-side MOSFET connected to a load.

Fig. 24C is a circuit diagram showing the use of the gate driver of the present invention in a synchronous boost converter.

Fig. 24D is a circuit diagram showing the use of the gate driver of the present invention in a synchronous buck converter.

Fig. 25A is a circuit diagram showing a gate driver of the present invention used with a P-channel high side MOSFET connected to a load.

Fig. 25B is a circuit diagram illustrating the use of the gate driver of the present invention in a complementary buck converter.

Detailed Description

While the design and fabrication of power MOSFETs can be used to optimize or miniaturize the product of on-resistance and gate charge of devices used in power switching applications, power losses can also be minimized by limiting the amount of gate charge that moves during each switching transition. This task can be done in two ways-either by limiting the maximum gate drive to the point of optimization or by retaining (sustaining) some gate charge during the switching transition. The present application discloses ways to preserve some of the gate charge during subsequent (subsequent) switching cycles.

One embodiment of the invention is illustrated in fig. 5, where a circuit 200 illustrates the manner in which the gate of a power MOSFET203 that controls a load 204 is driven. The load 204 may include a voltage V_DDAny electrical component connected to or with V_DDA component of an electrical network connected and optionally connected to a ground voltage or to another voltage source. The input signal to the gate driver 202 is a logic signal output from a buffer or inverter 201, the buffer or inverter 201 having a voltage at a supply voltage V_ccAnd an output terminal for switching between the ground voltage and the ground voltage. In general, the supply voltage V_ccAnd V_DDIs not the same and is generally less than V_DDAlthough this need not be the case.

The gate driver 202 drives the gate-source terminal of the MOSFET203, repeatedly charging and discharging the gate with a voltage range smaller than that at the output terminal of the buffer 201. At gate voltage V_GSHIn the high or fully on condition of the MOSFET203 as indicated, the gate of the MOSFET203 is biased to the potential:

V_GS＝V_GSH＝V_cc。

thereby, the MOSFET is driven into its linear region, i.e. operated as a variable resistance, so that the drain current I is given by_D：

I_D＝V_DS/R_DS(on)。

Under such conditions, V_D＝V_DS<<V_GSAnd V_GS>>V_tWherein V is_tIs the threshold voltage of the MOSFET 203.

In contrast to the situation in a conventional gate drive circuit, in which the power MOSFET is biased in the second state to be fully "off" with its gate shorted to its source, in the technique of the present invention, rather than blocking (shutdown) the MOSFET203, it is biased in a low or partially on condition V_GSLThe gate potential is:

V_GS＝V_GSL＝V_BIAS。

suppose V_BIASIs small, typically close to the threshold voltage, then in this state, V is_DS>(V_GS－V_t) And the device is such that the drain current is relatively independent of the drain voltage V_DSSo that the drain current I is given by_D：

I_D＝I_DIAS∝V_BIAS。

Grid potential V_BIAS>0 is established by the bias supply 205 and the bias voltage 205 may comprise a fixed value reference voltage or a multiple thereof. Alternatively, V_BIASCan be used as V_ccIn multiples of (c). As shown, the gate driver 202 performs the selection of two possible gate potentials V_BIASAnd V_ccOne of the functions of a single pole double throw switch. In contrast to conventional methods of biasing the MOSFET gate, the gate of MOSFET203 is not driven to ground.

Typically, I_DBIASIs compared with the gate-source voltage V of MOSFET_gsMagnitude of leakage current through MOSFET equal to zeroAt least one or two orders of magnitude (i.e., 10 to 100 times) larger, and I_DBIASIs no more than one or two orders of magnitude less than the current in the MOSFET when it is in its fully on condition (i.e., 1% to 10% of it). Gate-source voltage V of MOSFET in its saturated low current state_BIASTypically in the range of 10% to 125% of its extrapolated threshold voltage, preferably in the range of 25% to 100% of its extrapolated threshold voltage. Extrapolated threshold voltages are defined in dieter k, schroder, semiconductor materials and device characteristics (1990), the contents of which are hereby incorporated by reference.

For gate bias of a few hundred millivolts above and below threshold, e.g. V_GS＝V_tWith a gate bias of 400mV, the saturated drain current changes dramatically. It is difficult to choose the gate bias that generates a particular desired drain current, especially when manufacturing variability is taken into account. Setting the voltage source 306 at a fixed value may result in a wide lot-to-lot (lot-to-lot) deviation in the saturated drain current in the MOSFET 308. Therefore with the fixed gate bias approach it must be possible to screen (screen) the product to fit a specific range of drain currents. For example, the screening limits for drain current of a 1W switching regulator with fixed bias used in portable applications may include the specified ranges shown in table 1:

TABLE 1

In low power applications (typically with drain currents in the range of 0.5A to 5A when the MOSFET is fully on), too much saturation current wastes power, which can result in lower overall converter efficiency if not compensated for by reducing diode recovery losses (offset). In high power converters (typically with drain currents in the range of 5A to 50A when the MOSFET is fully on), such small losses are negligible and, even at higher bias currents, the noise gain can compensate for any efficiency impact penalty. Note that there are also lower limits; the benefits of the disclosed techniques in shunting diode current and reducing the charge stored in the diode are reduced or lost altogether if the drain current in the low current saturation mode falls below some specified value.

The switching waveforms of circuit 200 are shown in the graph of FIG. 6, with V plotted against time in graphs 220, 230, 240, and 250, respectively_IN、V_GS、I_DAnd V_DS. As shown in graph 220, input V to gate buffer 202_INAt ground voltage 221, i.e., 0V and V_ccAlternating between input voltages 223 at ground voltages 221 and V_ccThere are rapid transitions 222 and 224 between the input voltages 223.

The gate voltage V of the drive MOSFET203 shown in graph 230_GSIs at a voltage V_BIASAnd V_ccAlternating between, never reaching zero. As shown, V_GSTransitions 232 and 234 and V in_INTransitions 222 and 224 in (a) are synchronous and in phase, but the polarities may be opposite. And V as shown_GSPulse-to-pulse, drain current I in semi-logarithmic plot 240_DAt a quantity I_DBIASMinimum current 241 and magnitude (V)_DS/R_DS(on)) Alternates between a minimum current 241 and a maximum current 243, there being transitions 242 and 244 between the minimum current 241 and the maximum current 243.

The drain voltage V across the MOSFET203_DSIn magnitude (V)_DD-V)≈V_DDMaximum voltage 251 and magnitude (I)_D·R_DS(on)) Alternates between the minimum voltages 253. Voltage V carrying a small current I across_DBIASThe voltage drop of the load 204. If I_DBIASBelow 1mA and preferably in the range of 1 to 100 mua, then the power dissipation in the MOSFET203, i.e.,

P_BIAS＝I_DBIAS·(V_DD-V)≈I_DBIAS·V_DD

and can be ignored. Power in saving gate drive losses is achieved by limiting the gate drive voltage range and thus limiting the swing of the gate charge.

Minimize gate charge swing: the concept of power conservation described above is illustrated in graph 280 of FIG. 7, which includes V_GS(on the left y-axis) and V_DSRelative to gate charge Q (on the right y-axis)_GGraph (on the x-axis). The solid lines indicate the range of gate and drain voltages in devices operating in accordance with the present invention, while the solid and dashed lines together indicate the same range in devices operating using conventional gate drive techniques.

Specifically, in conventional gate drive, the gate charge starts at zero and then increases to point 287 along curves 281, 282, 283, and 284. If input V_ccIncreasing, then the maximum gate charge Q_GHWill increase further along the straight line 285 beyond point 287. As the gate charge increases, the corresponding drain voltage is driven from V in the off state of the MOSFET203_DDThe move is started and then via curves 290, 291 and 292 to the on-state of MOSFET203 at point 294. If the input voltage V is_ccIncrease, then even Q_GLinearly increasing in this region, voltage V_GSWill also fall along curve 293 only slightly below point 294.

In conventional switching applications, all of the charge on the gate of the MOSFET during turn-on drains to ground during turn-off. The total gate charge corresponds to charging the gate to V_CCAnd then discharged to ground, resulting in a large "swing" of the gate voltage and gate charge. The gate charge swing is defined herein as:

ΔQ_G≡Q_GH-Q₀＝Q_G(V_GH)-0。

then, for the conventional gate drive method, the total gate charge swing is:

ΔQ_G＝Q_G(V_cc)-0＝Q_GH。

referring again to the graph 280 in fig. 7, when the gate is driven in accordance with the present invention, the gate charge follows curves 283 and 284, alternating only between points 286 and 287. Then, the improved gate charge swing Δ Q 'is given by'_G:

ΔQ′_G≡Q_GH-Q_GL＝Q_G(V_GH)-Q_G(V_G(on)). Wherein Q is_GL>0. Because (Q)_GH–Q_GL)<Q_GHSo less gate charge is required to switch at a given frequency and charge or (Q) is passed along the path from zero to point 286_GL–Q_G0)＝Q_GLThe power required to drive the gate is proportionally reduced.

To better illustrate the reduced gate charge swing, the method of the present invention may be represented as Q, as illustrated in graph 320 of FIG. 9_GGraph with respect to time, wherein the change in charge appearing on the MOSFET gate is at magnitude Q with charge and discharge transitions 322 and 324_GL(Curve 321) and magnitude Q_GH(curve 323). Since there is always some minimum charge Q left on the device gate_GLThe charge represented by area 325 is preserved from one cycle to the next, correspondingly increasing the efficiency of the gate drive.

Minimize average power loss: as previously mentioned, the power loss associated with driving a gate in accordance with the present method is given by:

P_drive＝(Q_G·V_G)/T＝Q_GH·V_GH·f。

then, the corresponding power savings P associated with the reduced charge during high frequency MOSFET gate drive_GsavedIs given by:

P_Gsaved＝(Q_GL·V_G(on))/T＝Q_GL·V_G(on))·f。

referring again to graph 280 in FIG. 7, when using the techniques of the present invention, the drain voltage V_DSThe cut-off operating region represented by the (skip) curves 290 and 291 is skipped by changing from point 296 to point 294 along the curve 292. At point 294, the voltage across the power MOSFET is represented by I_D·R_DS(on)It is given.

Further illustrated in FIG. 8 is current I_DAnd the drain voltage V_DSIn which a switching waveform 303 of a switching converter such as the buck converter 1 is superimposed on a signal representing the gate voltage V_SG0To V_GS5On the mosfet i-V curve family. The slave gate voltage is equal to V_GS0And I_D>Starting at point 301 of 0, the gate of the MOSFET is biased in its saturation region 305 and V_DSWhile relatively constant, the current follows V along curve 302_GSAnd (4) increasing. The gate voltage V represented by the I-V curve 306_GS3Hereinafter, the drain voltage V_DSChanges along curve 303 until the MOSFET operates in its linear region of operation 307, at which time V_DSContinues to fall along curve 304 but I_DSubstantially unchanged. The gate discharge process transitions in opposite directions between the two same endpoints 301 and 304.

For an on-time T in each cycle of the period T_onThe average power loss for the fully on condition of (a) is given by:

wherein D ≡ t_on/T。

Referring again to FIG. 7, at point 296, a low current condition, i.e., the voltage across the MOSFET203 is represented by V_DS＝(V_DD-V)≈V_DDIs given and is in the duration t_sat＝T-t_onThe corresponding power losses during this period are:

the total conduction loss in the power MOSFET is then the conduction loss P when the MOSFET is biased to be fully on in its linear region_condAt interval t with the MOSFET in its saturation operating region_satDuring which the bias current I_DBIASInduced power loss P_BIASAnd is, or

Wherein T ═ T_sat+t_on) And it is varied from cycle to cycle in variable frequency operation, or in fixed frequency operation with duty cycle D:

P′_cond＝I_D ²·R_DS(on)·D+I_DBIAS·V_DD·(1-D)。

using the disclosed technique, the total conduction and gate drive losses in the device are then given by:

wherein the term with square brackets represents gate drive and conduction loss P using conventional gate drive techniques_loss. Substituting this term yields the following relationship:

where T varies from cycle to cycle in variable frequency operation, or for fixed frequency operation,

P′_loss＝[P_loss]+(I_DBIAS·V_DD·(1-D))-(Q_GL·V_GL·f)。

for the disclosed process, power P 'is conserved'_loss<P_lossAnd therefore, the first and second electrodes are,

this means that the power saved by reducing the gate drive must be compensated by the bias current I_DBIASAny additional power consumed by the resulting increased conduction losses. When at a fixed frequency f and duty cycle D ≡ t_onIn the case of/T operation, the equation can be expressed as:

(I_DBIAS·V_DD·(1-D))＜(Q_GL·V_GL·f)。

power saving in reduced gate drive versus increased power consumption P due to bias current_BIASMore beneficially, at higher frequencies f and for lower V_DDThe input condition more easily satisfies this condition.

Is difficult to be aligned with I_DBIASRelative to Q_GL·V_GLThe relationships between make any general conclusions as they are relevant and dependent on the manufacturing process and design of a particular power MOSFET. Increasing Q in a driver circuit for a given device_GL·V_GLI.e. increasing V_BIASWill reduce gate drive loss but also make I_DBIASIncreasing and increasing the conduction losses. Thus, the bias conditions for optimized power savings are technology specific.

The duty cycle D is specific for each switching application. For example, in the step-down buck converters shown in fig. 1A, 1B, and 1C, the duty cycle of high-side MOSFETs 2, 11, and 21 is set to D-V_out/V_inGiven therein, V_in＝V_DD. Substituting this expression gives us the specific conditions for the buck regulator when the disclosed reduced gate drive method is beneficial:

(I_DBIAS·(V_DD-V_out))＜(Q_GL·V_GL·f)。

this equation means that the disclosed low gate drive loss technique is not as beneficial as the difference between the output voltage and the input voltage of the buck converter increases.

For a boost converter, as shown in FIG. 1D, the conversion ratio V_out/V_in1/(1-D), where D reflects the on-time of low-side MOSFET 31. Rearranging and using V_in/V_outSubstitute (1-D) for IThey present specific conditions for the boost regulator when the disclosed reduced gate drive method is beneficial:

in boost converters, i.e. at V_out>V_inThe disclosed method is more beneficial when generating a larger output voltage from a lower input voltage.

Referring again to the graph 280 in FIG. 7, when the MOSFET203 is operating in its linear region, V is connected across the MOSFET203_DSThe voltage drop almost reaches its minimum at point 295. In the operation described, the gate drive circuit "overdrives" the MOSFET to the gate bias 294, although with minimal benefit in reducing on-resistance or voltage drop. It is not easy to achieve prevention of the gate from being overdriven since the gate of the MOSFET is partially charged to less than V_ccCauses the same power losses to occur elsewhere in the circuit and does not result in an increase in efficiency.

Reduced gate drive loss circuit with shutdown (shutdown) mode: fig. 10 illustrates another embodiment in accordance with the present invention. In many applications, when the power MOSFET is not switched, for example, when the computer is in a standby or sleep mode, it may be desirable to provide a power MOSFET that is capable of providing a high voltage output when the power MOSFET is not switchedExtended periods of time can occur. Under such operating conditions, any conduction current from the battery through the load and power MOSFET, even as I_BIASSuch a small amount of on-current will discharge the battery over time. A solution to the problem of extended off-times is to modify the disclosed invention to include an off-mode.

Circuit 350 illustrates a general description of the disclosed power MOSFET augmented with reduced gate drive loss with increased off-mode characteristics. Similar to circuit 200 of fig. 5, circuit 350 includes a gate driver 352, but in this case, gate driver 352 does not have two states, but rather has three states, namely, fully conductive with low resistance, saturated, and biased at V_BIASTo turn on a small fixed current and to turn off completely with low leakage current. Accordingly, gate driver 352 has two inputs, namely IN to receive a logic or PWM signal, and an enable pin to turn off the device.

As shown, the output of buffer 351 will range from V_ccA signal to ground, i.e., a digital signal switched from rail to rail, is fed to the "IN" input of gate driver 352. Whenever the enable terminal is biased to its "on" state, gate driver 352 responds to the signal on its "IN" terminal, and the output of gate driver 352 is at V_ccAnd V_BIASVoltage V alternating therebetween_GS1To drive the gate of MOSFET 353. The power MOSFET353 in turn provides the gate drive voltage V to the load 354_ccAnd V_BIASA determined current alternating between a high and a low drain current. As previously described, during high frequency operation, the voltage is controlled by biasing the gate of MOSFET353 to not less than V_BIASFrom cycle to cycle, preserves gate charge and reduces gate drive loss. Provided that the power savings achieved by limiting the gate charge swing is greater than the minimum drain current I during switching_BIASIncreased conduction losses, and thus increased efficiency.

When the enable signal is turned offWhen, the gate driver 352 switches to connect the gate of the MOSFET352 to ground, i.e. to its source and V_GS1A third state of 0. The drain current in power MOSFET353 is then reduced to I of the device_DSSLeakage current, i.e., leakage current from the junction of the drain to the source with the gate connected to the source. Even if the current I_BIASVery small, preferably in the range of microamps to tens of microamps-I_DSSEven less, preferably less than one microampere or even more than I_BIASSeveral orders of magnitude smaller.

Three conditions are illustrated and compared in fig. 11A-11F and summarized in table 2 below. In FIG. 11A, gate driver 361 biases the gate of MOSFET353 to V_GS＝V_ccAnd the device is fully on in the linear operating region of the MOSFET, i.e., as shown in the I-V plot 365 of fig. 11B, as a gate controlled variable resistance. The drain current and voltage in this region and at point 366 obey ohm's law, i.e., V_DS＝I_D·R_DS(on). In many power circuits, I_DIs determined by a voltage divider of the power MOSFET with other components in the circuit, in which the drain current I_D＝V_DS/R_DS(on)And the drain voltage V_DSProportionally. In circuits with inductors or other current sources switched at high frequency, I_DIs influenced by the circuit and V is adjusted accordingly_DS。

In the second state shown in fig. 11C, the gate buffer 371 biases the gate of the power MOSFET353 to a value V set by the voltage source or reference voltage source 355_GS＝V_BIAS. Then, as shown by point 376 in fig. 11D, MOSFET353 turns on drain current I_D＝I_BIAS. In this mode, the drain current I_DRelatively "constant", which means that it shows a relationship with V_DSMinimum dependency of the values. However, the drain current I_DStrongly dependent on the gate bias V_BIAS。

In the third state shown in fig. 11E, the gate buffer 381 will be MThe gate and source of the OSFET353 are shorted so that V_GS0. Assume that N-channel MOSFET353 is a MOSFET having a positive threshold voltage, i.e., V_th> 0, then, as illustrated in FIG. 11F, at V_GSOn 0, the device is off, with the drain current I in the off state_DSSCaused by junction leakage current. Albeit for V_DDThe reverse bias at point 386 appears to be zero, but the actual I plotted on the semi-logarithmic graph_DSSLeakage current may show some voltage dependence, but in general leakage current remains well below 1 μ Α within a specified drain voltage range of the power MOSFET.

The operating conditions of the tri-state gate driver and power MOSFET according to the invention are summarized in the following truth table:

IN	EN	VGS	MOSFET operation	Drain current	gDS
						H	H	Vcc	Linear region of motion	ID＝VDS/RDS(on)	1/RDS(on)
L	H	VBIAS	Saturation region	ID＝IDBIAS	Constant of
						H/L	L	0	Cut-off	ID＝IDSS	Constant of

TABLE 2

Table 2 reveals that when the enable terminal is biased to a high state, the power MOSFET is turned on depending on the logic input IN, but when the enable terminal is IN a low state, the MOSFET is turned off and the operation is not dependent on the IN signal. Will output conductance g_DS≡dI_D/dV_DSIncluding as a qualitative measure of drain voltage sensitivity.

In a preferred embodiment, the output V of the gate driver driving MOSFET353 during high frequency switching, as shown by square waves 411, 412, 413, and 414 in graph 410 of FIG. 12A_GSAt V_ccAnd V_BIASAlternate between them and follow logical input voltage transitions 404, 405, 406, and 407 as shown by the arrowed lines of graph 400. During this time, the enable signal EN shown by the dotted line is maintained at the high level V_ccUpper (curve 401). Similarly, as shown in the semi-logarithmic graph 420, as shown in the square waves 421, 422, 423, and 424, the drain current I_DFrom I_DBIASSwitch to V_DS/R_DS(on)And as shown in graph 430, the drain voltage V_DSAt waveforms 431, 432, 433 and 434 (V)_DD-V) and I_D·R_DS(on)Alternating between them.

At time t_sleepAs MOSFET353 enters sleep or off mode, signal V will be enabled_ENPull low (curve 402) and bias at zero volts (curve 403), coupling V_GSDriven down (curve 415) to zero volts (curve 416) with gate voltage below V_BIAS. In the off mode, the drain current I is shown in graph 420_DDecrease (curve 425) to a leakage current I of a magnitude close to zero_DSS(curve 426). Also, as shown in graph 430, during the switching of MOSFET353, V_DSJumping (curve 435) to voltage V illustrated by curve 435_DDSlightly higher than the maximum drain voltage (V) shown by curve 434_DD--V)。

In an alternative embodiment, as illustrated in fig. 12B, gate driver 352 may alternate between two different switching waveforms. As shown in graph 440, at time t₁Previously, the voltage output of gate driver 352 was at V_ccAnd V_BIASAlternating between them. At low Q of the gate driver according to the invention_GDuring the gate drive operation (region 441), the minimum gate drive is the bias voltage V_BIAS>0 (curve 442).

As previously mentioned, although the disclosed low gate charge gate drive techniques may improve efficiency under certain conditions, due to the bias current I that is present_DBIASThe associated conduction losses cause power losses that may reduce efficiency. If such a condition occurs, the operation of circuit 350 may be dynamically altered so as to facilitate therein at time t₁At gate voltage V_GSAt V_ccConventional rail-to-rail gate drive alternating with ground (curve 444) (region 443). The benefits of reduced gate charge swing are lost in the rail-to-rail spacing. At time t_sleepHere, the gate of the MOSFET is grounded 445 for some indefinite time corresponding to the sleep mode.

During rail-to-rail operation, as shown in FIG. 12CAs shown in graph 446, the circuit 350 may be operated to reduce noise associated with turn-on. During "soft switching" rail-to-rail operation (region 447), the gate voltage is driven to V during each on transition_cc(curve 449) first rises briefly to V_BIASA small duration (curve 448). The stepped (standing-stepped) gate waveforms of curves 448 and 449 reduce the slew rate (slewrate) of the waveform at the drain of MOSFET353 and may beneficially reduce noise.

Implementing tri-state low loss gate drive: fig. 13A-13E illustrate several circuits implementing power MOSFET gate drive with reduced drive losses. In fig. 13A, a complementary MOSFET gate driver comprising a high-side P-channel MOSFET451 and a low-side N-channel MOSFET453 drives the gate of a power MOSFET 454. N-channel pass transistor 452 also couples the gate of MOSFET454 to a reference voltage V provided by a reference voltage source 455_refAnd (4) connecting. The gate voltage on MOSFET452 must be sufficiently positive with respect to its source voltage to turn MOSFET452 on. Controlled by appropriate timing and logic circuitry, only one device is turned on at a time. When the high side MOSFET451 is turned on, V_GS＝V_battAnd MOSFET454 operates in its linear region. When MOSFET452 is turned on, V_GS＝V_refAnd biases MOSFET454 as a current source. When the low side MOSFET453 is turned on, V_GSAnd MOSFET454 is turned off.

As shown, the body of MOSFET452 is grounded. The grounded case is required to prevent the parasitic diode in MOSFET452 from conducting, since the gate voltage V depends on the state of MOSFETs 451 and 453_GSCan be greater or less than V_refThe value of (c).

By grounding the housing of MOSFET452, parasitic body diodes 457A and 457B remain permanently reverse biased. If the body of MOSFET452 is not grounded but instead incorporates an (incorporatate) source-body short, one of these diodes will be in parallel with the channel of MOSFET452, similar to diode 456 in parallel with MOSFET 454. The source-drain parallel diode is under one of various gate bias conditions, i.e., whenV_GS>V_BIASWhen V or when V_GS<V_BIASIt will become forward biased.

Other circuit techniques, such as the housing offset generator or "body picker" shown in fig. 13B, may be used to avoid this problem. As shown in circuit 460, pass transistor 462 includes parasitic PN junction diodes 469A and 469B. To prevent either diode from conducting, the network of two cross-coupled N-channel MOSFETs 468A and 468B biases the body potential of MOSFET462 so that whichever diode becomes forward biased is shorted out by the shunt MOSFET, leaving the other parasitic diode reverse biased or non-conducting.

For example, if V_GS>V_BIASThen diode 469B is forward biased and diode 469A is reverse biased. Due to V_GSBeing the more positive terminal, the N-channel MOSFET468B turns on and shorts out the forward biased diode 469B, taking the body of the MOSFET462 to its more negative V_BIASTerminal connected, turning off MOSFET468A and having diode 469A reverse biased and connected in parallel with MOSFET 462. As a symmetrical circuit, whenever the polarity is reversed, the device switches state and diode 469B becomes reverse biased and connected in parallel with pass transistor 462. The body bias generator technique may be applied, for example, to any pass transistor in the circuit 450. A pass transistor is defined herein as a MOSFET with neither the source nor the drain connected to a fixed power rail.

Circuit 460 is similar to circuit 450 except that cross-coupled MOSFETs 468A and 468B replace fixed reference voltage 455 with a digital-to-analog converter 465. The output of the D/A converter uses the digital control of converter 465 to adjust V_BIAS. As shown, the voltage output by the data converter 465 is up to a maximum amount V supplied by the reference voltage source 466_ref. Otherwise, circuit 460 of fig. 13B utilizes a complementary MOSFET gate driver including a high side P-channel MOSFET461 and a low side N-channel MOSFET463 that drives the gate of power MOSFET464 whenever N-channel pass transistor 462 is turned off. As before, the gate of MOSFET462 is opposite its sourceMust be biased positive enough to turn on the MOSFET 462.

Fig. 13C illustrates an embodiment of a D/a converter-driven power MOSFET having low drive losses made in accordance with the present invention. As shown in circuit 470, the gate of power MOSFET471 is powered by a multiplexer that includes only one N-channel and/or P-channel pass transistor 472, 473, 474, and 475 that can be turned on at a time. Low side MOSFET475 biases the gate of power MOSFET471 to V_G0At 0 or ground voltage, pass transistor MOSFET474 biases the gate of power MOSFET471 to V_G1＝V_BIAS1The pass transistor MOSFET473 biases the gate of the power MOSFET471 to V_G2＝V_BIAS2And high side MOSFET472 biases the gate of power MOSFET471 to V_G3＝V_batt. The housing biasing techniques described above may be employed if desired.

FIG. 13D illustrates another D/A converter driven power MOSFET in which the bias condition is generated by including resistors 496A, 496B, and 496C to generate a bias point V_G2And V_G1Is determined by the resistor divider network. The resistors are sized to set the bias point, e.g. V_G2＝V_batt·(R₂+R₃)/(R₁+R₂+R₃). Selecting V using an analog multiplexer containing MOSFETs 492, 493, 494, and 495_GSThe gate voltage. As shown, V_GS3＝V_batt，V_GS00, and an intermediate bias condition between these gate voltage values. Any number of resistors may be used to form the voltage divider network.

Alternatively, as shown in fig. 13E, a combination of a forward biased diode and a resistor may also be used. The voltage divider network need not contain a linear step (step), but may include greater resolution around the target bias voltage. All of the D/A converter gate drive methods described above provide for setting I during manufacture or during operation_DBIASSome degree of control of the value.

Using reduction of circuit feedbackThe gate drive loss circuit of (1): although setting I is provided_DBIASDifferent degrees of flexibility in value, but the above-described circuit and gate drive method employ a fixed bias voltage without automatically compensating for variations (variations) in the power MOSFET caused by manufacturing or operating condition changes.

For example, fig. 14A illustrates a circuit 550 implementing the gate driver 202 shown in fig. 5. As shown, the gate of power MOSFET556 is composed of an AND gate_ccThe connected high side P-channel MOSFET553 and source are biased at a reference voltage V provided by a voltage source 555_BIASCMOS driver drive of upper N-channel MOSFET 554. When MOSFET554 is biased in its low current ON state, then V_GS1＝V_BIASAnd a drain current I_DAnd (V)_BIAS-V_t) And (4) in proportion. Due to V_tWith temperature and with batch manufacturing, and the current varies accordingly.

To remove the effects of this variation, circuit 580 in FIG. 14B includes I_DCurrent feedback circuit 90, I_DCurrent feedback circuit 90 uses amplifier 588 to dynamically adjust the reference voltage V provided by reference voltage source 585_BIASTo force the drain current I_DReference current I provided for current source 589_refMultiples of (a). The magnitude of the drain current is measured by current sensor 590 and passed to the negative input of amplifier 588. The feedback stabilizes the output current. For the current I_DAny increase to amplifier 588 causes the negative input to amplifier 588 to decrease the output of amplifier 588, decreasing V_BIASAnd decrease I_DThereby compensating for the increase in current.

The net effect (neteffect) is shown in graph 600 of fig. 14C, in which the threshold voltage of the power MOSFET is plotted against the drain current I_DBIASThe influence of (c). When there is no feedback, V is shown by curve 602_t1Results in a drain current I_DIs reduced by a commensurable (commensurate). Instead, with feedback, the drain current 601 remains constant. The effect of the feedback is further illustrated in FIG. 14D, where I_DRelative to V_DSThe graph of (a) dynamically adjusts the gate bias to reduce the over current 607A to its target value 606 or, conversely, to increase the under drain current 607B to the target value 606.

In the embodiment of the invention shown in FIG. 15A, I is implemented using sense resistor 615B_DAnd (4) feedback of drain current. Voltage drop V across resistor 615B_sReference voltage V provided by operational amplifier 618 with respect to voltage source 619_REFPerforming differential amplification to generate a voltage V_BIAS. The bias voltage V is applied whenever the MOSFET614 is biased in an on-state condition_BIASDriving the gate of power MOSFET 616. The current sense resistor 615B increases the overall resistance in series with the electrical load 617 and thus reduces efficiency.

In another embodiment of the invention shown in fig. 15B, the improved circuit 620 utilizes a current mirror that includes a power MOSFET626A of gate width n · W and a sense MOSFET626B of gate width W, the power MOSFET626A and the sense MOSFET626B having common gate and source terminals and separate drain connections. Power MOSFET626A controls current I through load 629 under the gate control of a CMOS gate driver comprising a P-channel MOSFET623 and an N-channel MOSFET624_D. Operational amplifier 628 controls the current in current source 627, forcing the drain voltage V of MOSFET626B_βTo the same voltage as the drain of power MOSFET 626A. Assume V for MOSFETs 626A and 626B_GSSame when V_α＝V_βThe currents in the two devices are in a ratio determined by their relative gate widths n · W and W, respectively. Accordingly, when the power MOSFET626A turns on the drain current I_DRegardless of whether the MOSFET is in its linear or saturation operating region, from I_sense＝I_DThe sense current dependent on current source 627 is given by/n.

Sensing the current I_sense627 is mirrored to the current source 630 and transformed to a voltage V across the sense resistor 631_sense. Unlike resistor 615B in circuit 610, sense resistor 631 has no effect on increasing the resistance in series with load 629. Then, the voltage V is sensed_senseThe reference voltage V provided by amplifier 623 with respect to voltage source 632_REFDifferential amplification, generating an output voltage V at the source of MOSFET624_BIAS. Whenever V_GS1＝V_BIASWhen, i.e., when MOSFET624 is on and MOSFET623 is off, the current sensing circuit and bias network form a closed loop with negative feedback for the low drain current condition I in power MOSFET626A_BIASProviding stable control. Drain current I in MOSFET626A_DAny increase in (b) results in I being supplied by current source 627_senseThe current increases to balance the voltage. This in turn causes a current I_mirrorIncreases and makes V applied to the negative input terminal of the operational amplifier 633_senseAnd (4) increasing. Larger negative input signal makes V_BIASReduced, resulting in V at power MOSFET626A_GSReducing and compensating for the increased current, thus maintaining I despite deviations (variations) in temperature or manufacturing_DIs constant.

One advantage of the current mirror circuit 620 over the circuit 610 is that it does not introduce any additional voltage drop in series with the electrical load 629 and thus improves the efficiency of energy transfer from the power supply to the load 629. Unlike the sense resistor technology embodied in circuit 610, the current mirror approach embodied in circuit 620 can only be used with common source split drain MOSFETs such as MOSFETs 626A and 626B, whose drains may be separately connected. It cannot be used with common-drain devices such as trench-gated (gated) vertical DMOS or planar vertical DMOS.

Alternatively, the circuit 650 shown in fig. 15C may be employed to accurately monitor the drain current in the discrete power MOSFET656 without introducing a large resistance sense resistor in series with the load 657. The sense current 660 is then used to control I during low current conduction_DBIASAnd for sensing a short circuit condition in a high current low resistance state. An application entitled "CascodeCurrentSensorForDiscretepowerSemiconductors" filed concurrently with this application and incorporated herein by reference [ attorney docket No. AATI-26-DS-US]Therein describedA method for influenza detection.

Specifically, as shown in fig. 15C, the gate bias applied to the power MOSFET656 is controlled by a gate driver including a P-channel MOSFET653 and an N-channel MOSFET 654. Grid potential V_GSMay contain V when operating in a low resistance condition_ccOr may contain V when operating in a low current state_BIAS. Controlling voltage V using feedback_BIASTo generate a desired output current I_DBIASRegardless of operating conditions or variations in manufacturing processes. Current sensing is achieved using a low resistance low voltage MOSFET658A with a gate width n · W in series with a power MOSFET 656. The power MOSFET656 may comprise low or high voltage devices and need not be integrated with other component parts in the circuit 650. The current sensing element comprises a current mirror MOSFET658B that is monolithically fabricated with a larger MOSFET658A and shares the gate width W of the common source and separate drains.

In a preferred embodiment, the gates of both MOSFETs 658A and 658B are biased to supply voltage V_ccAnd are therefore biased into their low resistance linear operating region. Even at high I_DOn drain current, the low resistance of MOSFET658A also ensures the voltage V at the drain of MOSFET658A_αAnd remains low. The drain voltage of MOSFET658B is designated V_β. Differential amplifier 659 controls the current I in the dependent current source 660_senseUntil the drain voltages of MOSFETs 658A and 658B are equal, i.e., V_β＝V_α. Under such conditions, I_sense＝(I_D/n) and accurately measures the current I flowing into the power MOSFET656_DRegardless of its bias condition.

I is divided using a current mirror 661 in series with a sense resistor 664_senseIs mirrored as a proportional current I_mirrorTo generate a and V_αProportional sensing voltage V_sense. Because of the voltage gain of the operational amplifier 659 despite the fact that the voltage V is_αSmall but can make the signal V_senseIs large. V_senseIs controlled by the operational amplifier 663 relative to the voltage source 662 generated reference voltage V_BIASAnd (4) differential amplification.

In closed loop operation, when MOSFET654 is on and MOSFET653 is off, the output of amplifier 663 is at I_DEqual to the target current I_DBIASWhen has a value of-V_BIASThe output voltage of (1). If I_DToo small, current I_mirrorWill also decrease, thereby decreasing V to the negative input of operational amplifier 663_senseA voltage. The lower negative input voltage causes the output voltage of amplifier 663 to increase, which in turn drives the gate of power MOSFET656 to a higher bias, I_DIncreasing to its target value.

When the N-channel MOSFET654 is off and the P-channel MOSFET653 is on, the power MOSFET656 is biased to its high current state and ignores the reduced output of the operational amplifier 663 across the resistor 655. The voltage V can still be used for short-circuit and overcurrent protection purposes_senseTo monitor the current I in MOSFET658A_D. As shown, the voltage V is passed through a hysteresis comparator 670_senseWith a reference voltage V provided by a voltage source 671_refAnd (6) comparing. When V is_senseExceeds V_refTime, current I_DToo high and the overcurrent is off, i.e., OCSD comparator 670 generates a high logic output signal that informs the system that an overcurrent condition has occurred and that power MOSFET656 should be turned off.

Thus, by utilizing a current sensing technique including a sense resistor, a current mirror, cascode current sensing, or any other method, and by combining the current sensing technique with negative feedback to adjust the gate bias V_BIASCan accurately control the drain current I_DBIASThe value of (c). By controlling I_DBIASCan also be controlled in accordance with the method of the present invention and in accordance with the graph of fig. 9, the minimum gate charge Q remaining on the power MOSFET gate during the low state of each switching cycle_GLTo minimize gate drive loss.

Circuit with reduced gate drive loss with current trimming: although the above technique uses current inversionIs fed to set I_DBIASThe value of the low current condition, but for many applications, current accuracy and circuit complexity may be more than required. A MOSFET due to saturation has a drain current given by the equation:

I_D＝k(V_GS-V_t)²，

the drain current is proportional to a transconductance factor and is proportional to (V)_GS-V_t) Is proportional to the square of the threshold voltage, the most dominant process parameter affecting the saturation current. Also, precise current control can be reasonably achieved by electrical fine tuning of the circuit to compensate for threshold variability as part of the fabrication process.

As shown in fig. 16A, a power MOSFET gate driver 701 with low drive loss made in accordance with the present invention is utilized at V for low resistance operation_ccAnd V for low current conduction_BIASAlternating voltages therebetween to drive the gate of the power MOSFET 702. Fixed voltage source 706 sets V_BIASThe value of (c). After manufacture, the current I is measured by a test device_DAnd use it to adjust the fine tuning network 705 until I_DMeasured value of (D) and bias current I_DBIASIs matched. This calibration is preferably performed at room temperature.

Since saturation current also varies with temperature, primarily due to threshold voltage, optional temperature compensation circuit 709 may be used to adjust V_BIAS706 to hold I_DSemi-constant for temperature.

The fine tuning gate drive circuit 720 shown in fig. 16B includes a gate driver having MOSFETs 721 and 722, a power MOSFET724, and a load 725. Bias voltage V for the remaining components for implementing trimming_BIASIncluding providing a reference voltage V_refA reference voltage source 726, a resistor divider network 728 including resistors 728A and 728B and 729a-729e, one-time programmable (OTP) MOSFETs 730a-730e, bias multiplexers 731a-731e, and an OTP programmer 727. Resistors 728A and 728B each have a value R_AAnd R_B。

The OTPMOSFETs 730a-730e exhibit a ratio V after fabrication_ccMuch lower normal threshold voltage. During operation, multiplexers 731a-731e bias the gate of each of the OTPMOSFETs 730a-730e to V_ccEach of the OTPMOSFETs 730a-730e is turned on and one of the resistors 729a-729e in parallel therewith is shorted out. For example, in the unprogrammed state, the OTPMOSFET730c has a threshold of 0.7V. When the multiplexer 731c connects the gate of the OTPMOSFET730c with V_ccWhen connected, it turns on and shorts out the corresponding resistor 729 c.

In the unprogrammed state, all resistors 729a-729e are shorted out so that V is passed through resistor divider 728_BIASThe method comprises the following steps:

programming involves connecting the gate of any given one of the OTPMOSFETs 730a-730e to the programmer 727 and biasing the device to saturation at a high voltage. This process generates hot carriers and permanently charges the gate oxide, increasing the threshold voltage of the device to a higher value so that under normal operation, the OTPMOSFET is non-conductive. Thus, the parallel resistor 729a-729e is inserted into the voltage divider 728, adjusting the resistor divider ratio and V_BIASThe value of (c). The values of resistors 729a-729e may be the same or different, such that trimming may be linear or non-linear. Dependent on resistor 729a-729e, the trim output may range from up to V_refTo a fraction V thereof_refAnd/m. Such as shown in fig. 16C, the codes may be arranged in any number of combinations. As shown, the codes C1 through C8 correspond to various resistor combinations that depend on those resistors shorted by the unprogrammed OTPMOSFETs 730a-730 e. Code C1 goes from V at the lowest voltage_BIASBegins (line 741) and increases (line 742) with the various bits programmed by turning off individual ones of the OTPMOSFETs 730a-730 e. An alternative pattern, indicated by line 743, uses a non-linear step and is of magnitude V_refEnds with the maximum voltage (straight line 744).

Although many specific programming sequences are possible, the method for trimming V is shown in FIG. 16D_BIASGeneral programming algorithm 780 where the voltage V will be fixed_DSApplied to operate at low current, i.e. I_DBIASPower MOSFET724 in the state. After this bias is applied in step 781, the drain current I is measured in step 782_DAnd the drain current I is converted to the drain current I in step 783_DAnd I_DBIASAre compared within a certain tolerance. If the current is too low, one or more of the OTPMOSFETs 730a-730e are programmed in step 784, increasing V_BIASAnd I_D. The process is then repeated (step 785) until I is measured_DTo achieve I_DBIASThen the program terminates (step 786).

In FIG. 16E is shown I_DBIASExample of programming, wherein the manufactured product has a quantity I_initial(line 801) and the current increases during each iteration until reaching exactly I_DlowTo I_DhighIs shown as a straight line 802 outside the target range. In the fifth iteration, the current is increased to a value within the target range, represented by line 804, and the process is terminated. While this procedure can be performed at room temperature, the same procedure can also be used at higher temperatures.

Alternatively, the braiding may be performed at two temperaturesThe equation-one is to correct for errors in the initial current, and the other is to fine tune to compensate for the effects of threshold variations with temperature. The temperature compensation circuit 709 in FIG. 16A may assume a certain temperature coefficient, for example, at-3 mV/deg.C, to avoid the need for trimming at high temperatures. In any event, fine tuning was used to increase I_DBIASAnd thus more closely control the gate charge swing of the MOSFET 702.

Reduced gate drive loss circuit with current mirror drive: in the above-mentioned technique, I_DBIASThe magnitude of (d) depends on the threshold of the power MOSFET. In one case, active trimming is used to adjust V_BIASTo generate I_DBIASThe target value of (2). In another case, current feedback is employed to force I in closed loop operation_DTo a target value I_DBIAS。

In another embodiment of the present invention, a reduced gate drive loss circuit utilizes a gate drive technique that is insensitive to threshold fluctuations of the power MOSFET. One such method of eliminating sensitivity to threshold utilizes a current mirror gate drive circuit 820 shown in FIG. 17A. Without actually sensing the current, this technique employs the following principle: two MOSFETs monolithically fabricated will exhibit substantially matched threshold voltages and drain currents that are approximately scaled (scale) in proportion to the MOSFET gate width at saturation under the same gate drive conditions.

Specifically, MOSFETs 824A and 824B are monolithically fabricated as current mirror 830. The power MOSFET824A is a low resistance device with a large gate width n · W, while the current mirror MOSFET824B has a gate width W — one "n" times the gate width of the MOSFET 824A. The gate of MOSFET824A is driven from three inputs-V by gate driver 821_cc、V_BIASAnd option driving selected from the ground voltage. When selecting V_ccPower MOSFET824A is biased to operate in its low resistance state within its linear region. When a voltage is selected, the power MOSFET824A is turned off and no current flows.

When selecting V_BIASThe gate of power MOSFET824AThe pole drive is determined by a bias network comprising a current source 822 and a mirror MOSFET 824B. An equivalent circuit in this mode is shown in FIG. 17B, where the fixed current source 822 is selected or preset to supply the target current I_DBIASDivided by the width ratio "n". Let this current I_DBIASThe/n feeds into a MOSFET824B whose drain and gate are shorted, i.e., threshold connected. The threshold connected MOSFET824B is self-biased, meaning that it adjusts its gate voltage to the potential V needed to carry the drain current supplied by the fixed current source 822_BIAS. By definition, because of V_DS＝V_GSEnsures the saturation condition V_DS>(V_GS-V_t) Is always satisfied, the threshold connected MOSFET operates in its saturation region.

This V is_BIASThe voltage, i.e., the gate voltage of MOSFET824B, is also the gate voltage on high power MOSFET 824A. Provided that V is on MOSFET824A_DSIs very large, meaning I_DBIASNot too large, then it is also in saturation and the current in MOSFETs 824A and 824B should be scaled by the ratio "n". If current source 822 is preset to current I_DBIASN, then the current in the MOSFET824A and the load 823 should be:

I_D＝n·(I_DBIAS/n)＝I_DBIAS。

since the threshold voltages of MOSFETs 824A and 824B are closely matched, V occurs in both devices due to process variations or temperature_tAnd is suppressed as common mode noise. For example, if V is for any reason_tDown to (V)_t-ΔV_t) Then, V_BIASDecrease by a proportional amount to (V)_BIAS-ΔV_t). Gate driven slave (V) on MOSFET824A_BIAS-V_t) Change to the same value as the original condition:

(V_BIAS-ΔV_t)-(V_t-ΔV_t)＝(V_BIAS-V_t)。

thus, using current mirror gate drive cancels the effect of threshold variation.

Thus, secondary (secondary) factors such as short channel effects, series resistance, quasi-saturation, etc. cause the current to be set at I_DBIASAny error in (c). Trimming circuit 831 can be employed to adjust the value of current source 822 as part of the manufacturing process, if desired.

A current mirror gate drive circuit 860 without trimming is shown in fig. 18. The gate drive circuit 860 includes a current mirror MOSFET pair 861, a load 863, a tri-state gate driver comprising MOSFETs 864, 865, and 870, a break-before-make (BBM) buffer 866, and a bias current generator MOSFET pair 871 having a resistor 869. As shown, the power MOSFET862A may be biased in a low-resistance state when the P-channel MOSFET864 is turned on, may be biased in a fully off non-conductive state when the N-channel MOSFET870 is turned on, and may be biased at a low controlled current I when the N-channel MOSFET865 is turned on_DBIASIs saturated. Under the control of the BBM buffer 866, only one of the MOSFETs 864, 865 and 870 may be turned on at a time.

MOSFET pair 861 includes a power MOSFET862A having a gate width n · W and a small current mirror MOSFET862B having a gate width W. Using the voltage V on the gate and drain of MOSFET862B_BIASThe device conducts a drain current I_DBIASAnd/n. This current is established by current mirror 871, which includes P-channel MOSFETs 867 and 868. The threshold connected MOSFET868 conducts a current I set by the resistor 869 having a magnitude_ref：

Current I_refMirrored by MOSFET867 to drive MOSFET 862B. Given P-channel threshold voltage V_tpThe value R of the resistor 869 is adjusted to set this current to the target value I_DBIAS/n。

FIG. 19 illustrates a current mirror gate driver 880 made in accordance with the present invention using a supply voltage V_refReference voltage source 890 and resistor 889 implementing I_ref. Then, the current I is given by_ref：

Wherein the value of R is selected such that I_ref＝I_DBIAS/n。

Circuit 880 illustrates yet another embodiment of a tri-state gate driver. The gate driver includes a connection V driven by logic AND gates 892 AND 893 AND inverters 894, 895, AND 896_ccP-channel MOSFET884, connection V_BIASAnd an N-channel MOSFET885 connected to ground, and an N-channel MOSFET 891. Whenever the enable signal EN is in a logic low state, the outputs of the AND gates 892 AND 893 are low to turn off the MOSFET885 AND, inverted by the inverter 894, the output of the AND gate 892 biases the gate of the P-channel MOSFET884 high, turning it off. The low-level enable signal inverted by inverter 896 drives grounded MOSFET891 with a high gate bias, turning it on, and shorting the gate of power MOSFET882A to ground. In this state, MOSFET891 is on and MOSFET884And 885 is turned off.

When the enable signal EN is high, the output of the inverter 896 is low and the MOSFET891 is turned off. When EN is input as a high level to the AND gates 892 AND 893, their outputs depend only on the state of the input pin IN. When IN is high, inverter 895 drives the input AND output of AND gate 893 low AND turns off N-channel MOSFET 885. However, the high input drives the input AND output of AND gate 892 high AND is inverted by inverter 894, driving the gate of P-channel MOSFET884 low, turning on P-channel MOSFET 884. In such a state, MOSFET884 is on and MOSFETs 885 and 896 are off.

Conversely, when EN is high AND IN is low, inverter 895 drives the input AND output of AND gate 893 high AND turns on N-channel MOSFET 885. However, the low input drives the input AND output of AND gate 892 low AND is inverted by inverter 894, driving the gate of P-channel MOSFET884 high, turning off P-channel MOSFET 884. In such a state, MOSFET885 is on and MOSFETs 884 and 896 are off.

When combinational logic is used, only one of the three MOSFETs 884, 885, or 891 that drives the gate of the power MOSFET882A is turned on at any one time. Thus, circuit 880 operates as a tri-state gate driver that controls the conduction and gate charge swing of power MOSFET882A in accordance with the present invention. Table 3 is a truth table for the logic of the tri-state gate driver:

TABLE 3

Another variation of a current mirror gate driver in accordance with the present invention is illustrated in FIG. 20, where a tri-state gate driver 901 utilizes a value of V_GS1Drive the gate of power MOSFET903A to one of three potentials-V_ccEarth voltage or V_BIAS. Voltage V_BIASFrom conductionCurrent I from controlled current source 904_refIs determined by the threshold connected MOSFET 903B. MOSFETs 903B and 903A having gate widths W and n · W, respectively, together constitute a monolithically fabricated MOSFET pair 902.

The current I is regulated by a D/A converter 906 under the control of digital logic, a digital signal processor, or a microprocessor 907_refAnd, if desired, the current I can be adjusted dynamically and in real time_ref. The D/a converter 906 and the associated current source 904 may together form a current output D/a converter.

An example of a current-mode D/a converter 947 that directly drives the mirror MOSFET942B is illustrated in fig. 21B. The current mode D/A converter 947 includes a reference voltage V generator_refReference voltage source 949 to eliminate the voltage V to the power supply_ccSensitivity to fluctuations. Alternatively, as shown in fig. 21A, the controlled voltage source 928 may be controlled using a D/a converter 929 to generate the current I_ref. The voltage V is applied using a resistor 927 having a value R_refIs converted into an electric current, thereby I_ref＝(V_ref-V_tn) and/R. As previously described, a series of resistors and OTPMOSFETs may be used to fine tune the exact value of R.

To be in favor of V_BIASCan adjust the drain current ID during saturation in response to changing conditions_satI.e. I_DBIASThe value of (c). For example, I can be_DBIASAdjusted to be conductive during linear low resistance state_DlinThe percentage of (a), i.e.,

I_Dsat＝I_DBIAS∝I_Dlin＝V_cc/R_DS(on)。

in the drawing I_DBIASRelative to I_DlinFig. 22A of the drawings shows such an example. Curve 983 in graph 980 illustrates a constant percentage of analog feedback control using linear region current. Alternatively, I of the contained current, shown as curves 982a, 982b, and 982c, may be implemented using D/A converters and digital control_DBIASIs increased. As a ginsengTest, will be constant I_DBIASShown as line 981. In the graph 990 of FIG. 22B, I_DBIASVaries as a function of frequency f (curve 992) rather than remaining constant (curve 991).

A circuit for reducing gate drive loss using switched bias current mirror drive: in the previous current mirror drive circuit, the power MOSFET gate bias is driven from V_cc、V_BIASAnd optionally a select multiplexed gate driver determination in ground voltage. In such embodiments, the devices are hardwired to the threshold connection, i.e., have V_GS＝V_DSCurrent mirror MOSFET fed current source setup V_BIAS。

An alternative approach illustrated in fig. 23A is to use the ground voltage and bias supply current I during high frequency switching_refThe gate bias on the current mirror MOSFET1002B is switched. When P-channel MOSFET1004 is on and the enable signal is high, gate driver 1005 connects the gate of N-channel MOSFET1002B to ground, turning off MOSFET 1002B. As a result, V_GS1＝V_ccAnd power MOSFET1002A is biased to a low resistance state in which MOSFET1006 remains off.

In the saturation low current mode, MOSFET1004 is off and the enable signal has a high level, gate driver 1005 shorts the gate to the drain of mirror MOSFET 1002B. At the same time, MOSFET1006 is turned on and reference voltage source 1008 supplies current I to threshold-connected MOSFET1002B through resistor 1007_ref. The mirror MOSFET1002B is only at V_GS1＝V_BIASIs threshold connected during the time period of (a). As a result, the drain current I is utilized_DBIASPower MOSFET1002A is biased into saturation.

If the enable signal is low, gate driver 1005 couples the gate of MOSFET1002B to V_ccConnect, turn it on, and ground the gate of power MOSFET 1002A. Under this condition, MOSFETs 1004 and 1006 remain off.

The switching bias circuit 1000 has the advantage of requiring only two large facetsThe integrating MOSFET acts as a buffer to drive the gate of power MOSFET1002A, i.e., high side MOSFET1004 which drives power MOSFET1002A to a low resistance state, and provides V for power MOSFET1002A to operate in saturation_BIASThe gate drives and turns off the multi-function mirror MOSFET1002B of the power MOSFET 1002A.

Fig. 23B illustrates one form of the circuit 1000 in which the gate driver that drives the gate of the current mirror MOSFET1022B includes an N-channel MOSFET1025 to ground for turning off MOSFET1022B, and an N-channel MOSFET1029 that shorts the gate and drain of MOSFET 1022B. Biasing the gate of the mirror MOSFET1022B at voltage V with MOSFET1026_BIASThe above. MOSFET1024 is used to drive power MOSFET1022A to a low resistance state.

Application and topology of a circuit to reduce gate drive loss: the above-described method and circuit for driving a power MOSFET with low gate drive loss may be applied to a power MOSFET of a low-side, high-side or push-pull configuration of an N-channel or P-channel conduction type. Fig. 24A-24D illustrate low loss gate drivers using N-channel power MOSFETs, while fig. 25A and 25B illustrate low loss gate drivers using P-channel and complementary power MOSFETs.

As described above, the gate driver may comprise a two-state driver that switches between a low resistance fully on condition and a limited current saturation MOSFET condition. Alternatively, the gate driver may include a tri-state buffer that switches between a low resistance fully on condition, a limited current saturation MOSFET condition, and a fully off condition for sleep mode operation. Each power MOSFET in the power circuit may employ one of the low gate drive loss techniques or alternatively, only one of the power devices may utilize the low drive loss approach.

FIG. 24A illustrates the generation of V using a voltage source 1106 to drive a grounded, i.e., low side configured, N-channel power MOSFET1101_BIASAnd by generating V_ccA voltage source 1105. By generating V_DDPower MOSFET1101 supplied by voltage source 1104 and a load1103 may include: v in the Low resistance State_DDR; constant current I when saturated_DBIAS(ii) a And I when no handover is performed_D0. When the enable signal EN is low and the gate of the power MOSFET1101 is grounded, switching is inhibited. Voltage source 1104 (V)_DD) And 1105 (V)_cc) May contain the same power. By passing at V_ccAnd V_BIASLimits gate bias during switching, reduces gate charge swing, and improves the efficiency of power MOSFET1101 during switching.

FIG. 24B illustrates the generation of V with a floating voltage source 1126, powered by a bootstrap capacitor 1128, driving a high side, i.e., source follower configured, N-channel power MOSFET1121_BIASThe floating tri-state gate driver 1122. Whenever the MOSFET1121 is turned off and the voltage V across the load 1123_xAt earth voltage or less than supply voltage V_ccThen, V is generated_ccVoltage source 1125 charges bootstrap capacitor 1128 through bootstrap diode 1127. Bootstrap capacitor 1128 at V_GS1＝V_boot≈V_ccThe gate driver 1222 is powered and the MOSFET1121 is fully turned on with low resistance.

By generating V_DDMay be equal to V when the MOSFET1121 is in a low resistance state_DDR; when the MOSFET1121 is in saturation, it may be equal to a constant current I_DBIAS(ii) a Or may be equal to zero when MOSFET1121 is not being switched. When the enable signal EN is low and the gate of the power MOSFET1121 is connected to its source voltage V_xWhen connected, MOSFET1121 is disabled from switching. The gate driver 1122 is fed with level shifting of an enable signal and an input signal by a level shift circuit 1129. Voltage source 1124 (V)_DD) And 1125 (V)_cc) May be a single voltage source. By passing at V_ccAnd V_BIASSwitching the gate of the MOSFET1121 in between reduces gate charge swing and improves the efficiency of the MOSFET1121 during switching.

FIG. 24C illustrates synchronized liftingA voltage converter 1160 including a low side N-channel power MOSFET1161, a synchronous rectifier MOSFET1166, and low loss gate drivers 1162 and 1167 in accordance with the present invention. As shown, V is generated using a voltage source 1163_BIASLTri-state gate driver 1162 is driven by V_battPower is supplied and drives a grounded low side configured N-channel power MOSFET 1161. The current in power MOSFET1161 may be equal to V when MOSFET1161 is in a low resistance state_xR; when MOSFET1161 is saturated, it may be equal to constant current I_DBIAS(ii) a Or may be equal to zero when MOSFET1161 is not switched. When the enable signal EN is low and the gate of the power MOSFET1161 is grounded, switching is inhibited. When enabled, a Pulse Width Modulation (PWM) controller 1164 determines the pulse width and on-time of MOSFET1161, which in turn controls the current flowing to inductor 1165. By passing at V_battAnd V_BIASLLimits the gate bias of the MOSFET1161 during switching, reduces gate charge swing, and improves the efficiency of the power MOSFET1161 during switching.

Boost converter 1160 also illustrates that whenever low side MOSFET1161 turns off and V_xQuickly exceed (flyabove) V_outA PN junction rectifying diode 1169 that is turned on. To reduce power losses, the floating N-channel synchronous rectifier MOSFET1166 is turned on for some portion of the time that the low side MOSFET1161 is off. As shown, synchronous rectifier MOSFET1166 is driven by a binary gate driver 1167 and is powered by a bootstrap capacitor 1172. Whenever V_xNear ground voltage, V_battThe bootstrap capacitor 1172 is charged through a bootstrap diode 1171. Voltage V_bootFloat at V_xSo that the gate driver 1167 is supplied with the voltage V_xIs independent of the magnitude of V_boot≈(V_batt-V_f)。V_fIs the forward bias voltage across the bootstrap diode 1171 when the bootstrap capacitor 1172 is charged.

Floating dual gate driver 1167 drives the gate of floating MOSFET1166 with a potential V_GSF＝V_bootOperating at a low on-state voltage drop, using a potential V_GSF＝V_BIASFMake it operate at a current I_DBIASA saturated current source. The synchronous rectifier MOSFET1166 is preferably driven out of phase with the low side MOSFET1161 by inverting the break-before-make buffer 1173 so that only one MOSFET operates in a low resistance high current state at a time. According to the invention, during such an interval, the other MOSFET can be switched off or on with a small bias current I_DBIASTo reduce gate charge swing. Since N-channel MOSFET1161 exhibits a larger drain voltage transition during conduction than synchronous rectifier MOSFET1166, the benefit of the present invention in limiting gate charge swing is greatest for gate driver 1162 driving low-side MOSFET 1161. However, driver 1167 driving synchronous rectifier MOSFET1166 reduces gate drive losses and, more importantly, reduces efficiency losses and noise generated by diode recovery in rectifier diode 1169. Application No. [ attorney docket No.: no. AATI-18-DS-US]The subject of biasing the synchronous rectifier MOSFET as a current source to control diode recovery is presented. Table 4 is a truth table describing the various combinations described above.

TABLE 4

Note also that in the embodiment of fig. 24C, only the gate driver 1162 is tri-stated, since the MOSFET1161 forms a series shunt from the battery input to ground. Entering MOSFET1166 into a sleep mode in which MOSFET1166 is disabled does not prevent V_battCharging output capacitor 1170 to approximately V_battThis is because every time V is turned on_batt>V_outDiode 1169 is forward biased. The primary benefit of putting synchronous rectifier MOSFET1166 into sleep mode is to prevent capacitor 1170 from reversing direction vs_battThe discharge is gradual.

In bookIn another embodiment of the invention, an N-channel synchronous buck converter 1180 with reduced gate drive losses in accordance with the present invention is illustrated in fig. 24D. As shown, buck converter 1180 includes generating V using floating voltage source 1183_BIASHThe floating tri-state gate driver 1182. Gate driver 1182 is powered by bootstrap capacitor 1185 and drives a high-side, source-follower configured, N-channel power MOSFET 1181. Whenever MOSFET1181 turns off and voltage V_xAt earth voltage or less than supply voltage V_battWhen, V_battBootstrap capacitor 1185 is charged through bootstrap diode 1184. Bootstrap capacitor 1185 at V_GSH＝V_boot≈V_battDuring the interval (2) the gate driver 1182 is powered and the MOSFET1181 is fully turned on with a low resistance.

MOSFET1181 has its on-time controlled by PWM controller 1193. The pulse width supplied to MOSFET1181 is modulated to control the current flowing through inductor 1190 and charging capacitor 1191. When closed-loop control is used, the feedback signal V is used_FBWill output a voltage V_outFed back to PWM controller 1193 to regulate the input voltage V_battAnd changes in load current to regulate the output voltage. Whenever MOSFET1181 saturates and conducts a low current I_DBIASInductor 1190 forces V_xBelow ground, as a result, diode 1189 becomes forward biased. Each time gate driver 1187 biases the gate of MOSFET1186 to V_battA low side N-channel MOSFET1186 is included to shunt current through the lower voltage drop path to reduce diode turn-on losses.

Conversely, whenever high side MOSFET1181 is at V_GSH＝V_bootWhen current is conducted in a low resistance state, V is passed_GSL＝V_BIASThe gate buffer biases the synchronous rectifier MOSFET1186, and the synchronous rectifier MOSFET conducts a low current I_DBIAS. BBM circuit 1192 prevents both high-side MOSFET1181 and low-side MOSFET1182 from conducting high current at the same time.

Since high-side MOSFET1181 exhibits a larger drain voltage transition during conduction than synchronous rectifier MOSFET1186, the benefits of the present invention in limiting gate charge swing are greatest for gate driver 1182 driving high-side MOSFET 1181. However, the gate driver 1187 driving the synchronous rectifier MOSFET1186 results in a reduction in gate drive losses and, more importantly, reduces the efficiency loss and noise generated by diode recovery in the rectifier diode 1189.

In the above-referenced application [ attorney docket number: the subject of controlling diode recovery by biasing the synchronous rectifier MOSFET into a current source is presented in AATI-18-DS-US ]. Table 5 is a truth table describing the various combinations described above.

TABLE 5

Note also that only gate driver 1182 needs to be tri-stated, since turning off either MOSFET1181 or 1186 interrupts the slave V_battA current path to ground voltage.

In another embodiment of the present invention, circuit 1200 in FIG. 25A illustrates the generation of V using voltage source 1203_BIASThe tri-state gate driver 1202. Generating V_DDVia connection V_ccI.e. a P-channel power MOSFET1201 in a high side configuration to drive a load 1204. The current in power MOSFET1201 and load 1204, supplied by voltage source 1205, may be equal to V in the low resistance state of MOSFET1201_DDR; when MOSFET1201 is saturated, it may be equal to constant current I_DBIAS(ii) a And may be equal to zero when MOSFET1201 is not switching. When the enable signal EN is low and the gate of the power MOSFET1201 is connected to V_DDWhen connected, MOSFET1201 is disabled for switching.

E.g. biased at V_DDThe Enable (EN) and Input (IN) signals may be passed to logic that switches between VDD and ground, as indicated by inverters 1206 and 1209 from ground. If the power supply voltageV_DDGreater than V_ccThe EN and IN signals must be level shifted to V_DD. In the embodiment of FIG. 25A, the level shifting circuit uses an N-channel MOSFET1207 and a resistor 1208 to transform the output of inverter 1206 to V_DDAnd an input signal IN' switched with a ground voltage. Similarly, an N-channel MOSFET1210 and resistor 1211 convert the output of inverter 1029 to a voltage at V_DDAnd an enable signal EN' switched with a ground voltage. Alternatively, V may be supplied by a single power supply_ccAnd V_DDSo that no level shifting circuit is required. In summary, by being at V_DDAnd V_BIASLimits the gate bias of the power MOSFET1201 during switching therebetween, reduces gate charge swing, and improves the efficiency of the power MOSFET during switching.

A complementary synchronous buck converter 1220 with reduced gate drive losses in accordance with the present invention is illustrated in fig. 25B. Converter 1220 includes a high-side reference tri-state gate driver 1222, which high-side reference tri-state gate driver 1222 generates V with a high-side reference voltage source 1223_BIASHFrom V_battDirectly supplies power and drives the high side, i.e., common source configured P-channel power MOSFET 1221.

The on-time of the MOSFET1221 is controlled by the PWM controller 1231. The width of the pulse delivered to the gate of MOSFET1221 is modulated to control the current flowing through inductor 1228, charging capacitor 1229. Using feedback signal V when closed-loop control is used_FBMake the output voltage V_outFed back to the PWM controller 1231 to regulate the output voltage for variations in the input voltage and load current. Whenever MOSFET1221 saturates and conducts a low current I_DBIASInductor 1228 forces V when_xBelow ground, as a result, diode 1227 becomes forward biased. Each time gate driver 1225 biases the gate of MOSFET1224 to V_battLow side N-channel MOSFET1224 is included to shunt current through the lower voltage drop path to reduce diode turn-on losses.

In contrast, whenever the high side P-channel MOSFET1221 is at V_GSH＝-V_battWhen the current is conducted in the low resistance state in the case of (3), V is used_GSL＝-V_BIASSynchronous rectifier MOSFET1224 is biased by a gate buffer and synchronous rectifier MOSFET1224 conducts a low current I_DBIAS. BBM circuit 1230 prevents MOSFETs 1221 and 1224 from conducting high current simultaneously.

Since P-channel MOSFET1221 exhibits a larger drain voltage transition during conduction than synchronous rectifier MOSFET1224, the benefits of the present invention in limiting gate charge swing are greatest for gate driver 1222 driving high-side P-channel MOSFET 1221. However, the gate driver 1225 driving synchronous rectifier MOSFET1224 reduces gate drive losses and, more importantly, reduces the efficiency loss and noise generated by diode recovery in rectifier diode 1227.

In the above-referenced application [ attorney docket number: the subject of controlling diode recovery by biasing the synchronous rectifier MOSFET into a current source is presented in AATI-18-DS-US ]. Table 6 is a truth table describing the various combinations described above.

TABLE 6

Also note that only the gate driver 1222 needs to be tri-stated, since turning off either MOSFET1221 or 1224 interrupts the slave V_battA current path to ground voltage.

While specific embodiments of the invention have been described herein, it will be understood by those of ordinary skill in the art that the described embodiments are illustrative only and not limiting. The broad principles of the present invention are defined by the claims that follow.

Claims (30)

1. A circuit, comprising:

a power MOSFET (203);

a gate driver (202), an output terminal of the gate driver (202) being connected to a gate terminal of the power MOSFET (203), the gate driver (202) comprising a first input terminal and a second input terminal, the first input terminal being connected to a first voltage source (V)_cc) Connected to a second voltage source (V)_Bias) Connecting; and

a switching element for switching the gate between the first input terminal and the second input terminalAt the output of the pole driver (202), at the first voltage source (V)_cc) The provided first voltage is delivered to the gate terminal to cause the power MOSFET (203) to be in a fully on condition, and when the second voltage source (V) is applied_Bias) The provided second voltage, when delivered to the gate terminal, causes the power MOSFET to be in a low current condition in which a magnitude of a drain current of the power MOSFET is no less than 10 times a magnitude of a leakage current of the power MOSFET in its off condition and no greater than 10% of the magnitude of the current of the power MOSFET in its fully on condition.

2. A circuit according to claim 1, further comprising a buffer (201) connected to the gate driver (202) for repeatedly switching the output between the first and second inputs.

3. The circuit of claim 1, wherein the switching element comprises a CMOS pair (451, 453), a first MOSFET (451) of the CMOS pair (451, 453) being connected between the first input and the output, a second MOSFET (453) of the CMOS pair (451, 453) being connected between the second input and the output.

4. The circuit of claim 1, wherein the gate driver (352) further comprises a third input connected to the source terminal of the power MOSFET (353), the switching element being capable of switching the output between the first, second and third inputs.

5. The circuit of claim 4, wherein the gate driver comprises:

a CMOS pair (451, 453), a first MOSFET (451) of the CMOS pair (451, 453) being connected between the first input and the output, a second MOSFET (453) of the CMOS pair (451, 453) being connected between the third input and the output; and

a third MOSFET (452), the third MOSFET (452) being connected between the second input terminal and the output terminal.

6. The circuit of claim 1, wherein the power MOSFET (586) is connected to a load (587) in the power circuit.

7. The circuit of claim 6, further comprising a feedback circuit (585, 588, 589, 590) connected between the power circuit and the second terminal of the gate driver (583, 584), the feedback circuit (585, 588, 589, 590) generating an error signal for maintaining a current of the power MOSFET (586) at a target value under low current conditions.

8. The circuit of claim 7, wherein the feedback circuit (585, 588, 589, 590) includes a current sensor (590) connected in the power circuit.

9. The circuit of claim 8, wherein the feedback circuit (585, 588, 589, 590) comprises an amplifier (588).

10. The circuit of claim 9, wherein the second voltage source comprises a variable voltage source (585), the current sensor (590) being connected to a first input of the amplifier (588), a second input of the amplifier (588) being connected to a reference current source (589), an output of the amplifier (588) being connected to the variable voltage source (585).

11. The circuit of claim 7, wherein the power circuit comprises a sense resistor (615B).

12. The circuit of claim 11, wherein the feedback circuit includes an amplifier (618) and a reference voltage source (619), a first input of the amplifier (618) is connected with the sense resistor (615B), a second input of the amplifier (618) is connected with the reference voltage source (619), and an output of the amplifier (618) is connected with a second end of the gate driver (613, 614).

13. The circuit of claim 7, wherein the feedback circuit comprises:

a current mirror arrangement generating a mirror current having a magnitude corresponding to a current (I) in the power circuit_D) Is proportional to the size of the capsule;

a sense resistor (631) connected with the current mirror arrangement such that the mirror current flows through the sense resistor (631).

14. The circuit of claim 13, further comprising an amplifier (633), a first input of the amplifier (633) being connected to a reference voltage source (632), a second input of the amplifier (633) being connected to the sense resistor (631), and an output of the amplifier (633) being connected to a second input of the gate driver (623, 624).

15. The circuit of claim 14, wherein the feedback circuit includes a second MOSFET (658A) in series with the power MOSFET (656).

16. The circuit of claim 6, wherein the second voltage source comprises a fixed voltage source (706).

17. The circuit of claim 16, further comprising

A current sensor connected in the power circuit; and

a trimming circuit (705) connected to the current source and the fixed voltage source (706), the trimming circuit (705) adapted to adjust the magnitude of the second voltage in response to an output signal from the current sensor.

18. The circuit of claim 17, wherein the trimming circuit comprises a plurality of one-time programmable MOSFETs (730a-730e) and a plurality of resistors (729a-729e) connected in series in a voltage divider network, each of the resistors (729a-729e) being connected in parallel with a corresponding one of the one-time programmable MOSFETs (730a-730 e).

19. The circuit of claim 6, further comprising a current mirror MOSFET (824B), gate and drain terminals of the current mirror MOSFET (824B) being shorted together and connected to the second terminal of the gate driver (821).

20. The circuit of claim 19, further comprising a current sensor connected in the power circuit.

21. The circuit of claim 20, further comprising a variable current source (822) connected to said current mirror MOSFET (824B).

22. The circuit of claim 21, further comprising a trimming circuit (831) coupled to the current source and the variable current source (822), the trimming circuit (831) adapted to adjust a magnitude of the current supplied by the variable current source (822) in response to an output signal from the current sensor.

23. The circuit of claim 6, further comprising a current source (892) connected with said current mirror MOSFET (882B), said current source (892) adapted to supply a current (I) having a specified proportion of a magnitude equal to a desired magnitude of current in said power MOSFET (882A) in a low current condition_ref)。

24. The circuit of claim 23, wherein the current source (904) comprises a variable current source (904).

25. The circuit of claim 24, further comprising a digital-to-analog converter (906) connected to an input of the variable current source (904), and a digital device (907) connected to an input of the digital-to-analog converter (906).

26. The circuit of claim 1, wherein the power MOSFET is a component of a boost converter, the power MOSFET is connected in series with an inductor, and a synchronous rectifier MOSFET is connected between an output of the boost converter and a common node between the power MOSFET and the inductor.

27. The circuit of claim 1, wherein the power MOSFET is a component of a buck converter, the power MOSFET is connected in series with a synchronous rectifier MOSFET, and an inductor is connected between an output of the buck converter and a common node between the power MOSFET and the synchronous rectifier MOSFET.

28. The circuit of claim 1, wherein the second voltage is established at a level such that switching the power MOSFET (203) between a fully on condition and a low current condition reduces the amount of charge that must be moved into and out of the gate of the power MOSFET (203) during each switching cycle, thereby reducing power losses to charge and discharge the gate such that power savings more than compensates for additional power losses from drain current that continues to flow into the power MOSFET (203) in its low current condition, thereby increasing the overall efficiency of the power MOSFET (203).

29. A circuit, comprising:

a power MOSFET (203);

a gate driver (202), an output terminal of the gate driver (202) being connected to a gate terminal of the power MOSFET (203),the gate driver (202) comprises a first input terminal and a second input terminal, the first input terminal being connected to a first voltage source (V)_cc) Connected to a second voltage source (V)_Bias) Connecting; and

a switching element for switching an output of the gate driver (202) between the first input terminal and the second input terminal, at the first voltage source (V)_cc) The provided first voltage is delivered to the gate terminal to cause the power MOSFET (203) to be in a fully on condition, and when the second voltage source (V) is applied_Bias) The provided second voltage, when delivered to the gate terminal, causes the power MOSFET to be in a saturated low current condition in which the gate-source voltage of the power MOSFET is in a range of 10% to 125% of an extrapolated threshold voltage of the power MOSFET.

30. The circuit of claim 29, wherein the gate-source voltage of the power MOSFET in the saturated low current condition is in a range of 25% to 100% of an extrapolated threshold voltage of the power MOSFET.