HK1182530B - Transistor with self-aligned channel width - Google Patents

Abstract

The invention relates to transistor with self-aligned channel width. A device includes a transistor including a source and a drain disposed in a substrate and a gate disposed above the substrate. The gate includes a first longitudinal member disposed above the source and the drain and running substantially parallel to a channel of the transistor. The first longitudinal member is disposed over a first junction isolation area. The gate also includes a second longitudinal member disposed above the source and the drain and running substantially parallel to the channel of the transistor. The second longitudinal member is disposed over a second junction isolation region. The gate also includes a cross member running substantially perpendicular to the channel of the transistor and connecting the first longitudinal member to the second longitudinal member. The cross member is disposed above and between the source and the drain.

Description

Transistor with self-aligned channel width

Technical Field

The present invention relates generally to electronic devices, and particularly, but not exclusively, to transistors.

Background

Image sensors are widely used in digital still cameras, cellular phones, security cameras, as well as medical, automotive and other applications. Lower cost image sensors are fabricated on silicon substrates using complementary metal oxide semiconductor ("CMOS") technology. Among the large number of image sensors, an image sensor typically includes hundreds, thousands, or even millions of light sensor cells or pixels. A typical individual pixel includes a microlens, a filter, a photosensitive element, a floating diffusion region, and one or more transistors for reading out signals from the photosensitive element. As image sensor pixels become smaller, the transistors inside them must also become smaller. However, as the size of transistors in image pixels shrinks, conventional transistor technology encounters isolation challenges and increased manufacturing costs.

Shallow trench isolation ("STI") and local oxidation of silicon ("LOCOS") are isolation techniques used in image pixels. LOCOS is suitable for image sensors, but it is difficult to reduce the size of pixels with LOCOS technology. STI typically has less work into the active region of the transistor than LOCOS and can be selected instead of LOCOS. However, both techniques produce an isolation edge effect in which the isolation region intersects the active portion of the transistor. The isolation edge effects can negatively affect the electrical characteristics of the transistor. For example, STI can cause a white pixel (a.k.a. "hot pixel") or a dark pixel. One component of the isolation edge effect is sometimes referred to as the narrow width effect, which is increasingly becoming a factor in small geometry MOSFET design.

As transistors become smaller, fabrication tools also become more expensive. Reducing the size of the transistors requires tools with smaller tolerances, and these precision tools can increase manufacturing costs. The photomask used in photolithography is one example of a transistor fabrication tool that requires tighter tolerances. Another byproduct of making smaller transistors is the higher defect rate due to misalignment of the transistor structure during the fabrication process.

Disclosure of Invention

One aspect of the claimed invention provides an apparatus. The device includes a transistor. The transistor includes: a source and a drain disposed in a substrate; and a gate disposed over the substrate, wherein the gate includes: a first longitudinal member disposed over the source and the drain and running substantially parallel to a channel of the transistor, wherein the first longitudinal member is disposed over a first junction isolation region; a second longitudinal member disposed over the source and the drain and running substantially parallel to the channel of the transistor, wherein the second longitudinal member is disposed on an opposite side of the source and the drain from the first longitudinal member, and wherein the second longitudinal member is disposed over a second junction isolation region; and a lateral member running substantially perpendicular to the channel of the transistor and connecting the first longitudinal member to the second longitudinal member, wherein the lateral member is disposed above and between the source and the drain.

Another aspect of the claimed invention provides an image sensor. The image sensor includes an array of imaging pixels, each image pixel including: a photosensitive element for accumulating image charge in response to light; a floating diffusion region to receive the image charge from the photosensitive element; and a transfer gate disposed between the photosensitive element and the floating diffusion region to selectively transfer the image charge from the photosensitive element to the floating diffusion region, wherein the floating diffusion region is coupled to a readout transistor and a reset transistor. The readout transistor and the reset transistor each include: a source and a drain disposed in a substrate; and a gate disposed over the substrate, wherein the gate includes: a first longitudinal member disposed over the source and the drain and running substantially parallel to a channel of the transistor, wherein the first longitudinal member is disposed over a first junction isolation region; a second longitudinal member disposed over the source and the drain and running substantially parallel to the channel of the transistor, wherein the second longitudinal member is disposed on an opposite side of the source and the drain from the first longitudinal member, and wherein the second longitudinal member is disposed over a second junction isolation region; and a lateral member running substantially perpendicular to the channel of the transistor and connecting the first longitudinal member to the second longitudinal member, wherein the lateral member is disposed above and between the source and the drain, and wherein a distance between the first longitudinal member and the second longitudinal member defines a width of the channel of the transistor.

Another aspect of the claimed invention provides a method of fabricating a transistor. The method comprises the following steps: forming a polysilicon layer over a substrate; etching the polysilicon layer to form a gate, wherein the gate includes first and second longitudinal members connected by a transverse member; forming a mask over the gate, the mask exposing drain and source regions in the substrate for implantation, wherein the mask also exposes a portion of the two longitudinal features and the entire lateral feature of the gate for implantation; and implanting dopants while forming the mask over the gate to form a source and a drain disposed in the substrate, wherein the source and the drain are self-aligned to the shape of the gate.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

Fig. 1A is a top view of a conventional transistor.

FIG. 1B is a cross-sectional view through line 1B-1B' of the conventional transistor in FIG. 1A.

Fig. 2A is a plan view illustrating a transistor according to an embodiment of the present invention.

Figure 2B is a cross-sectional view through line 2B-2B' of figure 2A illustrating a transistor according to an embodiment of the invention.

Figure 3 is a plan view illustrating one example of a transistor gate shape according to an embodiment of the invention.

Fig. 4 is a flow chart illustrating a process for fabricating a transistor according to an embodiment of the invention.

Figure 5A is a plan view illustrating a gate and an implanted region according to an embodiment of the invention.

Fig. 5B is a plan view illustrating a mask according to an embodiment of the present invention.

Figure 6 is a plan view illustrating a gate and an implanted region according to an embodiment of the invention.

Figure 7 is a plan view illustrating a gate and two implanted regions according to an embodiment of the invention.

Figure 8 is a plan view illustrating a gate and an implanted region according to an embodiment of the invention.

FIG. 9 is a functional block diagram illustrating an imaging sensor according to an embodiment of the present invention.

FIG. 10 is a circuit diagram illustrating sample pixel circuitry for two image sensor pixels within an image sensor according to an embodiment of the invention.

Detailed Description

Embodiments of apparatus and methods of fabrication of transistors are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Fig. 1A is a plan view of a conventional transistor, and fig. 1B is a cross-sectional view through line 1B-1B' of the conventional transistor in fig. 1A. Transistor 100 includes a gate 105, a gate insulation layer 110, a source 115, a drain 120, a substrate 125, and STI 130. The gate length 135 is illustrated as the distance between the source 115 and the drain 120. Transistor width 140 is illustrated as the width of source 115 or drain 120. Substrate 125 may include an epitaxial layer grown on a substrate. When the bias voltage on the gate 105 reaches the threshold voltage, the transistor 100 is turned "on" and a conductive channel (not illustrated) is formed between the source 115 and the drain 120. STI130 provides electrical isolation between any adjacent transistors or other adjacent electrical components. Some conventional transistors may use LOCOS instead of STI 130.

Fig. 2A is a plan view illustrating a transistor 200, and fig. 2B is a cross-sectional view through line 2B-2B' of fig. 2A, according to an embodiment of the invention. The illustrated embodiment of the transistor 200 includes an H-type gate 205, a gate insulation layer 210, a source 215, a drain 220, a substrate 225, and a junction isolation 230. When the bias voltage on the gate 205 reaches the threshold voltage, the transistor 200 is turned "on" and a conductive channel is formed in the substrate 225 between the source 215 and the drain 220. The substrate 225 may comprise an epitaxial layer grown on a substrate.

The illustrated embodiment of the H-type gate 205 includes a first member 250, a second member 255, and a lateral member 260. The H-type gate 205 may be made of polysilicon. In the illustrated embodiment, the H-type gate 205 is made of a continuous block of polysilicon, and the first member 250, the second member 255, and the lateral member 260 are illustrated for descriptive purposes. The lateral member 260 continues substantially perpendicular to the channel of the transistor 200 and connects the first member 250 with the second member 255. The lateral member 260 continues substantially perpendicular to the first member 250 and the second member 255 and is disposed above and between the source 215 and the drain 220. The gate length 235 is the distance between the source 215 and the drain 220 at the lateral feature 260. The width of the channel of the transistor 200 is approximately the distance between the first member 250 and the second member 255. In the illustrated embodiment, the first and second members 250, 255 may extend longitudinally (in the same direction as the gate length 235) as space constraints allow.

In the illustrated embodiment in fig. 2A, the source 215 and drain 220 have a T-shape due to the fabrication method described below. Those skilled in the art will recognize that the boundaries of the source 215 and drain 220 may expand slightly from the illustrated boundaries due to diffusion. Additionally, if the angled implant approach is utilized, the boundaries of the source 215 and drain 220 may be different than illustrated.

Junction isolation 230 provides electrical isolation between any adjacent transistors or other adjacent electrical components. There are a variety of methods and techniques for junction isolation 230. One approach is to increase the doping level between the transistors. For example, if the substrate 225 is P-type doped and the source 215 and drain 220 are N-type doped, additional P-type doping would be added to the area surrounding the source 215 and drain 220 to isolate the transistor 200 from neighboring transistors. In this example, junction isolation 230 may be denoted as P +, and substrate 225 may be denoted as P-to show its relative doping levels. In one embodiment, polysilicon field plate isolation is used in addition to junction isolation 230. In other embodiments, polysilicon field plate isolation is not used with junction isolation 230. Junction isolation 230 is used to avoid transistor damage and stress resulting from etching trenches for STI130 in substrate 125. STI-induced damage, particularly near the corners of the STI, can result in hot pixels and/or increased dark current.

The shape and placement of the H-type gate 205 may also reduce undesirable electrical effects, including reducing narrow width effects. For example, the channel of the transistor (which flows substantially under the lateral member 260) may not flow under the bottom edge of the first member 250 or under the top edge of the second member 255. Since these edges are offset from the channel, the narrow width effect, which is a component of the isolation edge effect, can be suppressed.

Figure 3 is a plan view illustrating one example of a transistor gate shape according to an embodiment of the invention. The transistor 300 includes a surrounding gate 305, a source 315, a drain 320, and a junction isolation 330. The surrounding gate 305 includes a first feature 350, a second feature 355, a lateral feature 360, a first encapsulation feature 365, and a second encapsulation feature 370. The surrounding gate 305 may be made of polysilicon. In the illustrated embodiment, the surrounding gate 305 is made of a continuous block of polysilicon, and the first member 350, the second member 355, the lateral member 360, the first encapsulation member 365, and the second encapsulation member 370 are illustrated for descriptive purposes. A conduction channel of the transistor 300 is formed in the substrate between the source 315 and the drain 320 below the lateral member 360. The lateral member 360 continues substantially perpendicular to the channel of the transistor 300 and connects the first member 350 and the second member 355. The lateral member 360 continues substantially perpendicular to the first member 350 and the second member 355 and is disposed above and between the source 315 and the drain 320. First encapsulating member 365 continues substantially parallel to transverse member 360 and connects first member 350 and second member 355. The first feature 350, the second feature 355, the lateral feature 360, and the first encapsulation feature 365 surround the cavity aligned above the drain 320. The second encapsulating member 370 continues substantially parallel to the transverse member 360 and connects the first member 350 and the second member 355. The first feature 350, the second feature 355, the lateral feature 360, and the second encapsulation feature 370 surround a cavity aligned above the source 315. In the illustrated embodiment of fig. 3, the source 315 and drain 320 have rectangular shapes, but other shapes are possible. As mentioned above, the boundaries of the source 315 and drain 320 may expand slightly from the illustrated boundaries due to diffusion.

The shape and placement of the surrounding gate 305 may reduce the narrow width effect almost the same as the H-type gate 205. For example, the channel of the transistor (which flows substantially under the lateral member 360) may not flow under the bottom edge of the first member 350 or under the top edge of the second member 355. Since these edges are offset from the channel, the narrow width effect, which is a component of the isolation edge effect, can be suppressed. The additional features surrounding the gate 305 (the first and second encapsulation features 365, 370) may also provide additional self-alignment functions, as described below.

Fig. 4 is a flow diagram illustrating a process 400 for fabricating a transistor according to an embodiment of the invention. Process 400 is one example of how transistor 200 or transistor 300 can be fabricated. The process 400 is described in conjunction with fig. 5A, 5B, 6, 7, and 8. The order in which some or all of the process blocks appear in process 400 should not be considered limiting. Rather, those skilled in the art, having the benefit of the present disclosure, will appreciate that some of the process blocks may be performed in a variety of orders, or even in parallel, not illustrated.

In process block 405, a polysilicon layer is formed over a substrate. In process block 410, the polysilicon layer is etched to form a gate including two longitudinal features connected by a lateral feature. In one embodiment, the gate is shaped like an H-gate 205. In another embodiment, the gate is shaped like the surrounding gate 305. Other gate shapes are possible that include two longitudinal sections connected by a transverse section.

In process block 415, a source/drain mask is formed over the gate shapes etched in process block 410 (exposing the implant regions). In process block 420, dopants are implanted into the exposed implant regions to form sources and drains that are self-aligned to the gates. In one embodiment, a source/drain mask 575 (fig. 5B) exposes implant region 530 by masking regions outside of implant region 530 for implantation. The implant region 530 includes the source region 515, the drain region 520, a portion of the first feature 250 and the second feature 255, and the entire lateral feature 260. When implanting dopants using, for example, an ion beam, some of the dopants are implanted into the substrate (into the source region 515 and the drain region 520), while some dopants will be implanted in the exposed portion of the H-type gate 205 and thus do not penetrate the substrate. Thus, exposing portions of the H-type gate 205 for implantation allows the shape of the H-type gate 205 to act as a mask-which helps define the location of the source and drain regions 515, 520 in the substrate. The result is that dopants are implanted in the source region 515 and the drain region 520 and aligned with the H-type gate 205. Thus, the location of the source/drain mask 575 over portions of the H-type gate 205 "self-aligns" the source and drain regions 515, 520 with the shape of the H-type gate 205 by virtue of the implantation process. In one embodiment, the source/drain mask 575 is omitted and the accuracy of the implant combined with the masking function of the H-type gate 205 defines the source region 515 and the drain region 520.

With the shape of the H-type gate 205 partially used as a mask, the transistor width of the transistor 500 may be defined by the distance between the first member 250 and the second member 255, rather than strictly by the accuracy of the source/drain mask 575. Thus, the vertical boundaries of the source/drain mask 575 that expose the implant regions 530 need only be precise enough to be within the confines of the width of the first features 250 (illustrated in fig. 5A as first feature width 525) and the width of the second features 255 in order for the shape of the H-type gate 205 to define the width of the transistor. Because the tolerances of the source/drain mask 575 may be relaxed, the expense associated with a more sophisticated mask (used in manufacturing transistors) may be reduced. Another advantage of having the H-type gate 205 partially used as a mask is that greater precision (relative to dopant implantation) can be obtained in the etching process to form the shaped gate from the polysilicon layer. The greater precision due to etching the gate (e.g., H-type gate 205) combined with the gate being used in part as a mask results in more precise source and drain placement.

In the embodiments described above, the H-type gate 205 may be exposed for ion implantation, and the H-type gate 205 may have the same dopant type as the source region 515 and the drain region 520. In other embodiments, the source/drain mask 575 may be formed such that the implant region 530 exposes only the source region 515 and the drain region 520 for ion implantation. In other words, the source/drain mask 575 may be formed to mask the entire H-type gate 205 from ion implantation; thus, the H-type gate 205 may be undoped.

In fig. 6, implant region 630 is also an example of an implant region in process block 415. The implant region 630 may be exposed by a source/drain mask similar to source/drain mask 575. The implant region 630 includes the source region 615, the drain region 620, a portion of the first and second features 350, 355, a portion of the first and second encapsulation features 365, 370, and the entire lateral feature 360. Similar to the H-shaped gate 205, the shape of the surrounding gate 305 may function in part as a mask. However, the H-type gate 205 only allows for relaxed tolerances on the vertical boundaries of the source/drain mask 575. In contrast, the wrap-around gate 305 would allow for relaxed tolerances for the vertical and horizontal boundaries of the source/drain mask (exposing the implant region 630) because the first and second encapsulation members 365, 370 help define the source region 615 and the drain region 620. Accordingly, the tolerance of the source/drain mask exposing the implant region 630 may be relaxed according to the first feature width 625 and the first encapsulation feature width 635. Where the wrap-around gate 305 helps define the illustrated vertical and horizontal boundaries of the source region 615 and the drain region 620, the size of the source region 615 and the drain region 620 may be reduced, allowing for a smaller transistor 600. The benefits of the partial use of the surrounding gate 305 as a mask in conjunction with the source/drain mask exposing the implanted region 630 may also provide the benefits of an inexpensive mask and more precise source and drain placement, as described above.

In the embodiments described above, the surrounding gate 305 may be exposed for ion implantation, and the surrounding gate 305 may have the same dopant type as the source region 615 and the drain region 620. In other embodiments, a source/drain mask may be formed such that only source region 615 and drain region 620 are exposed for ion implantation. In other words, the source/drain mask may be formed to mask the entire surrounding gate 305 from ion implantation.

Figure 7 is a plan view illustrating a gate and two implanted regions according to an embodiment of the invention. The transistor 700 includes an H-type gate 205, a source region 715, and a drain region 720. LDD implant regions 725 illustrate where transistor 700 will be lightly doped. In one embodiment, the LDD mask exposes LDD implant regions 725. The HDD implant region 730 illustrates where the transistor 700 will be lightly doped. In one embodiment, the HDD mask exposes the HDD implant region 730. The LDD implant and HDD implant will combine to form the source and drain of transistor 700. The LDD implant region 725 and HDD implant region 730 are examples of implant regions mentioned in process block 415. In one embodiment, an LDD mask is first formed that exposes LDD implant regions 725, dopants are implanted into LDD implant regions 725, spacers (which may be oxide or nitride) are formed around H-type gate 205, a HDD mask is formed that exposes HDD implant regions 730, and dopants are implanted into HDD implant regions 730. If spacers are formed around the H-type gate 205, they may cause the HDD implant to be offset from the H-type gate 205.

In the embodiments described above, the H-type gate 205 may be exposed for ion implantation, and may be exposed for both LDD implantation and HDD implantation. In other embodiments, LDD and/or HDD masks may be formed to mask the entire H-type gate from ion implantation.

Figure 8 is a plan view illustrating a gate and an implanted region according to an embodiment of the invention. Transistor 800 includes an H-type gate 205, a source region 815, and a drain region 820. In one embodiment, the source/drain mask exposes the implant region 830 for implantation. The implant region 830 is not positioned over the first member 250 or the second member 255, but rather over the transverse member 260. Thus, the dopants implanted in the source region 815 and the drain region 820 will be self-aligned with the lateral features, but may not be self-aligned with the first feature 250 and the second feature 255. However, once the dopants are implanted into the implant region 830, the dopants may diffuse under the first and second members 250, 255. Additionally, if an angled implant method is utilized, the boundaries of the source region 815 and the drain region 820 may be different than illustrated.

FIG. 9 is a functional block diagram illustrating an imaging sensor 900 according to an embodiment of the invention. The illustrated embodiment of imaging sensor 900 includes a pixel array 905, readout circuitry 910, functional logic 915, and control circuitry 920. The pixel array 905 is a two-dimensional ("2D") array of imaging sensors or pixels (e.g., pixels P1, P2 …, Pn). In one embodiment, each pixel is a complementary metal oxide semiconductor ("CMOS") imaging pixel. As illustrated, each pixel is arranged into a row (e.g., row R1-Ry) and a column (e.g., column C1-Cx) to acquire image data of a person, place, or object, which can then be used to render a 2D image of the person, place, or object. The transistor structures and processes of the present invention may be used in an imaging sensor 900. In one embodiment, the transistor 200 may be included in an imaging sensor 900 or in an image pixel in a pixel array 905. In another embodiment, the transistor 300 may be included in an imaging sensor 900 or in an image pixel in a pixel array 905.

After each pixel has acquired its image data or image charge, the image data is read out by readout circuitry 910 and transferred to function logic 915. The readout circuit 910 may include an amplification circuit, an analog-to-digital ("ADC") conversion circuit, or others. The function logic 915 may simply store the image data or even manipulate the image data by applying post-image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). In one embodiment, readout circuitry 910 may readout a row of image data at a time along readout column lines (illustrated) or may readout the image data using a variety of other techniques (not illustrated) such as serial readout or full parallel readout of all pixels simultaneously. The control circuitry 920 is coupled to the pixel array 905 to control the operating characteristics of the pixel array 905. For example, the control circuitry 920 may generate a shutter signal for controlling image acquisition.

FIG. 10 is a circuit diagram illustrating a sample pixel circuit 1000 of two four-transistor ("4T") pixels within an imaging array, according to an embodiment of the invention. Pixel circuit 1000 is one possible pixel circuit architecture for implementing each pixel within pixel array 905 of fig. 9. However, it should be understood that embodiments of the invention are not limited to 4T pixel architectures; rather, those skilled in the art, with the benefit of the present disclosure, will appreciate that the present teachings are applicable to 3T designs, 5T designs, and various other pixel architectures as well.

In fig. 10, pixels Pa and Pb are arranged in two rows and one column. The illustrated embodiment of each pixel circuit 1000 includes a photodiode PD, a transfer transistor T1, a reset transistor T2, a source follower ("SF") transistor T3, a select transistor T4, and a storage capacitor C1. During operation, the transfer transistor T1 receives a transfer signal TX that transfers the charge accumulated in the photodiode PD to the floating diffusion node FD. In one embodiment, floating diffusion node FD may be coupled to a storage capacitor (not shown) for temporarily storing image charge.

A reset transistor T2 is coupled between a power supply rail VDD and the floating diffusion node FD to reset the pixel (e.g., discharge or charge the FD and PD to a preset voltage) under control of a reset signal RST. Floating diffusion node FD is coupled to control the gate of SF transistor T3. SF transistor T3 is coupled between the power supply rail VDD and select transistor T4. SF transistor T3 operates as a source follower providing a high impedance connection to the floating diffusion FD. Finally, select transistor T4 selectively couples the output of pixel circuitry 1000 to the readout column line under control of a select signal SEL. In one embodiment, the TX signal, the RST signal, and the SEL signal are all generated by control circuitry 920. In one embodiment, each transistor in the pixel circuit 1000 except the transfer transistor T1 will have the structure of a transistor in the present invention. For example, in one embodiment, the reset transistor T2, SF transistor T3, and select transistor T4 would have the structure of transistor 200 (including the H-type gate 205). In one embodiment, the reset transistor T2, SF transistor T3, and select transistor T4 would have the structure of transistor 300, including surrounding gate 305, while the pass transistor T1 would have a conventional gate structure, such as gate 105. One reason the transfer transistor T1 may have a conventional gate structure (e.g., gate 105) instead of the gate structure discussed in this disclosure (e.g., H-type gate 205) is that the larger gate structure may block light directed toward the photodiode PD portion of the transfer transistor T1.

The above description of illustrated embodiments of the invention, including what is described in the Abstract of the disclosure, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (15)

1. A transistor device, comprising:

a transistor, comprising:

a source and a drain disposed in a substrate; and

a gate disposed over the substrate, wherein the gate includes:

a first longitudinal member disposed over the source and the drain and running substantially parallel to a channel of the transistor, wherein the first longitudinal member is disposed over a first junction isolation region;

a second longitudinal member disposed over the source and the drain and running substantially parallel to the channel of the transistor, wherein the second longitudinal member is disposed on an opposite side of the source and the drain from the first longitudinal member, and wherein the second longitudinal member is disposed over a second junction isolation region;

a lateral member running substantially perpendicular to the channel of the transistor and connecting the first longitudinal member to the second longitudinal member, wherein the lateral member is disposed above and between the source and the drain;

a first enclosing member running parallel to the transverse member and connected to the first longitudinal member and the second longitudinal member;

a drain cavity aligned over the drain and surrounded by portions of the first encapsulation member, the lateral member, and the first and second longitudinal members;

a second enclosing member continuing parallel to the transverse member and connected to the first and second longitudinal members on the opposite side thereof from the first enclosing member; and

a source cavity aligned over the source and surrounded by portions of the second encapsulation member, the lateral member, and the first and second longitudinal members,

wherein the device comprises image pixels, the device further comprising:

a photosensitive element for accumulating image charge in response to light;

a floating diffusion region to receive the image charge from the photosensitive element; and

a transfer gate disposed between the photosensitive element and the floating diffusion region to selectively transfer the image charge from the photosensitive element to the floating diffusion region,

wherein the transistor is coupled to read out the image charge from the floating diffusion region.

2. The device of claim 1, wherein a transfer transistor includes the photosensitive element, the floating diffusion region, and the transfer gate, and wherein the gate of the transistor is included in any transistor of the image pixel except for the transfer gate of the transfer transistor.

3. The device of claim 1, wherein the drain cavity is aligned over the drain and the source cavity is aligned over the source.

4. The apparatus of claim 1, wherein a width of the channel of the transistor is a distance between the first longitudinal component and the second longitudinal component.

5. The device of claim 1, wherein the source and the drain comprise a lightly doped region and a highly doped region.

6. The apparatus of claim 1, wherein a width of the channel of the transistor is a distance between the first longitudinal component and the second longitudinal component.

7. The device of claim 1, wherein the source and the drain comprise a lightly doped region and a highly doped region.

8. The device of claim 7, wherein the highly doped region of the source and the highly doped region of the drain are offset from being aligned below the lateral member.

9. The device of claim 1, wherein at least a portion of the source and at least a portion of the drain are aligned below the lateral member, an inside edge of the first longitudinal member, and an inside edge of the second longitudinal member.

10. An image sensor comprising an array of imaging pixels, each image pixel comprising:

a photosensitive element for accumulating image charge in response to light;

a floating diffusion region to receive the image charge from the photosensitive element; and

a transfer gate disposed between the photosensitive element and the floating diffusion region to selectively transfer the image charge from the photosensitive element to the floating diffusion region, wherein the floating diffusion region is coupled to a readout transistor and a reset transistor, each comprising:

a source and a drain disposed in a substrate; and

a gate disposed over the substrate, wherein the gate includes:

a first longitudinal member disposed over the source and the drain and running substantially parallel to a channel of the transistor, wherein the first longitudinal member is disposed over a first junction isolation region;

a second longitudinal member disposed over the source and the drain and running substantially parallel to the channel of the transistor, wherein the second longitudinal member is disposed on an opposite side of the source and the drain from the first longitudinal member, and wherein the second longitudinal member is disposed over a second junction isolation region;

a lateral member running substantially perpendicular to the channel of the transistor and connecting the first longitudinal member to the second longitudinal member, wherein the lateral member is disposed above and between the source and the drain, and wherein a distance between the first longitudinal member and the second longitudinal member defines a width of the channel of the transistor;

a first enclosing member running parallel to the transverse member and connected to the first longitudinal member and the second longitudinal member;

a drain cavity aligned over the drain and surrounded by portions of the first encapsulation member, the lateral member, and the first and second longitudinal members;

a second enclosing member continuing parallel to the transverse member and connected to the first and second longitudinal members on the opposite side thereof from the first enclosing member; and

a source cavity aligned over the source and surrounded by portions of the second encapsulation member, the lateral member, and the first and second longitudinal members.

11. The image sensor of claim 10, wherein at least a portion of the source and the drain are aligned below the lateral member, an inside edge of the first longitudinal member, and an inside edge of the second longitudinal member.

12. The image sensor of claim 10, wherein the drain cavity is aligned over the drain and the source cavity is aligned over the source.

13. The image sensor of claim 10, wherein a width of the channel of the transistor is the distance between the first and second longitudinal components.

14. A method of fabricating a transistor, the method comprising:

forming a polysilicon layer over a substrate;

etching the polysilicon layer to form a gate, wherein the gate includes a first longitudinal member and a second longitudinal member connected by a lateral member, wherein the first longitudinal member is disposed over a first junction isolation region, the second longitudinal member is disposed over a second junction isolation region;

forming a mask over the gate, the mask exposing drain and source regions in the substrate for implantation, wherein the mask also exposes a portion of the first and second longitudinal members and the entire lateral member of the gate for implantation; and

implanting dopants while forming the mask over the gate to form a source and a drain disposed in the substrate, wherein the source and the drain are self-aligned to the shape of the gate,

wherein the gate further comprises:

a first enclosing member running parallel to the transverse member and connected to the first longitudinal member and the second longitudinal member; and

a second enclosing member running parallel to the transverse members and connected to the first and second longitudinal members on the opposite side of the first and second longitudinal members from the first enclosing member.

15. The method of claim 14, further comprising:

forming an insulating sidewall around the gate;

forming a second mask over the gate, the second mask exposing a portion of the drain region and a portion of the source region for implantation; and

implanting a second dopant while forming the second mask over the gate, wherein the second dopant is added to the source and the drain disposed in the substrate.