HK1180455B - Isolation area between semiconductor devices having additional active area - Google Patents

Abstract

An isolation area that provides additional active area between semiconductor devices on an integrated circuit is described. In one embodiment, the invention includes a complementary metal oxide semiconductor transistor of an image sensor having a source, a drain, and a gate between the source and the drain, the transistor having a channel to couple the source and the drain under the influence of the gate, and an isolation barrier surrounding a periphery of the source and the drain to isolate the source and the drain from other devices, wherein the isolation barrier is distanced from the central portion of the channel.

Description

Isolation regions between semiconductor devices with additional active regions

Technical Field

The present invention relates generally to integrated circuits, and more particularly to reduction of random telegraph signal noise in complementary metal oxide semiconductor image sensor circuits.

Background

In integrated circuits, designers have attempted to increase circuit density. In other words, designers attempt to place more electronic devices in the same amount of space. The active devices are located in a region called the active region. Other regions are filled with insulators, spacers, or gaps that are simply unusable due to limitations of a particular layout design or manufacturing equipment.

In optical sensors, designers attempt to increase the amount of space for the photodiode (or any other type of optical sensor) compared to other devices. This allows for larger or more photoelectric sites in the same amount of space, thereby improving the quality of the sensor output, or reducing the overall size of the sensor with the same quality, or both. For optical sensors, increasing the amount of active area for the same total amount of area may allow for higher quality circuitry, or allow for a reduction in space for electronics for non-photoelectric sites.

STI (shallow trench isolation) and STI implant protection are used in integrated circuits to protect devices from other nearby devices. STI may be particularly useful for providing protection from devices that accumulate charge (e.g., capacitors, photodiodes, and power supply components). When transistors are protected using STI and STI implants, the width of the active area of the device becomes much smaller. For transistors, the active area under the gate region will typically be reduced. Thus, the device is made less efficient or must be made larger to accommodate STI and STI implant protection.

For photodiodes and sensor arrays, as the process scales down and the devices become smaller, the amount of charge accumulated by the photodiodes becomes smaller. As the signal level decreases, the signal-to-noise ratio becomes smaller. In order to maintain the same signal quality, the noise level must also be reduced. One noise source in the sensor array is RTS (random telegraph signal) noise, but other noise sources are also present. RTS noise is at least partially due to Si and SiO in the system₂Defects at the interface between the layers. It is believed that charge carriers are trapped and released at these interface defects. The charge measured on the other side of the defect will follow as it flows over the defectThe machine is increased or decreased. While this noise can cause problems in a variety of devices, it has a significant effect on the source follower transistors within the pixels. At low light levels, RTS noise from the source follower is the dominant noise source limiting imaging quality.

A variety of noise reduction techniques are used to reduce the effects of RTS noise. Correlated double sampling, for example, reduces the effects of a variety of random noise sources. However, it does not completely eliminate RTS noise. The pixels may also be physically modified to reduce the effects of RTS and other noise sources. The buried channel source follower has less RTS noise. This may be because the buried channel pushes the highest potential in the channel away from the Si-SiO₂Interface, thereby making the carrier from Si-SiO₂The likelihood of defect entrapment at the interface is minimized. These methods all require a large area, reducing pixel density and increasing cost.

Disclosure of Invention

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

Fig. 1A is a diagram of a top view of a partial de-layering of a conventional transistor structure implemented on a substrate of an integrated circuit.

Fig. 1B is a diagram of a cross-sectional view along line B-B of the conventional transistor of fig. 1A.

Figure 2A is a diagram of a top view of a partial de-layering of an improved transistor structure implemented on a substrate of an integrated circuit according to an embodiment of the invention.

Figure 2B is a diagram of a cross-sectional view along line B-B of figure 2A of the improved transistor structure of figure 2A, according to an embodiment of the invention.

Figure 3A is a diagram of a top view of a partial de-gradation with improved transistor structures adjacent photodiodes implemented on a substrate of an integrated circuit according to an embodiment of the invention.

Figure 3B is a diagram of a cross-sectional view along line B-B of figure 3A of the improved transistor structure of figure 3A, according to an embodiment of the present invention.

Fig. 4 is a diagram of a cross-sectional view of the starting layers of the transistor of fig. 3B including an implanted well according to an embodiment of the invention.

Fig. 5 is a diagram of a cross-sectional view of the structure of fig. 4 including a protective implant according to an embodiment of the present invention.

Figure 6 is a diagram of a cross-sectional view of the structure of figure 5 including a gate oxide and a gate electrode according to an embodiment of the invention.

FIG. 7 is a block diagram illustrating a backside illuminated imaging system according to an embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating pixel circuitry for two 4T pixels within a backside illuminated imaging system according to an embodiment of the invention.

FIG. 9 is a hybrid cross-sectional and circuit diagram of a backside illuminated imaging pixel with overlapping pixel circuits according to an embodiment of the present invention.

Detailed Description

According to one embodiment of the present invention, the channel directly under the source follower gate region is widened. This can be accomplished by removing most of the STI (shallow trench isolation) under the gate electrode as well as the adjacent STI protection doping features. These two features effectively narrow the transistor channel with which they are used. Widening the source follower transistor channel under its polysilicon gate electrode can be used to reduce electron trapping at the STI interface at the channel edge.

In one embodiment of the invention, additional active areas are added to the area between the transistor and the adjacent active area. This may increase the device width by avoiding STI and STI protection implants (p-type for NMOS, n-type for PMOS). Instead of STI structures, source regions are added. The enlarged active area causes electron flow from the source to the drain away from the STI sidewalls. Thus, any electron trapping and release along the STI sidewalls as well as along the typical top corners of the STI can be significantly minimized.

Embodiments of transistors having a wider active area under the gate are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. The term "or" as used herein is generally intended to encompass a meaning that includes a sexual function, such as "and/or".

Generally, integrated circuits include circuitry for a variety of applications. The applications use a wide variety of devices such as logic devices, imagers (including CMOS and CCD imagers), and memories (e.g., DRAM and NOR and NAND based flash memory devices). These devices typically employ transistors for performing a variety of functions, including the switching and amplification of signals. The invention is presented in the context of a CMOS (complementary metal oxide semiconductor) imaging integrated circuit in the form of a camera chip adapted for use with a camera for machine vision, recording and communication, although the invention is not so limited.

The term "substrate" includes substrates formed using semiconductors based on silicon, silicon-germanium, gallium arsenide, and the like. The term substrate may also refer to previous process steps that have been performed on the substrate to form regions and/or junctions in the substrate. The term substrate may also include various technologies such as doped and undoped semiconductors, epitaxial layers of silicon, and other semiconductor structures formed on a substrate. Although the invention is described in the context of transistors on a substrate, the structures may be formed on a substrate that may be thinned later.

FIG. 1A is a diagram of a top view of a conventional transistor structure 100 and related environment that can be implemented on a substrate for an integrated circuit for a photosensor array. The transistor may be a source follower of a sensor array as described below or any other transistor. The transistor is built on a substrate with a doped layer 120 or implanted well formed therein.

The source 180 and drain 190 of the transistor are disposed on either side of the central gate electrode 150. The source electrode contact 185, the drain electrode contact 195, and the gate electrode contact 170 allow electrical connection to be made to the node of the transistor. Isolation structures 155 are formed around the active regions of the source, drain and gate. The isolation structure 155 may be formed using a process such as Shallow Trench Isolation (STI) or local oxidation of silicon (LOCOS). The STI may be surrounded by STI protection implant layers 145 formed on either side of the STI.

The photosensitive region 125 is formed in doped layers on either side of the transistor. The photodiode is also surrounded by isolation structures 155, such as STI and protection implants 145, to isolate it from other nearby circuitry. In the illustrated example, the transistors may be source follower transistors between photodiodes of an image sensor array. However, the present invention is not limited thereto.

FIG. 1B is a diagram of a cross-section of the structure 100 of FIG. 1A taken along line B-B of FIG. 1A. Conventional transistor structures are implemented on a substrate 110 of an integrated circuit for a photosensor array. A doped layer 120 or implanted well is formed in the substrate as the base of the transistor. The doped implant region 120 is typically formed to have one conductivity or doping type (e.g., p-type). The substrates are typically of the same doping type (e.g., p-type).

Both the photosensitive region and the transistor have associated active areas, which are those substrate surface areas associated with each device that are enclosed by STI regions and demarcated at the surface of the substrate. In the illustrated example, any surface region enclosed by STI is an active region. The photosensitive region 125 can be formed by forming an n-type doped region and various contact structures (not shown) that can extend deep into the substrate. The photodiode is shown in a generalized shape in order to simplify the illustration. As is well known, the pinning layer 135 is formed over the photodiode.

STI isolation structures 155 are formed near or inside the p-well 120 to isolate the transistors and also around the photodiode to isolate the photodiode. The isolation structure 155 using the STI process may be formed by etching a void within the doped layer 120 and depositing a dielectric material (e.g., silicon dioxide) within the void. The deposited dielectric material may be planarized using CMP. STI protection implant layers 145 are formed on either side of the STI, typically after the formation of the voids but before the deposition of the dielectric fill material of the STI. This may be formed by implanting additional dopant material, such as boron, into the doped silicon layer 120 to form a protective layer. The STI protection implant acts as a protection barrier and helps keep the moving carriers of adjacent devices away from STI defects, but if any portion of the protection implant reaches into the active area of the transistor, it may consume some of the effective electrical width of the transistor channel portion of its active area.

The transistor gate includes a transistor gate electrode 150 formed on the gate oxide layer 130. A gate oxide layer 130 is grown on top of all the active areas and remains at least at the intersection between the transistor gate electrode and the transistor active area at the end of the fabrication process. A dielectric layer 165 is formed over center gate electrode 150 and gate oxide layer 130.

The source and drain (not shown) of the transistor are disposed along axes at right angles to the faces of the cross-section shown in fig. 1b. The source and drain are formed within a previously defined active region of the transistor. The region between the source and drain and under the gate (where transconductance occurs) is the transistor channel region.

Transistor gate electrode 150 is typically comprised of polysilicon and is formed on portions of the active region and portions of isolation structure 155.

Additional layers, such as, inter alia, an insulating layer 165, may be formed over the transistor gate electrode 150 and regions that isolate the STI structures 155 and the protection implants 145. Metal contacts (e.g., contact 170) may be formed within the insulating layer by etching cavities and filling the cavities with metal. Metallization layers or other types of conductive traces may be formed on portions of the metal contacts and insulating layers so that electrical connections may be made between the transistor gate electrode 150 and other devices formed within the substrate 110 and above within the substrate 110.

Fig. 2A is a diagram of a top view of a novel transistor structure 200 with reduced RTS noise. This transistor may also be implemented on a substrate for an integrated circuit of a photosensor array, although the invention is not so limited. The transistor may be a source follower of a sensor array as described below or any other transistor. The transistor is built on a substrate into which a doped layer 220 or implanted well is formed.

The source 280 and drain 290 of the transistor are disposed on either side of the central gate 250. The source electrode contact 285, the drain electrode contact 295, and the gate electrode contact 270 allow electrical connection to be made to the node of the transistor. Isolation structures 255 (e.g., STI) are formed around the active areas of the source, drain, and gate. The STI may be surrounded by STI protection implant layers 245 (e.g., formed on either side of the STI, see fig. 2B).

In contrast to the STI structure of fig. 1A and 1B, in the example of fig. 2A, the STI extrapolates away from the normal boundary region of the active area under the gate electrode defining the additional active area along a portion of the channel region as shown. The channel region in a conventional layout is a region with a high current density during conduction of the transistor, where part of the current flows from source to drain along the STI regions that define it on both sides.

The interaction of the channel current with it to define the STI can be a significant cause of RTS noise. By transferring the STI under the gate electrode as shown in fig. 2A and thereby expanding the active area along a portion of the transistor channel, there is reduced interaction due to increased separation of the channel current from the STI, and thus RTS noise is reduced. However, this configuration may affect the operation of the transistor, as the channel width may not be constant along the length of the transistor. The channel width can also be affected by transferring the STI outward over a portion of the transistor length.

Figure 2B is a diagram of a cross section of the transistor structure of figure 2A taken along line B-B of figure 2A. In fig. 2A, it can be readily seen that the STI255 is farther from the transistor channel region located inside the transistor or the implanted well 220 of the transistor than in fig. 1B. It can also be seen that the STI protection implant layer 245 is also farther from the transistor channel region. This allows for a wider channel in the transistor along a portion of its length, possibly improving its performance. In addition, it reduces RTS noise that may be caused by STI near the channel.

As in fig. 1B, the transistors are implemented on a substrate 210 of an integrated circuit. For BSI (backside illumination) photosensors, the substrate may be thinned to improve the blue and green response. Structure 200 includes a substrate 210 on which a doped well implant layer 220 (e.g., p-type) is formed. Protective isolation structures 255, such as STI with STI protective implant layer 245, are formed on either side of doped layer 220. The source and drain (not shown) are typically formed using a material having a second conductivity type (e.g., n-type). A gate oxide layer 230 is formed over the trench and STI.

The transistor gate electrode 250 is typically comprised of polysilicon and is shown in the cross-section of fig. 2B as being formed over a region of the gate oxide layer 230. Additional layers, such as, inter alia, insulating layer 265, may be formed over transistor gate electrode 250 and regions of isolation structures 255 and protection implants 245. Metal contacts (e.g., contact 270) may be formed within the insulating layer by etching cavities and filling the cavities with metal. Metallization layers or other types of conductive traces may be formed on the metal contacts as well as portions of the insulating layer so that electrical connections may be made between the transistor gate electrode 250 and other devices formed within and above the substrate.

Fig. 3A shows the same transistor structure as in fig. 2A, modified to accommodate a photodiode 225 on either side of the transistor. These photodiodes are similar to the photodiodes of fig. 1A and 1B. As in fig. 1A and 2A, the figures are similar to a partially de-hierarchal plan view. Gate electrode 250 is coupled to gate electrode contact 270. Source 275 and contact 280 are on one side of the gate, while drain 290 and contact 295 are on the other side of the gate. The transistor is formed in the active region 220 between the source 275 and the drain 290 in an implanted well 220 located between two n-type photodiodes 225. The source 280 and drain 290 are formed as n-type implants and are isolated from the n-type photodiode by a p-type well 220 in which the source and drain are disposed. The source and drain are also isolated by the p-type substrate underlying the entire structure and by the STI layer 255 (where present). The p-type implanted well 215 may also isolate the n-type photodiode from the transistor in the absence of STI between the n-type photodiode and the transistor.

In the illustrated example, STI255 is used to isolate the photodiode and active area and source follower from any external components, as well as partially isolate them from each other. Although the STI layer is shown as a single layer in this and some other figures, it may also include an implanted protective layer, such as boron protection implant layer 145 as shown in fig. 1B.

In contrast to fig. 2A, the STI255 in fig. 3A does not completely surround and isolate the channel of the transistor. Rather, the STI barrier extends away from the transistor active area and toward the photodiode 225. This occurs near the edges of the gate electrode on both sides of the gate. The STI barrier is then joined with the STI barrier of the photodiode. Similarly, the STI barrier of the photodiode does not completely surround the photodiode, but faces away from the photodiode and toward the transistor gate electrode. This leaves a portion of the active area of the transistor unprotected by the protective STI isolation trench. This also leaves the portion of the photodiode closest to the gate unprotected by the protective STI isolation trench. Thus, the active area of the transistor has no STI along a portion of its channel and RTS noise is reduced.

As shown in fig. 3A, additional lines of STI256 extend between the periphery of the transistor and the periphery of the photodiode. Typically, such a line will also include a protective implant layer (not separately shown). This line connects the STI of the transistor with the STI of the nearest photodiode. While these lines effectively isolate the transistors and photodiodes from other nearby components (not shown), they do not isolate the transistors and photodiodes from each other. To this end, an additional p-well 215 is formed at the edge of the transistor and photodiode.

The STI barrier defines the width of the source follower channel by defining the width of the active region where the source 280 and drain 290 meet the channel at the edge of the gate electrode 250. However, the central region of the source follower channel does not have an STI layer defining it. In this central region of the source follower contained within doped layer 220 and along the length of doped layer 220, the channel width is defined by additional p-well 215.

Referring to fig. 3B, additional p-wells 215 can be seen on either side of the transistor channel and overlap doped layers 220. Fig. 3B is a diagram of a cross section of the alternative transistor structure of fig. 3A taken along B-B in fig. 3A. The transistor of fig. 3B is substantially the same as the transistor of fig. 2B, except for the pattern of the STI and the additional p-well. As shown, the active area of the central portion of the channel of fig. 3B is larger than the corresponding area of fig. 2B. The presence of this additional active area is primarily at the expense of STI isolation regions and STI protection implants that no longer define or delimit the channel width in that region.

The additional p-well 215 serves to isolate the source follower channel from the photodiode. The additional p-well 215 may typically have the same doping concentration as the p-doped well 220 or a higher doping concentration than the p-doped well 220. The additional p-type well 215 may typically have a doping concentration equivalent to that of the guard implant 245.

For a photosensor array, the elimination of a portion of the STI region along the length of the source follower channel (as shown) provides a slightly wider channel and greatly reduces the RTS noise source. The particular shapes, locations, and relative sizes may be modified to suit any particular application.

Fig. 4-6 are diagrams of the transistor structure of fig. 3B at different stages of formation. Fig. 4 shows substrate 210 with doped layer 220 formed over it as a well implant. The doped layer 220 is generally formed to have the first conductivity type. For example, the first conductivity type may be p-type and the second conductivity type may be n-type, or vice versa. Doped layer 220 may be, for example, a p-well formed in a p-type substrate. Various levels of dopant implantation may be applied to form various structures and/or to adjust transistor voltage thresholds. In one example, at 10¹³A/cc to 10¹⁵Doped layer 220 is doped at a concentration of/cc. The center doped layer contains the active region of the transistor.

Similarly, an n-doped region 225 of the photodiode can be formed on either side of the transistor. The photodiode may be doped to 10¹⁴A/cc to 10¹⁶And/cc, depending on the particular embodiment. Additional components may be formed in additional wells, depending on the particular embodiment. Photoresist may be used to cover some areas to form these deposition areas while depositing dopants on other areas and then removing the photoresist, as is known in the art.

In fig. 5, isolation structure 215 may be formed as a well on either side of doped well 220. Isolation structure 215 is formed alongside or abutting or overlapping doped well 220 and may be formed by doping or implanting a first conductivity type (e.g., p-type). In addition, a pinning layer 235 is formed on the photodiode region 225. Typically, the isolation region is masked while the central p-well and photodiode regions are formed. Next, the central well is masked while forming a p-type isolation region in the remaining portion of the active region.

Figure 6 shows the structure after a gate oxide layer 230 is formed by forming a silicon dioxide film on the surface of the active area (i.e., anywhere there is no STI). Isolation and protection implant regions (not shown) may be added, in addition to the gate oxide layer 230, as desired, to either side of the STI regions, for example. A polysilicon layer is deposited for the transistor gate electrode 250. As shown, gate oxide 230 separates gate electrode 250 from protective implant region 215. The gate electrode 250 may extend over the top of the gate oxide region and the isolation region 215. Gate electrode 250 may be formed by depositing polysilicon, polysilicon/silicide, and/or any other suitable conductor or metal layer. Suitable metals include Ni, W, Ti, Co, and silicides of these and other metals. Sidewall insulating spacers (not shown) may also be formed using conventional processes.

The source and drain (not shown) may have been formed prior to the formation of the gate oxide 250 and isolation region 245, but are typically formed after the gate oxide. These elements are located in front of and behind the plane of the cross-section shown in the figures, as indicated in fig. 2A and 3A. The gate electrode 250 may be patterned using a resist and an etching method.

In one embodiment, a contact etch stop layer (not shown) may be deposited on the gate electrode of the transistor. The contact etch stop layer may be Ti, TiN, or a suitable material having a low resistivity. The etch stop layer may then be used in conjunction with the etch and may be thinned using CMP. A deposited and planarized insulating layer 265, such as BPSG (borophosphosilicate glass), PSG (phosphosilicate glass), BSG (borosilicate glass), etc., may also be added to complete the device. The insulating layer may be planarized using, for example, CMP, resist etch back, or spin-on glass (SOG) to form the resulting structure. After deposition of the insulating layer, contacts and electrical connections may also be formed.

The gate electrode contact 270 may be formed by first forming a void by etching or in some other manner. A contact etch stop layer may be used to control the depth of the etch. The contact etch may stop at the gate electrode surface or may be allowed to proceed within the gate electrode. The gate contact may then be formed in any of a number of different ways, such as by depositing a metal layer on or within the void etched into the insulating layer. Metallization layers and additional insulating layers may be added to suit any particular application. The contacts are coupled to other components or circuits that are not shown for simplicity of illustration.

Fig. 7 is a block diagram illustrating a backside illuminated imaging system 201 to which embodiments of the present invention may be applied. The illustrated embodiment of imaging system 201 includes pixel array 206, readout circuitry 211, functional logic 216, and control circuitry 221.

Pixel array 206 is a two-dimensional ("2D") array of backside illuminated imaging sensors or pixels (e.g., pixels P1, P2 …, Pn). In one embodiment, each pixel is a Complementary Metal Oxide Semiconductor (CMOS) imaging pixel. As illustrated, each pixel is arranged into rows (e.g., rows R1-Ry) and columns (e.g., columns C1-Cx) to acquire image data of a person, place, or object, which can then be used to render a 2D image of the person, place, or object.

After each pixel has acquired its image data or image charge, the image data is read out by readout circuitry 211 and transferred to functional logic 216. The readout circuitry 211 may include amplification circuitry, analog-to-digital ("ADC") conversion circuitry, or other circuitry. Function logic 216 may simply store the image data or otherwise manipulate the image data by applying post-image effects (e.g., cropping, rotating, removing red-eye, adjusting brightness, adjusting contrast, or other effects). In one embodiment, readout circuitry 211 may readout a row of image data along readout column lines (illustrated) one row at a time, or may readout the image data using a variety of other techniques (not illustrated), such as a serial readout or a full parallel readout of all pixels simultaneously.

The control circuit 221 is coupled to the pixel array 206 to control the operating characteristics of the pixel array 206. For example, the control circuit 221 may generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal is a global shutter signal used to simultaneously enable all pixels within pixel array 206 to simultaneously capture their respective image data during a single acquisition window. In an alternative embodiment, the shutter signal is a rolling shutter signal, whereby each row, column, or group of pixels is sequentially enabled during successive acquisition windows.

FIG. 8 is a circuit diagram illustrating a pixel circuit 301 that back-illuminates two four-transistor ("4T") pixels within an imaging array, according to an embodiment of the invention. The illustrated pixel circuit 301 is one possible pixel circuit architecture for implementing each pixel within the pixel array 201 of fig. 2. However, it should be understood that embodiments of the invention are not limited to 4T pixel architectures; indeed, one of ordinary skill in the art having had the benefit of the present disclosure will appreciate that the present teachings are also applicable to 3T designs, 5T designs, and various other pixel architectures.

In fig. 8, pixels Pa and Pb are arranged in two rows and one column. The illustrated embodiment of each pixel circuit 301 includes a photodiode PD, a transfer transistor T1, a reset transistor T2, a source follower ("SF") transistor T3, a select transistor T4, and a storage capacitor C1. During operation, transfer transistor T1 receives a transfer signal TX that transfers charge accumulated in photodiode PD to floating diffusion node FD. In one embodiment, floating diffusion node FD may be coupled to a storage capacitor for temporarily storing image charge.

A reset transistor T2 is coupled between the power supply rail VDD and the floating diffusion node FD to reset the pixel (e.g., discharge or charge the FD and PD to a preset voltage) under control of a reset signal RST. Floating diffusion node FD is coupled to control the gate of SF transistor T3. SF transistor T3 is coupled between the power supply rail VDD and select transistor T4. SF transistor T3 operates as a source follower providing a high impedance connection to floating diffusion FD. Finally, select transistor T4 selectively couples the output of pixel circuit 300 to the readout column line under control of a select signal SEL.

In one embodiment, the TX signal, the RST signal, and the SEL signal are generated by control circuitry 221. In embodiments where the pixel array 206 operates with a global shutter, a global shutter signal is coupled to the gate of each transfer transistor T1 in the entire pixel array 206 to simultaneously begin the transfer of charge from each pixel's photodiode PD. Alternatively, the rolling shutter signal may be applied to a group of transfer transistors T1.

Fig. 9 is a hybrid cross-section and circuit diagram of a backside illuminated imaging pixel 401 with overlapping pixel circuits according to an embodiment of the present invention. Imaging pixel 401 is one possible implementation of pixels P1 through Pn within pixel array 206. The illustrated embodiment of imaging pixel 401 includes a substrate 405, a color filter 410, a microlens 415, a PD region 420, an interconnect diffusion region 425, a pixel circuit region 430, a pixel circuit layer 435, and a metal stack 440. The illustrated embodiment of pixel circuit area 430 includes 4T pixels (which may be replaced with other pixel designs) as well as other circuits 431 (e.g., gain circuits, ADC circuits, gamma control circuits, exposure control circuits, etc.) disposed on diffusion wells 445.

Floating diffusion 450 is disposed within diffusion well 445 and is coupled between the gates of transfer transistor T1 and SF transistor T3. The illustrated embodiment of metal stack 440 includes two metal layers M1 and M2 separated by inter-metal dielectric layers 441 and 443. Although fig. 9 illustrates only two layers of metal stacks, metal stacks 440 may include more or fewer layers for routing signals on the front side of pixel array 206. In one embodiment, a passivation or pinning layer 470 is disposed on the interconnect diffusion region 425. Finally, STI regions isolate imaging pixel 401 from neighboring pixels (not illustrated).

As illustrated, the imaging pixels 401 are photosensitive to light 480 incident on the back side of their semiconductor die. By using a backside illumination sensor, the pixel circuit region 430 can be positioned in an overlapping configuration with the photodiode region 420. In other words, the pixel circuit 300 can be placed near the interconnected diffusion regions 425 and between the photodiode region 420 and the front side of the die without preventing the light 480 from reaching the photodiode region 420.

By placing the pixel circuits in an overlapping configuration with the photodiode region 420, the photodiode region 420 no longer competes with the pixel circuits for valuable die real estate as opposed to a side-by-side configuration. In fact, pixel circuit area 430 may be enlarged to accommodate additional or larger components without detracting from the fill factor of the image sensor. Embodiments of the present invention enable other circuits 431, such as gain control or ADC (analog-to-digital converter) circuits (e.g., ADC305), to be placed in close proximity to the respective photodiode region 420 without reducing the sensitivity of the pixel. By inserting gain control and ADC circuits in close proximity to each PD region 420, circuit noise may be reduced and noise immunity improved because electrical interconnections between PD regions 420 and additional intra-pixel circuitry are shorter. Furthermore, the backside illumination configuration provides greater flexibility in routing signals on the front side of the pixel array 206 within the metal stack 440 without interfering with the light 480. In one embodiment, shutter signals are routed within the metal stack 440 to pixels within the pixel array 206.

In one embodiment, pixel circuit regions 430 over PD regions 420 of adjacent pixels within pixel array 206 may be grouped to create a common die footprint. This common die footprint may support shared circuitry (or inter-pixel circuitry) in addition to the basic 3T, 4T, 5T, etc. pixel circuitry. Alternatively, some pixels may contribute their unused die footprint over their PD region 420 to neighboring pixels that require additional pixel circuit space to implement larger or more advanced intra-pixel circuitry. Thus, in some embodiments, other circuitry 431 may overlap with two or more PD regions 420 and may even be shared by one or more pixels.

In one embodiment, the substrate 405 is doped with a p-type dopant. In this case, the substrate 405 and the epitaxial layers grown thereon may be referred to as a p-substrate. In a P-type substrate embodiment, the diffusion well 445 is a P + well implant, while the photodiode region 420, the interconnect diffusion region 425, and the floating diffusion 450 are n-type doped. The floating diffusion 450 is doped with dopants of the opposite conductivity type from the diffusion well 445 to create a p-n junction within the diffusion well 445, thereby electrically isolating the floating diffusion 450. In embodiments where the substrate 405 and the epitaxial layers thereon are n-type, the diffusion wells 445 are also n-type doped, while the photodiode region 420, the interconnect diffusion region 425, and the floating diffusion 450 have opposite p-type conductivity.

The above description of illustrated embodiments of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Indeed, the scope of the invention should be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (14)

1. A light sensor circuit, comprising:

a complementary metal oxide semiconductor transistor of an image sensor having a source, a drain and a gate electrode between the source and the drain, the transistor having an active region located below the gate electrode, the active region forming a channel between the source and the drain under the influence of the gate electrode; and

an isolation barrier disposed along outer edges of the source and the drain that are not directly below the gate electrode, the isolation barrier continuing below the gate electrode and then extrapolating away from the active area while still below the gate electrode, wherein a restricted section of the isolation barrier continuing below the gate electrode isolates the channel to a first width before extrapolating away from the active area, and wherein the extrapolated section of the isolation barrier extrapolates away from the active area such that a width of the channel becomes wider than the first width.

2. The circuit of claim 1, wherein the isolation barrier comprises shallow trench isolation.

3. The circuit of claim 1, further comprising a photodiode of the image sensor, the transistor having a first conductivity type, and the photodiode having a second conductivity type, wherein a central portion of the channel is wider than the first width, and wherein the isolation barrier is absent between the central portion of the channel and the photodiode under the gate electrode.

4. The circuit of claim 3, further comprising an isolation region between the channel and the photodiode, the isolation region having the first conductivity type to isolate the channel from the photodiode.

5. The circuit of claim 4, wherein the isolation region is to isolate the channel without the isolation barrier.

6. The circuit of claim 5, wherein the central portion of the channel underlying the gate electrode of the transistor is isolated by the isolation region.

7. The circuit of claim 3, wherein the transistor comprises a source follower transistor, and wherein the isolation barrier comprises shallow trench isolation between the transistor source and the photodiode and between the transistor drain and the photodiode.

8. The circuit of claim 4, wherein the isolation region is doped to have the first conductivity type, and wherein the isolation region is doped to a concentration equal to or higher than the channel.

9. The circuit of claim 4, wherein the central portion of the channel abuts the isolation region, and wherein the photodiode is adjacent to the isolation region.

10. A light sensor array, comprising:

a plurality of complementary metal oxide semiconductor source follower transistors, each formed within a respective well of semiconductor material, the wells having a first conductivity type, each transistor having a source, a drain and an active region for forming a channel underlying a gate;

a plurality of photodiodes formed in the semiconductor material, each formed in a well of a second opposite conductivity type and having a detector region;

an isolation barrier disposed along an edge of the source and the drain facing away from the gate electrode, the isolation barrier continuing under the gate electrode and then extending away from the active region while still under the gate electrode, wherein a restricted section of the isolation barrier extending under the gate electrode before extending away from the active region isolates each respective channel to a first width, and wherein an extended section of the isolation barrier extends away from the active region such that the width of each respective channel becomes wider than the first width; and

an isolation region between a central portion of each respective channel and a corresponding photodiode, the isolation region formed within the semiconductor material as a well of the first conductivity type to isolate the transistor from the photodiode.

11. The light sensor array of claim 10, wherein the isolation barrier comprises shallow trench isolation, and wherein the isolation barrier is disposed between the source and the photodiode and between the drain and the photodiode.

12. The photosensor array of claim 10, wherein the isolation region abuts the central portion of each respective channel.

13. The photosensor array of claim 10, wherein the isolation region is distal to the central portion of each respective channel.

14. The photosensor array of claim 10, wherein the transistors are formed in p-type implant wells of the semiconductor material, and wherein the isolation regions are formed as p-type implant wells having a doping equal to or higher than a doping of the transistor implant wells.