HK1179760B - A semiconductor device having an efuse structure for a one time programmable memory - Google Patents

Abstract

The present invention is directed to a semiconductor device having an eFuse structure for a one time programmable memory(OTP) and method of fabrication thereof. The semiconductor device comprising: a base substrate having a shallow trench isolation (STI) formation; a first metal layer formed on the STI formation, having a shape that defines an anode, a cathode, and a fuse neck connected between the cathode and the anode; an undoped polysilicon (poly) region formed on the fuse neck of the first metal layer; and a second metal layer having a first portion and a second portion that are formed on the first metal layer on opposite sides of the poly region, the first portion of the second metal layer formed on the anode, and the second portion of the second metal layer formed on the cathode.

Description

Semiconductor device having electric fuse structure for one-time programmable memory

Technical Field

The present invention relates generally to one-time programmable (OTP) memories and, more particularly, to OTP memories fabricated using a Gate-last high-K metal Gate (Gate-last high-KMetalGate) fabrication process.

Background

In the field of data storage, there are two common types of storage devices. The first type of storage device is a volatile memory. Volatile memory loses stored information when power is removed from the volatile memory circuit. The second type of storage device is a non-volatile memory. Nonvolatile memory retains stored information even after power is removed from the nonvolatile memory circuit. Some non-volatile memory designs allow reprogramming, while others allow only one-time programming.

One-time programmable (OTP) memory represents a type of non-volatile memory that can be programmed once, typically by permanently programming fuses to open a connection, or by permanently programming anti-fuses (anti-fuses) to close a connection.

Currently, the following types of fuses are utilized as electrical fuses (electronic fuses, eFuses): gate oxide breakdown (gateoxidebeakdown), hot carriers, silicide fuses, interconnected metal fuses (interconnected metal fuses). The HKMG process allows for a high-K dielectric to replace the silicon dioxide gate dielectric used in prior generation casting techniques. The use of high-K dielectrics allows further miniaturization of micro-electrical components. Furthermore, the previous generation fuses require high current levels on the order of hundreds of microamperes to blow.

What is needed, therefore, is an electrical fuse that is compatible with the HKMG process conventionally utilized in 28nm casting techniques. In addition, it would be beneficial if electrical fuses could be utilized by applying lower current levels than conventional electrical fuses.

Disclosure of Invention

According to an embodiment of the present invention, there is provided a semiconductor device having an electrical fuse structure for a one-time programmable memory (OTP), including: a base substrate having a Shallow Trench Isolation (STI) structure; a first metal layer formed on the STI structure, having a shape defining an anode, a cathode, and a fuse neck connected between the cathode and the anode; an undoped polysilicon (poly) region formed on the fuse neck of the first metal layer; and a second metal layer having a first portion and a second portion formed on the first metal layer and on opposite sides of the polycrystalline region, the first portion of the second metal layer being formed on the anode and the second portion of the second metal layer being formed on the cathode.

According to the semiconductor device of the present invention, the polycrystalline region is formed only on the fuse neck of the first metal layer, and separates the first portion and the second portion of the second metal layer.

According to the semiconductor device of the present invention, the polycrystalline region has a substantially higher resistance than the first metal layer and the second metal layer.

According to the semiconductor device of the present invention, if a voltage is applied across the anode and the cathode, the resulting current mainly flows through the fuse neck of the first metal layer.

According to the semiconductor device of the present invention, the OTP is programmed by increasing the current until the fuse neck of the first metal layer fails and becomes substantially open.

According to the semiconductor device of the present invention, the current required to open the fuse neck is in the order of single digit microamperes.

According to the semiconductor device of the present invention, the thickness of the first metal layer is substantially smaller than the thickness of the second metal layer and the polycrystalline region.

The semiconductor device of the present invention wherein the first metal layer has a thickness of between about 5 nm and about 30nm and the second metal layer has a thickness of between about 30nm and about 70 nm.

According to the semiconductor device of the present invention, the second metal layer connects the electrical fuse structure to the blown MOSFET.

According to the semiconductor device of the present invention, wherein the blown MOSFET is configured to supply a current to the electrical fuse to melt the first metal layer.

The semiconductor device according to the present invention further comprises a high-K dielectric layer disposed between the STI region and the first metal layer.

According to the semiconductor device of the present invention, wherein a width of the first metal layer in the fuse neck is substantially smaller than a corresponding width of the first metal layer in the anode or the cathode.

According to the semiconductor device of the present invention, the width of the first metal layer in the fuse neck is about 20 to 50 nm.

According to an embodiment of the present invention, there is provided a semiconductor device having an electrical fuse structure for a one-time programmable memory (OTP), including: a base substrate having a Shallow Trench Isolation (STI) structure; an anode comprising a first portion of a first metal layer; a first portion of a second metal layer disposed on and in contact with the first portion of the first metal layer; a cathode comprising a second portion of the first metal layer; a second portion of the second metal layer disposed on and in contact with the second portion of the first metal layer; a fuse neck connecting the anode to the cathode, including a third portion of the first metal layer; an undoped polysilicon (poly) region disposed on and in contact with the third portion of the first metal layer, the poly region disposed between and separating the first and second portions of the second metal layer; wherein the first, second and third portions of the first metal layer are laterally disposed on the STI structure in a continuous manner to provide a low resistance current path from anode to cathode prior to programming.

According to the semiconductor device of the present invention, the thickness of the first metal layer is substantially smaller than the thickness of the second metal layer.

According to the semiconductor device of the present invention, the resistance of the polycrystalline region is substantially higher than the resistance of the first metal layer, so that the current carried (transmitted) by the current path mainly flows through the first metal layer.

According to the semiconductor device of the present invention, the OTP is programmed by increasing the current until the third portion of the first metal layer fails, causing a high resistance current path between the anode and cathode.

According to an embodiment of the present invention, there is provided a method including: forming a dummy layer on a surface of an STI structure within a semiconductor substrate, the dummy layer including a high-K dielectric layer, a metal layer, an undoped polysilicon (poly) layer, and a nitride layer; forming a gate pattern in an electric fuse region using an etching process on the dummy layer providing the electric fuse gate; removing the nitride layer over the poly layer in the electrical fuse region; forming a mask on a portion of the polycrystalline layer; removing exposed portions of the polycrystalline layer not covered by the mask, thereby forming a fuse neck polycrystalline region and an empty shell on opposite sides of the fuse neck polycrystalline region; removing the mask; and filling a second grid metal layer in the hollow shell.

The method according to the present invention, wherein the fuse neck poly region is a portion of an electrical fuse structure including a cathode, an anode, and a fuse neck connected between the cathode and the anode.

According to the method of the present invention, wherein the fuse neck polycrystalline layer exists only on the fuse neck further including a portion of the first metal layer

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.

Fig. 1 shows the layout of a conventional OTP circuit.

Fig. 2a-2c show top and cross-sectional views of a known electrical fuse structure.

Fig. 3 shows a layout of an OTP circuit according to an exemplary embodiment of the present invention.

Fig. 4a-4c show top and cross-sectional views of an electrical fuse structure according to an exemplary embodiment of the present invention.

Fig. 5 shows a flowchart providing exemplary steps for manufacturing an IC arrangement according to an embodiment of the present invention.

Fig. 6a-6h illustrate the products of exemplary steps processed in the flowchart of fig. 5 according to an exemplary embodiment of the present invention.

Fig. 7a-7b illustrate top and cross-sectional views of another electrical fuse structure in accordance with an exemplary embodiment of the present invention.

The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements (elements). Additionally, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears.

Detailed Description

The following detailed description refers to the accompanying drawings to illustrate exemplary embodiments consistent with this invention. References in the detailed description to "one exemplary embodiment," "an exemplary embodiment," etc., indicate that the exemplary embodiment described may include a particular feature, structure, or characteristic, but every exemplary embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such terms do not necessarily refer to the same exemplary embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an exemplary embodiment, it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other exemplary embodiments whether or not explicitly described. Furthermore, it should be understood that the spatial descriptions used herein (e.g., "above," "in.. below," "up," "left," "right," "down," "top," "bottom," "vertical," "horizontal," etc.) are for illustrative purposes only, and that actual implementations of the structures described herein may be spatially arranged in any direction or manner.

The exemplary embodiments described herein are provided for purposes of illustration and are not intended to be limiting. Other exemplary embodiments are possible, and modifications may be made to these exemplary embodiments within the spirit and scope of the invention. Therefore, the detailed description is not intended to limit the invention. Rather, the scope of the invention is to be defined only by the following claims and their equivalents.

The following detailed description of exemplary embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge within the skill of the relevant art, readily modify and/or adapt for various applications such exemplary embodiments without undue experimentation, without departing from the spirit and scope of the present invention. Therefore, such adaptations and modifications are intended to be encompassed within the meaning and variety of equivalents of the exemplary embodiments based on the teachings and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings herein.

The exemplary embodiments described herein are provided for illustrative purposes and are not limiting. Further structural and operational implementations, including modifications/alterations, will become apparent to persons skilled in the relevant arts in light of the teachings herein.

Conventional electrical fuse

Fig. 1 shows the layout of a conventional OTP circuit 100. The OTP circuit 100 includes a decoder 102 that provides a voltage to the gate of a MOSFET 104. In addition, the voltage Vdd is applied to the anode (negative electrode) of the electrical fuse 108, and the cathode (positive electrode) of the electrical fuse 108 is coupled to the MOSFET 104. (electrical fuses will be explained herein as semiconductor fuse elements that may be used to support, for example, OTP.) current 106 is allowed to flow based on the voltage applied to the gate of MOSFET104, resulting in a blow (blowout) in conventional electrical fuse 108. The reason why the blowing occurs is because the portion of the electrical fuse 108 is too narrow for carrying current, causing thermal destruction of the semiconductor material constituting the portion of the electrical fuse.

FIG. 2a shows a top view of a conventional electrical fuse 200 having a silicide used as a fuse element. It includes an anode 201 connected to a cathode 203 via a fuse neck (fuse) 202. In one embodiment, the electrical fuse 200 may be functionally similar to the electrical fuse 108.

Fig. 2b shows a cross-sectional view of a conventional electrical fuse 200 before any programming occurs. It includes a Shallow Trench Isolation (STI) structure (feature) 204, with a polysilicon (poly) layer 205 over the STI structure 204. A top silicide layer 206 is over the poly 205, where the poly 205 carries any current during programming and breaks down if programmed to do so, creating an open circuit as shown in figure 2 c.

Fig. 2c shows a cross-sectional view of the conventional electrical fuse 200 after programming has occurred. Due to the application of programming, there is a blow in the blow region 207 of the silicide layer 206. This programming will cause the bit to read a "0" as opposed to a "1" because it will be in the pre-programmed state presented in FIG. 2 b.

The electrical fuse 200 is not compatible with the back gate HKMG process. The back gate HKMG process requires a process in which a high-K dielectric layer is used for the gate structure. In addition, during fabrication, the deposition of the gate metal is the final step in the process and replaces the silicide layer 206. The electrical fuse 200 is not compatible with the back gate HKMG process because it does not include a high-K dielectric and utilizes a silicide layer on top.

Details of the invention

Fig. 3 shows a layout of an OTP circuit 300 according to an exemplary embodiment of the present invention. The OTP circuit 300 includes a decoder 302 that provides a voltage to the gate of a MOSFET 304. In addition, a voltage Vdd is applied to the anode 312, and the cathode 314 is coupled to the drain of the MOSFET 304. Based on the voltage applied to the gate of MOSFET304, current 306 is allowed to flow, resulting in the blowing of fuse neck region 308 in electrical fuse 310. Specifically, when the MOSFET304 is conductive, then the cathode 314 is grounded, resulting in a current 306 flowing through the fuse neck region 308. Because there is no resistance in the current path (other than the wire resistance), the fuse neck region will thermally break, creating an open circuit.

Fig. 4 illustrates a top view of an electrical fuse 400 according to an exemplary embodiment of the present invention. It comprises an anode 401 connected to a cathode 403 via a fuse neck 402. The region 404 of the fuse neck 402 comprises undoped polysilicon, which has a relatively high resistivity compared to the semiconductor metal layer.

Fig. 4b shows a cross-sectional view of the electrical fuse 400 before any programming occurs. It includes an STI structure 405 with a high-K dielectric layer 406 disposed over the STI structure 405. A first gate metal layer 407 is disposed over high-K dielectric layer 406. A second gate metal layer 408 is disposed over the first gate metal layer 407, wherein the second gate metal layer 408 has a first portion 408a and a second portion 408b, wherein an undoped poly structure 409 is between the first portion 408a and the second portion 408 b. The undoped poly structure 409 extends in the horizontal direction, as shown in the figure, for the same length as the region 404 discussed above. Prior to programming, gate metal layer 407 is laterally continuous and has a low resistance between anode 401 and cathode 403. Undoped poly structure 209 provides high resistance and is located on top of gate metal layer 407 and separates the first and second portions of second gate metal layer 408.

In one embodiment, the anode 401, the fuse neck 402, and the cathode 403 may be functionally similar to the anode 312, the cathode 314, and the fuse neck region 308, respectively.

FIG. 4c shows a cross-sectional view of the electrical fuse 400 after programming has occurred, in accordance with an exemplary embodiment of the present invention. Due to the programming application, there is a blow in the blow region 410 of the gate metal layer 407. After the gate metal layer 407 has blown in the blown region 410, there is a high resistance between the anode 401 and the cathode 403, since only the signal channel is provided by the undoped poly structure 409, which has a high resistance with respect to the continuous metal layer 407.

In an exemplary embodiment of the invention, the width 411 of the neck fuse 404 (e.g., the gate metal layer 407) may be 20-50 nm. In addition, the gate metal layer 407 as a fuse may have a thickness 412 of 5-30 nm. However, the second gate metal layer 408 may have a thickness 413 of 30-70 nm. Thus, second gate metal layer 408 may be moderately substantially thicker than first gate metal layer 407.

An advantage of the OTP structure is that it is sufficiently compatible with a 28nm back-gate high-K metal gate process without the need for additional processes or masks. In addition, because the gate metal is used as the fuse material, the thickness can be reduced to a relatively small size (5-30 nm), which requires less current to blow the fuse than conventional silicides. For example, in one exemplary embodiment, the current may be on the order of microamperes, rather than the hundreds of microamperes utilized in the conventional art where silicide is the fuse material. In addition, the size of the blown MOSFET304 can also be extremely small, since a small amount of current is required to blow the fuse. As will be apparent, the electrical fuse structure 400 may be fabricated in the same process layout as the main line FETs in IC fabrication.

Manufacturing method

Fig. 5 shows a flowchart 500 providing exemplary steps for fabricating an IC device having an electrical fuse, such as electrical fuse 400, in accordance with an embodiment of the present invention. Other structural and operational embodiments will be apparent to those skilled in the relevant arts based on the following discussion. The steps shown in fig. 5 need not occur in the order shown. The steps of fig. 5 are described in detail below in conjunction with the semiconductor layers shown in fig. 6A-6H.

In step 502, a gate deposition is performed, whereby various types of layers including a high-K dielectric layer, a metal layer, a polycrystalline layer, and a nitride layer are deposited on a silicon substrate (substrate) having an STI structure. For example, fig. 6a shows a silicon (Si) substrate 601 with STI structures 602. Over the substrate 601, a dummy layer (dummy) 603 is formed. Dummy layer 603 may include a high-K dielectric layer 604, a metal layer 605, an undoped polysilicon layer (herein "polysilicon") 606, and a nitride layer 607.

In step 504, a gate pattern is formed by using an etching process. In one embodiment, portions of all layers above a silicon substrate having STI structures are etched away. In one exemplary embodiment, the gate patterning is performed using an etching process, such as dry etching, wet etching, or plasma etching. Also, a mask process may be used to form the gate pattern. For example, fig. 6b shows a gate pattern formed by etching away a portion of dummy layer 603. An electrical fuse gate 608 is formed in the electrical fuse region 610, and a transistor gate (transistor) 609 is formed in the transistor region 611.

The electric fuse gate 608 and the transistor gate 609 hold the composition of the dummy layer 603. For example, electrical fuse gate 608 and transistor gate 609 may include high-K dielectric layer 604, metal layer 605, poly layer 606, and nitride layer 607. As illustrated, "a" and "b" are designated for identifying the remaining portions of the same layer in the electrical fuse region 610 and the transistor region 611, respectively. For example, eFUSE gate 608 has high-K dielectric layer portion 604a, while transistor gate 609 has high-K dielectric layer portion 604 b.

In step 506, spacers are formed around the respective gates, and source/drain regions are implanted into the silicon substrate. For example, fig. 6c shows a first space 612 and a second space 613 on the substrate 601. In one embodiment, the first spacers 612 are vertically connected to both sidewalls of the electrical fuse gate 608, and the second spacers 613 are vertically connected to both sidewalls of the transistor gate 609. For example, the first and second spacers 612, 613 may be formed of silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, titanium nitride, various low-K dielectrics, or any combination thereof. The first and second spacers 612, 613 may be formed by using one of the deposition processes mentioned above and by applying an anisotropic etching technique to form the desired spacer features. In addition, source and drain regions 614 are implanted into the substrate 601. In one embodiment, the source and drain regions 614 may define a region (area) of the substrate 601 where dopants may be implanted using the base of the second spacers 613.

For example, source and drain regions 614 may be implanted laterally within the substrate 601 alongside each sidewall of the transistor gate 609. In one embodiment, the source and drain regions 614 are constructed by doping the substrate 601 with an impurity such as arsenic, phosphorous, or boron. Doping with boron increases the positive charge to form the p-type region, while doping with arsenic or phosphorus increases the electrons to form the n-type region. Other dopants may also be used to achieve the preferred configuration. The source and drain regions 614 may be formed using processes such as ion implantation, diffusion, and photolithography.

In step 508, a silicide layer is formed on the surface of the substrate. For example, fig. 6d shows a silicide layer 615 formed on a portion of the surface of the substrate 601. In particular, a silicide layer 615 is formed on top of the source and drain regions 614 implanted within the substrate 601. For example, the silicide layer 615 may serve as an electrical contact for the source and drain regions 614.

In step 510, a nitride layer is formed over the silicide layer and the STI structures. For example, fig. 6e shows a nitride layer 616 formed over the STI structure 602 and the silicide layer 615. Nitride layer 616 may be formed by using various deposition techniques mentioned above. The nitride layer 616 insulates the electrical fuse region 610 and the transistor region 611. For example, a nitride layer 616 is deposited over the silicide layer 615 and the STI structure 602, thereby encasing the electrical fuse gate 608 and the transistor electrode 609. The top surfaces of nitride layer 616 and nitride layer 607 may be polished using CMP (polishedback) to expose poly layer 606 of electrical fuse gate 608 and transistor gate 609 for further processing as described below.

In step 512, a mask is formed on a surface of the polycrystalline layer in the electric fuse region. For example, FIG. 6f shows a mask 617 located over the poly 606a in the electrical fuse region 610. The mask 617 allows the poly to be removed by a process of etching the poly layer 606 in the electrical fuse region 610 and the transistor region 611. Specifically, the mask protects a portion of the poly 606 such that only the portion of the poly 606a (outside the mask 617) will be removed from the electrical fuse region 610, but the entire poly 606b in the transistor region 611 will be removed.

In step 514, the exposed poly is removed, and then the mask is removed, allowing fillable regions (fillaberegories) to form. For example, FIG. 6g shows that the poly layer (or "region") 606a still remains with a fillable region 618 formed around the poly layer 606a in the electrical fuse region 610. However, all of the poly layer 606b is removed from the transistor region 611. Further, the mask 617 is removed from the surface of the polycrystalline layer 606 in the electric fuse region 610.

In step 516, a second gate metal is filled on any exposed portions of the gate layer. For example, fig. 6h shows a gate metal layer 619 formed to fill the space of the fillable regions 618 on each side of the polycrystalline layer 606a in the electrical fuse region 610 and between the spacers 613 in the transistor region 611. Due to process 500, an electrical fuse for an OTP is formed in electrical fuse region 610 including high-K dielectric layer 604a, first metal layer 605a, and poly 606a, and a second metal layer having regions 619a, b. The first metal layer 605 and the poly layer 606a form a fuse neck region that is blown/unblown during programming, while the second metal regions 619a, b form the anode and cathode, respectively, of an electrical fuse for OTP. Also, the FET transistor is formed in the transistor region 611 adjacent to the electric fuse region 610. The gate of the FET includes a high-K dielectric layer 604b, a first metal layer 605b, and a second metal layer 619 c. The source and drain are formed from source and drain regions 614 having silicide contacts 615. Thus, an advantage of process 500 is that both the OTP and FET transistor devices are fabricated in a single semiconductor process run and on the same semiconductor wafer without any additional masking or processing steps.

According to an embodiment, process 500 may be used during the fabrication of integrated circuits that may include Static Random Access Memory (SRAM) and/or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as P-channel field effect transistors (PFET), N-channel field effect transistors (NFET), Metal Oxide Semiconductor Field Effect Transistors (MOSFET), complementary metal oxide semiconductor field effect transistors (CMOS), bipolar transistors, high voltage transistors, and other similar devices.

In another exemplary embodiment of the invention, the process 500 may be followed by a Back-end-of-line (BEOL) portion of the manufacturing state in which contacts, interconnect lines, vias and dielectric structures may be formed.

Other variants

Fig. 7a shows a top view of an electrical fuse 700 according to another exemplary embodiment of the present invention. It includes an anode 701 connected to a cathode 703 via a fuse neck 704. All of the fuse necks 704 include undoped poly.

Fig. 7b shows a cross-sectional view of the electrical fuse 700 before any programming occurs. It includes an STI structure 705 with a high-K dielectric layer 706 over the STI structure 705. A first gate metal layer 707 is disposed over high-K dielectric layer 706. Above first gate metal layer 707 is a second gate metal region 708, where an undoped poly structure 709 is located between second gate metal regions 708a and 708 b. The undoped poly structure 709 extends in the horizontal direction for the same length as the fuse neck 704 discussed above.

In one embodiment, eFUSE 700 is functionally similar to eFUSE 400 and blows in a similar manner.

In addition, in further illustrative embodiments, the fuse neck in an electrical fuse cannot be focused, where the amount of gate metal on either side of the poly structure may be unequal.

Conclusion

Embodiments of the present invention have been described above with the aid of functional building blocks illustrating the implementation of specific functions and relationships thereof. Boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specific functions and relationships thereof are appropriately performed.

The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such exemplary embodiments without undue experimentation, without departing from the general concept of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

The breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims (8)

1. A semiconductor device having an electric fuse structure for one-time programmable memory OTP, comprising:

a base substrate having a Shallow Trench Isolation (STI) structure;

a first metal layer formed on the STI structure, having a shape defining an anode, a cathode, and a fuse neck connected between the cathode and the anode;

an undoped poly region formed on the fuse neck of the first metal layer; and

a second metal layer having a first portion and a second portion formed on the first metal layer and on opposite sides of the poly region, the first portion of the second metal layer being formed on the anode and on a first portion of the fuse neck, and the second portion of the second metal layer being formed on the cathode and on a second portion of the fuse neck; wherein the polycrystalline region is formed on a third portion of the fuse neck between the first portion and the second portion of the fuse neck.

2. The semiconductor device of claim 1, wherein the poly region is formed only on the fuse neck of the first metal layer and separates the first portion and the second portion of the second metal layer.

3. The semiconductor device according to claim 1, wherein the polycrystalline region has a higher resistance than the first metal layer and the second metal layer.

4. The semiconductor device according to claim 1, wherein a thickness of the first metal layer is smaller than thicknesses of the second metal layer and the polycrystalline region.

5. The semiconductor device of claim 1, further comprising a high-K dielectric layer disposed between the STI structure and the first metal layer.

6. The semiconductor device of claim 1, wherein a width of the first metal layer in the fuse neck is less than a corresponding width of the first metal layer in the anode or the cathode.

7. A semiconductor device having an electric fuse structure for one-time programmable memory OTP, comprising:

(a) a base substrate having a Shallow Trench Isolation (STI) structure;

(b) an anode comprising

(bl) a first portion of the first metal layer;

(b2) a first portion of a second metal layer disposed on and in contact with the first portion of the first metal layer;

(c) a cathode comprising

(cl) a second portion of the first metal layer;

(c2) a second portion of the second metal layer disposed on and in contact with the second portion of the first metal layer;

(d) a fuse neck connecting the anode to the cathode, comprising

(dl) a third portion of the second metal layer disposed on and in contact with the third portion of the first metal layer;

(d2) a fourth portion of the second metal layer disposed on and in contact with the fourth portion of the first metal layer;

(d3) an undoped polycrystalline region disposed on and in contact with a fifth portion of the first metal layer, the polycrystalline region disposed between and separating the third and fourth portions of the second metal layer;

wherein the first, third, fifth, fourth, and second portions of the first metal layer are laterally disposed on the STI structure in a continuous manner, thereby providing a low resistance current path from the anode to the cathode prior to programming.

8. The semiconductor device according to claim 7, wherein a thickness of the first metal layer is smaller than a thickness of the second metal layer.