HK1179412B - Half-finfet semiconductor device and related method - Google Patents

Abstract

The present invention is directed to a half-finfet semiconductor device and related method. According to one embodiment, a half-FinFET semiconductor device comprises a gate structure formed over a semiconductor body. The semiconductor body includes a source region comprised of a plurality of fins extending beyond a first side of the gate structure and a continuous drain region adjacent a second side of the gate structure opposite the plurality of fins. The continuous drain region causes the half-FinFET semiconductor device to have a reduced ON-resistance. A method for fabricating a semiconductor device having a half-FinFET structure comprises designating source and drain regions in a semiconductor body, etching the source region to produce a plurality of source fins while masking the drain region during the etching to provide a continuous drain region, thereby resulting in the half-FinFET structure having a reduced ON-resistance.

Description

Half-fin FET semiconductor device and method of manufacturing the same

Technical Field

The present invention relates generally to the field of semiconductors. More particularly, the present invention relates to the field of semiconductor transistor fabrication.

Background

Complementary Metal Oxide Semiconductor (CMOS) technology has found widespread use in the semiconductor industry due to its many advantages. For example, the high density, low power consumption and relative noise immunity associated with CMOS devices make them suitable for implementation in Integrated Circuits (ICs), e.g., to provide control logic for modern electronic systems. However, standard CMOS transistors are typically low voltage devices. As a result, power applications such as power switching and voltage regulation, for example, are typically performed by high power conversion of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), such as Laterally Diffused Metal Oxide Semiconductor (LDMOS) devices, which are typically formed alongside CMOS logic devices on an IC wafer.

Not surprisingly, an important measure of the performance of an LDMOS device is its breakdown voltage, which should preferably be high. Another important measure of LDMOS performance is its on-resistance, or Rdson, which should preferably be low. As device dimensions continue to shrink, so-called short channel effects (such as channel leakage) produce undesirable power losses even when the transistor is nominally off. In an attempt to reduce or substantially eliminate off-state leakage in standard CMOS transistors, CMOS fabrication is increasingly moving towards fin field effect transistor (FinFET) architectures, in part because improved channel loss can be achieved using FinFET designs. However, implementing a FinFET structure makes it more challenging to implement an LDMOS with the desired low Rdson.

Strategies for reducing Rdson in conventional LDMOS devices may include controlling the proximity of the transistor gate and various drain-side elements. For example, Rdson of conventional LDMOS devices can be reduced by narrowing the width of a Shallow Trench Isolation (STI) structure formed between the gate and the highly doped drain region or by increasing the overlap of the gate over a drain extension well surrounding the STI structure. However, these conventional changes to the LDMOS device to advantageously reduce Rdson may simultaneously and undesirably result in a reduction in the breakdown voltage of the LDMOS device.

Accordingly, there is a need to overcome the disadvantages and shortcomings of the prior art by providing a solution that accommodates emerging CMOS process flows, is capable of providing a power MOSFET configured to simultaneously exhibit low Rdson and robust resistance to voltage breakdown (robustness).

Disclosure of Invention

The present application relates to a half-fin FET (half-fin FET) semiconductor device and related methods, substantially as shown in and/or described in connection with at least one of the figures.

(1) A half-fin FET semiconductor device, comprising:

a gate structure formed over the semiconductor body;

the semiconductor body includes a source region comprised of a plurality of fins extending beyond a first side of the gate structure;

the semiconductor body further includes a continuous drain region adjacent a second side of the gate structure opposite the plurality of fins;

wherein the continuous drain region causes the half-fin FET semiconductor device to have a reduced on-resistance.

(2) The half-fin FET semiconductor device of (1), further comprising a channel region underlying the gate structure and connected to the plurality of fins.

(3) The half-fin FET semiconductor device of (1), wherein the half-fin FET semiconductor device is an n-channel metal oxide semiconductor (NMOS) device.

(4) The half-fin FET semiconductor device of (1), wherein the half-fin FET semiconductor device is a p-channel metal oxide semiconductor (PMOS) device.

(5) The half-finfet semiconductor device of (1), wherein the half-finfet semiconductor device is a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device.

(6) The half-fin-FET semiconductor device of (1), wherein the half-fin-FET semiconductor device further comprises a spacer formed between the continuous drain region and the gate structure.

(7) The half-fin FET semiconductor device of (1), wherein the plurality of fins are silicon fins.

(8) The half-finfet semiconductor device of (1), wherein the gate structure comprises a gate and a gate dielectric interposed between the gate and the semiconductor body.

(9) The half-fin FET semiconductor device of (1), wherein the gate structure comprises a polysilicon gate and a gate dielectric selected from one of silicon oxide and silicon nitride interposed between the polysilicon gate and the semiconductor body.

(10) The half-fin FET semiconductor device of (1), wherein the gate structure comprises a metal gate and a high- κ gate dielectric disposed between the metal gate and the semiconductor body.

(11) A method of fabricating a semiconductor device having a half-fin FET structure, the method comprising:

designating a source region and a gate region within a semiconductor body;

etching the source region to produce a plurality of source fins while masking the drain region during the etching to provide a continuous drain region, thereby producing the half-finfet structure;

wherein the half-fin FET structure results in the semiconductor device having a reduced on-resistance.

(12) The method of (11), further comprising forming a spacer within a drain extension well of the semiconductor body between the continuous drain region and a gate structure of the semiconductor device.

(13) The method of (11), wherein the half-finfet semiconductor device having the half-finfet structure is an n-channel metal-oxide-semiconductor (NMOS) device.

(14) The method of (11), wherein the half-finfet semiconductor device having the half-finfet structure is a p-channel metal-oxide-semiconductor (PMOS) device.

(15) The method of (11), wherein the half-fin FET semiconductor device having the half-fin FET structure is a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device.

(16) The method of (11), further comprising forming a gate structure over the semiconductor body between the continuous drain region and the plurality of source fins, the gate structure over a channel region connected to the plurality of source fins.

(17) The method of (11), wherein the plurality of source fins are silicon fins.

(18) The method of (11), further comprising forming a gate structure over the semiconductor body between the continuous drain region and the source fin, the gate structure comprising a polysilicon gate and a silicon oxide gate dielectric disposed between the polysilicon gate and the semiconductor body.

(19) The method of (11), further comprising forming a gate structure over the semiconductor body between the continuous drain region and the source fin, the gate structure comprising a polysilicon gate and a silicon nitride gate dielectric disposed between the polysilicon gate and the semiconductor body.

(20) The method of (11), further comprising forming a gate structure over the semiconductor body between the continuous drain region and the source fin, the gate structure comprising a metal gate and a high- κ gate dielectric disposed between the metal gate and the semiconductor body.

Drawings

Fig. 1 illustrates a top view of a half-finfet semiconductor device implemented as a laterally diffused metal-oxide-semiconductor (LDMOS) device, according to an embodiment of the invention.

Fig. 2 illustrates a flow diagram of a method for fabricating a semiconductor device having a half-fin FET structure, according to one embodiment of the invention.

Fig. 3A provides a cross-sectional view of a half-fin FET semiconductor device at an early stage of fabrication along perspective line 3 AB-3 AB in fig. 1, in accordance with an embodiment of the present invention.

Fig. 3B provides a cross-sectional view of a half-fin FET semiconductor device at an early stage of fabrication along perspective line 3 AB-3 AB in fig. 1, in accordance with an embodiment of the present invention.

Fig. 3C provides a cross-sectional view of the half-finfet semiconductor device at an intermediate stage of fabrication, along perspective line 3C-3C of fig. 1, in accordance with an embodiment of the present invention.

Fig. 3D provides a cross-sectional view of the half-finfet semiconductor device at an intermediate stage of fabrication, along perspective line 3D-3D of fig. 1, in accordance with an embodiment of the present invention.

Fig. 3E provides a cross-sectional view of a half-finfet semiconductor device according to an embodiment of the invention, taken along perspective line 3E-3E of fig. 1.

Fig. 3F provides a cross-sectional view of a half-finfet semiconductor device corresponding to the device shown in fig. 3E, taken along perspective line 3F-3F of fig. 1, in accordance with an embodiment of the present invention.

Fig. 3G provides a cross-sectional view of a half-finfet semiconductor device corresponding to the device shown in fig. 3E, taken along perspective line 3G-3G in fig. 1, in accordance with an embodiment of the present invention.

Fig. 4 provides a cross-sectional view of a half finfet semiconductor device according to another embodiment of the present invention, taken along perspective line 4-4 of fig. 1.

Detailed Description

The invention relates to a half-fin FET semiconductor device and related methods. While the invention has been described with reference to specific embodiments, it will be apparent that the principles of the invention as defined by the claims appended hereto are not to be applied solely to the embodiments of the invention described herein. Moreover, in the description of the present invention, certain details have been omitted so as not to obscure the inventive aspects of the present invention. Those of ordinary skill in the art will appreciate the details omitted.

The drawings in the present application and their accompanying detailed description are directed to merely exemplary embodiments of the invention. To maintain brevity, other embodiments of the invention which use the principles of the present invention are not specifically described in the present application and are not specifically illustrated by the present drawings. It should be understood that, unless otherwise specified, identical or corresponding elements in the figures may be denoted by identical or corresponding reference numerals. Furthermore, the drawings and examples in this application are generally not drawn to scale and are not intended to correspond to actual relative dimensions.

Fig. 1 illustrates a top view of a half-finfet semiconductor device 100 implemented as a laterally diffused metal-oxide-semiconductor (LDMOS) device, which overcomes the disadvantages and drawbacks of the conventional techniques, according to one embodiment of the present invention. As shown in fig. 1, a half-finfet semiconductor device 100, represented by an n-channel metal-oxide-semiconductor (NMOS) device, may be formed in a semiconductor body 102 (which may comprise silicon, for example). The half-finfet semiconductor device 100 includes: a gate structure 142 including a gate 144 formed in the semiconductor body 102 over the channel region 150; a source region 122 including a plurality of source fins 122a, 122b, and 122c (hereinafter referred to simply as "source fins 122 a-122 c") separated by and bounded by an isolation region 124; and a continuous drain region 112. According to this embodiment, source fins 122 a-122 c extend beyond a side 147 of gate structure 142, while continuous drain region 112 is disposed adjacent a side 148 of gate structure 142 opposite source fins 122 a-122 c. As can be seen in fig. 1, continuous drain region 112 is separated from one side 148 of gate structure 142 by drain extension well 108, which is also shown as a continuous region (e.g., a region not comprised of fins) and extends under gate structure 142. In addition, fig. 1 shows a P-type body well region (ptypebodywell) 106 under the gate structure 142.

Fig. 1 also shows a planar topology 101 of a half-finfet semiconductor device 100, depicting a continuous drain region 112, a drain extension well 108, and a portion of a channel region 150; and fig. 1 also shows FinFET topology 103 of half-FinFET semiconductor device 100, depicting source region 122 and another portion of channel region 150 connected to source fins 122 a-122 c. It should be noted that the gate structure 142 is shown in clear outline, while the gate 144 is shown as a top surface of the gate structure 142 to represent the bi-planar/FinFET nature of the channel region 150. In other words, what is shown in fig. 1 is that the portion of the channel region 150 adjacent to the drain extension well 108 is implemented as a continuous (e.g., planar) channel region, while the portion of the channel region connected to the source fins 122 a-122 c is implemented using channel fins disposed below the gate structure 142, each channel fin including a P-type body well region 106 connected to a respective one of the source fins 122 a-122 c.

By employing FinFET topology 103 with source region 122 therein, channel region 150 disposed below gate structure 142 and connected to source fins 122 a-122 c, while using such a half-fin FET device topology of continuous drain region 112, drain extension well 108, and the portion of channel region 150 adjacent to drain extension well 108, as implemented using conventional planar transistor topology 101, embodiments of the present invention are configured to have a reduced on-resistance (Rdson) as compared to LDMOS devices implemented using more conventional FinFET structures. That is, embodiments of the present invention are configured to advantageously achieve the low Rdson desired for LDMOS devices and provide the high voltage breakdown resistance required for LDMOS devices while achieving the performance advantages associated with FinFET devices, such as reduced off-channel leakage.

Half-finfet semiconductor device 100 may be suitable for use in, for example, a Power Amplifier (PA) or a power management circuit implemented within a mobile communication device. Additionally, because the half-fin FET semiconductor device 100 may be fabricated using processing steps currently included in and/or anticipated by emerging Complementary Metal Oxide Semiconductor (CMOS) casting process flows, the half-fin FET semiconductor device 100 may advantageously be fabricated with standard CMOS devices and may be uniformly integrated with CMOS logic within, for example, an Integrated Circuit (IC) fabricated on a semiconductor wafer or wafer containing the semiconductor body 102. For example, the half-fin FET semiconductor device 100 may be fabricated by a FinFET fabrication process using a 22nm technology node and other technology nodes. Indeed, the principles of the present invention may be adjusted with additional advances in manufacturing technologies below the 22nm node.

It should be noted that the specific features illustrated in fig. 1 are provided as exemplary embodiments of the principles of the present invention and are shown together with the features to help clarify the concept thereof. With emphasis on clearly understanding the concepts, it should be understood that the structures and features shown in FIG. 1 and those shown in FIGS. 3A, 3B, 3C, 3D, 3E, 3F, 3G, and 4 may not be drawn to scale. Further, it should be noted that the semiconductor device type, such as represented by half finfet semiconductor device 100, specific details of its overall layout, and specific dimensions of its feature formation are by way of example only and should not be taken as limiting.

For example, although the embodiment shown in fig. 1 features the half-finfet semiconductor device 100 as an NMOS device, more generally, the half-finfet semiconductor device 100 in accordance with the principles of the invention may include an NMOS or PMOS device. Further, for example, in certain embodiments, the principles disclosed herein may be used to fabricate one or more substantially distinct device types, such as BiCMOS devices.

The half-finfet semiconductor device 100 is further described below in conjunction with fig. 2, 3A, 3B, 3C, 3D, 3E, 3F, and 3G, while an alternative embodiment of the half-finfet semiconductor device 100 is shown in fig. 4. Referring to fig. 2, fig. 2 shows a flow chart 200 embodying a method for fabricating a semiconductor device having a half-fin FET structure in accordance with an embodiment of the present invention. Certain details and features of flowchart 200 that are apparent to a person of ordinary skill in the art have been omitted. For example, a step may comprise one or more substeps or may involve specialized equipment or materials known in the art. Although steps 210 through 240 shown in flowchart 200 are sufficient to describe one embodiment of the present invention, other embodiments of the present invention may apply steps different from those shown in flowchart 200 and may include more or fewer steps.

Referring now to fig. 3A, the structure 300 in fig. 3A provides a cross-sectional view of the half-fin FET semiconductor device 100 at an early stage of fabrication along perspective line 3 AB-3 AB in fig. 1, in accordance with an embodiment of the present invention. In fig. 3A, structure 300 shows a semiconductor body 302 that includes a substrate 304, which may be, for example, a group iv semiconductor substrate (such as a P-type substrate containing silicon or germanium). The semiconductor body 302 containing the substrate 304 corresponds to the semiconductor body 102 in fig. 1. It should be noted that in fig. 3A, structure 300 shows a portion of semiconductor body 102 along line of sight 3 AB-3 AB in fig. 1 prior to performing step 210 in flowchart 200 shown in fig. 2.

Referring to FIGS. 3B, 3C, 3D, 3E, 3F, and 3G, structures 310, 320, 330, 340E, 340F, and 340G illustrate the results of performing steps 210, 220, 230, and 240 of flowchart 200 of FIG. 2 on semiconductor body 102 as viewed from perspective lines 3 AB-3 AB, 3C-3C, 3D-3D, 3E-3E, 3F-3F, and 3G-3G, respectively. For example, structure 310 shows structure 300 after performing step 210, structure 320 shows semiconductor body 102 along perspective line 3C-3C after performing step 220, and so on. It should be noted that fig. 3E, 3F, and 3G illustrate structures from three different vantage points along lines of visibility 3E-3E, 3F-3F, and 3G-3G in fig. 1 (e.g., corresponding to the structures of the half-fin FET semiconductor device 100 shown in fig. 1) after performing step 340, and these structures are labeled in respective fig. 3E, 3F, and 3G as structures 340E, 340F, and 340G, respectively.

Referring to step 210 in fig. 2, and additionally to structure 310 shown in fig. 3B, step 210 of flowchart 200 includes designating source and drain regions in semiconductor body 302. As shown in fig. 3B, step 210 corresponds to designating region 322 to form a source region of the half-finfet semiconductor device and designating region 312 to form a drain region of the half-finfet semiconductor device.

Continuing to step 220 in fig. 2 and referring to structure 320 in fig. 3C, step 220 of flowchart 200 includes etching the source regions to form source fins 322a, 322b, and 322C (hereinafter "source fins 322 a-322C"). Fig. 3C presents a cross-sectional view of a half-finfet structure 320 corresponding to perspective line 3C-3C in fig. 1 prior to forming isolation region 124 and implanting source region 122. Thus, the source fins 322 a-322 c may be considered to correspond to the source fins 122 a-122 c, respectively, at an intermediate stage of fabrication. The source fins 322 a-322 c may be formed in the semiconductor body 302 by using, for example, a plasma etch or other dry etch process as is known in the art, and may comprise silicon fins.

Continuing with step 230 in fig. 2 and referring to structure 330 in fig. 3D, step 230 in flowchart 200 includes masking the drain region during etching of source fins 322 a-322C shown in fig. 3C to provide a continuous drain region. Fig. 3D presents a cross-sectional view of the half-finfet structure 330 corresponding to perspective line 3D-3D shown in fig. 1, prior to implantation of the P-type body well 106, the N-type drain extension well 108, and the continuous drain region 112. As shown in fig. 3D, step 230 may be performed by forming a mask 332 over the designated drain region 312 within the substrate 304. Mask 332 may take the form of, for example, a photoresist layer comprising a polymer matrix containing, for example, styrene, acrylate, or methacrylate monomers. Mask 332 may be formed by any suitable deposition process known in the art. Referring again to fig. 1, the presence of mask 332 over drain region 312 during the performance of step 220 allows drain region 312 to be provided as a continuous drain region 112 despite the etching process that forms source fins 122 a-122 c, thereby forming a half-finfet structure for half-finfet semiconductor device 100.

It should be emphasized that, although steps 220 and 230 are described herein as distinct steps to aid in understanding the concept, in practice, the masking process applied in step 230 is contemplated to be the same as the masking process used to achieve the formation of the source fins 322 a-322C shown in fig. 3C. Accordingly, the inventors contemplate that steps 220 and 230 of flowchart 200 may be performed substantially simultaneously.

Continuing now to step 240 in fig. 2 and with reference to structure 340E shown in fig. 3E, step 240 in flowchart 200 includes implanting body well 306 and drain extension well 308, forming gate structure 342 including gate 344 and gate dielectric 346 between continuous drain region 312 and the source region containing source fin 322b, and implanting continuous drain region 312 and the source region including source fin 322 b. Fig. 3E presents a cross-sectional view of half finfet structure 340E, corresponding to perspective lines 3E-3E shown in fig. 1. In fig. 3E, structure 340E shows semiconductor body 302 including substrate 304, P-type body well 306 formed in or over substrate 304, and N-type drain extension well 308 formed in or over substrate 304. In some embodiments, P-type body well 306 and N-type drain extension well 308 may be formed within an epitaxial semiconductor layer, such as a silicon or germanium epitaxial layer, formed on substrate 304. Alternatively, in some embodiments, the P-type body well 306 and the N-type drain extension well 308 may be formed within the substrate 304. Fig. 3E also shows a gate structure 342 containing a gate 344 and a gate dielectric 346 disposed between the gate 344 and a channel region 350. The P-type body well 306, the N-type drain extension well 308, the channel region 350, the gate structure 342, and the gate 344 correspond to the P-type body well 106, the N-type drain extension well 108, the channel region 150, the gate structure 142, and the gate 144, respectively, of fig. 1.

As described above, it will be understood from the description shown in fig. 1 and 3E that the channel region 350 may include a plurality of fin regions formed in the P-type body well 306 connected to respective source fins 122 a-122 c and extending through the gate structure 142/342 or extending under the gate structure 142/342 to connect the drain extension well 308, and as shown in fig. 3E, the channel region may also extend under the gate structure 342. In addition, the gate structure 142 shown in fig. 1 may be implemented as a multi-gate structure having multiple planar interfaces with the channel fins connected to the source fins 122 a-122 c, such as a so-called "tri-gate".

Such an embodiment is more clearly shown in FIG. 3F, which shows a cross-sectional view of a structure 340F along the perspective line 3F-3F shown in FIG. 1, according to one embodiment of the present invention. As can be appreciated with reference to fig. 3F in conjunction with fig. 1, structure 340F corresponds to a portion of channel region 150 that is located below gate structure 142 and is implemented using FinFET topology 103. Fig. 3F illustrates a plurality of channel fins (hereinafter "channel fins 306a-306 c") including P-type body well fins 306a, 306b, and 306c separated by and bounded by isolation regions 324 corresponding to the isolation regions 124 shown in fig. 1. In addition, as shown in fig. 3F, a gate structure 342 containing a gate 344 and a gate dielectric 346 may be conformally deposited over the channel fins 306a-306c to form the multi-gate type topology described above.

In contrast, fig. 3G depicts a cross-sectional view of structure 340G along perspective line 3G-3G shown in fig. 1 and corresponding to a portion of channel region 150 located below gate structure 142 and implemented using planar topology 101. Fig. 3G illustrates a continuous N-type drain extension well 308 formed in or above the substrate 304 and corresponding to a portion of the channel region 150 adjacent to the drain extension well 108 shown in fig. 1. As further shown in fig. 3G, the structure 340G includes a laterally planar gate structure 342 including a gate 344 and a gate dielectric 346 formed over the drain extension well 308.

For example, gate 344 may comprise polysilicon and may be formed of, for example, silicon oxide (SiO)_2）Or silicon nitride (Si)₃N₄) Over the appropriate gate dielectric 346. Alternatively, the gate 344 may comprise a gate metal and the gate dielectric 346 may be fabricated using suitable known CMOS fabrication stepsIs realized as hafnium oxide (HfO) for example₂) Zirconium oxide (ZrO)₂) And the like. For example, in embodiments where structure 340 corresponds to an n-channel device, gate 344 may be formed of any gate metal suitable for an NMOS device, such as tantalum (Ta), tantalum nitride (TaN), or titanium nitride (TiN). Furthermore, in embodiments employing structure 340 so as to correspond to a p-channel device, gate 344 may be formed from any gate metal suitable for a PMOS device, such as molybdenum (Mo), ruthenium (Ru), or tantalum nitride carbide (TaCN).

Referring to fig. 4, fig. 4 illustrates a cross-sectional view of a half-finfet semiconductor device 400 in accordance with another embodiment of the invention from a vantage point corresponding to perspective line 4-4 shown in fig. 1. In fig. 4, the half-finfet semiconductor device 400 includes a semiconductor body 402 including a substrate 404, a P-type well region 406, an N-type drain extension well 408, a source fin 422b, a continuous drain region 412, and a channel region 450, corresponding to the semiconductor body 302 including the substrate 304, the P-type well region 306, the N-type drain extension well 308, the source fin 322b, the continuous drain region 312, and the channel region 350 shown in fig. 3E. In addition, fig. 4 shows a gate structure 442 formed over the semiconductor body 402 and disposed over the channel region 450. The gate structure 442 includes a gate 444 and a gate dielectric 446 and corresponds to the gate structure 342 of figure 3E including the gate 344 and the gate dielectric 346.

Fig. 4 also shows a spacer 414 that is not similarly described in the previous figures. Spacers 414 are formed between continuous drain region 412 and gate structure 442. The spacers 414 may comprise Shallow Trench Isolation (STI) structures, such as made of SiO₂The STI structure is formed and may be formed according to known CMOS fabrication process steps. According to the embodiment shown in fig. 4, spacers 414 may be used to provide additional voltage breakdown resistance to half-finfet structure 400. Furthermore, as with the half-fin FET semiconductor device 100 shown in fig. 1, the embodiment shown in fig. 4 is configured to have a reduced on-resistance (Rdson) as compared to an LDMOS device implemented using a more conventional FinFET structure. That is, the embodiment shown in FIG. 4 can achieve the desired low Rdson for LDMOS devices, and through spacersEx-vivo 414 provides improved high voltage breakdown resistance while achieving the performance advantages of the related FinFET design.

Thus, by implementing a semiconductor device using a half-fin FET topology, embodiments of the present invention can advantageously achieve performance improvements for related FinFET designs, such as reduced off-state leakage. In addition, embodiments of the present invention provide robust voltage resistance and reduced Rdson by maintaining a planar crystal topology on the drain side of a half-finfet semiconductor device implemented as an LDMOS device. Furthermore, by coordinating the fabrication of half-finfet semiconductor devices with existing CMOS process flows, the present application discloses devices that are not only compatible with CMOS fabrication processes for 22nm technology nodes and other technology nodes, but are also devices that can be fabricated without substantially increasing the number of process steps beyond those required to fabricate conventional CMOS transistors. Additionally, embodiments of the half-fin FET devices disclosed herein are contemplated to advantageously expand with advances in manufacturing processes below the 22nm technology node.

From the above description of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, although the present invention has been described with reference to certain specific embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. The described embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. It is to be understood that the invention is not limited to the particular embodiments disclosed herein, but is capable of various rearrangements, modifications, and substitutions without departing from the scope of the invention.

Claims (9)

1. A half-fin FET semiconductor device, comprising:

a gate structure formed over the semiconductor body;

the semiconductor body includes a source region comprised of a plurality of fins extending beyond a first side of the gate structure;

the semiconductor body further comprises a continuous drain region adjacent a second side of the gate structure, wherein the second side is opposite the plurality of fins;

wherein the continuous drain region causes the half-fin FET semiconductor device to have a reduced on-resistance,

wherein the continuous drain region is separated from the second side of the gate structure by a drain extension well.

2. The half-fin FET semiconductor device of claim 1, further comprising a channel region underlying the gate structure and connected to the plurality of fins, wherein the plurality of fins are silicon fins.

3. The half-fin FET semiconductor device of claim 1, wherein the half-fin FET semiconductor device is one of an n-channel metal-oxide-semiconductor (NMOS) device, a p-channel metal-oxide-semiconductor (PMOS) device, a laterally diffused metal-oxide-semiconductor (LDMOS) device.

4. The half fin-FET semiconductor device of claim 1, wherein the gate structure includes a gate and a gate dielectric disposed between the gate and the semiconductor body, wherein the gate is a polysilicon gate and the gate dielectric is a gate dielectric selected from one of silicon oxide and silicon nitride disposed between the polysilicon gate and the semiconductor body, or the gate is a metal gate and the gate dielectric is a high- κ gate dielectric disposed between the metal gate and the semiconductor body.

5. A method of fabricating a semiconductor device having a half-fin FET structure, the method comprising:

designating a source region and a gate region within a semiconductor body;

etching the source region to produce a plurality of source fins while masking a drain region during the etching to provide a continuous drain region, thereby producing the half-finfet structure;

wherein the half-fin FET structure results in the semiconductor device having a reduced on-resistance.

6. The method of claim 5, further comprising forming a spacer within a drain extension well of the semiconductor body between the continuous drain region and a gate structure of the semiconductor device.

7. The method of claim 5, wherein the half-fin FET semiconductor device having the half-fin FET structure is one of an n-channel metal oxide semiconductor (NMOS) device, a p-channel metal oxide semiconductor (PMOS) device, a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device.

8. The method of claim 5, further comprising forming a gate structure over the semiconductor body between the continuous drain region and the plurality of source fins, the gate structure over a channel region connected to the plurality of source fins, wherein the plurality of source fins are silicon fins.

9. The method of claim 5, further comprising forming a gate structure over the semiconductor body between the continuous drain region and the source fin, the gate structure comprising a gate and a gate dielectric disposed between the gate and the semiconductor body, wherein the gate is a polysilicon gate and the gate dielectric is a gate dielectric selected from one of silicon oxide and silicon nitride disposed between the polysilicon gate and the semiconductor body, or the gate is a metal gate and the gate dielectric is a high- κ gate dielectric disposed between the metal gate and the semiconductor body.