HK1179355B - Method of forming a flash controller for a camera and structure therefor - Google Patents

Description

Method of forming flash controller for camera and structure thereof

The present application is a divisional application of an invention patent application having an application date of 26/3/2008, an application number of 200880123822.1, entitled "method of forming flash controller for camera and structure thereof".

Technical Field

The present invention relates generally to electronics, and more particularly to methods and structures for forming semiconductor devices.

Background

In the past, various circuits and methods have been used to control the formation of a photo flash that is used to illuminate an object while taking a picture with a digital camera. The most common architecture used to control a photo flash utilizes a microcontroller to create the timing pulses required to turn on the flash assembly at the desired intensity. The microcontroller typically forms a digital pulse stream that forms the required timing. However, the microcontroller is also used to provide other functions, which may delay the formation of the flash sequence or may interfere with the synchronization between the flash sequence and the shutter of the camera.

Therefore, it is desirable to have a flash controller for a camera that more accurately controls the flash sequence.

Disclosure of Invention

According to an aspect of the present invention, there is provided a flash controller for a camera, comprising: an interface circuit operably coupled to receive a plurality of control words from outside the flash controller; a first flash control channel configured to receive and store at least a first control word of the plurality of control words and responsively control a first current through a first light source to a first value, wherein the first light source is external to the flash controller; and a second flash control channel configured to receive and store at least a second control word of the plurality of control words and responsively control a second current through the first light source to a second value, wherein the first current and the second current are two separate currents.

According to another aspect of the present invention there is provided a method of forming a flash controller for a camera, comprising the steps of: configuring an interface circuit of the flash controller to receive a plurality of control words from outside the flash controller; and configuring a plurality of flash control channels to receive and store the plurality of control words and responsively form a control signal that controls a first current through a first light source external to the flash controller and that controls a second current through the first light source, wherein the first current and the second current are two separate currents.

Drawings

Fig. 1 schematically illustrates an embodiment of a portion of an exemplary form of a flash system including an exemplary embodiment of a flash controller according to the present invention;

FIG. 2 schematically illustrates an embodiment of a portion of a current control channel of the flash controller of FIG. 1, in accordance with the present invention;

FIG. 3 schematically illustrates an embodiment of a portion of another current control channel of the flash controller of FIG. 1, in accordance with the present invention;

FIG. 4 schematically illustrates an embodiment of a portion of the converter circuit of the flash controller of FIG. 1, in accordance with the present invention; and

fig. 5 schematically shows an enlarged plan view of a semiconductor device including the flash controller of fig. 1 according to the present invention.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Moreover, descriptions and details of well-known steps and components are omitted for simplicity of the description. As used herein, a current carrying electrode is a component that carries current through the device, such as the source or drain of an MOS transistor, or the collector or emitter of a bipolar transistor, or the cathode or anode of a diode; and the control electrode denotes a component of the device that controls the current through the device, such as the gate of a MOS transistor or the base of a bipolar transistor. Although these devices are explained herein as certain N-channel or P-channel devices, or N-type or P-type doped regions, one of ordinary skill in the art will recognize that complementary devices are also possible in accordance with the present invention. Those skilled in the art will recognize that the word "during, at the same time, when," relating to circuit operation as used herein is not an exact term to indicate that an action will occur as soon as there is a start-up action, but rather that there may be some slight but reasonable delay, such as a propagation delay, between reactions provoked by the initial action. Use of the word "about" or "substantially" means that the value of a component has a parameter that is expected to be very close to a specified value or location. However, as is well known in the art, there is always a slight variation in the blocking value or position exactly as specified. It is well established in the art that variations up to at least 10% are reasonable variations from the ideal target exactly as described.

Detailed Description

Fig. 1 schematically illustrates an embodiment of a portion of an exemplary form of a flash system 10, the flash system 10 being used to illuminate an object being photographed by a camera. System 10 receives power from a power source, such as a battery 11, connected between an input terminal 12 and a return terminal 13 of system 10. A plurality of light sources, such as a first LED16 and a second LED27, are used for various functions, including illuminating an object to be photographed. In some embodiments, the system 10 may include only one light source or may include more light sources. The capacitor 14 serves as a power source to help provide power to the LEDs 16 and 27. Fig. 1 also schematically illustrates a portion of an exemplary embodiment of a flash controller 45 for controlling the operation of the light source.

Because the flash sequence of a digital camera may require one or more light sources for various different functions, the controller 45 is configured to operate the plurality of light sources at a plurality of different current values and current durations in order to form the appropriate flash sequence. The light source may also be operated for other functions. For example, the light source may be operated to provide light for a longer duration to illuminate the object in a manner similar to a flashlight. A flash sequence for taking a picture may include activating (enable) a first light source, such as LED16, at a first value to sense and measure the distance between the camera and the object to be illuminated. The flash sequence may then include flashing the LED16 at a second current value as part of the red-eye reduction operation, and thereafter, the flash sequence may include operating a second light source, such as LED27, at a very high intensity in order to illuminate the object and capture the photographic image. The controller 45 is configured with a plurality of flash control channels that facilitate the formation of multiple sequences and different current values required for multiple light intensities.

Controller 45 receives operating power between a voltage input 46 and a voltage return 47 that are typically connected to terminals 12 and 13, respectively. The controller 45 provides voltage and current to the charge capacitor 14 through the voltage output 59. The current drive output 61 and the current drive output 62 of the controller 45 are connected to control the respective currents 17 and 29 through the LEDs 16 and 27, respectively. Current control output 67 is connected to control current 19 through LED16, and current control output 70 is connected to control current 31 through LED 27. Sense input 68 of controller 45 is used to sense the value of current 19 and sense input 71 of controller 45 is used to sense the value of current 31. Overload inputs 65 and 69 are applied to sense an overload of respective currents 19 and 31. Controller 45 also includes inputs 49 and 50 that facilitate connecting controller 45 to receive command words from a source external to controller 45. The command word typically has parameters that controller 45 uses to control the operation, values and sequence of currents 17, 19, 29 and 31. Enable input 52 may be set active to initiate a flash sequence of controller 45 separately from a control sequence requested by a control word received via inputs 49 and 50.

Controller 45 may also include a power converter 80, power converter 80 receiving power between input 46 and return 47 and storing energy in capacitor 14 to power LEDs 16 and 27. A bus interface circuit or bus interface 75 is coupled to receive control words from outside the controller 45 on inputs 49 and 50. For example, inputs 49 and 50 may represent a serial communication protocol such as I²C. SPI, RS-232, or other types of serial or parallel protocol compatible interfaces known to those skilled in the art. Controller 45 also includes a plurality of flash control channels including flash control channel 82, flash control channel 90, and flash control channel 103, each of which receives a control word and controls the value and timing of currents 17, 19, 29, and 31. The clock, control and logic block 78 is configured to receive command words from the bus interface 75 and form control signals and control words or data words for activating components within each flash control channel 82, 90 and 103. Block 78 generally includes a clock circuit that generates a clock signal that is provided to the components of channels 82, 90, and 103 to synchronize their operation and to act as a time generator. The block 78 outputs data on the bus 79 that is stored within the channels 82, 90 and 103 as control words that control the operation of the channels 82, 90 and 103. Bus 79 is preferably bi-directional and, in some embodiments, may be used to read data from channels 82, 90, and 103. Bus 79 is a general toolThere is a parallel bus of N number of data bits and preferably 8 data bits.

The flash control channel 82 includes a pulse width control circuit 83, a current value circuit 84, a current setting or I setting circuit 85, and outputs connected to the respective outputs 61 and 62. Flash control channel 90 includes a delay circuit 91, a pulse width control circuit 92, a current value circuit 94, a current setting or I-setting circuit 95, an output connected to output 67, and an input connected to input 68. Flash control channel 103 includes a delay circuit 104, a pulse width control circuit 106, a current value circuit 110, an output connected to output 70, and an input connected to input 71. Channels 90 and 103 preferably include respective current overload detection circuits 99 and 109, with current overload detection circuits 99 and 109 having inputs connected to respective inputs 65 and 69.

In a typical flash sequence, the bus interface 75 receives a serial data stream from a source external to the controller 45, such as a microprocessor. The serial data stream includes command words with various commands to be executed by the controller 45. The command word may include data to be stored in different registers as a control word to control the operation of the controller 45, as well as the address of the register into which the data is to be stored. The command word may also include a command instructing the block 78 to initiate a flash sequence, or may include a command to turn on the LEDs 16 and 27 as a light source, such as a flash. Bus interface 75 typically transfers the serial data stream to block 78, and block 78 decodes the command words and addresses and provides control signals and data to the components of lanes 82, 90 and 103. For example, the block 78 may receive the command word and decode the target address within the control word to form a control signal for activating one of the components in the flash control channels 82, 90 and 103 and store the data of the command word in the buffer of that corresponding component or components.

Pulse width control circuit 83 includes a storage element such as a buffer in which the first control word from bus 79 may be stored. The control word in circuit 83 represents the width or duration of current 17. Current value circuit 84 includes another storage element such as a buffer in which a second control word representing the value of current 17 is stored. Current setting circuit 85 forms the desired value for current 17 in response to the value stored in the buffer of circuit 84. Delay circuit 91 includes a storage element that stores a third control word that represents a time delay between when block 78 decodes the control word that instructs controller 45 to initiate the flash sequence and when channel 90 actually begins to form current 19. Pulse width control circuit 92 includes a storage element, such as a buffer, that stores a fourth control word for controlling the duration of current 19, while current value circuit 93 includes a storage element, such as a buffer, that stores a fifth control word that represents the value of current 19. Current setting circuit 95 forms the desired value of current 19 in response to the value stored in the buffer of circuit 93. In a similar manner, delay circuit 104 includes a storage element, such as a buffer, that stores a sixth control word that represents another time delay between the time block 78 decodes the control word that instructs controller 45 to initiate the flash sequence and the time at which channel 103 actually begins to form current 31. Pulse width control circuit 106 includes a storage element, such as a buffer, that stores a seventh control word that is used to determine the duration of current 31. Current value circuit 108 includes a storage element, such as a buffer, that stores an eighth control word that represents the value of current 31. Current setting circuit 110 forms the desired value for current 31 in response to the value stored in the buffer of circuit 108. In order to load data from bus 79 into the appropriate circuitry as a control word, block 78 forms a load signal for enabling the appropriate buffer to load or store data from bus 79. Block 78 forms the load signal by deciphering the address received in the command word which block 78 receives from the interface 75. The load signal L1A is a load signal of the circuit 83, the load signal L2A is a load signal of the circuit 91, the load signal L2B is a load signal of the circuit 92, the load signal L2C is a load signal of the circuit 93, the load signal L3A is a load signal of the circuit 104, the load signal L3B is a load signal of the circuit 106, and the load signal L3C is a load signal of the circuit 108.

Those skilled in the art will recognize that the control words may be stored serially in the components of each channel 82, 90 and 103, for example, three consecutive control words may be stored, or bus 79 may be wide enough to form one control word, each control word having three portions, a different portion being stored in each component of the respective channel, or bus 79 may be a serial bus that stores the control words serially in the storage elements of each component of the respective channel.

After block 78 stores all of the control words in channels 82, 90, and 103, block 78 may receive a command word instructing controller 45 to initiate a flash sequence. Alternatively, the start input 52 may be set to active to initiate a flash sequence. The clock, control and logic block 78 receives the enable command word (or active enable signal) and sends a clock signal (CK) to the components of the channels 82, 90 and 103 in addition to the enable signal, which enables the operation of each of the components within the channels 82, 90 and 103. For example, enable signal E1 may be used to enable channel 82 to form currents 17 and 29 in response to values stored in circuits 83 and 84. Enable signal E2 may be used to enable respective circuits 91, 92, and 93 to form current 19 in response to the value of a control word stored in the respective circuit. Enable signal E3 may be used to enable the respective circuits 104, 106, and 108 to form current 31 in response to the value of the control word stored in the respective circuits.

Fig. 2 schematically illustrates a portion of an exemplary embodiment of a current control circuit 85. This description refers to fig. 1 and 2. Control circuit 85 includes a bus input 87 connected to bus 79 and a control input 86 connected to receive an enable output signal from pulse width control circuit 83. Buffers 121-128 may be used to act as buffers for circuit 85 from bus 79. Circuit 85 also includes a current control block 130 that forms current 17 and a current control block 150 that forms current 29. Blocks 130 and 150 are shown in a general manner by arrows. Enable latch 161 is used to enable and disable block 150. The current control block 130 includes an enable switch such as transistor 141, a current generator circuit including transistor 131 and current source 140, a current mirror including current mirror transistor 132 and 138 connected to transistor 130 in a current mirror configuration, and a current switch such as transistor 142 and 147. Similarly, current control block 150 includes a start switch such as transistor 162, a current generator circuit including transistor 151 and current source 160, a current mirror including current mirror transistor 152 and 158 connected to transistor 151 in a current mirror configuration, and a current switch such as transistor 163 and 169. Current source 140 is essentially a current source that is enabled to form current I1 when transistor 141 is enabled, and current source 160 is essentially a current source that is enabled to form current I2 when transistor 162 is enabled.

For the case when controller 45 receives a command word on inputs 49 and 50 to begin forming either of currents 17 or 29, block 78 forms a clock signal (CK) and asserts enable signal E1 to enable operation of channel 82. Circuit 83 asserts an enable output signal received by circuit 85 on an enable input 86. The control word stored in circuit 84 is received by circuit 85 on input 87. Enabling input 86 enables transistor 141 and thus source 140 to form current I1 flowing through transistors 141 and 131. The state of the inputs received by buffers 121-127 determine which current switch transistors 142-147 are activated. The enabled transistors pass current through respective ones of transistors 132-138 to form current 17. The value of current 17 is determined by which transistors 142-147 are enabled and is thus formed in response to the value of the control word stored in circuit 84. A portion of the data of the control word is used to determine the number of transistors 142-147 used to conduct current in order to form the appropriate value of current 17. The more transistors 142-147 that are activated, the greater the value of current 17. The size ratio between transistor 130 and transistor 132-138 may be selected to provide various values of current 17. For example, the ratio may be constant for all of the transistors 132-138, or each ratio may be different. In the preferred embodiment, the ratio is binary weighted such that transistor 138 is the same size as transistor 131, transistor 137 is twice that size, transistor 136 is four times that size, transistor 135 is eight times that size, and so on. In this preferred embodiment, the source 140 and the transistor dimensions are selected to form a current 17 having a value ranging from about 1 milliamp (1ma) to about 200 milliamps (200 ma). As can be seen, the output signal formed by circuit 85 is an analog signal.

For the exemplary embodiment shown in FIG. 2, the state of one bit received from bus 79 is used to initiate the operation of block 150. When the bit goes high, latch 161 is set to enable transistor 162. When the enable signal from circuit 83 is inactive, latch 161 is reset to disable transistor 162. Those skilled in the art will recognize that other logic schemes may be used to control the state of block 150. For example, another control block, such as another circuit 83, may be used to store another control word for the operation of the control block 150. Similar to block 130, the state of the inputs received by buffers 121-127 determine which current switch transistors 163-169 are activated. The enabled transistor causes current to flow through a corresponding current mirror transistor of transistors 152 and 158, thereby forming current 29. The value of current 29 is determined by which transistors 163 and 169 are activated and is thus formed in response to the value of the control word stored in circuit 84. The data of this control word is used to determine the number of transistors 163 and 169 used to conduct current in order to form the appropriate value of current 29. The more transistors 163-169 that are activated, the greater the value of current 29. Similar to the case of block 130, the size ratio between transistors 151 and 152 and 158 may be selected to provide a variety of different currents.

After the expiration of the time specified by the control word stored in circuit 83, circuit 83 deasserts the control signal on input 86 of circuit 85 and circuit 85 terminates currents 17 and 29. Because block 150 has a separate enable input, block 150 and corresponding current 29 selectively operate independently of the operation of block 130 and current 17.

Fig. 3 schematically illustrates an exemplary embodiment of a portion of current control circuit 95. Current control circuit 95 includes an enable input 96 connected to receive an enable output from circuit 106 and a data input 97 connected to receive a control word stored in circuit 93. Input 97 typically has a number of lines (Z) sufficient to transfer data for the control word stored in circuit 93. The circuit 95 further includes a start and decode block 184, a voltage reference generator including a voltage reference or reference 176 and a voltage divider formed by resistors 177 and 182, a switch formed as a transistor 185 and 187, and an amplifier 190. Amplifier 190 and the voltage reference generator are used to control the value of current 19 in response to the value of the control word stored in circuit 93.

Referring to fig. 1 and 3, after the command word instructing the controller 45 to initiate a flash sequence is received at block 78, block 78 sends a clock signal (CK) to the components of the channel 90 in addition to the E2 enable signal, the E2 enable signal enabling the operation of each component within the channel 90. Delay circuit 91 receives the CK signal and generates a time delay specified by the value of the control word stored in circuit 91. After the delay formed by circuit 91 has expired, circuit 91 generates an output signal that is used to activate circuit 92 to generate a time that is representative of the width or duration of current 19. Those skilled in the art will recognize that if the control word stored in circuit 91 is zero, there is no delay resulting from the command word and circuit 91 asserts the output signal substantially immediately. Upon being enabled, circuit 92 generates an enable output signal that is received by circuit 95 on input 96. Asserting this enable signal causes circuit 95 to begin forming current 31 at a value specified by the control word stored in circuit 93. When circuit 95 is enabled from circuit 92, the control word stored in circuit 93 is used to selectively enable circuit 95 to form current 19 at a specified value. Block 184 receives data from circuit 93 and selectively enables one of transistors 185 and 187 as dictated by the value of the control word. The enable transistor 185 couples the first value to an input node 189, the input node 189 being connected to the non-inverting input of the amplifier 190. Enabling transistor 186 instead of transistor 185 applies a different voltage to amplifier 190, and so on. Although only three transistors are shown in fig. 3, circuit 95 may include any number of transistors that may be selectively activated in response to the value of a control word stored in circuit 93. Amplifier 190 receives the voltage from node 189 and the CS feedback signal from input 68 and forms an output voltage on output 67 that is used to enable transistor 22 to conduct current 19 at a certain value. As can be seen, the output signal formed by circuit 95 is an analog signal. The value of current 19 forms the CS signal on input 68 that is received on the inverting input of amplifier 190, forcing the value of current 19 to a value that maintains the voltage on the non-inverting input of amplifier 190 substantially equal to the voltage on node 189.

The current overload detection circuit 99 is used to detect an open circuit or a short circuit at the cathode of the LED 16. The circuit 99 may monitor the drain to source voltage of the transistor 22 to detect a short circuit or monitor the voltage across the LED16 to detect an open circuit. Circuits for detecting open or short circuits are well known to those skilled in the art. Note that circuit 109 is similar to circuit 99 except that circuit 109 performs the same function for LED 27.

After the time specified in the control word of circuit 92 expires, circuit 92 deasserts the enable signal to circuit 95, which then terminates current 19. Those skilled in the art will appreciate that the output signal from circuit 91 and the enable signal from circuit 92 may be provided to a logic circuit, such as an AND gate, and the output of the logic circuit may be used to enable circuit 95. For such an embodiment, the output signal from circuit 91 is not used to enable circuit 92, enabling circuit 92 to begin operation upon receiving the E2 enable signal from block 78.

After the block 78 receives the command word instructing the controller 45 to initiate the flash sequence, the block 78 sends a clock signal (CK) to the components of the channel 103 in addition to the E3 enable signal, the E3 enable signal enabling the operation of each component within the channel 103. Channel 103 is formed similarly to channel 90. Delay circuit 104 receives the CK signal and generates a time delay specified by the value of the control word stored in circuit 104. Generally, the time specified in circuit 104 is no less than the time required for channel 90 to form and then terminate current 19, so that current 31 forms after current 19 is terminated. However, in some operations it may be preferable for currents 19 and 31 to form or overlap by just a certain amount simultaneously. Controller 45 is configured to facilitate such operation because the operations of channels 90 and 103 are independent of each other. Thus, it can be seen that the delay time formed by circuit 104 causes channel 103 to begin forming current 31 at a first time relative to current 19, and that this first time is formed in response to the difference in the values of the control words stored in circuits 91 and 104.

After the delay formed by circuit 104 expires, circuit 104 generates an output signal that is used to activate circuit 106 to generate a time that is representative of the width or duration of current 31. Upon being enabled, the circuit 106 generates an enable output signal that is received by the circuit 110. Asserting the enable signal causes circuit 110 to begin forming current 31 at a value specified by a control word stored in circuit 108. Circuit 110 is generally formed similarly to circuit 95, and thus start-up circuit 110 selectively forms current 31 at the prescribed value stored in circuit 108. The values of external resistors 24 and 36 may be different values so that currents 19 and 32 may be formed with different values.

After the time specified by the control word stored in circuit 106 expires, the enable signal to circuit 110 is deasserted, causing circuit 110 to terminate current 31.

Fig. 4 schematically illustrates a portion of an exemplary embodiment of a transducer 80. The converter 80 includes a charge pump circuit 81 for charging the capacitor 14 and a precharge circuit 119. Charge pump circuit 81 may be any of a variety of well known charge pump circuits for receiving a voltage, such as a voltage between input 46 and return 47, and charging an output capacitor, such as capacitor 14, to a voltage greater than the voltage received between input 46 and return 47. The charge pump circuit 81 may or may not include a circuit that adjusts the value of the voltage developed across the capacitor 14. Such charge pump circuits also typically include flying capacitors such as capacitors 37 and 38 that are selectively coupled in series with each other or with the voltage between input 46 and return 47 during operation of circuit 81 in order to generate the desired voltage for storage on capacitor 14.

In addition to circuit 81, converter 80 includes a precharge circuit 119 for charging capacitor 14 to a voltage less than the voltage received between input 46 and return 47. The value of capacitor 14 is typically large to provide the large value of current generally required for current 31 to provide the desired amount of light from LEDs 16 and 27. The value of current 19 or 31 is now typically about 2.5 amps (2.5A) and is expected to increase to, for example, 10 amps (10A) as the need for greater flash intensity increases. For example, the capacitor 14 may have a value between about 0.25 farad to 1.0 farad or more. To minimize drain on the battery 11, a pre-charge circuit 119 is used to slowly charge the capacitor 14 with a small value of current before starting the circuit 81. Slowly precharging the capacitor 14 facilitates charging large capacitors from a power limited source, such as a lithium ion battery. Precharging the capacitor 14 minimizes the amount of time required for the circuit 81 to charge the capacitor 14 when the circuit 81 is activated. Circuit 81 is enabled by an enable signal received on input 58 and precharge circuit 119 is enabled by an enable signal received on input 57. This configuration facilitates enabling precharge circuit 119 independent of the enabled or disabled operating state of circuit 81.

Circuit 119 includes a current source 114, a start-up transistor 118, a first current mirror including current mirror connected transistors 113 and 117, and a second current mirror including current mirror connected transistors 115 and 116. When the enable signal on input 57 is asserted by forcing input 57 low, transistor 118 is disabled, thereby allowing current to flow from source 114 through transistor 113. The current through transistor 113 forces a substantially similar current to flow through transistor 117 and through transistor 115. The current through transistor 115 forces a substantially equal current to flow through transistor 116 and thus also through output 59 to charge capacitor 14. Circuit 119 charges capacitor 14 until the voltage stored on capacitor 14 is substantially equal to the voltage between inputs 46 and 47 minus the voltage drop across transistor 116 (which is typically on the order of hundreds of millivolts). Circuit 119 has no feedback signal from the voltage stored on capacitor 14 and therefore circuit 119 does not regulate the value of the voltage on capacitor 14. The value of the current provided by circuit 119 to capacitor 14 is determined by the transistor size ratio in the current mirror and the value of the current provided by source 114. The current provided by circuitry 119 typically has a value of about 90 to 150 milliamps (90-150ma), and preferably about 120 milliamps (120 ma). After capacitor 14 is precharged, circuit 119 no longer provides current to capacitor 14. Thereafter, the circuit 81 may be activated to increase the voltage stored on the capacitor 14.

To facilitate this functionality of the controller 45, first and second inputs of the interface 75 are connected to respective inputs 49 and 50 of the controller 45. The bus input of interface 75 is typically connected to the bus interface input of block 78. The clock output of block 78 is commonly connected to the clock inputs of circuits 83-84, 91-93 and 104, 106 and 108. A first enable output of block 78 is connected to an enable input of circuit 83, a second enable output of block 78 is connected to an enable input of circuit 84, a third enable output of block 78 is connected to an enable input of circuit 91, a fourth enable output of block 78 is connected to an enable input of circuit 92, a fifth enable output of block 78 is connected to an enable input of circuit 93, a sixth enable output of block 78 is connected to an enable input of circuit 104, a seventh enable output of block 78 is connected to an enable input of circuit 106, and an eighth enable output of block 78 is connected to an enable input of circuit 108. An enable output of circuit 83 is connected to an input 86 of circuit 85. An enable output of circuit 91 is connected to another enable input of circuit 92, and circuit 92 has an enable output connected to enable input 96 of circuit 95. An enable output of circuit 104 is connected to another enable input of circuit 106, and circuit 106 has an enable output connected to input 111 of circuit 110. A source of transistor 41 is commonly connected to the sources of transistors 142-147, return 47, and transistors 162-169. The drain of transistor 141 is connected to a first terminal of a source 140, source 140 having a second terminal commonly connected to the drain and gate of transistor 131 and the gate of transistors 132 and 138. A source of transistor 131 is commonly connected to the source of transistors 132-138 and output 61. A drain of transistor 142 is connected to a drain of transistor 132. A drain of transistor 143 is connected to a drain of transistor 133. A drain of transistor 134 is connected to a drain of transistor 144, a drain of transistor 135 is connected to a drain of transistor 145, a drain of transistor 136 is connected to a drain of transistor 146, a drain of transistor 137 is connected to a drain of transistor 147, and a drain of transistor 138 is connected to a drain of transistor 148. The inputs of buffers 121 and 128 are connected to input 87. The output of buffer 121 is commonly connected to the gates of transistors 142 and 162. The output of buffer 122 is commonly connected to the outputs of transistors 143 and 164. The output of buffer 123 is commonly connected to the gates of transistors 144 and 165. The output of buffer 124 is connected to the gates of transistors 145 and 166. The output of buffer 125 is connected to the gates of transistors 146 and 167. The output of buffer 126 is connected to the gates of transistors 147 and 168. The output of buffer 127 is connected to the gates of transistors 148 and 169. The output of buffer 128 is connected to the gate of transistor 162. A drain of transistor 162 is connected to a first terminal of source 160. A second terminal of source 160 is commonly connected to a drain and a source of transistor 151 and to a gate of transistors 152 and 158. The sources of transistors 151 and 158 are connected to output 62. The drain of transistor 152 is connected to the drain of transistor 162, the drain of transistor 153 is connected to the drain of transistor 164, the drain of transistor 154 is connected to the drain of transistor 165, the drain of transistor 155 is connected to the drain of transistor 166, the drain of transistor 156 is connected to the drain of transistor 167, the drain of transistor 157 is connected to the drain of transistor 168, and the drain of transistor 158 is connected to the drain of transistor 169. Referring to FIG. 3, block 184 has an enable input connected to input 96 and a data input connected to input 97. A first output of block 184 is connected to a gate of transistor 185, a second output is connected to a gate of transistor 186, and a third output is connected to a gate of transistor 187. The drains of transistors 185, 186 and 187 are commonly connected to node 189 on the non-inverting input of amplifier 190. An inverting input of amplifier 190 is connected to input 68 and an output of amplifier 190 is connected to output 67. Reference 176 is connected to receive power between input 41 and return 47 and has an output connected to a first terminal of resistor 177. A second terminal of resistor 177 is commonly connected to a source of transistor 185 and a first terminal of resistor 178. A second terminal of resistor 178 is connected to a first terminal of resistor 179 and to a source of transistor 186. A source of transistor 187 is connected to a first terminal of resistor 180 and a first terminal of resistor 182. A second terminal of resistor 182 is connected to return 47. A second terminal of resistor 180 is connected to a second terminal of resistor 179.

Fig. 5 schematically illustrates an enlarged plan view of a portion of an embodiment of a semiconductor device or integrated circuit 195 that is formed on semiconductor die 196. Controller 45 is formed on die 196. Die 196 may also include other circuits that are not shown in fig. 5 for simplicity of the drawing. Controller 45 and device or integrated circuit 195 are formed on die 196 by semiconductor manufacturing techniques that are well known to those skilled in the art.

In view of the foregoing, it is apparent that a new device and method is disclosed. Included, among other features, is forming a plurality of flash control channels, each having an input for receiving a control word and having an output for controlling a value of current through a light source. Two of the channels may be used to control two different current values through the same light source. Forming the channels on the semiconductor substrate reduces the cost of a system using the flash controller. Using multiple flash control channels more accurately controls the timing and intensity of the light formed by the light source, allows the light source to be used for multiple functions, and provides more flexibility in light source control.

While the subject matter of the present invention has been described with specific preferred embodiments, it is evident that many alternatives and variations will be apparent to those skilled in the semiconductor arts. For clarity of explanation, block diagrams of preferred embodiments of the channels 82, 90 and 103 are illustrated, however, other embodiments should provide similar operation. For example, circuits 85, 95, and 110 may use other circuit configurations to control the values of respective currents 17 and 29, 19, and 31, so long as the configurations control the values of the currents in response to the control words. The relationship between the delay provided by the delay circuit and the onset of current flow may have other relationships and configurations. Further, more flash control channels may be added to control more LEDs, or some LEDs may operate in parallel. Although transistors 22 and 32 are shown external to the controller, in some embodiments, these transistors may be included within the controller, e.g., formed on the same substrate as the controller. Moreover, the word "connected" is used throughout for clarity of description, but is intended to have the same meaning as the word "coupled". Accordingly, "connected" should be interpreted to include direct connections or indirect connections.

Claims (15)

1. A flash controller for a camera, comprising:

an interface circuit operably coupled to receive a plurality of control words from outside the flash controller;

a first flash control channel configured to receive and store at least a first control word of the plurality of control words and responsively control a first current through a first light source to a first value, wherein the first light source is external to the flash controller; and

a second flash control channel configured to receive and store at least a second control word of the plurality of control words and responsively control a second current through the first light source to a second value, wherein the first current and the second current are two separate currents.

2. The flash controller of claim 1, further comprising a third flash control channel configured to receive and store at least a third control word of the plurality of control words and responsively control a third current through a second light source to a third value, the third flash control channel configured to begin forming the third current at a first time relative to forming the second current in response to a value of the third control word.

3. The flash controller of claim 1, wherein the first flash control channel comprises a first storage element for storing at least a first portion of the first control word.

4. The flash controller of claim 3, wherein the first flash control channel comprises a first pulse width control circuit having the first storage element for storing at least the first portion of the first control word, wherein the first pulse width control circuit is configured to control a duration of the first current in response to the first portion of the first control word.

5. The flash controller of claim 4, wherein the first flash control channel comprises a first current value circuit having a second storage element for storing at least a second portion of the first control word, wherein the first current value circuit is configured to control a value of the first current responsive to the second portion of the first control word.

6. The flash controller of claim 1, wherein the first flash control channel forms a first analog signal that forms the first current, and wherein the second flash control channel forms a second analog signal that controls the second current.

7. The flash controller of claim 1, further comprising a charge pump controller and a pre-charge circuit configured to charge an external capacitor to a first value with a third current before initiating operation of the charge pump controller, wherein the pre-charge circuit does not include a regulator circuit that controls a voltage value stored on the external capacitor.

8. A method of forming a flash controller for a camera, comprising the steps of:

configuring an interface circuit of the flash controller to receive a plurality of control words from outside the flash controller; and

configuring a plurality of flash control channels to receive and store the plurality of control words and responsively forming a control signal that controls a first current through a first light source external to the flash controller and that controls a second current through the first light source, wherein the first current and the second current are two separate currents.

9. The method of claim 8, wherein the step of configuring the plurality of flash control channels comprises: configuring the plurality of flash control channels to form an analog control signal that controls a value of the first current.

10. The method of claim 8, wherein the step of configuring the plurality of flash control channels comprises: configuring a first flash control channel of the plurality of flash control channels to receive and store a first control word of the plurality of control words and to control a timing and a value of the first current through the first light source in response to the first control word.

11. The method of claim 10, wherein configuring the first flash control channel to receive and store the first control word comprises: configuring the first flash control channel to determine a time to initiate the first current in response to a first portion of the first control word; configuring the first flash control channel to establish a value of the first current in response to a second portion of the first control word; and configuring the first flash control channel to establish a duration of the first current in response to a third portion of the first control word.

12. The method of claim 10, further comprising configuring a second flash control channel of the plurality of flash control channels to receive and store a second control word of the plurality of control words and to control a timing and a value of the second current through the first light source in response to the second control word.

13. The method of claim 10, further comprising configuring a second flash control channel of the plurality of flash control channels to receive and store a second control word of the plurality of control words, and controlling a timing and a value of a third current through a second light source in response to the second control word, wherein the second light source is external to the flash controller.

14. The method of claim 13, further comprising configuring the second flash control channel to begin forming a third current through the second light source at a first time relative to the first flash control channel beginning forming the first current through the first light source, wherein the second flash control channel forms the first time in response to a value of the second control word.

15. The method of claim 13, wherein configuring the second flash control channel to receive and store the second control word comprises: configuring the second flash control channel to determine a time to initiate a third current through the second light source in response to a first portion of the second control word; configuring the second flash control channel to establish a value of a third current through the second light source in response to a second portion of the second control word; and configuring the second flash control channel to establish a duration of a third current through the second light source in response to a third portion of the second control word.