HK1178998B - Memory object relocation for power savings - Google Patents

Description

Memory object relocation for power saving

Background

Computer power consumption can be a significant expense to data centers and many other operators of computer systems. Since computers that consume large amounts of power also typically have high cooling costs, power consumption is often accompanied by cooling and other expenses within the data center.

SUMMARY

A computer system may manage objects in memory to consolidate less frequently accessed objects into memory regions that may operate in a low power state where access times to memory objects may be increased. By operating at least some of these memory regions in a low power state, significant power savings can be achieved. The computer system may have several memory regions that may be independently power controlled, and memory objects may be moved to each memory region to optimize power consumption. In some embodiments, operating system level functions may manage memory objects based on parameters collected from usage history, memory topology and performance, and inputs from applications.

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

Brief Description of Drawings

In the drawings:

FIG. 1 is a diagram illustration of an embodiment showing a system with memory management.

FIG. 2 is a diagram illustration of an embodiment showing a power curve over time for a memory device.

FIG. 3 is a flow diagram illustrating an embodiment of a method for optimizing memory objects in a memory region.

Detailed Description

The memory management system may consolidate high frequency used memory objects and less frequently used memory objects into separately controllable memory regions. Memory regions with less frequently used memory objects may be operated in a low power mode, while memory regions with memory objects that are used at a high frequency may be operated in a high power mode.

The memory management system may operate as an operating system function and may use information about the hardware topology, the usage of individual memory objects, inputs from applications, and other parameters to determine optimized locations for individual memory objects. Optimizations may be performed to maximize different parameters, such as power savings, overall performance, performance of a particular application, performance of a particular virtual machine instance, or other parameters.

Many memory devices may have different operating characteristics. In a typical volatile memory device, a low power state may be used to maintain data in the memory, while a high power state may be used to access data using a read or write command. Typically, accessing such a device in a low power state may be accomplished by raising the power state and performing the access. This access typically has latency characteristics that affect the performance of the operation.

The memory management system may collect historical information about memory objects to determine where to place the objects. The historical information may include monitoring access frequency, access type, and access performance. The historical information may be used, at least in part, to identify candidate low power memory regions.

The memory management system may also evaluate changes made to the memory objects to determine whether the changes improve or worsen power consumption and performance. Changes with an overall negative impact may be undone in some cases.

Throughout this specification, like reference numerals refer to like elements throughout the description of the figures.

When elements are referred to as being "connected" or "coupled," the elements can be directly connected or coupled together or one or more intervening elements may also be present. In contrast, when elements are referred to as being "directly connected" or "directly coupled," there are no intervening elements present.

The present subject matter may be embodied as devices, systems, methods, and/or computer program products. Accordingly, some or all of the inventive subject matter may be embodied in hardware and/or in software (including firmware, resident software, micro-code, state machines, gate arrays, etc.). Furthermore, the present subject matter may take the form of a computer program product on a computer-usable or computer-readable storage medium having computer-usable or computer-readable program code embodied in the medium for use by or in connection with an instruction execution system. In the context of this document, a computer-usable or computer-readable medium may be any medium that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

The computer-usable or computer-readable medium may be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. By way of example, and not limitation, computer readable media may comprise computer storage media and communication media.

Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by an instruction execution system. Note that the computer-usable or computer-readable medium could be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted, of otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.

Communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term "modulated data signal" means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media. Combinations of any of the above should also be included within the scope of computer readable media.

When the subject matter is embodied in the general context of computer-executable instructions, the embodiment may comprise program modules, executed by one or more systems, computers, or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Typically, the functionality of the program modules may be combined or distributed as desired in various embodiments.

FIG. 1 is a diagram illustration of an embodiment 100 showing a system with a memory management system. Embodiment 100 is a simplified example of a computer system that may manage power consumption by consolidating less frequently used memory objects into memory regions that may operate in a low power state.

The diagram of FIG. 1 illustrates various functional components of a system. In some cases, a component may be a hardware component, a software component, or a combination of hardware and software. Some components may be application layer software and other components may be operating system layer components. In some cases, the connection of one component to another component may be a tight connection, where two or more components operate on a single hardware platform. In other cases, the connection may be made over a network connection spanning a long distance. Embodiments may use different hardware, software, and interconnect architectures to implement the described functionality.

Embodiment 100 illustrates a computer system that can manage memory objects to save power and optimize performance. Embodiment 100 may represent any type of computing device that may have a processor and memory. Examples may include desktop computers, server computers, handheld computing devices, mobile phones, personal digital assistants, or any other device having a processor and memory.

Embodiment 100 may optimize power and performance by moving less frequently used memory objects to memory regions that may operate in a low power state. Those frequently used memory objects may also be incorporated into memory regions capable of operating at high power.

The basic optimization routine may place objects in a low power memory region when those objects are not accessed frequently. Many complex algorithms may use various levels of historical data, input from applications that create and use memory objects, and monitoring of performance and power consumption to find optimized placements.

Many different memory technologies exist and each may have different characteristics. In general, many types of volatile memory may consume a small amount of power to refresh the memory, and may consume a larger amount of power when performing read or write operations. In many memory technologies, the transition from a low power state to a high power state may result in some delay in responding to a request. Thus, a memory device operating in a low power state may consume less power, but may pay a performance penalty. A more detailed illustration of this operation can be seen in embodiment 200 presented later in this specification.

In general, operating a memory device at a low power level may have an associated performance cost. To minimize performance costs, those memory objects that are not frequently accessed or those memory objects that can tolerate slower response times may be incorporated onto a memory device that is capable of operating at a low power level.

The memory management system may manage memory in a number of different ways, and may use different optimization mechanisms, which may vary based on the associated application, usage history, memory device type, or other factors.

A simple version of the memory management system may monitor memory blocks to identify those memory blocks that are frequently accessed as well as those memory blocks that are less frequently accessed. This version may track each unit of memory, such as a page of memory, and determine statistics describing how frequently a block of memory is used. An optimization routine may attempt to bring memory objects together based on their frequency of use in order to operate in a manner that places as many memory regions as possible in a low power mode.

In tracking versions of the history for each unit of memory, the history may be removed or deleted when certain changes may be made to the memory device. For example, if the purpose of a memory region is to be re-determined as a high usage to low usage memory region, the history for that region may be deleted so that the history may not adversely affect the memory management algorithm.

The system of embodiment 100 may have a processor 106 and memory regions, each of which may be independently controlled to operate in different power states.

For purposes of this specification and claims, a memory region is a portion of memory that is independently controllable to operate in different power states.

Many memory technologies are capable of operating in a low power state for maintaining or refreshing memory and a high power state for performing read or write operations. In these memory technologies, the memory may exhibit higher performance in a high power state and lower performance in a low power state. Other memory technologies may have additional power states with different power consumption and different performance characteristics.

The main performance characteristic of the memory state may be the latency between the time a read or write request is received and the time a completion response is transmitted. In some embodiments, other performance characteristics may be considered during optimization, including bandwidth, access time, random read or write cycle time, page mode read or write cycle time, time required to enter or exit the low power mode, and other performance characteristics.

In some embodiments, an optimization routine may use predefined performance characteristics of the memory devices used to compute the optimized placement. In other embodiments, the performance monitor may periodically test or monitor performance so that actual performance values may be used.

Embodiment 100 illustrates several different configurations of memory regions. In some cases, a memory region may be composed of several memory devices. In other cases, a single device may have multiple memory regions, while in still other cases, a single memory device may be viewed as a single memory region.

The memory devices may be memory packages such as DIPs, SIPPs, SIMMs, DIMMs, and other memory packages. These packages may include a printed circuit board and one or more integrated circuits. In other embodiments, the memory device may be a single integrated circuit or a portion of an integrated circuit. Some memory devices are easily removable by a user, such as a universal serial bus memory device.

The memory device may be any type of memory device, including volatile and non-volatile memory devices. Volatile memory devices may maintain memory contents as long as power is supplied to the memory device. Non-volatile memory can preserve memory contents even when power is removed from the device. Examples of volatile memory include Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and other types of volatile memory. Examples of non-volatile memory include flash memory, electrically erasable programmable read-only memory (EEPROM), and various other types of non-volatile memory.

The memory area 108 may include a plurality of memory devices 110 and 112. Memory devices 110 and 112 may be, for example, separate memory packages. The memory device 114 may be a single device that includes two memory regions 116 and 118. In another construction, the memory area 120 may include a single memory device 122.

In many computing devices, memory can be structured in a typical homogenous manner, meaning that there may be multiple memory regions that are the same or are considered to be the same in performance. In many cases, these memory regions may also be constructed to be the same size.

In some computing devices, the memory may include dissimilar memory devices or constructs. For example, a computing device may have several DRAM memory devices as well as flash memory devices.

In some computing devices, two or more portions of memory may be combined in a striped (striped) or staggered configuration. Interleaving or striping is a mechanism that can improve memory performance by using non-contiguous memory locations to store data in memory. In a typical interleaved memory application, two memory devices are accessible by placing odd addresses on one memory device and even addresses on a second memory device. In many cases, particularly for operations involving large amounts of data, the interleaved memory may have a faster response time or greater bandwidth than the non-interleaved memory. Indeed, an interleaving mechanism using two memory devices may increase throughput by increasing the bandwidth of data that may be processed by the memory system.

When two or more memory devices or memory regions are interleaved at a fine granularity such that a typical memory access will access multiple devices or regions, the combination of interleaved devices or regions may be considered a single memory region for controlling a high power or low power state.

In some embodiments, two or more devices may be configured for interleaved memory operations, while other memory devices may be configured to be non-interleaved. In a typical desktop, laptop, or server computer, the memory configuration of the computer is set prior to booting the computer. In some devices, these configurations may be set at a basic input/output system (BIOS) level configuration.

Each memory region is capable of operating in a different power state. In a typical DRAM memory device, read and write operations may be performed in a high power state, while the same operations may not be performed while the memory device is in a low power state. Other devices may have different capabilities and different capabilities in various power states. For example, some devices may permit read operations while disallowing write operations in a low power state. In another example, some memory devices may permit read and write operations to be performed at low power levels, but with slower response times or different performance characteristics than when in a high power state.

In some memory technologies, a memory device may have more than two power states, each of which may allow different operations with respective performance characteristics.

Different techniques and architectures may be used to control when a memory region enters and exits a low power state. In some embodiments, a memory region may have a controller that monitors accesses to the memory region and reduces the power state when no access occurs for a period of time. When a request for a read or write operation is received, the controller may boost the power level in response to the request. After a period of time without operation of the memory device, the controller may cause the memory device to enter a low power state. In many embodiments, this controller may be a hardware component that may operate without external input.

Examples may include a memory controller 124 that may manage power states of the memory regions 108. In another example, the memory controller 126 may be a component or built-in functional component of the memory device 114. Yet another example may be a memory controller that may be part of the processor 106.

In some embodiments, the memory controller may receive an external input. For example, the memory manager may send a message or signal to the memory controller to enter a low power state. This communication may be transmitted as part of a read or write operation or may be a separate communication.

In some embodiments, various power monitoring mechanisms may exist in hardware. The power monitoring mechanism can measure the power consumption of a particular device or group of devices on an instantaneous, periodic, or other basis. The power monitoring mechanism may be used to determine power consumption or power savings when monitoring various operations, and may be used as part of an optimization algorithm for memory object placement.

For example, the power monitor 128 can monitor and measure the power consumption of the memory devices 110 and 112. In some cases, the power monitor 128 can measure the power consumption of each memory device 110 and 112 individually or just as an aggregate group. This power monitoring device may be a component of the power supply or distribution system for the memory devices 110 and 112. In another example, the memory device 114 may include a power monitor 130 that may measure the power consumption of the memory device 114.

In yet another example, the power monitor 132 may be a system level power monitoring system capable of measuring power consumption across the system. Depending on the configuration, the power monitor 132 can distinguish between and measure power consumption by computer components, groups of components, memory devices, groups of memory devices, or other portions of the computer system.

The processor 106 may execute various components of the software 104. The software components described in embodiment 100 are example components that may be used to manage objects in memory. Other embodiments may have different software configurations or some functions may be implemented in hardware, for example.

In a typical monitoring system, the operating system 136 may perform many low-level functions, while various applications 138 may perform higher-level functions. Generally, an operating system may act as a hardware interface for applications, which are computer programs that perform particular functions for a user. Operating systems typically provide functions used by applications such as memory management, networking, security, file systems, and other functions.

The application 138 may create many different memory objects 140 that may be stored in various memory devices in the hardware 102. Memory object 140 may be as small as a single bit or may be a large database containing many gigabytes of data. In some cases, a read or write operation to a memory object may involve reading or writing the entire memory object. In other cases, a read or write operation may involve reading or writing only a portion of a memory object.

The memory manager 134 may operate as part of an operating system 136 to manage memory locations in order to optimize power consumption and performance. In other embodiments, some or all of the functionality of memory manager 134 may be applications 138, while still other embodiments may have some or all of the functionality of memory manager 134 as hardware components.

In many cases, memory manager 134 may include a mapping engine that helps determine characteristics about the memory devices. For example, the mapping engine may test the latency during read queries while the memory is in a low power state and while the memory device is in a high power state. The mapping engine may perform these tests as active tests, where the mapping engine may configure the memory device to a particular state, then perform read or write operations and make measurements. In some embodiments, the mapping engine may operate passively and may monitor read and write queries of other applications to measure latency and other parameters.

The memory manager 134 may maintain a mapping between virtual memory addresses and physical memory addresses. The mapping may allow the application to reference the memory object using the virtual address. When a memory object is moved from one memory region to another, the physical address may change in the mapping without affecting the virtual address.

Memory manager 134 may monitor memory objects stored in a memory region and may move memory objects to a different memory region to optimize power usage.

Memory manager 134 may operate in a number of different architectures. Two different architectures are discussed herein, but other architectures may also be used. In a first architecture, memory manager 134 may monitor all memory objects contained in memory. Such a memory manager may optimize placement by identifying memory regions for low frequency access memory objects and other memory regions for high frequency access memory objects, and then the memory manager may consolidate the less frequently used memory objects together, allowing those memory regions to operate in a low power state and thereby save power.

This architecture may evaluate all memory regions to select candidate memory regions for low power and high power states, and then may move memory objects to cause at least one memory region to operate in a low power state. This architecture can perform extensive optimizations to customize memory object locations for performance and/or power savings.

In another architecture, memory manager 134 may monitor and manage memory objects in a subset of the memory regions. Such a memory manager may monitor memory regions to identify high frequency access memory objects and then move those memory objects to other memory regions. In this architecture, the memory manager is operable to remove those memory objects that may cause the memory region to operate in a higher power state.

The second architecture may monitor a smaller set of objects and may be able to perform certain optimizations with less overhead and complexity than the first architecture. In one embodiment, the memory region may be identified as a low power memory region in the BIOS or another setup mechanism. The selection may remain unchanged while the computer system is running, and may or may not change.

The second architecture may identify only high frequency memory objects and move those objects to other memory regions. Some embodiments may also identify low frequency memory objects in other memory regions for moving to low frequency memory regions.

The memory manager 134 may have a performance monitor 144 that may monitor access to objects and performance of various memory regions. The performance metrics may be stored in a historical database 148.

Accesses to the memory objects may be monitored and characterized to identify the memory objects for placement in the appropriate memory regions. In some embodiments, performance monitor 144 may track statistics for each memory region. In this embodiment, each page or memory object of memory may have a set of statistics indicating accesses to the memory object. In other embodiments, performance monitor 144 may monitor read and write operations and may identify those memory objects having a high access frequency. In this embodiment, separate statistics may or may not be maintained for each memory object or memory page in memory.

When an embodiment identifies those objects with high access frequencies, the remaining objects may be assumed to be low frequency access objects. This embodiment may preserve less statistics and information about objects in memory.

Performance monitor 144 may also measure latency, response time, throughput, or other performance parameters of the memory region. In this embodiment, the performance monitor 144 may store the actual performance characteristics of the memory regions for use in optimization. Some such embodiments may measure the performance characteristics of the system before and after the optimized locations of the various memory objects are implemented. Such measurements may be used to verify that the optimized location performs as expected, and in the event that the new location does not perform as well as the previous settings, such measurements may be used to fall back to the previous location.

The memory manager 134 may have an optimizer 142 that may identify and optimize the placement of memory objects and cause those memory objects to be moved according to the optimized placement. The optimizer 142 may use different input information to perform the optimization. In some embodiments, the history database 148 may be consulted to identify high or low frequency access memory objects.

Some embodiments may include indicators from various applications 138 that may identify particular memory objects that are to have a higher or lower access frequency. For example, an application may be changing the running state from an active mode to a dormant or inactive mode. When this change occurs, the application 138 may communicate directly or indirectly with the memory manager 134 and the optimizer 142 to move the memory objects associated with the application to the appropriate memory region.

Some memory managers 134 may have power monitors 146. The power monitor 146 may be used to collect actual power consumption data when a memory region is in a high power state or a low power state. The power monitor 146 may interface and communicate with the various hardware power monitors 128, 130, and 132.

In some embodiments, memory manager 134 may use power monitor 146 to calculate power savings. In one such embodiment, memory manager 134 may measure the power consumption of a memory device when in a low power state and also when the memory device is in a high power state. The difference between power consumption times the length of time the device is in a low power state may be calculated as an approximate power savings.

Some embodiments may verify performance and power savings after implementing the change. These embodiments may measure performance and power savings before and after moving memory objects to different memory regions, and may revert to previous configurations if sufficient performance or power savings are not achieved.

In some embodiments, the hardware 102 may be configured using BIOS prior to booting the operating system 132. The BIOS may be used to configure various memory regions. In some embodiments, BIOS settings may be used to identify some memory regions as interleaved and specific memory regions as candidate memory regions for low power state operation.

The BIOS 150 may also include a start-up test process 152. The launch test process 152 may perform performance measurements of various memory regions. The boot test process 152 may cycle through each memory region and perform read and write operations when the memory region is in a high power state and the same when the memory region is in a low power state. Each memory region may be tested in this manner and the performance of the memory region may be stored for use by an optimization algorithm or routine.

FIG. 2 is a diagram of an embodiment 200 showing a power graph of a memory device or memory region versus time. Embodiment 200 is not to scale, but rather is intended to illustrate general power consumption and performance concepts that may reflect actual operation of many different memory technologies.

The illustration of embodiment 200 is an example of a typical DRAM memory device. Other devices may have different power consumption characteristics.

Embodiment 200 illustrates consumed power 204 with respect to time 202. A curve representing power consumption 206 is shown.

At the beginning of the curve, a high power state 208 is shown. In time period 210, a read or write operation may be initiated and may end in time period 214. During this operation, the memory device may consume a higher level of power as indicated by region 212. After this operation, the device may remain in the high power state 208.

The operation up to time period 214 illustrates a typical read or write operation when the memory device is in the high power state 208. During this operation, latency 216 may reflect the time between receiving a command and responding to the command, as shown by time periods 210 and 214.

In many embodiments, the memory controller may monitor the memory device in the high power state 208 and may cause the device to enter the low power state 224 at time period 218. Many such embodiments may wait a predetermined amount of time, shown as time period 220, of inactivity before entering low power state 224.

When a typical memory device is in the low power state 224, the device may not be able to respond to read or write requests. Some memory devices are capable of performing some operations in the low power state 224 while other operations may only be performed in the high power state 208.

At time period 226, a read or write operation may be received. Because the device is in the low power state 224, the device may consume a higher power level 228 during the ramp-up period 227. After the ramp-up period 227, the device may process operations during period 229 and return to the high power state 208 at period 230.

Because the device is in the low power state 224 when a read or write operation is received at the time period 226, the latency 232 for responding to the request may be much longer than the latency 216 when the device is in the high power state 208. The increased latency 232 may be a performance factor encountered when the device is operating in a low power state.

FIG. 3 is a flow diagram illustrating an embodiment 300 of a method for managing memory objects. Embodiment 300 is a simplified example of a method that may be performed by a memory manager, such as memory manager 134 of embodiment 100.

Other embodiments may use a different order, additional or fewer steps, and different names or terms to achieve similar functionality. In some embodiments, various operations or groups of operations may be performed in parallel with other operations, in a synchronous or asynchronous manner. The steps selected herein were chosen to illustrate some principles of operation in a simplified form.

Embodiment 300 illustrates an optimization method that may be performed by a memory manager. The method of embodiment 300 is merely one example of a method that may be used to operate some memory regions in a low power mode with minimal performance degradation.

The optimization of embodiment 300 may relocate individual memory objects so that power savings and performance may be optimized. By locating infrequently used memory objects together in a common memory region, the memory region may be operated in a low power state. In some embodiments, the optimization algorithm may perform a trade-off between power saving and performance characteristics, and the optimization algorithm may be variable to enable a user to select weighting factors for power saving or performance.

The optimization algorithm may be any type of heuristic, process, or mechanism for determining memory object placement. In some embodiments, simple heuristics may be used, while other embodiments may perform complex optimizations by evaluating many different placement scenarios and selecting one of those scenarios. In many such optimizations, performance costs and/or power costs may be calculated for each scheme, as well as projected revenue or performance gains (if any) in terms of power savings. Still other embodiments may use other optimization mechanisms.

In block 302, a memory topology may be determined. The memory topology may include various characteristics that identify each memory region and the memory regions. These characteristics may vary between different embodiments and may include the size and performance characteristics of the memory regions, the address space occupied by each memory region, the mechanism used to control the memory regions, and other factors.

The memory topology may include definitions and configuration banks, memory ranks (memorrank), specific DIMMs, memory channels, memory circuits, integrated circuit devices, power rails (power rails) or controls for memory regions, and other elements that define the memory configuration. The definition of the memory topology may be different for various embodiments and may be tailored to the type of optimization and level of control that the memory manager may have in the device. In some cases, the memory manager can manage memory objects at a precise level of control, such as being able to identify the particular memory circuit in which a memory object may be stored. In other cases, the memory manager may have a coarser level of control.

In some embodiments, different memory regions may have different performance characteristics, and those performance characteristics may be used to optimize memory object placement. For example, if a memory region includes two interleaved DIMM memory devices, the memory region may have a faster response time and better throughput than other memory regions with non-interleaved DIMM memory. Thus, memory regions containing interleaved DIMM memory devices may be considered candidate memory regions for high access frequency memory objects, while other memory regions may be candidate memory regions for low power state operations and infrequently accessed memory objects.

The memory topology may include a mechanism for a memory manager to control the memory regions. These mechanisms may include messaging or communication mechanisms that a memory manager may use to request that a memory region operate in a high power or low power state.

In some embodiments, the topology determined in block 302 may be determined during a BIOS or boot operation, which may be performed at or before the start of loading and executing an operating system. The topology may be determined by BIOS level or operating system level routines that may detect each memory region, perform queries, and collect topology information.

In some such embodiments, performance testing may be performed on each memory region to determine performance metrics for those memory regions. This test may involve setting the memory region to a low power state and measuring the latency of read or write requests to the memory region, and also performing a similar test when the memory region is set to a high power state.

In block 304, the memory objects may be monitored for access frequency, performance, and power consumption. Block 304 may include many different monitored factors that may be used by the optimization routine.

If optimization is not performed in block 306, the process may return to block 304 to generate a history of access frequencies and other factors. In some embodiments, performance and power consumption may vary with the workload of the device and the data stored in memory. In these embodiments, performance and power consumption data may be collected and stored for individual memory objects or groups of memory objects.

The optimization in block 306 may be triggered by different mechanisms in different embodiments.

In these embodiments, the optimization may be performed on a periodic basis, such as every few minutes, every hour, every day, or some other predetermined basis. In these embodiments, a timer or other mechanism may initiate the optimization in block 306.

In some embodiments, the device operates for long periods of time, such as a server or other computer that may continue to operate for many days, weeks, or months. These devices typically have regular time periods in which the load on the device fluctuates. Typically, these time periods are predictable. For example, a server used by an enterprise may be busy during normal business hours, but may be lightly used at night and during non-business hours. This server may perform some operations at night, such as, for example, backup operations. This server may have a predictable time at which usage of the device may change, and may perform optimization before or immediately after the usage may change.

In these embodiments, the performance monitor may monitor the periodic usage of the device and may predict when optimization may be performed based on the device's past history.

In some embodiments, a change in the application may indicate that optimization may be performed. The performance monitor may monitor a particular application or general computing activity on the device and may determine that one or more applications have increased or decreased activity. Based on the activity change, optimization may be performed.

Some embodiments may trigger optimization based on direct notification from an application. For example, an application that has been triggered to exit sleep mode and perform a large number of computations may send an alert, trigger, or other indicator to the memory manager to optimize memory locations based on a change in the state of the application.

In block 308, an optimized scope may be determined. In some embodiments, optimization may be performed for a particular memory region, memory object with particular characteristics, or other scope.

In some cases, the optimization may be performed on all memory regions and may consider all memory objects. In these embodiments, the optimization in block 310 may analyze the usage history of all memory objects, identify high and low frequency usage memory objects, identify memory regions for those memory objects, and move the memory objects to the corresponding memory regions. In many cases, this optimization may evaluate many different placement schemes, and an optimized placement scheme may be selected based on performance and power factors.

In some such embodiments, sets of memory regions may be identified for memory objects having similar frequencies of use. In some cases, memory objects may be consolidated in a memory region based on a frequency of use metric that is independent of other memory objects. In some cases, memory objects whose usage frequency is related to other memory objects may be merged into a memory region. For example, several memory objects may have similar usage patterns, where these objects are frequently used at the same time, and may be inactive at the same time. These objects may be merged into the same memory region to maximize power savings. In some embodiments, these memory objects may be related to a single application and may be identified by their relationship to the application. In other embodiments, the usage history of the memory objects may be compared to group memory objects that are both heavily and lightly used.

In some embodiments, optimizations may be performed for specific kinds of data or for data associated with specific applications. In such a case, the optimization of block 310 may only consider moving those memory objects that have a specified type of data or are associated with a specified application. Such an optimization routine may identify memory regions for the high and low power states and move memory objects accordingly.

In some embodiments, the optimization routine may operate by identifying memory objects that are accessed at high frequency and aggregating those memory objects in a specified memory region. Rather, these embodiments may operate by identifying infrequently accessed memory objects and moving those memory objects to regions of memory that may often be in a low power state. These embodiments may identify memory objects from other memory regions to fill the identified memory regions.

Other embodiments may use an optimization routine that checks a memory region to identify memory objects to be moved from the memory region. For example, designated high-frequency-access memory regions may be analyzed to identify non-high-frequency-access memory objects, and attempts may be made to move those memory objects to other memory regions. In another example, a memory region designated as a low power state memory region may be analyzed to identify high frequency-accessed memory objects in the memory region, and the optimization routine may attempt to move those memory objects to other memory regions.

In embodiments where optimization is performed for a particular application or a particular type of data, those memory objects may be analyzed to determine whether the memory regions in which they are stored are appropriate for those objects. For example, such optimization may identify individual memory regions as being heavily accessed or lightly accessed, and then compare the identified memory objects to determine whether the usage history of those memory objects is compatible with the memory regions. Any incompatibilities may be corrected by moving incompatible memory objects to a different memory region.

Throughout this specification, the optimization routine has been exemplified by specifying memory regions or memory objects as two classes: frequently accessed and infrequently accessed. This designation serves as a simplified way of describing the optimization, but is not intended to be limiting. In some embodiments, the access frequencies of memory objects and memory regions may be grouped in two, three, four, or more levels or categories. For example, memory objects and memory regions may be grouped into high frequency, mid frequency, and low frequency categories.

In some embodiments, the type of access to a memory object may affect performance and power savings. In some embodiments, those memory objects having similar access types may be grouped together in a memory region. For example, some embodiments may group memory objects frequently accessed using read commands separately from memory objects frequently accessed using write commands. In another example, some embodiments may group read-only data separately. While data types such as Boolean data, string data, numeric data, or other complex data types may be exposed to the memory manager, some embodiments may group memory objects by these data types. In another example, memory objects created by a particular application may be grouped together.

The optimization in block 310 may result in identification of objects to move in block 312, as well as identification of candidate memory regions for high frequency access and low frequency access. The low frequency access memory regions may be those memory regions that may be operated in a low power mode as much as possible. Upon identifying the memory objects to be moved, the low frequency access objects may be moved to a low power region in block 314 and the high frequency access objects are moved to a high frequency access memory region in block 316.

After implementing the changes in blocks 314 and 316, the system may operate in block 318. During the operation of block 318, those memory regions having infrequently accessed memory objects may be operated in a lower power state more than prior to the change of blocks 314 and 316. If such an improvement is found in block 322, the change may be saved in block 326 and the process may return to block 304. If such an improvement is not detected in block 322, the change may be rolled back to the previous configuration in block 324 and the process may return to block 304.

Block 322 may examine the optimized performance and power savings of block 310 and may determine whether the optimization goal has been reached. In some embodiments, the optimization goal may be purely power savings or may be a combination of power savings and performance. If those goals are not met, the system may undo the change in block 324.

The foregoing description of the present subject matter has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the subject matter to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the appended claims encompass such alternative embodiments beyond the scope of the prior art.

Claims (15)

1. A system for memory object relocation, comprising:

a plurality of memory regions, each of the memory regions having at least a low power state and a high power state;

a controller configured to separately and independently manage power states of the memory regions;

a performance monitor configured to monitor performance of the plurality of memory regions and accesses to a plurality of memory objects;

an optimizer configured to identify and optimize placement of the plurality of memory objects and to cause movement of the plurality of memory objects according to the optimized placement;

a processor configured to manage memory contents by a method comprising:

monitoring each of the plurality of memory objects to determine an access frequency of each of the memory objects;

identifying the first memory object as a low frequency access object;

monitoring each of the plurality of memory regions to determine a performance metric for each of the memory regions;

determining an optimized location for each of the plurality of memory objects based on the performance metrics;

identifying the first memory region as a candidate memory region for low power operation according to the determined optimized location;

moving the first memory object to the first memory region; and

operating the first memory region in the low power state.

2. The system of claim 1, wherein the method further comprises:

identifying the second memory region as a candidate memory region for high power operation;

identifying a second memory object in the first memory region as a high frequency access object;

moving the second memory object from the first memory region to the second memory region; and

operating the second memory region in the high power state.

3. The system of claim 2, wherein the system further comprises:

calculating a power savings by monitoring the first memory region to determine a length of time the first memory region is operating in the low power state and determining a power savings from the length of time.

4. The system of claim 2, wherein the plurality of memory regions are the same memory region.

5. The system of claim 2, wherein at least two of the plurality of memory regions are dissimilar.

6. The system of claim 5, wherein one of the memory regions is a removable memory region.

7. The system of claim 2, wherein the second memory region is an interleaved memory region comprising at least two memory devices with interleaved addressing.

8. The system of claim 1, further comprising:

a mapping engine configured to test at least one of the memory regions to determine a latency of a read query while the memory region is in the low power state.

9. The system of claim 8, wherein the mapping engine is further configured to operate as part of a boot operation.

10. The system of claim 8, wherein the mapping engine is further configured to determine a first power consumption when the memory region is in the low power state and a second power consumption when the memory region is in the high power state.

11. The system of claim 1, further comprising:

a power monitoring system configured to measure power consumption of each of the memory regions.

12. A method performed on a computer processor, the method comprising:

receiving a memory topology comprising a range of memory addresses for each of a plurality of memory regions, each of the plurality of memory regions being individually controllable to a high power state and a low power state;

monitoring a plurality of memory objects in the memory region to determine an access frequency of each of the plurality of memory objects;

monitoring each of the plurality of memory regions to determine a performance metric for each of the memory regions;

determining an optimized location for each of the plurality of memory objects based on the performance metrics;

identifying the first memory region as a candidate memory region for low power operation according to the determined optimized location;

identifying a first memory object as a high frequency access object and located in the first memory region;

moving the first memory object to a second memory region; and

operating the first memory region in the low power state.

13. The method of claim 12, further comprising:

identifying the second memory region as a candidate memory region for high power operation;

identifying a second memory object in the second memory region as a low frequency access object;

moving the second memory object from the second memory region to the first memory region; and

operating the second memory region in the high power state.

14. The method of claim 13, further comprising:

detecting a first interaction with the second memory object while the first memory region is in the low power state;

measuring a first latency of the first interaction; and

storing the first waiting time.

15. The method of claim 14, further comprising:

detecting a second interaction with the second memory object while the first memory region is in the high power state;

measuring a second latency of the second interaction; and

storing the second wait time.