HK1176741B - Semiconductor device having doped epitaxial region and its methods of fabrication - Google Patents

Description

Semiconductor device with doped epitaxial region and method of manufacturing the same

Technical Field

The present invention relates to the field of semiconductor processing, and more particularly, to a semiconductor device having a doped epitaxial region and a method of fabricating the same.

Background

Improving the performance of semiconductor devices, particularly transistors, has always been a major concern in the semiconductor industry. For example, during the design and fabrication of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), a common goal is always to increase the electron mobility of the channel region and reduce parasitic resistance to improve device performance.

For example, other methods of improving device performance include: the overall resistance of the MOSFET is reduced by doping the region between the source/drain regions and the channel region, which is referred to as the "tip" or source/drain extension region of the MOSFET. For example, dopants are implanted into the source/drain regions, and an annealing step diffuses the dopants toward the channel region. However, there is a limitation in controlling the dopant concentration and position. Furthermore, the implantation and doping methods do not address the issue of lateral undercutting or parasitic resistance at the tip region.

Drawings

Fig. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

Fig. 2 is a sectional view illustrating a semiconductor device according to another embodiment of the present invention.

Fig. 3 is a sectional view illustrating a semiconductor device according to another embodiment of the present invention.

Fig. 4 is a perspective view illustrating a semiconductor device according to another embodiment of the present invention.

Fig. 5A to 5F are sectional views illustrating a method of manufacturing the semiconductor device shown in fig. 1.

Fig. 6A to 6F are sectional views illustrating a method of manufacturing the semiconductor device shown in fig. 2.

Fig. 7A to 7C are sectional views illustrating a method of manufacturing the semiconductor device shown in fig. 3.

Fig. 8A to 8I are perspective views illustrating a method of manufacturing the semiconductor device shown in fig. 4.

Fig. 9-15 are cross-sectional views of the semiconductor device shown in fig. 8E-8I.

Fig. 8E' is a perspective view illustrating an alternative embodiment of the semiconductor device shown in fig. 8E.

Fig. 9' is a perspective view illustrating an alternative embodiment of the semiconductor device shown in fig. 9.

Detailed Description

Semiconductor devices having doped epitaxial regions and methods of fabricating the same are described. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. In other instances, well known semiconductor processing techniques and features have not been described in particular detail in order to not unnecessarily obscure the present invention.

Embodiments of the present invention describe methods of forming an epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is in-situ carbon and phosphorus doped silicon (Si) deposited by a cyclical deposition-etch process_y(C,P)_1-y) And (4) a region. From silicon (Si) very highly doped with phosphorus_yP_1-y) An epitaxial cap layer back-fills the cavity created under the spacer during the cyclical deposition-etch process. Due to (Si)_yP_1-y) The combined effects of increased electron mobility at the channel region, reduced short channel effects (due to carbon inhibiting phosphorus diffusion), and reduced parasitic resistance provided by very high phosphorus doping in the epitaxial cap layer, fabrication of the epitaxial region and cap layer stack in a self-aligned epitaxial Tip (SET) structure provides significant transistor performance gain.

Fig. 1 shows a cross-sectional view of a semiconductor device according to an embodiment of the invention. The semiconductor device includes a substrate 200 made of a semiconductor material such as, but not limited to, monocrystalline silicon. In one embodiment, substrate 200 is a silicon film of a silicon-on-insulator (SOI) substrate, or a multilayer substrate including silicon, silicon germanium, a III-V compound semiconductor.

A gate dielectric 310 is formed on the channel region of the substrate 200. In one embodiment, dielectric layer 310 is made of a material such as, but not limited to, silicon oxide (e.g., SiO)₂) Any known insulating material. In another embodiment, dielectric layer 310 is formed from a material having a dielectric constant substantially greater than the dielectric constant (i.e., k) of silicon dioxide>3.9) of a high-k dielectric material. Examples of high-k dielectric materials include, but are not limited to, tantalum oxide (Ta)₂O₅) Titanium oxide (TiO)₂) And hafnium oxide (HfO)₂)。

A gate electrode 320 is formed on the gate dielectric 310. In one embodiment, the gate electrode is made of any well-known material such as, but not limited to, polysilicon. In other embodiments, the gate electrode 320 is made of a metal or metal alloy material such as, but not limited to, platinum, tungsten, or titanium.

In one embodiment, the hard mask 410 is formed on top of the gate electrode 320. In one embodiment, hard mask 410 is made of a material such as, but not limited to, silicon nitride or silicon oxynitride. Spacers 420, 440 are formed on opposing sidewalls of the gate electrode 320. In one embodiment, the spacers 420, 440 are formed along the entire sidewall width of the gate electrode 320. Spacers 420, 440 include sidewalls 421, 441 and bottom surfaces 422, 442. In one embodiment, the spacers 420, 440 are made of a material such as, but not limited to, silicon nitride, silicon dioxide, or silicon oxynitride.

In an embodiment of the present invention, a recessed source interface 220 and a recessed drain interface 230 are formed on the substrate 200 on opposite sides of the gate electrode 320. In one embodiment, a portion of the recessed source interface 220 extends laterally under the bottom surface 422 of the spacer 420 and under a portion of the gate electrode 320. Similarly, a portion of the recessed drain interface 230 extends laterally under the bottom surface 442 of the spacer 440 and under a portion of the gate electrode 320.

A source region 501 is formed on the recessed source interface 220. In an embodiment of the present invention, the source region 501 includes an epitaxial region 531 formed on the recessed source interface 220. A cap layer 541 is formed on the epitaxial region 531. The source region 501 includes a source epi-tip region 503, the source epi-tip region 503 including portions of an epi region 531 and a cap layer 541 formed directly under the spacer 420 and the gate dielectric 310.

A drain region 502 is formed on the recessed drain interface 230. In one embodiment, the drain region 502 includes an epitaxial region 532 formed on the recessed drain interface 230. A cap layer 542 is formed over the epitaxial region 532. The drain region 502 includes a drain epi-tip region 504, and the drain epi-tip region 504 includes portions of an epi region 532 and a cap layer 542 formed directly under the spacers 440 and the gate dielectric 310. By forming the source and drain epi-tip regions 503, 504 relatively close to the channel region, a greater hydrostatic stress is induced on the channel region, resulting in higher electron mobility and increased drive current.

In an embodiment of the present invention, the epitaxial regions 531, 532 comprise silicon and carbon doped with phosphorus in which case the semiconductor device shown in FIG. 1 is an NMOS planar or tri-gate transistor with a self-aligned epi tip (set) structure in one embodiment, the epitaxial regions 531, 532 comprise a silicon-based epitaxial layer having a carbon concentration of about 0.5 atomic% to 4 atomic% and about 9 × 10¹⁹cm^-3To 3 × 10²¹cm^-3In a particular embodiment, the epitaxial regions 531, 532 include a carbon concentration of 2.2 atomic% and 2 × 10²⁰cm^-3Silicon of phosphorus concentration. The substitutional carbon (more than 2 atomic%) in the epitaxial regions 531, 532 of the source and drain regions 501, 502 exerts a hydrostatic stress on the channel region, which increases electron mobility. Furthermore, substitutional carbon inhibits any subsequent treatmentAny phosphorus diffusion during the thermal anneal, thereby reducing short channel effects.

In an embodiment of the present invention, the cap layers 541, 542 are epitaxial layers comprising silicon doped with phosphorus in one embodiment, the cap layers 541, 542 comprise a material having a thickness of about 8 × 10¹⁹cm^-3To 3 × 10²¹cm^-3In a particular embodiment, the cap layers 541, 542 include a silicon cap having a concentration of 2 × 10²¹cm^-3Silicon of phosphorus concentration. The high phosphorus concentration level in the cap layers 541, 542 reduces parasitic resistance, particularly in the contact resistance between the salicide and the source/drain regions 501, 502.

Fig. 2 shows a cross-sectional view of a semiconductor device similar to fig. 1. The substrate 200 is made of {001} silicon and includes a recessed source interface 240 having a {111} plane 241 in a {111} crystal plane of the {001} silicon substrate 200 and a recessed drain interface 250 having a {111} plane 251 in a {111} crystal plane of the {001} silicon substrate 200. The 111 planes 241, 251 provide reduced volume in the depletion layer (depletion) and correspondingly improved control of short channel effects. In one embodiment, the recessed source and drain interfaces 240, 250 each further comprise a 010 plane 242, 252 in a 010 crystal plane of the 001 silicon substrate 200, wherein the 010 plane 242, 252 extends directly below the gate electrode 320. The 010 planes 242, 252 help to more precisely define the metallurgical (metallurgical) channel length of the semiconductor device and reduce short channel effects.

Similar to fig. 1, the semiconductor device shown in fig. 2 includes a source region 501 and a drain region 502, each having an epitaxial region 531, 532 and a cap layer 541, 542. Epitaxial regions 531, 532 and cap layers 541, 542 are formed on the recessed source and drain interfaces 240, 250 including their 111} faces 241, 251 and 010} faces 242, 252. The source region 501 comprises a source epi-tip region 505, the source epi-tip region 505 comprising a portion of the cap layer 541 and the epitaxial region 531 surrounded by the spacers 420, the gate dielectric 310 and the 111, 010 faces 241, 242. The drain region 502 comprises a drain epi-tip region 506, the drain epi-tip region 506 comprising a portion of a cap layer 541 and an epi region 532 surrounded by spacers 440, gate dielectric 310 and {111}, {010} faces 251, 252. Forming the source and drain epi-tip regions 505, 506 relatively close to the channel region induces greater hydrostatic stress on the channel region, thereby increasing electron mobility, which results in higher drive current.

Fig. 3 shows a cross-sectional view of a semiconductor device similar to fig. 2. In one embodiment, the source and drain regions 501, 502 each comprise an epitaxial layer 610, 620 formed on recessed source and drain interfaces 240, 250, wherein the recessed source and drain interfaces 240, 250 comprise their 111} planes 241, 251 and 010} planes 242, 252.

The source region 501 includes a source epi-tip region 611, the source epi-tip region 611 including a portion of an epitaxial layer 610 surrounded by spacers 420, gate dielectric 310, and {111}, {010} faces 241, 242. The drain region includes a drain epi-tip region 621, the drain epi-tip region 621 including a portion of the epitaxial layer 610 surrounded by the spacer 440, the gate dielectric 310, and the 111, 010 faces 251, 252. Forming the source and drain epi-tip regions 611, 621 relatively close to the channel region induces greater hydrostatic stress on the channel region, thereby increasing electron mobility, which results in higher drive current.

In an embodiment of the present invention, the epitaxial layers 610, 620 comprise silicon doped with phosphorus in one embodiment, the epitaxial layers 610, 620 comprise a silicon material having a thickness of about 8 × 10¹⁹cm^-3To 3 × 10²¹cm^-3In a particular embodiment, epitaxial layers 610, 620 include silicon with a phosphorus concentration of 2 × 10²¹cm^-3Silicon of phosphorus concentration. The high phosphorus concentration level in the epitaxial layers 610, 620 reduces parasitic resistance, particularly in the contact resistance between the salicide and the source/drain regions 501, 502.

Fig. 1, 2 and 3 illustrate the application of an epitaxial region in a planar transistor to increase electron mobility at the channel region or to reduce contact resistance at the source/drain regions. It can be appreciated that the epitaxial region is not limited to planar transistors, but can be fabricated on other devices such as, but not limited to, tri-gate transistors. Fig. 4 shows a perspective view of a tri-gate device including a substrate 200 having a semiconductor body or fin 260 (shown in phantom). Gate electrodes 340 are formed on three surfaces of the fin 260 to form three gates. A hard mask 410 is formed on top of the gate electrode 340. Gate spacers 460, 470 are formed on opposing sidewalls of the gate electrode 340. The source region includes an epitaxial region 531 formed on the recessed source interface 266 and the sidewalls of fin 260. A cap layer 541 is deposited over the epitaxial region 531.

Fig. 5A-5F illustrate a method of forming a semiconductor device as discussed with respect to fig. 1. The fabrication of the semiconductor device begins with providing a substrate 200 as shown in fig. 5A. A gate dielectric 310 is formed on the desired channel region of the substrate 200. In one embodiment, the gate dielectric 310 is formed by any well-known method, such as, but not limited to, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD).

A gate electrode 320 is formed on the gate dielectric 310. In an embodiment of the present invention, the gate electrode 320 is a sacrificial gate electrode, which is subsequently replaced by the actual gate electrode in a replacement gate process. A hard mask 410 is formed on top of the gate electrode 320. In an embodiment of the present invention, the gate electrode 320 and the hard mask 410 are deposited using PVD or CVD and then the gate electrode 320 and the hard mask 410 are patterned using well-known photolithography and etching techniques.

Spacers 420, 440 are then formed on opposing sidewalls of the gate electrode 320. Spacers 420, 440 include sidewalls 421, 441 and bottom surfaces 422, 442 formed on the top surface of substrate 200. In one embodiment, the spacers 420, 440 are formed by using well-known techniques, such as depositing a layer of spacer material over the entire substrate 200 including the gate electrode 320, and then anisotropically etching the layer of spacer material to form the spacers 420, 440 on the sidewalls of the gate electrode 320.

Next, a source region and a drain region are formed on the substrate 200. In an embodiment of the present invention, the fabrication of the source and drain regions begins with recessing portions of the substrate 200 using well-known etching techniques such as, but not limited to, dry etching or wet etching. In an embodiment of the present invention, substrate 200 is recessed using a wet etch comprising an etchant chemistry that is substantially selective to substrate 200 to form a recessed source interface 220 and a recessed drain interface 230 as shown in fig. 5B.

In one embodiment, the wet etch undercuts the spacers 420, 440 and forms a source epi-tip cavity 271 between the bottom surface 422 of the spacer 420 and the recessed source interface 220 and a drain epi-tip cavity 272 between the bottom surface of the spacer 440 and the recessed drain interface 230. As a result, the source epi-tip cavity 271 and the drain epi-tip cavity 272 expose the bottom surfaces 422, 442 of the spacers 420, 440. In one embodiment, the source epi-tip cavity 271 and the drain epi-tip cavity 272 also expose portions of the gate dielectric 310. As a result, the portion of the recessed source interface 220 extends laterally under the spacers 420 and under the portion of the gate electrode 320. Similarly, a portion of the recessed drain interface 230 extends laterally under the spacer 440 and under a portion of the gate electrode 320.

It can be appreciated that the wet etch can be controlled (e.g., by adjusting the etch duration) such that the source and drain epi-tip cavities 271, 272 do not expose the gate dielectric 310. For example, the recessed source interface 220 extends laterally only under the spacers 420, and the recessed drain interface 230 extends laterally only under the spacers 440.

In an embodiment of the present invention, the recessed source and drain interfaces 220, 230 define a channel region of the semiconductor device. The channel region refers to the portion of the substrate 200 directly below the gate dielectric 310 and between the recessed source and drain interfaces 220, 230.

Next, an epitaxial region is deposited on each of the recessed source and drain interfaces 220, 230 by alternately exposing the substrate 200 to the first precursor and the second precursor. In fig. 5C, the fabrication of the epitaxial region begins with exposing the entire substrate 200 to a first precursor so as to deposit epitaxial films 511, 512 on the recessed source and drain interfaces 220, 230. In the case where the substrate 200 is made of monocrystalline silicon, the recessed source and drain interfaces 220, 230 are monocrystalline surfaces that allow epitaxial growth of epitaxial films 511, 512 thereon. While on the other hand, the hard mask 410, spacers 420, 440, and gate dielectric 310 are amorphous surfaces. As a result, amorphous layer 513 is deposited on the top surface of hardmask 410, sidewalls 421, 441 and bottom surfaces 422, 442 of spacers 420, 440, and portions of the bottom surface of gate dielectric 310.

In an embodiment of the present invention, the first precursor includes a silicon-containing compound, a carbon-containing compound, and a dopant. In one embodiment, the silicon-containing compound includes, but is not limited to, silanes and halogenated silanes. Such silicon-containing compounds include Silane (SiH)₄) Disilane (Si)₂H₆) Trisilane (Si)₃H₈) Dichlorosilane (SiH)₂Cl₂) And pentachlorosilane.

In one embodiment, the carbon-containing compound includes, but is not limited to, an organosilane. For example, the carbon-containing compound includes monomethylsilane (CH)₃-SiH₃). In one embodiment, a carbon-containing compound is reacted with hydrogen (H)₂) Or argon. For example, monomethylsilane (CH)₃-SiH₃) With hydrogen (H)₂) Or argon in which CH₃-SiH₃The concentration of (c) is in the range of 0.5% to 20%.

In an embodiment of the present invention, the dopant is an n-type dopant such as, but not limited to, phosphorus or arsenic. In one embodiment, the use is without any hydrogen or such as N₂Or inert gas diluted Phosphine (PH) of Ar₃) A phosphorous dopant is incorporated into the epitaxial film. In another embodiment, phosphine gas is mixed with hydrogen gas, e.g.As hydrogen (H)₂) Medium 3% phosphine (pH)₃) A mixture of (a).

In one embodiment, the first precursor is delivered and released onto the substrate 200 with a carrier gas. In one embodiment, the carrier gas includes, but is not limited to, hydrogen (H)₂) Or any other gas such as nitrogen (N)₂) An inert gas of argon and helium, or any combination thereof.

In an embodiment of the invention, the substrate 200 is exposed to the first precursor at a temperature of about 500 to 700 degrees celsius and a pressure of about 5 to 300 torr for a duration of about 3 to 60 seconds. In a specific embodiment, the substrate 200 is exposed to the first precursor at a temperature of 600 degrees celsius and a pressure of 30 torr for a duration of 15 seconds.

In one embodiment, the epitaxial films 511, 512 are grown to have a thickness of about 6 to 100 angstroms. In a specific embodiment, the epitaxial films 511, 512 are grown to have a thickness of 50 angstroms. In the case where a phosphorous dopant is used for the first precursor, the deposited epitaxial films 511, 512 are crystalline films containing silicon and carbon doped with phosphorous (i.e., silicon layers doped with in-situ carbon and phosphorous). The amorphous layer 513 contains silicon doped with phosphorus and carbon.

An optional surface pretreatment can be performed on the substrate 200 prior to exposing the substrate 200 to the first precursor to promote epitaxial growth and reduce surface defects. In an embodiment of the present invention, the surface preparation comprises a hydrogen bake treatment (in fig. 5B) performed on the substrate 200 in order to clean the recessed source and drain interfaces 220, 230. The hydrogen bake treatment releases oxygen and rebuilds the surface so that the epitaxial films 511, 512 can be easily nucleated without defect formation. In one embodiment, the hydrogen bake process is performed at about 700 to 1050 degrees celsius for a duration of about 10 to 120 seconds. In an embodiment of the present invention, hydrogen chloride (HCl) is added to the hydrogen bake treatment. Hydrogen chloride (HCl) is capable of removing approximately 1 to 3 monolayers of the recessed source and drain interfaces 220, 230, rendering them free of oxygen, hydrocarbons, and any other contaminants. In one embodiment, the range of about 700 to 900 is takenThe hydrogen baking process with hydrogen chloride (HCl) is performed at a lower temperature of the degree of ° celsius for a duration of about 10 to 120 seconds. Alternatively, chlorine gas (Cl)₂) Germane (GeH)₄) Or Phosphine (PH)₃) Can be used as an additive or alternative chemical compound to hydrogen chloride (HCl).

In an alternative embodiment, the surface pretreatment utilizes an etching step to clean the recessed source and drain interfaces 220, 230. In one embodiment, the etching step uses an etchant gas, such as, but not limited to, hydrogen (H)₂) Anhydrous hydrochloric acid (HCl) or germane (GeH)₄) And hydrogen (H)₂) A mixture of (a). In another embodiment, the surface pretreatment uses a combination of an etching step and a hydrogen bake treatment.

Prior to exposing the substrate 200 to the second precursor, a cleaning process can be performed to remove the first precursor and other byproducts from the substrate 200. In one embodiment, the purge process injects a gas such as, but not limited to, nitrogen (N)₂) Helium or argon to remove any unreacted first precursor or by-products.

Next, in fig. 5D, the entire substrate 200 is exposed to a second precursor in order to remove the amorphous layer 513 from the sidewalls 421, 441 and bottom surfaces 422, 442 of the spacers 420, 440. In addition, the second precursor also removes any amorphous layer 513 formed on the hard mask 410 and under the gate dielectric 310. In one embodiment, the second precursor 900 uses an etchant chemistry that etches the amorphous layer 513 faster than the epitaxial films 511, 512. In one embodiment, second precursor 900 is an etchant gas, such as, but not limited to, hydrogen (H)₂) Anhydrous hydrochloric acid (HCl) and germane (GeH)₄) And hydrogen (H)₂) A mixture of (a). Germane (GeH)₄) Allowing etching by catalysis, providing high etch rates at low temperatures.

In one embodiment, the substrate 200 is exposed to the second precursor at a pressure of about 30 to 300 torr for a duration of about 5 to 60 seconds. In a specific embodiment, the substrate 200 is exposed to the second precursor at a pressure of 80 torr and for a duration of 20 seconds. In one embodiment, the temperature is maintained at substantially the same level when the substrate 200 is exposed to the first precursor and the second precursor simultaneously.

Due to the weak chemical bonds between the amorphous layer 513 and the hard mask 410, spacers 420, 440, and gate dielectric 310, the second precursor easily removes the amorphous layer 513 deposited thereon. The second precursor reacts with the amorphous layer 513 and converts it into a byproduct, thereby removing the amorphous layer 513 from the hard mask 410, spacers 420, 440, and gate dielectric 310.

On the other hand, the epitaxial films 511, 512 have strong chemical bonds with the recessed source and drain interfaces 220, 230. Due to the strong chemical bonds, the second precursor removes only a small portion of the epitaxial films 511, 512. In one embodiment, the thickness of the epitaxial films 511, 512 deposited during fig. 5C or the duration of exposure of the second precursor to the substrate 200 in fig. 5D can be adjusted to effectively remove the amorphous layer 513 while maintaining a sufficient thickness of the epitaxial films 511, 512.

Fig. 5C and 5D show one deposition-etch cycle to form epitaxial films 511, 512 on the recessed source and drain interfaces 220, 230. In one embodiment, the deposition-etch cycle is repeated using the same type of first and second precursors until a desired number of epitaxial films are deposited. For example, fig. 5E shows epitaxial regions 531, 532 that each contain ten epitaxial films.

It can be appreciated that neither epitaxial regions 531, 532 are limited to only ten epitaxial films. In one embodiment, about 3 to 100 deposition-etch cycles are performed to form the epitaxial regions 531, 532. In a specific embodiment, 30 deposition-etch cycles are performed to form the epitaxial regions 531, 532 having a thickness of about 30 nanometers.

In an embodiment of the present invention, the deposited epitaxial regions 531, 532 have a graded carbon or phosphorous concentration. The carbon and phosphorus concentrations of each epitaxial film deposition can be optimized to provide optimal selectivity and defect-freeIn one embodiment, the graded carbon concentration of the epitaxial regions 531, 532 (shown in FIG. 5E) begins at about 0.5 atomic% of the lowermost epitaxial film and gradually increases to a desired level of about 2 atomic% in the uppermost epitaxial film¹⁹cm^-3Started and gradually increased to about 2 × 10 of the uppermost epitaxial film²¹cm^-3In one embodiment, the deposited epitaxial regions 531, 532 have a graded carbon concentration (0.5-2 atomic%) and a graded phosphorus concentration (8 × 10)¹⁹-2×10²¹cm^-3) Combinations of (a) and (b).

As shown in fig. 5E, epitaxial regions 531, 532 are selectively formed on the recessed source and drain interfaces 220, 230. However, removal of the amorphous layer 513 during each deposition-etch cycle results in voids or cavities 281, 282 formed between the bottom surfaces 422, 442 of the spacers 420, 440 and the top surfaces of the epitaxial regions 531, 532. In one embodiment, the cavities 281, 282 also extend between portions of the gate dielectric 310 and the epitaxial regions 531, 532. The cavities 281, 282 may cause detrimental effects on the transistor performance and thus need to be eliminated. In one embodiment of the present invention, the cavities 281, 282 are substantially backfilled by cap layers 541, 542 selectively deposited on the epitaxial regions 531, 532, as shown in FIG. 5F.

In an embodiment of the present invention, the cap layers 541, 542 are selectively deposited on the epitaxial regions 531, 532 in a single deposition process by exposing the substrate 200 to a third precursor. In one embodiment, the third precursor includes the same silicon-containing compound and dopant as the first precursor, and the same etching gas as the second precursor.

In the case where the epitaxial regions 531, 532 are crystalline films having silicon and carbon doped with phosphorus, the third precursor forms the cap layers 541, 542 using the same phosphorus dopant. The crystalline surface of the epitaxial layers 531, 532 allows for epitaxial growth of cap layers 541, 542 thereon, and as a result, the cap layers 541, 542 are epitaxial layers containing silicon doped with phosphorus. In addition to backfilling the cavities, the phosphorus doped silicon cap layers 541, 542 also provide the advantage of inducing tensile stress on the channel region, thereby increasing electron mobility and improving device performance.

In one embodiment, a co-flow deposition technique is used to simultaneously expose the substrate 200 to a silicon-containing compound, dopant, and etchant gases. In one embodiment, the etchant gas does not include germane (GeH)₄). The etchant gas readily removes any silicon and phosphorus containing compounds that are weakly bonded to the hard mask 410 and spacers 420, 440 during deposition, thereby depositing the cap layers 541, 542 on the epitaxial regions 531, 532 and not on the hard mask 410 or spacers 420, 440.

In an embodiment of the invention, the substrate 200 is exposed to the third precursor at a temperature of about 550 to 800 degrees celsius and a pressure of about 10 torr to atmospheric pressure for a duration of about 30 to 900 seconds. In a specific embodiment, the substrate 200 is exposed to the first precursor at a temperature of 635 degrees celsius and a pressure of 600 torr, for a duration of 180 seconds.

In one embodiment, the cap layers 541, 542 are grown to have a thickness of approximately 50 to 500 angstroms. In a particular embodiment, the cap layers 541, 542 are grown to have a thickness of 300 angstroms.

Portions of the epitaxial region 531 and cap layer 541 directly below the spacer 420 and gate dielectric 310 form the source epi-tip region 503. Similarly, the portions of the epitaxial region 532 and cap layer 542 directly under the spacer 440 and gate dielectric 310 form the drain epi-tip region 504. By forming the source and drain epi-tip regions 503, 504 relatively close to the channel region, a greater hydrostatic stress is induced on the channel region, resulting in higher electron mobility and increased drive current. The stress can be further amplified by increasing the carbon concentration of the source and drain epi-tip regions 503, 504 during the fabrication of the epitaxial regions 531, 532. Furthermore, the carbon concentration of the source and drain epi-tip regions 503, 504 also helps to suppress any phosphorus diffusion during the subsequent thermal anneal.

In an embodiment of the present invention, the gate electrode 320 is a sacrificial gate electrode, which is subsequently replaced by the actual gate electrode in a replacement gate process. In one embodiment, the replacement gate process begins by depositing a mask on the cap layers 541, 542 and then planarizing the mask to be coplanar with the hard mask 410 (not shown). Next, the hard mask 410 and the gate electrode 320 are removed using well-known etching techniques. After removing hard mask 410 and gate electrode 320, the actual gate electrode is deposited on gate dielectric 310. In one embodiment, the actual gate electrode is a metal gate electrode comprising a material such as, but not limited to, platinum, tungsten, or titanium. This completes the manufacture of the semiconductor device shown in fig. 1.

Fig. 6A-6F illustrate a method of forming a semiconductor device as discussed with respect to fig. 2. As shown in fig. 6A, the fabrication of the semiconductor device begins with providing a substrate 200. The semiconductor device shown in fig. 6A is the same as the semiconductor device shown in fig. 5A, and thus will not be discussed in detail. Briefly, the semiconductor device includes a gate dielectric 310 formed on a desired channel region of the substrate 200. A gate electrode 320 is formed on the gate dielectric 310. In an embodiment of the present invention, the gate electrode 320 is a sacrificial gate electrode, which is subsequently replaced by the actual gate electrode in a replacement gate process. A hard mask 410 is formed on top of the gate electrode and spacers 420, 440 are formed on the sidewalls of the gate electrode 320.

Next, a source region and a drain region are formed on the substrate 200. In an embodiment of the present invention, the fabrication of the source and drain regions begins with recessing portions of the substrate 200 using well-known etching techniques such as, but not limited to, dry etching or wet etching. In an embodiment of the present invention, the substrate 200 is recessed using a wet etch that is substantially selective to the substrate 200 to form a recessed source interface 240 and a recessed drain interface 250 as shown in fig. 6B.

In an embodiment of the present invention, substrate 200 is made of 001 silicon. The wet etch uses an etchant chemistry that etches the 001 silicon substrate 200 based on the crystal orientation, especially when the etch in the other crystal orientation is much faster, etching the 001 silicon substrate 200 along the 111 crystal planes of the silicon substrate 200 is much slower to form the 111 planes 241, 251. As a result, a source epi-tip cavity 271 is formed between the bottom surface 422 of the spacer 420 and the {111} plane 241. A drain epi-tip cavity 272 is formed between the bottom surface of the spacer 440 and the 111 planes 251.

Wet etch chemistries include, but are not limited to, ammonia-based or amine-based etchants. An example of an ammonia-based etchant is ammonia hydroxide (NH)₄OH), tetramethylammonium hydroxide (TMAH), and benzyltrimethylammonium hydroxide (BTMH). Wet etch chemistries include other types of etchants such as potassium hydroxide (KOH) and sodium hydroxide (NaOH).

In one embodiment, the wet etch also creates 010 planes 242, 252 in the channel region of 001 silicon substrate 200. The 010 planes 242, 252 extend directly below the gate dielectric 310. In a particular embodiment, the 010 planes 242, 252 are formed up to a length of about 3 nanometers from the gate dielectric 310.

Next, an epitaxial region is deposited on each of the recessed source and drain interfaces 240, 250 by alternately exposing the substrate 200 to the first precursor and the second precursor. As shown in fig. 6C, 6D, and 6E, the method of fabricating the epitaxial region is similar to the fabrication method discussed in fig. 5C, 5D, and 5E. An optional surface pretreatment can be performed on the substrate 200 prior to exposing the substrate 200 to the first precursor to promote epitaxial growth and reduce surface defects. In one embodiment, the surface pretreatment includes a hydrogen bake treatment and/or etching step as previously discussed in fig. 5C to clean the recessed source and drain interfaces 240, 250.

Starting with fig. 6C, the entire substrate 200 is exposed to the first precursor so as to deposit epitaxial films 511, 512 on the recessed source and drain interfaces 240, 250. The recessed source and drain interfaces 240, 250, including their 111 planes 241, 251 and 010 planes 242, 252, are monocrystalline surfaces that allow epitaxial growth of epitaxial films 511, 512 thereon. On the other hand, the hard mask 410, spacers 420, 440, and gate dielectric 310 are amorphous surfaces, thereby depositing an amorphous layer 513 thereon. The same first precursors and process conditions as discussed with respect to fig. 5C are applicable here and will not be discussed again.

Next, in fig. 6D, the entire substrate 200 is similarly exposed to a second precursor to remove the amorphous layer 513 from the sidewalls 421, 441 and bottom surfaces 422, 442 of the spacers 420, 440. In addition, the second precursor also removes any amorphous layer 513 formed on the hard mask 410 and under the gate dielectric 310. The same second precursor and process conditions as discussed with respect to fig. 5D are applicable here and will not be discussed again.

FIGS. 6C and 6D show one deposition-etch cycle to form epitaxial films 511, 512 on recessed source and drain interfaces 240, 250 including their {111} planes 241, 251 and {010} planes 242, 252. the deposition-etch cycle is repeated until a desired number of epitaxial films are deposited. for purposes of illustration, FIG. 6E shows epitaxial regions 531, 532 each containing ten epitaxial films. in an embodiment of the invention, as previously described in FIG. 5E, the deposited epitaxial regions 531, 532 have a graded carbon or phosphorus concentration. for example, the lowermost epitaxial film of the deposited epitaxial regions 531, 532 (as shown in FIG. 6E) has a graded carbon concentration of about 0.5 atomic% and gradually increases to a desired level of about 2 atomic% of the uppermost epitaxial layer. alternatively, the lowermost epitaxial film of the deposited epitaxial regions 531, 532 has a graded carbon concentration of about 8 × 10¹⁹cm^-3And gradually increases to about 2 × 10 of the uppermost epitaxial film²¹cm^-3In one embodiment, the deposited epitaxial regions 531, 532 have a graded carbon concentration (0.5-2 atomic%) and a graded phosphorus concentration (8 × 10)¹⁹-2×10²¹cm^-3) Combinations of (a) and (b).

Removal of the amorphous layer 513 during each deposition-etch cycle similarly results in cavities 281, 282 formed between the bottom surfaces 422, 442 of the spacers 420, 440 and the top surfaces of the epitaxial regions 531, 532. As shown in fig. 6F, the cavities 281, 282 are substantially backfilled by cap layers 541, 542 selectively deposited on the epitaxial regions 531, 532.

In one embodiment, the cap layers 541, 542 are selectively deposited on the epitaxial regions 531, 532 in a single deposition process by exposing the substrate 200 to a third precursor. The same third precursor and process conditions as discussed with respect to fig. 5F are applicable here. In the case where the epitaxial regions 531, 532 are crystalline films having silicon and carbon doped with phosphorus, the third precursor forms the cap layers 541, 542 using the same phosphorus dopant. The crystalline surface of the epitaxial regions 531, 532 allows epitaxial growth of cap layers 541, 542 thereon, and as a result, the cap layers 541, 542 are epitaxial layers containing silicon doped with phosphorus. This completes the fabrication of the semiconductor device shown in fig. 2.

Fig. 7A-7C illustrate a method of forming a semiconductor device as discussed with respect to fig. 3. Beginning with fig. 7A, fabrication of a semiconductor device begins with providing a substrate 200. The semiconductor device shown in fig. 7A is the same as that of fig. 5A, and therefore will not be discussed in detail here.

Next, a source region and a drain region are formed on the substrate 200. In an embodiment of the present invention, the fabrication of the source and drain regions begins with recessing portions of the substrate 200 using well-known etching techniques such as, but not limited to, dry etching or wet etching. In one embodiment, as shown in fig. 7B, the wet etch used in fig. 6B is similarly applied here to recess the substrate 200 to form a recessed source interface 240 and a recessed drain interface 250. The wet etch uses the same etchant chemistry as described with respect to fig. 6B to form the 111 planes 241, 251 in the 111 crystal planes of the 001 silicon substrate 200. In one embodiment, the wet etch also creates 010 planes 242, 252 in the channel region of 001 silicon substrate 200.

Next, as shown in fig. 7C, epitaxial layers 610, 620 are selectively deposited on the recessed source and drain interfaces 240, 250. In an embodiment of the present invention, the epitaxial layers 610, 620 are selectively deposited in a single deposition process by exposing the substrate 200 to a precursor comprising an etchant gas.

In one embodiment, the precursor includes a silicon-containing compound and a dopant similarly described in fig. 5C. In one embodiment, the silicon-containing compound includes, but is not limited to, silanes and halogenated silanes. Such silicon-containing compounds include Silane (SiH)₄) Disilane (Si)₂H₆) Trisilane (Si)₃H₈) Dichlorosilane (SiH)₂Cl₂) And pentachlorosilane. In an embodiment of the present invention, the dopant is an n-type dopant such as, but not limited to, phosphorus or arsenic. In one embodiment, the use is without any hydrogen or such as N₂Or inert gas diluted Phosphine (PH) of Ar₃) To introduce phosphorous dopant into the epitaxial layer. In another embodiment, phosphine gas is mixed with hydrogen gas, such as hydrogen gas (H)₂) Medium 3% phosphine (pH)₃) A mixture of (a). In one embodiment, the etchant gas of the precursor includes, but is not limited to, hydrogen (H)₂) And anhydrous hydrochloric acid (HCl).

In one embodiment, a co-flight deposition technique is used to simultaneously deliver precursors including etchant gases to the substrate 200. In one embodiment, the substrate 200 is exposed to the precursor at a temperature of about 550 to 800 degrees celsius and a pressure of about 10 torr to atmospheric pressure for a duration of about 30 to 2000 seconds. In a specific embodiment, the substrate 200 is exposed to the first precursor at a temperature of 635 degrees celsius and a pressure of 600 torr for a duration of 800 seconds.

In one embodiment, the epitaxial layers 610, 620 are grown to have a thickness of about 30 to 2000 angstroms. In a particular embodiment, the epitaxial layers 610, 620 are grown to have a thickness of 750 angstroms. Where a phosphorous dopant is used, the epitaxial layers 610, 620 comprise silicon doped with phosphorous.

In the case where the substrate 200 is made of single crystal silicon, the recessed source and drain interfaces 240, 250, including their 111} planes 241, 251 and 010} planes 242, 252, are single crystal surfaces that allow epitaxial growth of the epitaxial layers 610, 620 thereon. Since the hard mask 410 and spacers 420, 440 have amorphous surfaces, the etchant gas readily removes any silicon and phosphorous containing compounds that are weakly bonded to the hard mask 410 and spacers 420, 440 during deposition, thereby depositing the epitaxial layers 610, 620 on the recessed source and drain interfaces 240, 250 and not on the hard mask 410 or spacers 420, 440.

The portion of epitaxial layer 610 deposited between spacers 420 and the 111, 010 faces 241, 242 forms a source epi-tip region 611. Similarly, the portion of epitaxial layer 620 deposited between spacer 440 and the 111, 010 planes 251, 252 forms drain epi-tip region 621. By forming the source and drain epi-tip regions 611, 621 relatively close to the channel region, a greater hydrostatic stress is induced on the channel region, thus resulting in higher electron mobility. In addition, the phosphorus doped silicon epitaxial layers 610, 620 induce tensile stress on the channel region, thereby increasing electron mobility and improving device performance. This completes the fabrication of the semiconductor device shown in fig. 3.

In addition, an optional surface pretreatment can be performed on the substrate 200 prior to exposing the substrate 200 to the precursor to promote epitaxial growth and reduce surface defects. For example, a similar hydrogen bake process as described with respect to fig. 5C is performed on the substrate 200 (in fig. 7B) to clean the recessed source and drain interfaces 240, 250 including their 111 planes 241, 251 and 010 planes 242, 252.

Figures 8A-8I illustrate a method of forming a tri-gate device as discussed with respect to figure 4. As shown in fig. 8A, fabrication of the tri-gate device begins with providing a substrate 200. The substrate 200 includes a semiconductor body or fin 260 extending from the substrate 200 through the isolation regions 710, 720. In one embodiment, the isolation regions 710, 720 are shallow trench isolations formed by conventional techniquesThe (STI) regions are formed by common techniques such as etching the substrate 200 to form trenches and then depositing an oxide material over the trenches to form the STI regions. The isolation regions 710, 720 are made of any material such as, but not limited to, silicon oxide (e.g., SiO)₂) Are known as insulating materials.

In one embodiment, the fin 260 includes a top surface 261 above the isolation region 700. Fin 260 also includes a front surface 262 exposed above isolation region 710, and a back surface 263 exposed above isolation region 720. In one embodiment, the fin 260 is made of the same semiconductor material as the substrate 200.

Next, in fig. 8B, a gate dielectric 330 is formed on portions of top surface 261, front surface 262, and back surface 263. In one embodiment, the gate dielectric 330 is formed by any well-known method such as, but not limited to, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD).

A gate electrode 340 is then formed on the gate dielectric 330 and portions 264, 265 of the fin 260 are exposed on either side of the gate electrode 340. In one embodiment, the gate electrode 340 is made of any well-known material such as, but not limited to, polysilicon. The gate electrodes 340 formed on the top surface 261, the front surface 262 and the back surface 263 create the three gates of the tri-gate device. Subsequently, a hard mask 410 is formed on top of the gate electrode 320.

Next, as shown in fig. 8C, gate spacers 460, 470 are deposited on opposing sidewalls of the gate electrode 340. In one embodiment, the spacers 460, 470 are formed by using well-known techniques, such as depositing a layer of spacer material over the entire substrate 200 including the gate electrode 320, and then anisotropically etching the layer of spacer material to form the spacers 460, 470 on the sidewalls of the gate electrode 340. At the same time, fin spacers 480, 490 are formed on the sidewalls of the exposed portions 264, 265 of the fin 260. In one embodiment, the gate spacers 460, 470 and the fin spacers 480, 490 are made of a material such as, but not limited to, silicon nitride, silicon dioxide, or silicon oxynitride.

Next, a source region and a drain region are formed on the substrate 200. In an embodiment of the present invention, the fabrication of the source and drain regions in fig. 8D begins by removing the fin spacers 480, 490 from the sidewalls of the exposed portions 264, 265 of the fin 260. The fin spacers 480, 490 are removed by well known etch techniques such as, but not limited to, dry etching or wet etching.

In one embodiment, the fin spacers 480, 490 are completely removed from the exposed portions 264, 265 of the fin 260 using an anisotropic wet etch. At the same time, the anisotropic wet etch also removes portions of the gate spacers 460, 470, exposing portions of the sidewalls of the hard mask 410. Since the height and thickness of the gate spacers 460, 470 are greater than the height and thickness of the fin spacers 480, 490, the anisotropic wet etch removes the fin spacers 480, 490 faster than the gate spacers 460, 470. The anisotropic wet etch can be controlled to completely remove the fin spacers 480, 490 but leave a sufficient thickness of the gate spacers 460, 470 on the gate electrode 340 so that the sidewalls of the gate electrode 340 are not exposed.

Next, an etch is performed on the substrate 200 to recess the exposed portions 264, 265 of the fin 260. In an embodiment of the present invention, as shown in fig. 8E, the etch recesses the exposed portions 264 using an etchant chemistry that is substantially selective to the fin 260 to form recessed source interfaces 266 below the top surface of the isolation regions 710, 720 and to form fin sidewalls 267. On the other side of the gate electrode 340, the exposed portion 264 is recessed to form a recessed drain interface 268 and a fin sidewall 269. In one embodiment, the recessed source and drain interfaces 266, 268 are approximately 100 to 400 angstroms below the top surface of the isolation regions 710, 720.

Fig. 9 illustrates a cross-sectional view of a tri-gate device showing a fin sidewall 267 extending from the top surface 261 to the recessed source interface 266 and a fin sidewall 269 extending from the top surface 261 to the recessed drain interface 268. In embodiments of the present invention, the fin sidewalls 267, 269 are substantially coplanar or flush with the gate spacers 460, 470 sidewalls 461, 471. In one embodiment, the fin sidewalls 267, 269 are 110 planes in a 110 crystal plane of the substrate 200 and the recessed source and drain interfaces 266, 268 are 100 planes in a 100 crystal plane of the substrate 200.

In an alternative embodiment, an anisotropic etch is used to form the fin sidewalls 267, 269 recessed into the gate spacers 460, 470. Fig. 8E' is a perspective view of the tri-gate device showing the fin sidewalls 267 recessed into the gate spacers 470. Fig. 9' is a cross-sectional view showing both fin sidewalls 267, 269 recessed below the gate spacers 460, 470. In one embodiment, the fin sidewalls 267, 269 are recessed up to about 25 to 200 angstroms from the gate spacer sidewalls 461, 471.

Continuing from fig. 8E, an epitaxial region is then deposited on each of the recessed source and drain interfaces 266, 268 by alternately exposing the substrate 200 to the first precursor and the second precursor. The method of fabrication of the epitaxial regions as shown in fig. 8F, 8G and 8H is similar to the method of fabrication discussed in fig. 5C, 5D and 5E.

Starting with fig. 8F, the entire substrate 200 is exposed to the first precursor so as to deposit an epitaxial film 511 on the recessed source interface 266 and fin sidewalls 267. At the same time, an epitaxial film 512 is deposited on the recessed drain interface 268 and fin sidewalls 269 as shown in the cross-sectional view of fig. 10. The recessed source and drain interfaces 266, 268 and the fin sidewalls 267, 269 are monocrystalline surfaces that allow epitaxial growth of the epitaxial films 511, 512 thereon. On the other hand, the hard mask 410, the gate spacers 460, 470 and the isolation regions 710, 720 are amorphous surfaces, and thus the amorphous layer 513 is formed thereon. The same first precursors and process conditions as discussed with respect to fig. 5C are applicable here and will not be discussed again.

Next, in fig. 8G, the entire substrate 200 is similarly exposed to a second precursor to remove the amorphous layer 513 from the gate spacers 460, 470 and the isolation regions 710, 720. In addition, the second precursor also removes any amorphous layer 513 formed on the hard mask 410. Figure 11 shows a cross-sectional view of the tri-gate device after amorphous layer 513 is removed. The same second precursor and process conditions as discussed with respect to fig. 5D are applicable here and will not be discussed again.

8F-8G and 10-11 illustrate one deposition-etch cycle forming epitaxial films 511, 512 on the recessed source and drain interfaces 266, 268 and fin sidewalls 267, 269. the deposition-etch cycle is repeated until a desired number of epitaxial films are deposited. in one embodiment, as shown in FIG. 12, the final epitaxial regions 531, 532 include five epitaxial films. in an embodiment of the invention, as previously discussed in FIG. 5E, the deposited epitaxial regions 531, 532 have graded carbon or phosphorus concentrations. for example, the lowermost epitaxial film of the deposited epitaxial regions 531, 532 (as shown in FIG. 12) has a graded carbon concentration of about 0.5 atomic% and gradually increases to a desired level of about 2 atomic% of the uppermost epitaxial film. alternatively, the lowermost epitaxial film of the deposited epitaxial regions 531, 532 has a graded carbon concentration of about 8 × 10¹⁹cm^-3And gradually increases to about 2 × 10 of the uppermost epitaxial film²¹cm^-3In one embodiment, the deposited epitaxial regions 531, 532 have a graded carbon concentration (0.5-2 atomic%) and a graded phosphorus concentration (8 × 10)¹⁹-2×10²¹cm^-3) Combinations of (a) and (b).

In an alternative embodiment where the fin sidewalls 267, 269 are recessed within the gate spacers 460, 470, the epitaxial regions 531, 531 are formed closer to the channel region of the tri-gate device, thereby inducing a higher amount of stress on the channel region.

As shown in fig. 8H and 13, removal of the amorphous layer 513 during each deposition-etch cycle similarly results in voids or cavities 281, 282 formed between the epitaxial regions 531, 532 and the isolation regions 710, 720. As shown in fig. 8I, 14 and 15, the cavities 281, 282 are substantially backfilled by selectively depositing cap layers 541, 542 over the epitaxial regions 531, 532.

In one embodiment, the cap layers 541, 542 are selectively deposited on the epitaxial regions 531, 532 in a single deposition process by exposing the substrate 200 to a third precursor. The same third precursor and process conditions as discussed with respect to fig. 5F are applicable here. In the case where the epitaxial regions 531, 532 are crystalline films having silicon and carbon doped with phosphorus, the third precursor forms the cap layers 541, 542 using the same phosphorus dopant. The crystalline surface of the epitaxial regions 531, 532 allows epitaxial growth of cap layers 541, 542 thereon, and as a result, the cap layers 541, 542 are epitaxial layers containing silicon doped with phosphorus. The phosphorus doped silicon cap layers 541, 542 provide the advantage of inducing tensile stress on the channel region of the semiconductor fin 260, which increases electron mobility and improves device performance. This completes the manufacture of the semiconductor device shown in fig. 4.

Thus, several embodiments of the invention have been described. However, those skilled in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims.

Claims (32)

1. A method of forming a semiconductor device, comprising:

providing a substrate with a gate electrode and spacers formed on sidewalls of the gate electrode;

etching the substrate to form a recessed interface;

forming an epitaxial region on the recessed interface by alternately exposing the substrate to a first precursor and a second precursor, wherein alternately exposing the substrate to the first precursor and the second precursor comprises:

exposing the substrate to the first precursor so as to deposit an epitaxial film on the recessed interface and an amorphous layer on the sidewalls and a bottom surface of the spacer; and

exposing the substrate to the second precursor to remove the amorphous layer from the sidewalls and the bottom surface of the spacer; and

selectively depositing a cap layer on the epitaxial region,

wherein forming the epitaxial region on the recessed interface results in a void between the epitaxial region and the bottom surface of the spacer; and is

Wherein the cap layer backfills the void.

2. The method of claim 1, wherein the first precursor comprises:

a silicon-containing compound comprising a silane;

a carbon-containing compound comprising an organosilane; and

a dopant comprising phosphorus.

3. The method of claim 2, wherein the epitaxial region comprises silicon and carbon doped with phosphorus.

4. The method of claim 1, wherein the second precursor is an etchant gas.

5. The method of claim 1, wherein the cap layer is selectively deposited on the epitaxial region by exposing the substrate to a third precursor comprising:

a silicon-containing compound comprising a silane;

a dopant comprising phosphorus; and

an etchant gas.

6. The method of claim 5, wherein the cap layer comprises silicon doped with phosphorus.

7. The method of claim 1, further comprising:

a hydrogen bake process is performed on the substrate prior to alternately exposing the substrate to the first precursor and the second precursor.

8. The method of claim 1, wherein etching the substrate to form the recessed interface comprises:

performing a wet etch to form a {111} plane in a {111} crystal plane of the substrate.

9. The method of claim 8, wherein the wet etch forms {010} planes in {010} crystallographic planes of the substrate.

10. The method of claim 8, wherein the wet etching uses an etchant chemistry selected from the group consisting of potassium hydroxide (KOH), sodium hydroxide (NaOH), ammonia-based etchants, or amine-based etchants.

11. A method of forming a semiconductor device, comprising:

providing a substrate having an insulating layer thereon and a semiconductor body extending from the substrate through the insulating layer;

forming a gate electrode on a portion of the semiconductor body, thereby defining an exposed portion of the semiconductor body;

depositing gate spacers on sidewalls of the gate electrode;

etching the exposed portion of the semiconductor body to form

A first surface recessed below a top surface of the insulating layer, an

A second surface coplanar with the gate spacer;

forming an epitaxial region on the first surface and the second surface by alternately exposing the substrate to a first precursor and a second precursor, wherein alternately exposing the substrate to the first precursor and the second precursor comprises:

exposing the substrate to the first precursor so as to deposit epitaxial films on the first and second surfaces and an amorphous layer on the insulating layer and the gate spacer; and

exposing the substrate to the second precursor to remove the amorphous layer from the insulating layer and the gate spacer; and

selectively depositing a cap layer on the epitaxial region,

wherein forming an epitaxial region on the first surface and the second surface results in a void between the epitaxial region and the insulating layer; and is

Wherein the cap layer backfills the void.

12. The method of claim 11, wherein depositing the gate spacer on the sidewall of the gate electrode comprises:

depositing body spacers on the sidewalls of the exposed portion of the semiconductor body.

13. The method of claim 12, further comprising:

removing the body spacers from the sidewalls of the exposed portion of the semiconductor body prior to etching the exposed portion of the semiconductor body.

14. The method of claim 11, further comprising:

etching the second surface such that the second surface is recessed into the gate spacers.

15. The method of claim 11, wherein the first precursor comprises:

a silicon-containing compound comprising a silane;

a carbon-containing compound comprising an organosilane; and

a dopant comprising phosphorus.

16. The method of claim 15, wherein the epitaxial region comprises silicon and carbon doped with phosphorus.

17. The method of claim 11, wherein the second precursor is an etchant gas.

18. The method of claim 11, wherein the cap layer is selectively deposited on the epitaxial region by exposing the substrate to a third precursor comprising:

a silicon-containing compound comprising a silane;

a dopant comprising phosphorus; and

an etchant gas.

19. The method of claim 18, wherein the cap layer comprises silicon doped with phosphorus.

20. A semiconductor device, comprising:

a substrate, comprising:

a gate electrode formed on the channel region of the substrate, an

A recessed source interface and a recessed drain interface formed on the substrate on opposite sides of the gate electrode;

first and second spacers formed on opposing sidewalls of the gate electrode, wherein a portion of the recessed source interface extends laterally under a bottom surface of the first spacer and a portion of the recessed drain interface extends laterally under a bottom surface of the second spacer;

a source region comprising:

a first epitaxial region formed on the recessed source interface, an

A first cap layer formed on the first epitaxial region, wherein a portion of the first cap layer is formed between the first epitaxial region and the bottom surface of the first spacer; and

a drain region comprising:

a second epitaxial region formed on the recessed drain interface, an

A second cap layer formed on the second epitaxial region, wherein a portion of the second cap layer is formed between the second epitaxial region and the bottom surface of the second spacer.

21. The semiconductor device of claim 20, wherein the first and second epitaxial regions each comprise silicon and carbon doped with phosphorus.

22. The semiconductor device of claim 21 wherein the first and second epitaxial regions each comprise silicon having

A carbon concentration in the range of 0.5 atomic% to 4 atomic%, and

9×10¹⁹cm^-3to 3 × 10²¹cm^-3A phosphorus concentration within the range of (1).

23. The semiconductor device of claim 21, wherein the first cap layer and the second cap layer each comprise silicon doped with phosphorus.

24. The semiconductor device of claim 23, wherein the first cap layer and the second cap layer each comprise a phosphorus concentration in a range of 8 × 10¹⁹cm^-3To 3 × 10²¹cm^-3Of silicon (ii) is described.

25. A semiconductor device, comprising:

a substrate having an insulating layer formed thereon;

a semiconductor body extending from the substrate through the insulating layer, wherein the semiconductor body comprises:

a top surface, a front surface and a back surface exposed above the insulating layer,

a first sidewall extending from the top surface to a source interface, an

A second sidewall opposite the first sidewall, the second sidewall extending from the top surface to a drain interface;

a gate electrode formed on the top surface, the front surface and the back surface of the semiconductor body;

first and second spacers formed on opposite sidewalls of the gate electrode;

a source region comprising:

a first epitaxial region formed on the first sidewall and the source interface, an

A first cap layer formed on the first epitaxial region, wherein a portion of the first cap layer is formed between the first epitaxial region and the insulating layer; and

a drain region comprising:

a second epitaxial region formed on the second sidewall and the drain interface, an

A second cap layer formed on the second epitaxial region, wherein a portion of the second cap layer is formed between the second epitaxial region and the insulating layer.

26. The semiconductor device of claim 25, wherein the first sidewall is substantially coplanar with the first spacer and the second sidewall is coplanar with the second spacer.

27. The semiconductor device of claim 25, wherein the first sidewall is recessed into the first spacer and the second sidewall is recessed into the second spacer.

28. The semiconductor device of claim 25, wherein the source interface and the drain interface are recessed below the top surface of the insulating layer.

29. The semiconductor device of claim 25, wherein the first and second epitaxial regions each comprise silicon and carbon doped with phosphorus.

30. The semiconductor device of claim 29 wherein the first and second epitaxial regions each comprise silicon having

A carbon concentration in the range of 0.5 atomic% to 4 atomic%, and

9×10¹⁹cm^-3to 3 × 10²¹cm^-3A phosphorus concentration within the range of (1).

31. The semiconductor device of claim 25, wherein the first cap layer and the second cap layer each comprise silicon doped with phosphorus.

32. The semiconductor device of claim 31, wherein the first cap layer and the second cap layer each comprise a phosphorus concentration in a range of 8 × 10¹⁹cm^-3To 3 × 10²¹cm^-3Of silicon (ii) is described.