HK1175886B - Recessed and embedded die coreless package - Google Patents

Description

Recessed embedded die coreless package

Background

With the development of semiconductor technology for higher processor performance, the development of package architectures may include package-on-package (PoP) architectures and other such assemblies. As the design of package structures becomes more complex, increased assembly costs typically result. Therefore, there is a need to significantly reduce the packaging and assembly costs of advanced packaging structures.

Drawings

While the specification concludes with claims particularly pointing out and distinctly claiming certain embodiments of the present invention, the advantages of this invention may be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:

figures 1a-1m illustrate a method for forming a structure according to one embodiment of the present invention.

Fig. 2 shows a system according to an embodiment of the invention.

Detailed Description

In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in connection with one embodiment may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views.

Methods of forming and utilizing microelectronic structures, such as package structures, and associated structures are described. Those methods may include: forming a cavity in the plating material to accommodate the die; attaching a die in the cavity; forming a dielectric material adjacent to the die; forming a via in a dielectric material adjacent to the die; forming a PoP island in the via; forming an interconnect in the via; the plating material is then removed to expose the PoP islands and the die. The method of the present invention enables the fabrication of package-on-package architectures, such as PoP assemblies, which include partially recessed and/or fully embedded dies, or any other type of Ball Grid Array (BGA) package.

Fig. 1a-1m illustrate an embodiment of a method for forming a microelectronic structure, such as a package structure. Fig. 1a shows a material 100. In one embodiment, material 100 may comprise a plating material, such as, but not limited to, a copper foil plating material. In some embodiments, any suitable plating material may be used, depending on the particular application. In fig. 1b, a cavity 102 may be formed in the material 100. In some embodiments, the cavity 102 may be formed using any suitable etching process, such as those known in the art. In one embodiment, the cavity 102 may be formed such that the cavity 102 may accommodate a die, such as a microelectronic die. The cavity 102 may include a bottom portion 101, an angled portion 103, and a top portion 105. In one embodiment, the bottom and top portions may be separated by a barrier layer to facilitate formation of the cavity structure, particularly for an etching process. In one embodiment (not shown), PoP island structures (described further herein) may be formed on the surface 101.

In one embodiment, the die 104 may be attached within the cavity 102 (fig. 1 c). In one embodiment, the die 104 may include a thin die 104 and may be less than about 150 microns thick. In one embodiment, die 104 may be attached to top portion 105 of cavity 101. In one embodiment, the die 104 may include at least one sidewall 106, a top side 107, and a bottom/active side 108. In some cases, the die 104 may be attached to the plating material 100 in the cavity 102 using an adhesive film and/or an attachment process. In one embodiment, an adhesive film (not shown) may be utilized as a permanent part of the final package, for example, to protect the die backside, provide a surface for marking, and/or to account for any warpage that may occur within the die 104. A dielectric material 110 may be formed on the plating material 100 adjacent to the die 104 in the cavity 102 of the plating material 100 (fig. 1 d). In one embodiment, the dielectric material 110 may be formed by, for example, a lamination process. The dielectric material 110 may be formed on the bottom portion 101 of the cavity 102, the angled portion 103 of the cavity 102, and a portion of the top portion 105 of the cavity 102 of the plating material 100 surrounding the die 104. A via 112 may be formed in a region 114 of the dielectric material 110 adjacent to the die 104 (fig. 1 e). In one embodiment, a package-on-package (PoP) island 113 may be formed within the via 112, wherein a portion of the plating material 100 may be removed to form the PoP island 113. In one embodiment, the plating material 100 and the dielectric material 110 may be removed using any suitable etching process.

In one embodiment, a PoP island structure 116 (fig. 1 f) may be formed in the PoP island region 113. The PoP island structures 116 may be formed in the PoP island regions 113 by utilizing, for example, an electroplating process, although the PoP island structures 116 may also be formed utilizing any suitable process. In one embodiment, the plating material 100 within the PoP island regions 113 may be utilized as a plating bus for forming the PoP island structures 116. In one embodiment, the plating material 100 may include copper foil that may be used as a plating bus. In some cases, the plating metallurgy may include gold, nickel, gold/nickel/palladium, and similar suitable materials, depending on the particular application. In one embodiment, wire bond pads may be plated on the PoP land 113, for example, to allow for hybrid technology stacking on the CPU die backside.

In one embodiment, vias 118 may be formed in die region 119, where die pads, such as copper die pads, may be exposed on active side 108 of die 104 (fig. 1 g). Vias 112 adjacent to the PoP island structures 116 (PoP island structures 116 in the dielectric region 114) and vias 118 in the die region 119 (fig. 1 h) may be plated with a metallic material to form PoP island structures 116 interconnect structures 117 and to form die pad interconnect structures 120. In one embodiment, the PoP island interconnect structures 117 may be electrically connected to the PoP island structures 116, and the die pad interconnect structures 120 may be electrically connected to die pads on the active side 108 of the die 104.

In one embodiment, the die pad interconnect structure 120 and the PoP interconnect structure 118 may be formed using a semi-additive process (SAP). In some embodiments, the die pad interconnect structure 120 and the PoP interconnect structure 118 may be formed in the same process, or in other embodiments, the die pad interconnect structure 120 and the PoP interconnect structure 118 may be formed in separate formation steps. A second dielectric layer 110' (fig. 1 i) may be formed on the die pad interconnect structure 120 and the PoP interconnect structure 118. A first metallization layer 121 may be formed in the second dielectric layer 110'.

Next, subsequent layers may be formed using, for example, a standard substrate SAP build-up process, wherein further dielectric layers 120 ″ and metallization layers 121' may be formed on top of each other to form a coreless substrate 125 by using a build-up process (fig. 1 j). The plating material 100 may then be removed from the die 104 and the PoP island structure 116 of the coreless substrate 125 to expose the PoP islands and the die, thereby forming a coreless package structure 126 (fig. 1 k). The coreless package structure 126 may include a corner-fill structure 127 surrounding the dielectric material 110 of the die 104, where the dielectric material 110 may surround the sidewalls 106 and the bottom 108 of the die 104, but where the dielectric material 110 is not present on the top side 107 of the die 104.

Fillet structure 127 may include a portion of dielectric 110 that is angled/raised relative to planar top portion 111 of dielectric 110 of coreless substrate 125. The geometry of the fillet structure 127 may be optimized to provide maximum reliability of the die/package, wherein the angle 128 of the fillet structure 127 may be varied to optimize reliability. In one embodiment, the angle of the fillet structure may comprise about 70 degrees or less, but may also vary depending on the application.

In one embodiment, coreless package structure 126 may include die 104 at least partially embedded in coreless substrate 125. In other embodiments, coreless package structure 126 may include die 104 substantially completely embedded in coreless substrate 125. In some embodiments, the top side 107 of the die 104 may be substantially coplanar with the top portion 111 of the dielectric 110. In another embodiment, there may be a distance 129 between the top side 107 of the die 104 and the top side 131 of the PoP island 116.

Coreless package structure 126 may include a package interconnect structure region 122 in which interconnect structures 124 (fig. 1 l) such as Ball Grid Array (BGA) balls may be attached. The PoP island structure 116 of the coreless package structure 126 may include raised plated islands 116 disposed on top of the coreless substrate 125, thereby enabling another package (e.g., a package-on-package structure) to be attached on top of the coreless package structure 126.

Fig. 1m depicts a PoP structure 130 in which a second package 132 is connected to a coreless package structure 126 by being attached to a PoP island structure 116. In one embodiment, the second package 132 may include a die 104' directly above the die 104 of the coreless package structure 126. The interconnect balls 124' of the second package 132 may be attached to the PoP island structures 116 of the coreless package structures 126.

Fig. 2 is a diagram illustrating an exemplary system 200 that is operable with a method for fabricating a microelectronic structure, such as the coreless package structure 126 of fig. 1 l. It will be appreciated that the present embodiment is but one of many possible systems in which the coreless package structure of the present invention may be used.

FIG. 2 illustrates a computer system according to one embodiment of the invention. System 200 includes processor 210, memory device 220, memory controller 230, graphics controller 240, input and output (I/O) controller 250, display 252, keyboard 254, pointing device 256, peripheral devices 258, and bus 260. Processor 210 may be a general purpose processor or an Application Specific Integrated Circuit (ASIC). I/O controller 250 may include a communication module for wired or wireless communication. Memory device 220 may be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, or a combination of these memory devices. Thus, in some embodiments, memory device 220 in system 200 need not necessarily include a DRAM device.

One or more of the components shown in system 200 may be included in one or more integrated circuit packages, such as coreless package structure 126 of fig. 11. For example, processor 210, or memory device 220, or at least a portion of I/O controller 250, or a combination of these components may be included in an integrated circuit package including at least one embodiment of the structure described in FIGS. 1a-1 m.

System 200 may include a computer (e.g., desktop, laptop, handheld, server, Web appliance, router, etc.), a wireless communication device (e.g., cellular telephone, cordless telephone, pager, personal digital assistant, etc.), a computer-related peripheral (e.g., printer, scanner, monitor, etc.), an entertainment device (e.g., television, radio, stereo, tape and compact disc player, video cassette recorder, camcorder, digital camera, MP3 (moving picture experts group, audio layer 3) player, video game, watch, etc.), and the like.

The benefits of the present invention enable a new package architecture that can meet the design requirements of future mobile/handheld system-on-chip (SoC) processors at a cost of about half that of current package architectures. Embodiments provide a method of embedding a die in a substrate, thereby enabling the elimination of many assembly processes. Embodiments enable thin die assembly, PoP compatibility, substrate design rule scalability, package thickness reduction, and package/assembly cost reduction. In addition, the substrate is no longer limited to strip fabrication capability, thereby enabling full panel processing, which also reduces cost.

Although the above description specifies certain steps and materials that may be used in the method of the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, all such modifications, changes, substitutions and additions are intended to fall within the spirit and scope of the invention as defined by the appended claims. Additionally, it should be understood that various microelectronic structures, such as package structures, are well known in the art. Accordingly, the figures provided herein illustrate only portions of exemplary microelectronic devices that are part of the practice of the present invention. Thus, the present invention is not limited to the structures described herein.

Claims (11)

1. A microelectronic structure, comprising:

a partially embedded die disposed in a coreless substrate, wherein the partially embedded die includes a top side and a bottom/active side, wherein the coreless substrate includes a dielectric material having a planar top portion and having a fillet structure that is raised relative to the planar top portion, wherein the fillet structure has an inclined portion that extends from the planar top portion to a position adjacent to the top side of the partially embedded die without extending above the top side of the partially embedded die, and wherein the fillet structure is adjacent to a sidewall of the partially embedded die; and

a raised PoP island adjacent to the partially embedded die on the planar top portion of the coreless substrate,

wherein the PoP islands are capable of receiving a second substrate.

2. The microelectronic structure of claim 1, further comprising an adhesive film disposed on a top surface of the partially embedded die, and wherein the coreless substrate comprises a portion of a PoP package structure.

3. The microelectronic structure of claim 1, wherein the coreless substrate comprises a portion of a PoP package structure, and wherein interconnect structures of a second package are disposed on the PoP islands of the coreless substrate.

4. The microelectronic structure of claim 3, wherein the die of the second package is directly above the partially embedded die disposed in the coreless substrate.

5. The microelectronic structure of claim 1, wherein there is a distance between the top side of the die and the top side of the PoP island.

6. A microelectronic structure, comprising:

a die disposed in a coreless substrate, wherein at least a portion of the die is embedded in the coreless substrate, and wherein the die includes a top side and a bottom/active side, wherein the coreless substrate includes a dielectric material having a planar top portion and having a fillet structure that is raised relative to the planar top portion, wherein the fillet structure has an inclined portion that extends from the planar top portion to a position adjacent to the top side of the die without extending above the top side of the die, and wherein the fillet structure is adjacent to a sidewall of the die;

a raised PoP island on the planar top portion of the coreless substrate adjacent to the die, wherein the PoP island and the die are capable of receiving a second substrate;

a dielectric film adjacent to the bottom/active side of the die, wherein a die interconnect structure is disposed in the dielectric film and connected to a pad of the bottom/active side of the die;

a PoP interconnect structure connected to the PoP island; and

a first metal layer disposed on the PoP interconnect structure and the die interconnect structure.

7. The microelectronic structure of claim 6, wherein the PoP islands comprise a plated metal.

8. The microelectronic structure of claim 6, wherein the coreless substrate comprises a portion of a coreless package structure, wherein a second package is connected to the coreless package structure.

9. The microelectronic structure of claim 8, wherein the interconnect structure of the second package is connected to the PoP islands of the coreless package structure.

10. The microelectronic structure of claim 6, wherein the die has a thickness of less than 150 microns.

11. The microelectronic structure of claim 6, further comprising a system, the system comprising:

a bus communicatively coupled to the microelectronic structure; and

a DRAM communicatively coupled to the bus.