HK1173556B - A method of forming a metal grid contact and dielectric pattern onto a solar cell layer requiring conductive contact - Google Patents

Description

Method of forming metal grid contact pattern and dielectric pattern onto solar cell layer requiring conductive contact

Information of related applications

This application claims the benefit of U.S. provisional patent application serial No.61/379,810, filed on 3/9/2010, which is incorporated herein by reference in its entirety.

The present application also relates to a commonly assigned U.S. provisional application No. 61/171,194 entitled "High-efficiency solar cell structures and methods of manufacture" filed earlier on 21/4/2009; and International patent application No. PCT/US10/31869, entitled "High-efficiency solarcell Structure and methods of manufacture", filed on 21/4/2010, commonly assigned. Each of these applications is also incorporated by reference herein in its entirety. All aspects of the invention may be used in combination with the disclosure of the above-mentioned application.

Technical Field

The present invention relates to a solar cell and a module thereof. More particularly, the present invention relates to improved solar cell structures and manufacturing methods for increasing cell efficiency.

Background

Solar cells provide a wide range of benefits to society by converting essentially unlimited solar energy into usable electrical energy. As their use increases, certain economic factors become important, such as mass production and efficiency (or efficiency).

Solar radiation is assumed to preferentially illuminate one surface of the solar cell, commonly referred to as the front side. Efficient absorption of photons within a silicon substrate is important in order to achieve high energy conversion efficiency of incident photons into electrical energy. This can be achieved by a good surface texture and an antireflective coating on the front side, and low parasitic absorption within all layers except the substrate itself. Furthermore, it is important to provide a reflective layer on the back side of the cell to improve internal light trapping. Another important parameter for the high efficiency of solar cells is the shading of the front surface by metal electrodes. In summary, an optimized metal grid requires a loss tradeoff between the shielding of the metal structure and the resistance of the metal structure. This optimization of the solar cell efficiency requires a grid with very narrow fingers and short distances between these fingers, which should have a high electrical conductivity. One practical way of forming such a structure is the subject of the present invention.

The production of solar cells may use, for example, screen printing techniques to print electrodes on the front surface. Silver paste can be printed on the silicon nitride anti-reflective coating and sintered through the coating in a high temperature process. This is a short process; however, due to the use of several non-metallic components in the printing paste, some of the intrinsic properties of this approach include relatively wide line widths in excess of 50 μm (typically about 100 μm) and rather low line conductivity of the metal grid. Moreover, the sintering process causes the metal paste components to penetrate through the antireflective layer into the substrate (where increased recombination occurs in the substrate). This is true for both cases where for front junction devices the pn junction can be severely damaged due to unfavorable penetration of the space charge region, and for back junction devices front surface recombination can increase and significantly reduce the collection efficiency of the back junction emitter.

Disclosure of Invention

The shortcomings of the prior art are overcome and additional advantages are provided by the present invention which, in one aspect, relates to a method of forming a metal grid contact and a dielectric pattern onto a layer requiring a conductive contact, comprising forming a metal film on the layer; forming an etch-resistant pattern on the metal film; etching the metal film, thereby leaving the etch resist pattern and the metal grid contact pattern under the etch resist pattern intact, while exposing other portions of the layer; forming a dielectric layer on the etch-resistant pattern and the exposed portion of the layer; and removing the etch-resistant pattern and the dielectric portion over the etch-resistant pattern, leaving a substantially coplanar metal grid contact and dielectric pattern on the layer requiring the conductive contact.

The layer requiring conductive contacts may comprise a portion of an optoelectronic device. The metal grid contact pattern may form the front and/or back contact electrodes of the solar cell; and the dielectric layer may be an optical anti-reflective layer or an optical reflective layer of the solar cell. The layer requiring conductive contacts may be a multifunctional layer that provides its own passivation such that substantially no passivation is required in the dielectric layer.

In one aspect, the etch-resistant pattern can be formed by direct writing and in-situ curing the etch-resistant pattern using, for example, ink-jet or screen printing.

A laser may be used to selectively open holes in the dielectric layer, thereby facilitating said removal of the etch-resistant pattern; in situ heat treatment of the etch-resistant pattern and the dielectric layer may be used to form holes, cracks, and/or other defects, thereby facilitating said removal of the etch-resistant pattern; the etch-resistant pattern may be "swelled" by exposure to a liquid absorbed into the etch-resistant pattern material to effect an increase in volume and area of the pattern material, thereby acting to fracture the opening through the dielectric layer to facilitate said removal of the etch-resistant pattern; and/or volume expansion of the etch resist pattern material, is used in conjunction with subsequent stripping of the mask material and dielectric layer.

Moreover, additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.

Drawings

The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIGS. 1A-1B are partial cross-sectional views of an exemplary solar cell during fabrication according to various aspects of the present invention;

2A-2D are partial cross-sectional views of an exemplary solar cell during fabrication according to various aspects of the present invention;

3A-3D are partial cross-sectional views of an exemplary solar cell during fabrication according to various aspects of the present invention;

4A-4J are partial cross-sectional views of an exemplary solar cell during fabrication, in accordance with various aspects of the present invention;

FIGS. 5A-5E are partial cross-sectional views of an exemplary solar cell during fabrication according to various aspects of the present invention; and

figure 6 is a partial cross-sectional view of a solar cell having a multifunctional layer requiring electrical contacts according to the present invention.

Detailed Description

The invention can be applied to a wide variety of solar cell structures. The following description illustrates exemplary embodiments of the invention (wherein like reference numerals are used to identify similar elements). The invention is not limited to these described embodiments.

In accordance with one embodiment of the present aspect, an improved structure for a solar cell 10, and method for front side and/or back side metallization of a solar cell 10, is disclosed in fig. 1A-B. The resulting final line width of the metallization line 14 may be on the order of 50 μm or less, and the total metal surface coverage of the front side may be about 7% or less.

Fig. 1A shows an optimized front side contact structure for a high efficiency solar cell 10. A dielectric coating, such as an anti-reflective coating 12, covers the underlying substrate 11 over the entire surface except under the metal contacts 14 (e.g., wires or other suitable structures). Similar structures can also be used as backside contacts for high efficiency solar cells. In this case, the coating 12 may function as a reflective layer.

As shown in fig. 1B, the metal contact 14 can serve as a seed layer to initiate electroplating of the electrode to a desired thickness. The thin metal contacts 14 can then be plated 14' to a desired thickness to achieve higher conductivity. Electroplating for accumulating or increasing the line conductivity, which provides a metal layer thickness on the order of up to about 100-300nm, may be sufficient to provide sufficient uniformity.

With reference to the partial cross-sections of fig. 2A-2D, obtaining such contacts on the battery 20 can be achieved using a lift-off process (lift-off process) in which a photoresist 23 is deposited on the substrate 21. The substrate can be covered by a dielectric coating such as an anti-reflective coating (ARC)22, as shown in fig. 2A. The resist can be partially exposed to uv light and developed and result in well defined resist structures in the micrometer range. This resist structure may allow, for example, ARC22 to be selectively etched by an acid, resulting in the structure shown in figure 2B. A thin metal film 24 may be deposited onto the resist and substrate of such a structure, which metal film 24 may be a stack of different materials. The metal deposition can be done by, for example, evaporation or sputtering. In a subsequent stripping step, the resist may be exposed to a solvent or caustic (or corrosive) solution, which etches the resist 23 through the open wings 26 and dissolves the resist 23, as shown in fig. 2C. Thus, the metal film is peeled off from the substrate, and the fine contact 24' can be obtained on the substrate as shown in fig. 2D.

This exemplary sequence (fig. 2A-D) shows a case of a resist with a negative flank, where the deposited metal layer is discontinuous and the solution can immediately strip off the resist 23 and thus the part of the metal layer 24 above the resist, leaving the line contact 24'.

To avoid the high cost and process complexity of lithographically defining the resist, and according to the present invention, relatively inexpensive techniques, such as ink-jet or screen printing, can be used for the deposition of the structured resist. However, non-ideal structures with vertical or defining sloped side edges can be obtained as shown in fig. 3A (which shows a cross-section of cell 30 with substrate 31, ARC32 and resist 33) and 3C (which shows a cross-section of cell 30 'with substrate 31', ARC32 'and resist 33'). This can produce a continuous metal film (34, 34 ', respectively) and resist removal cannot begin uniformly across the substrate from the flanks 36 and 36', as shown in fig. 3B and 3D, respectively. Defects, such as cracks, etc., may be required on the metal film to allow etching of the resist. This can significantly increase the time required for the stripping process and can even result in etching of the metal film when a caustic solution is used.

Other methods can also be used to form breaks in the metal layer at the resist steps to allow the solution to remove the resist. For example, processes using multiple layers of resist of different properties can produce flanks of negative slope, thus preventing the metal layer from covering the entire resist step. A heat treatment of the resist can be used which can cause cracks in the resist and cause the layers to be peeled off. Ultrasound techniques may also be used. But these methods can produce mechanical tearing of the metal layer at the flap. This approach can be difficult to control and places additional stress on the substrate and metallization, especially since 95% of the metal needs to be stripped for a typical 5% surface area contact area.

In addition to cost, for 5% metal coverage, 95% of the area must be covered with resist and then stripped, resulting in the process being prone to defects. The stripped material is metallic, relatively thick (e.g., hundreds of nanometers thick for good current distribution for subsequent electroplating), and ductile.

According to the present invention, metallization of fine contact (e.g., line) patterns for solar cells is provided using, for example, a lift-off process of an optical coating, such as an anti-reflective coating (ARC) or a Reflective Coating (RC). This method overcomes the above-mentioned limitation in the general lift-off process in which the metal layer is lifted off. Those problems lead to high cost of consumer products because the remaining 95% of the area needs to be covered by resist for 5% of the metallized portion. Photolithography can be a very complex and costly process. Ink jet or screen printing makes it extremely difficult to achieve minimum line widths narrower than 50 μm. Moreover, the side flaps are not shaped to enable advantageous peeling.

However, according to the present invention, the line resolution (linewidth) for metallization is not a function of the pitch, but rather of the amount of resist deposition, i.e. it is possible to use ink jet technology or dispensing methods that can print multiple lines up to 20 μm wide. The metal etch can be adjusted to create an undercut in the metal layer below the resist. This prevents the continued deposition of ARC (or RC) at the resist edges and provides a location for resist erosion. The laser opening in the ARC layer above the resist can also be used to form additional locations where the removal solution reaches the resist. The absence of metal undercuts results in a tight seal between the deposited ARC and the metal seed layer. It would be helpful if the electroplated metallization lines were composed of a metal that could contaminate the underlying substrate, such as copper, which could form defects in the silicon. The ARC then protects the substrate and prevents diffusion into the substrate. One advantage of the present invention is that only 5% resist coverage requires 5% contact coverage (as opposed to 95% for metal stripping). Also, the metal to be stripped is typically a thin (e.g., 50 to 100 nanometers) brittle material, rather than a ductile metal that is typically much thicker (hundreds of nanometers). In one embodiment of the invention, the removal of the resist may be performed by swelling the resist rather than dissolving it. The swelling or spreading of the resist leads to even further cracking of the ARC on top of the resist and increases the reaction speed. Uv-cured resists with a high solids content after curing are particularly well suited for this process.

Referring to the partial cross-sections of fig. 4A-J, methods according to various aspects of the present invention and the associated structures obtained, for example, for front side contact electrodes of silicon solar cells, are disclosed.

Summarizing this process generally with reference to fig. 4A-F, a metal film 44 may be deposited over an underlying substrate 41 (e.g., textured silicon) by, for example, Physical Vapor Deposition (PVD). Such a thin film metal can be, for example, nickel having a thickness of about 50 to 200 nanometers. A patterned resist 43 is then formed on the surface of the thin film metal. Such a patterned resist can be formed by inkjet printing, for example, using a commercially available print head (e.g., FujiFilm-dimatix se-128AA or konica minoltakm512M) and a commercially available inkjet resist (e.g., from sun chemical company or MacDermid company). As known to those skilled in the art, an ink jet printable resist should nominally have specific properties (e.g., viscosity, surface tension, acid resistance, curing and removal means) to enable compliance with overall process requirements (resolution, stability, etc.).

After the resist 43 is appropriately cured, the metal film not covered with the resist is etched with a suitable metal etching solution. A dielectric film 42/42' is then deposited over the entire structure. By choosing an appropriate reflectivity and thickness, such a dielectric film can form an anti-reflective coating. The resist 43 and the dielectric film 42' covering the resist are then removed. Such removal can be performed, for example, by dipping into a suitable solvent, along with ultrasonic agitation or other techniques described herein. Then, a plated metal 44' may be formed on the metal film. Thus, plated thin metal traces (less than 40 μm wide) surrounded by a dielectric antireflective coating on the front side of a silicon solar cell (such a structure is highly desirable) can be achieved by the present invention.

More specifically, and with reference to cross-section 40 of FIG. 4A, a metal contact film 44 is deposited on a substrate 41. This metal film can be a combination of one or more thin films of different metals or alloys. The term "substrate" is used broadly herein to mean any underlying layer requiring an electrically conductive connection. Thus, the above-described battery structure can include additional underlying functional layers. In fig. 4B, a resist pattern including a narrow line 43 is dispensed on the metal layer 44. The entire metal layer 44 is then etched (except for the portion covered by the resist 43). The extent of the metal etch can be controlled to form larger or smaller undercuts (e.g., fig. 4C) or no undercuts (e.g., fig. 4D).

As shown in fig. 4e.1, a dielectric coating 42 may be deposited on the surface and structure. This can create a discontinuity between the dielectric layer on the substrate 41 and the dielectric portion on the resist 42' due to the undercut of the metal etch. The resist removal mechanism 47 can erode or destroy (attack) the resist through discontinuities in the dielectric bodies (42-42'), such as undercuts formed during metal etching.

The deposited dielectric may be, for example, a spin-on-glass (SOG) coating, a hard polymer coating such as BCB (benzocyclobutene), or SU-8 photo-epoxy. More common examples of anti-reflective coatings (ARCs) include anti-reflective films having a reflectivity in the range of 1.4< n <3 (e.g., 1.7< n <2.5) and a thickness in the range of 20 nanometers to 110 nanometers (e.g., 60 nanometers to 100 nanometers). Examples include silicon nitride, silicon carbide, silicon oxide, titanium dioxide, transparent conductive oxides. Examples of Reflective Coatings (RC) include silicon oxide, other compounds with sufficient reflectivity, polymer resists, or epoxy. The dielectric portion may be deposited by, for example, Plasma Enhanced Chemical Vapor Deposition (PECVD) at a suitable deposition temperature.

In another aspect of the invention as shown in fig. 4f.1-4f.2, irradiation of a laser 48, or other similar technique, can be used to provide an opening locally in the dielectric layer 42 'because the laser 48 can form an opening in the resist 43 or locally remove the dielectric portion 42' without damaging the contact layer 44. The resist removing mechanism 47 can then erode the resist through the opening.

In another aspect of the invention as shown in fig. 4g.1-4g.2, the opening in the dielectric layer 42 'may originate from a pin hole 49 intentionally or inevitably formed in the dielectric film 42'. Alternatively, the opening in ARC layer 42 'may be formed by thermal expansion of resist 43, which cracks brittle dielectric film 42'. In any event, the resist removal mechanism 47 can then erode the resist through such pin holes, cracks, and/or similar openings.

Referring to fig. 4H, the stripping process (removal of the resist 43 and the overlying dielectric coating 42') may be performed by dissolution of the resist 43, i.e., nominally in the presence of a resist removal chemistry (e.g., a suitable resist solvent); possibly in combination with ultrasonic and/or megasonic agitation. In one embodiment of the invention, the resist is swelled by the removal chemistry. This local expansion causes cracking and a complete delamination process of the brittle dielectric 42'.

Referring to fig. 4I, after the resist is removed and the dielectric portions are stripped, the desired fine metal wires 44 are brought into contact with the substrate 41 and surrounded by the dielectric portions 42. When no or very little metal undercutting is performed during the fabrication sequence, then the resulting structure has a substantially coplanar metal grid pattern 44 surrounded by dielectric portions 42 with no or minimal gaps between the metal 44 and dielectric portions 42. This butt joint structure is significantly different from the prior art peel-off process.

Referring to fig. 4J, in a subsequent step, the metal grid pattern 44 can be thickened by the plating 44' to achieve the desired line conductivity, as described above.

Referring to fig. 5A-E, a similar process can also be performed on the back side of the solar cell, where a layer such as a Reflective Coating (RC) is necessary. Referring to cross-section 50 of fig. 5A, narrow lines of resist (or other suitable types of contacts, such as isolated regions, e.g., dots) 53 are dispensed onto a substrate 51 using the process described above (e.g., ink-jet or screen printing).

As shown in fig. 5B, a dielectric coating 52 may be deposited on the surface of the above-described composition and resist structure (e.g., RC in this example). A resist removal mechanism is then used to erode or destroy the resist through the discontinuous regions in the dielectric portion, resulting in the structure of fig. 5C.

As shown in fig. 5D, a metal contact film 54 is then deposited on the substrate 51 and creates a narrow contact line to the substrate 51 between the larger dielectric layer portions 52. Referring to fig. 5E, in a subsequent step, the metal layer 54 can be thickened by the plating layer 54' to achieve the conductivity, as described above.

The processes described above with respect to fig. 4A-F and 5A-E and the resulting structures can be performed together, even though their separate process steps (e.g., metallization, etching, etc.) can be performed simultaneously. Furthermore, either process (fig. 4A-F or 5A-E) can be used on the front or back side of the solar cell, depending on what connection/layer structure is desired. The term "substrate" is used broadly herein to mean any underlying layer requiring an electrically conductive connection. Thus, the above battery structure can include many types of additional bottom functional layers. For example, an n-type front side, an n-type wafer, a p-type back side, a multifunctional transparent conductivity, and a highly doped silicon compound can be used in combination with the present invention (or with one of the opposite polarities), such as disclosed in the above-incorporated U.S. patent application entitled "High-efficiency solar cell structures and methods of manufacturing". One such cell structure is shown in fig. 6, which is a partial cross-sectional view of a solar cell 60, the solar cell 60 having an n-type front side, an n-type wafer, a p-type back side and including a multifunctional transparent conductive highly doped silicon compound layer 61a that requires conductivity to contacts 64 a. The multifunctional layer 61a is an improvement over other technologies in that the functions of multiple layers are combined into the multifunctional layer 61 a. This layer can be electrically passivated, transparent and sufficiently conductive for vertical carrier flow to the electrodes (backside connection solar cells), the connections can be provided with a wafer 65, and/or reflection of incoming light can be reduced (e.g., anti-reflection coating). On the back side of the cell 60, the layer 61b can also provide improvements over other technologies. The layer 61b may provide the connection with the wafer 65, may have a reflective index that produces a high reflectivity for photons with wavelengths greater than 900 nanometers, and may make the vertical carrier flow from the wafer 65 to the metal electrode 64b sufficiently conductive.

Exemplary layers of the battery 60 include the following:

layer 61a may be an electrically passivated, transparent and conductive film with a reflective index of 1.4<n<3 in the range of; a thickness in a range of 20 nanometers to 110 nanometers; for a wafer of the n-type,specific resistance (specific resistance) less than 1000 ohm cm; highly doped n-doping is 1e18cm^-3<N_D<5e21cm^-3. Specific examples include:

n-type amorphous or polycrystalline silicon carbide: polycrystalline doped silicon carbide and nitrogen doped silicon carbide;

n-type amorphous or polycrystalline silicon: phosphorus-doped amorphous silicon and nitrogen-doped amorphous silicon;

n-type amorphous or polycrystalline diamond carbon: nitrogen-doped diamond carbon;

any of the above examples may include oxygen and hydrogen elements (n-type doped SiC)_xO_yH_z(ii) a n-type doped SiN_xO_yH_z)。

Layer 61b may be an electrically passivated, transparent and conductive film with a specific resistance of less than 1000 ohm-cm. Examples include:

p-type amorphous or polycrystalline silicon carbide: boron-doped silicon carbide, aluminum-doped silicon carbide, gallium-doped silicon carbide;

p-type amorphous or polycrystalline silicon: boron-doped silicon, aluminum-doped silicon, gallium-doped silicon;

p-type amorphous or polycrystalline diamond carbon: boron doped diamond carbon, aluminum doped diamond carbon.

Any of the above examples may include oxygen and hydrogen elements (p-type doped SiC)_xO_yH_z(ii) a p-type doped SiN_xO_yH_z)。

Layer 65 may be an n-type or p-type crystalline silicon wafer; the thickness is in the range w <300 μm, the base resistivity of the n-type wafer is greater than 0.5 ohm cm and less than 20 ohm cm, for the p-type wafer, greater than 0.1 ohm cm and less than 100 ohm cm.

Layer 66 may be an electrically passivated interfacial layer, less than 10 nanometers thick; there is no conductivity requirement because of the smaller thickness; there is no absorption limitation due to the small thickness. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polysilicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

Layer 67 may be an electrically passivated interfacial layer, less than 10 nanometers thick; there is no conductivity requirement because of the smaller thickness; there is no absorption limitation due to the smaller thickness. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

In accordance with the present invention, dielectric layer 62 is formed substantially coplanar with the contacts (e.g., contacts 64A and 64b) in accordance with the partial lift-off principle described above with reference to, for example, fig. 4A-J and 5A-E.

Certain advantages of the present invention are the compatibility of the "optical" layer with the resist layer when an underlying multifunctional layer is used (which does not require separate passivation).

Typically, the dielectric layer (i.e., layers 42, 52, 62 described above) also provides an electrical passivation function, which requires higher processing temperatures. However, if the underlying layer (e.g., layers 41, 51, 61a, 61b) is a multifunctional layer that is itself conductive and passivated, then separate passivation by layers 42, 52, 62 is not required. Thus, the materials 42, 52, 62 can be purely optical and not significantly passivated, enabling the use of lower processing temperatures and also providing greater processing compatibility with the resist layers described herein.

The present application relates to a commonly assigned U.S. provisional application entitled "High-efficiency solarcell structural and method of manufacture" filed earlier on 21/4/2009, application No. 61/171,194; and International patent application No. PCT/US10/31869, entitled "High-efficiency solarcell structural structures and methods of manufacture", filed on 21/4/2010, commonly assigned. Each of these applications is also incorporated by reference herein in its entirety. All aspects of the present invention may be used in combination with the disclosure of the above-mentioned application.

In addition to the solar cell examples disclosed herein, the invention extends to any type of integrated semiconductor circuit having multiple layers requiring conductive contacts.

In summary, certain aspects of the invention include the following:

a method of producing a metal grid pattern on a substrate, wherein a patterned ink or resist film applied in the substrate serves as a mask for metal etching and as a self-aligned mask for lift-off of subsequently deposited dielectrics;

a method of forming a metal grid pattern on a substrate, comprising depositing a metal film on a surface of the substrate, depositing an etch resist on top of the metal film, etching the metal film, depositing a dielectric on top of the substrate surface and on the resist, and removing the resist and the overlying dielectric;

a structure on a surface on a substrate, wherein a metal grid pattern is surrounded by a dielectric, and wherein there is no gap between the metal and the surrounding dielectric;

a method wherein a dielectric on a conductive silicon substrate is exposed only to resist strippers that preserve dielectric integrity, thereby minimizing unwanted plating across dielectric defects across the entire substrate;

a structure on a surface on a substrate, wherein a metal grid pattern is surrounded by a dielectric, and wherein there is no gap between the metal and the surrounding dielectric, resulting in an impenetrable seal between the dielectric and the metal grid pattern;

a structure in which a non-penetrable seal between a dielectric on a substrate and a front grid metal prevents migration of a contaminant metal into the substrate; and/or

A structure and method in which a highly conductive metal (such as copper) that is also contaminated is included in the front grid metal stack but is permanently isolated from migration into the underlying silicon substrate.

In any of the above aspects, the substrate may be an optoelectronic device; the metal grid pattern may form the front and/or back contact electrodes of the solar cell; the metal grid pattern may then be plated with metal to improve the conductivity of the metal grid; the dielectric may be an optical antireflective layer; and/or the dielectric may be an optically reflective layer.

The patterned resist can be direct-written and cured in situ without subsequent pattern mask exposure and development.

The patterned resist direct writing technique may be ink jet or screen printing.

A laser may be used to selectively open holes in the dielectric to facilitate erosion or destruction of the resist by the resist removal chemistry.

In situ heat treatment of the patterned resist and overlying dielectric may serve to form holes, cracks or other defects and thereby facilitate erosion of the resist by resist removal chemicals, such as by suitable resist solvents, possibly in combination with ultrasonic and/or megasonic agitation.

The patterned resist may "swell" by exposure to liquid absorbed into the material of the patterned resist, effecting an increase in the volume and area of the mask material, thereby acting to fracture the openings through the brittle dielectric coating.

The dielectric coating may be removed in a predefined pattern by volume expansion of the mask material and subsequent peeling of the mask material, along with the dielectric coating (which encapsulates the mask material).

The underlying substrate can be any type of layer that requires conductive connection, including multi-functional layers.

Although preferred embodiments have been depicted and described in detail herein, it will be apparent to those skilled in the relevant art that various modifications, additions, substitutions and the like can be made without departing from the spirit of the invention and these are therefore considered to be within the scope of the invention as defined in the following claims.

Claims (20)

1. A method of forming a metal grid contact pattern and a dielectric pattern onto a solar cell layer requiring conductive contacts, comprising:

forming a metal film on the solar cell layer;

forming an etch-resistant pattern on the metal film;

etching the metal film, thereby leaving the etch resist pattern and the metal grid contact pattern under the etch resist pattern intact while covering the first portion of the solar cell layer and exposing the second portion of the solar cell layer;

forming a dielectric layer on the etch resist pattern and the exposed second portion of the solar cell layer, while the dielectric layer on the exposed second portion of the solar cell layer constitutes a dielectric pattern; and

the etch-resistant pattern and the dielectric layer on the etch-resistant pattern are removed, leaving a coplanar metal grid contact pattern and dielectric pattern on the solar cell layer where conductive contacts are desired.

2. The method of claim 1, wherein the metal grid contact pattern forms front and/or back contact electrodes of the solar cell.

3. The method according to claim 2, wherein the dielectric layer is an optical anti-reflective layer or an optical reflective layer of the solar cell.

4. A method according to claim 3, wherein the solar cell layer requiring conductive contacts is an electrical passivation layer.

5. The method of claim 1, further comprising:

direct writing and curing the etch resist pattern in situ.

6. The method of claim 5, wherein said direct writing comprises ink-jetting or screen printing.

7. The method of claim 1, wherein said removing step comprises using a laser to selectively open holes in the dielectric layer to facilitate said removing of the etch-resistant pattern.

8. The method of claim 1, further comprising using an in-situ thermal treatment of the etch-resistant pattern and the dielectric layer to form defects to facilitate said removing of the etch-resistant pattern.

9. The method of claim 1, wherein the etch-resistant pattern is expanded by exposure to a liquid absorbed into the etch-resistant pattern material, thereby effecting an increase in volume and area of the etch-resistant pattern material, thereby acting to fracture the opening through the dielectric layer to facilitate said removal of the etch-resistant pattern.

10. The method of claim 1, wherein the removing step comprises a volume expansion of the etch-resistant pattern material and comprises a subsequent lift-off of the etch-resistant pattern along with the dielectric layer.

11. A method of forming a metal grid contact pattern and a dielectric pattern onto a layer requiring conductive contacts, comprising:

forming an etch-resistant pattern on a first portion of the layer requiring a conductive contact, the step of forming the etch-resistant pattern simultaneously leaving a second portion of the layer exposed;

forming a dielectric layer on the etch-resistant pattern and the exposed second portion of the layer requiring a conductive contact;

removing the etch-resistant pattern and the dielectric layer over the etch-resistant pattern, leaving a dielectric pattern on the layer requiring conductive contacts, wherein the dielectric pattern with coplanar gaps corresponds to the etch-resistant pattern; and

disposing a metal contact film on the layer and the dielectric pattern, the metal contact film filling the coplanar gaps with metal, leaving a coplanar metal grid contact pattern and dielectric pattern on the layer requiring conductive contact.

12. The method of claim 11, wherein the metal grid contact pattern forms a front and/or back contact electrode of the solar cell.

13. The method according to claim 12, wherein the dielectric layer is an optical anti-reflective layer or an optical reflective layer of the solar cell.

14. The method of claim 13, wherein said layer requiring conductive contact is an electrically passivation layer.

15. The method of claim 11, further comprising:

direct writing and curing the etch resist pattern in situ.

16. The method of claim 15, wherein said direct writing comprises ink-jetting or screen printing.

17. A method of forming a metal grid contact pattern and a dielectric pattern onto a solar cell layer requiring conductive contacts, wherein an applied etch resist pattern serves as a mask for metal etching and as a self-aligned mask for stripping subsequently deposited dielectrics, the method comprising: depositing a metal film on the solar cell layer, depositing an etch-resistant pattern on the metal film, etching the metal film according to the etch-resistant pattern, depositing a dielectric on top of the solar cell layer and on the etch-resistant pattern, and removing the etch-resistant pattern and the dielectric overlying the etch-resistant pattern, thus leaving a coplanar metal grid contact pattern and dielectric pattern on the solar cell layer requiring conductive contacts.

18. A solar cell formed according to the method of claim 17.

19. A solar cell formed according to the method of claim 11.

20. A solar cell formed according to the method of claim 1.