HK1172765A - Suspending column addressing in image sensors - Google Patents

Abstract

The subject application relates to suspending column addressing in image sensors. An image sensor includes a two-dimensional array of pixels having multiple column outputs and an output circuit connected to each column output. Each output circuit is configured to operate concurrent sample and read received by a column decoder that is electrically connected to each output circuit. The timing generator suspends the output of the column address sequence during a sample operation and resumes the output of the column address sequence at the end of the sample operation.

Description

Suspending column addressing in an image sensor

Cross reference to related applications

This application relates to U.S. patent application serial No. 12/952,466 filed on 11/23/2010.

Technical Field

This application relates generally to electronic image sensors for use in digital cameras and other image capture devices, and more particularly to sampling and reading techniques for use with electronic image sensors.

Background

A typical solid-state electronic image sensor includes a number of light-sensitive picture elements ("pixels") arranged in a two-dimensional array. These pixels are typically formed in a semiconductor material and have the property of accumulating charge resulting from electron-hole pairs formed by photons entering the pixel. In a Charge Coupled Device (CCD) image sensor, accumulated charge is read out of the image sensor by shifting the charge out of the array. Alternatively, in an Active Pixel Sensor (APS), the charge can be converted to a voltage by a circuit located within the array proximate to the pixel and the resulting voltage can be sampled and read in a scanning manner. APS image sensors are also referred to as Complementary Metal Oxide Semiconductor (CMOS) image sensors.

According to conventional practice, sampling and readout of pixel signals in a CMOS image sensor typically involves sampling all of the pixel signals in a given row into column circuits, and then reading out the entire sampled row of pixel signals from the column circuits in a sequential manner. This sampling and readout operation is performed row by row until the entire pixel array is read out. In conventional practice, the sampling operation and the readout operation do not overlap in time, and the sampling operation represents a substantial fraction of the total time required to read pixel signals from the array.

U.S. patent application publication No. 2009/0195681, entitled "Sampling and reading of an Image Sensor Having an imaging Color Filter Array Pattern," which is incorporated herein by reference, discloses Sampling and Readout of a CMOS Image Sensor in which Sampling of a pixel signal occurs simultaneously with Readout of a previously sampled pixel. In this scheme, two column circuits are provided for each column signal output from the pixel array. The pixel signal from a selected pixel is sampled by one of the column circuits while the previously sampled pixel signal in the other column circuit is read out. By overlapping the sampling operation and the readout operation in this manner, the amount of time for the sampling operation is eliminated. This reduces the total time required to read pixel signals from the array and increases the frame readout rate of the image sensor.

The sampling operation may sample system noise in addition to the pixel signal. Since the sampling operations described above occur simultaneously for an entire row of pixel signals, the captured system noise may be correlated with the entire sampled row of pixel signals or a portion of the sampled row of pixel signals. In an imaging system as described above, this row dependent noise produces visual artifacts in the captured image that cannot be exploited. In conventional non-overlapping sampling and readout of CMOS image sensors, system noise may be reduced by turning off the noise generator (particularly the clock signals to portions of the readout circuitry) during the sampling time. However, in the overlapping sampling and sensing operations outlined above, turning off the clock signal of the sensing circuit during sampling is not an option because the sensing operation occurs simultaneously with the sampling operation. Thus, while the simultaneous sampling and readout technique provides an improvement in readout time, it also increases sampling system noise and incurs a susceptibility to row-related visual artifacts that cannot be exploited.

Disclosure of Invention

Briefly, and in general terms, according to one aspect of this disclosure, this disclosure provides an image sensor including a two-dimensional array of pixels having a plurality of column outputs and an output circuit connected to each column output. Each output circuit is configured to operate simultaneous sample and read operations. The timing generator outputs a column address sequence received by a column decoder electrically connected to each output circuit. The timing generator pauses the column address sequence during a sampling operation and resumes the column address sequence at the end of the sampling operation.

Another aspect of the invention provides a method for reading out an image from an image sensor. The image sensor includes a two-dimensional array of pixels having a plurality of column outputs and an output circuit connected to each column output, where each output circuit is configured to operate simultaneous sample and read operations. The method begins by initiating a simultaneous sample and read operation in each output circuit. During a first sampling operation (e.g., a sampling operation on a pixel RESET signal), the column address sequence is halted. When the first sampling operation is completed, the column address sequence is restarted. During a second sampling operation, such as a sampling operation on the pixel SIGNAL, the column address sequence is again paused. When the second sampling operation is completed, the column address sequence is restarted. The suspension of the column address sequence may be repeated until all of the signals have been sampled from the pixel array and read out.

In both aspects of the invention, pixel data output from each output circuit may be stored while the sequence of column addresses is paused. The storage of the pixel data selectively delays the output of the pixel data to affect an uninterrupted output data stream of the pixel data.

Advantageous effects

The image sensor and the image capturing method according to the present invention are advantageous for reducing the time required to capture an image while reducing noise in the captured image. These image sensors and methods have a wide range of applications and many types of image capture devices can effectively use these sensors and methods.

Drawings

Embodiments of the invention are best understood with reference to the following drawings. The elements of the drawings are not necessarily to scale relative to each other.

FIG. 1 is a simplified block diagram of an image capture device in an embodiment in accordance with the invention;

FIG. 2 is a block diagram of a top view of a CMOS image sensor in an embodiment in accordance with the invention;

FIG. 3 is a more detailed diagram of the pixel array 202 shown in FIG. 2;

fig. 4 is a block diagram of the AFE circuit 212 shown in fig. 2;

FIG. 5 is a circuit diagram of a portion of the sample and sense output circuit 210 shown in FIG. 2;

FIG. 6 depicts an exemplary timing diagram for a non-simultaneous sample and read operation of the sample and sense out output circuit 210 shown in FIG. 2;

FIG. 7 depicts an exemplary timing diagram for a simultaneous sample and read operation of the column output circuit 210 shown in FIG. 2;

FIG. 8 is a flow chart of a method for suspending column readout in an embodiment in accordance with the invention;

FIG. 9 depicts an exemplary timing diagram of the method shown in FIG. 8;

FIG. 10 depicts a block diagram of circuitry to keep the intermittent data stream from FIG. 9 on hold using a digital buffer; and is

FIG. 11 depicts an exemplary timing diagram for the circuit shown in FIG. 10.

Detailed Description

Throughout the specification and claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meaning of "a", "an", and "the" includes plural references, and the meaning of "in. The term "couple" means either a direct electrical connection between the items coupled or an indirect connection through one or more passive or active intermediary devices. The term "circuit" means a single component or a plurality of components (active or passive) connected together to provide a desired function. The term "signal" means at least one current, voltage or data signal.

In addition, directional terminology, such as "on.. upper" (on), "over.. upper" (over), "top" (top), "bottom" (bottom), etc., is used with reference to the orientation of the figure being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the use of directional terminology is for purposes of illustration only and is in no way limiting.

Referring to the drawings, like numbers indicate like parts throughout the views.

FIG. 1 is a simplified block diagram of an image capture device in an embodiment in accordance with the invention. In fig. 1, the image capturing apparatus 100 is implemented as a digital camera. Those skilled in the art will recognize that a digital camera is but one example of an image capture device that may utilize an image sensor incorporating the present invention. Other types of image capture devices, such as, for example, cellular telephone cameras, scanners, and digital video cameras, may be used with the present invention.

In the digital camera 100, light 102 from a subject scene is input to an imaging stage 104. The imaging stage 104 may include conventional elements such as lenses, neutral density filters, iris and shutters. The light 102 is focused by an imaging stage 104 to form an image on an image sensor 106. The image sensor 106 captures one or more images by converting incident light into electrical signals. The digital camera 100 further includes a processor 108, memory 110, a display 112, and one or more additional input/output (I/O) elements 114. Although shown as separate elements in the embodiment of fig. 1, imaging stage 104 may be integrated with image sensor 106 and possibly one or more additional elements of digital camera 100 to form a camera module. For example, in an embodiment in accordance with the invention, the processor or memory may be integrated with the image sensor 106 in a camera module.

For example, the processor 108 may be implemented as a microprocessor, Central Processing Unit (CPU), Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), or other processing device or a combination of multiple such devices. The various elements of the imaging stage 104 and the image sensor 106 are controlled by timing signals or other signals supplied from the processor 108.

The memory 110 may be configured as any type of memory such as, for example, Random Access Memory (RAM), Read Only Memory (ROM), flash memory, disk-based memory, removable memory, or other types of storage elements in any combination. The intended image captured by the image sensor 106 may be stored by the processor 108 in the memory 110 and presented on the display 112. Display 112 is typically an active matrix color Liquid Crystal Display (LCD), although other types of displays may be used. For example, the additional I/O elements 114 may include various on-screen control devices, buttons or other user interfaces, network interfaces, or memory card interfaces.

It should be understood that the digital camera shown in fig. 1 may include additional or alternative elements of the type known to those skilled in the art. Elements not specifically shown or described herein may be selected from those known in the art. As previously stated, the present invention may be implemented in a wide variety of image capture devices. Moreover, certain aspects of the embodiments described herein may be implemented, at least in part, in the form of software executed by one or more processing elements of an image capture device. This software may be implemented in a straightforward manner given the teachings provided herein, as will be appreciated by those skilled in the art.

Referring now to FIG. 2, a block diagram of a top view of the image sensor 106 in an embodiment in accordance with the invention is shown. Image sensor 106 includes a number of pixels 200, which are typically arranged in a number of rows and a number of columns to form a pixel array 202. Image sensor 106 further includes a column decoder 204, a row decoder 206, digital logic 208, a plurality of sample and readout output circuits 210, and Analog Front End (AFE) circuits 212. The row decoder 206 provides control signals to the rows of pixels 200 in the pixel array 202. Some of these control signals are used to read out signals from individual rows of pixels. Other control signals are used to reset individual rows of pixels to known potentials.

Digital logic 208 includes control register 214, timing generator 216, Analog Front End (AFE) clock controller 218, Analog Front End (AFE) interface 220, and digital buffer 222. In an embodiment in accordance with the invention, control register 214 stores a number of clock cycles that occur before the column addressing signals are discontinued. Preferably, the column address signal is discontinued near the end of the sampling operation. If the addressing signal ceases too close to the end of the sampling period, there may still be noise from the timing/addressing that will be shown as image artifacts. If the addressing signal is terminated too quickly, performance will be degraded. The timing when the addressing signals are disabled is determined in accordance with the minimum length of the said disable effective to reduce or eliminate noise.

Timing generator 216 generates timing and control signals required to operate image sensor 106, including address signals to column decoder 204 and row decoder 206 that control the output of column and row address signals. The AFE clock controller 218 enables and disables (i.e., pauses) the AFE clock signal input to the AFE circuitry 212. The AFE clock controller receives an enable signal from the timing generator and when enabled it generates an AFE clock signal. In an embodiment in accordance with the invention, the timing generator counts clock pulses and generates an enable signal (used by the AFE clock controller) to halt the AFE clock signal. The AFE interface 220 receives data output from the AFE circuitry 212 and the digital buffer 222 stores data output from the AFE circuitry 212 to generate an uninterrupted data stream output from the image sensor.

Each column of pixels in the pixel array 202 is electrically connected to a sampling and readout output circuit 210. The sampling and readout output circuit 210 samples and holds analog signals output from the pixel columns. The column decoder 204 sequentially addresses the sample and sense output circuits 210 to sense the sampled analog signals. Each analog signal output from the sampling and readout output circuit 210 is amplified, conditioned, and converted into a digital signal by the AFE circuit 212.

Column decoder 204 and row decoder 206 have several alternative implementations that are well known to those skilled in the art. For example, the column decoder 204 may be a one-out-of-many decoder that accepts a digital column address in a binary code, Gray (Gray) code, or some other code and provides an output that selects a particular sample and sense output circuit based on the column address. Alternatively, the column decoder 204 may be a shift register that sequentially selects the sample and sense output circuits. Similar options are available for row decoder 206.

Furthermore, the sequence of reading the sampled pixel signals from the sampling and readout output circuits need not follow a strict order or numerical sequence, but may include skipping one or more of the sampling and readout output circuits, reading different blocks of the sampling and readout output circuits in different sequence orders, and reading the sampling and readout output circuits in a pseudo-random sequence. Similar options apply to the row control signals provided by the row decoder 206. All these options and others known to those skilled in the art are within the scope of the present invention, and the terms column decoder and row decoder do not limit any method and are broadly applicable to all methods for selecting columns and rows, respectively. In addition, all sequences of selecting sampling and readout output circuits for reading and all sequences of controlling row-based operations are within the scope of the present invention.

In an embodiment in accordance with the invention, the image sensor 106 is implemented as an x-y addressable image sensor formed on a single monolithic semiconductor die. In another embodiment in accordance with the invention, image sensor 106 is implemented as an x-y addressable image sensor having components or circuits formed on two or more stacked semiconductor dies. CMOS image sensors are one example of x-y addressable image sensors.

Portions of the functional blocks of the image sensor 106 may be implemented external to the image sensor 106 in other embodiments in accordance with the invention. By way of example only, the timing generator 216 may be implemented in a Field Programmable Gate Array (FPGA). Alternatively, the digital logic 208 and the AFE circuitry 212 may be included in separate integrated circuits.

The functionality associated with sampling and readout of the pixel array 202 and processing of corresponding image data may be implemented, at least in part, in the form of software stored in memory 110 (see fig. 1) and executed by the processor 108. Portions of the sampling and readout circuitry may be configured external to image sensor 106 or formed integral with pixel array 200, for example on a common integrated circuit with the photodetectors and other elements of the pixel array. Those skilled in the art will recognize that other peripheral circuit configurations or architectures may be implemented in other embodiments in accordance with the invention.

Fig. 3 is a more detailed diagram of the pixel array 202 shown in fig. 2. The pixel array 200 includes an active area 300 having columns 302 and rows 304 of photoactive pixels 200. Photoactive pixels 200 each include one or more photodetectors (not shown) that collect and store photo-generated charge carriers in response to incident light. The light activates the pixels 200 to capture an image of a scene.

Reference area 306 includes rows of dark reference pixels and reference area 308 includes columns of dark reference pixels. Dark reference pixels are typically covered by an opaque layer or light shield to prevent light from striking the pixel. The dark reference pixels are used to measure the amount of charge generated in the image sensor 106 in the absence of light. In embodiments in accordance with the invention, dark reference pixels can be constructed with or without photodetectors.

In an embodiment in accordance with the invention, the signals read out from the dark reference pixel rows in the reference area 306 are averaged together to provide a column-by-column dark offset reference. The dark offset reference is used to correct column fixed pattern offset (column fixed pattern noise). In an embodiment in accordance with the invention, the signals read out of the dark reference pixel columns in region 306 are averaged together to provide a row-by-row dark offset reference. The dark offset reference is used to correct for row time offset (row time noise).

Those skilled in the art will recognize that pixel array 202 may have millions to tens of millions of pixels that may be arranged in any configuration. By way of example only, rows of dark reference pixels can be located at the top and bottom of the pixel array 202. Alternatively, the photoactive pixels may be confined to a sub-array with rows and columns of dark reference pixels surrounding each edge of the sub-array. Another alternative disperses the dark reference pixels within pixel array 202 such that the dark reference pixels and the light activated pixels are intermixed.

Referring now to fig. 4, a block diagram of the AFE circuit 212 shown in fig. 2 is shown. The AFE circuitry 212 receives a differential pair of analog signals from each pixel in an embodiment in accordance with the invention. One analog SIGNAL is identified as RESET and the other SIGNAL is identified as SIGNAL. AFE circuit 212 amplifies and conditions the RESET and SIGNAL analog SIGNALs and converts the analog SIGNALs to digital SIGNALs.

The AFE circuitry 212 includes one or more signal processing blocks. In the illustrated embodiment, the AFE circuitry 212 includes an analog-to-digital converter (ADC)400 and an Analog Signal Processor (ASP) 402. In an embodiment in accordance with the invention, the ASP 402 includes two cascaded variable gain amplifiers 404, 406 connected in series, a signal summing node 408 connected to the input of the first variable gain amplifier in the string (e.g., amplifier 406), and a digital-to-analog converter (DAC)410 connected to the signal summing node. The RESET and SIGNAL SIGNALs are input into a SIGNAL summing node 408 and the output of a second variable gain amplifier (e.g., amplifier 404) is input into the ADC 400. Other embodiments of the present invention include one or more variable gain amplifiers. The DAC 410 and the signal summing node 408 are used for analog dark offset correction. The CLOCK signal AFE CLOCK is provided to the ADC 400 and the ASP 402. This clock signal synchronizes the sampling and conversion operations of the ADC 400 and ASP 402 with the sequential output of the sampling and readout output circuit 210. Although typical designs of elements of the ASP 402 include switched capacitors or other design approaches that require the use of timing signals (e.g., AFE CLOCK), alternative non-switching design approaches that do not require AFE CLOCK may be used for elements of the ASP 402.

Fig. 5 is a circuit diagram of a portion of the sampling and readout output circuit 210 shown in fig. 2. The sample and sense output circuit 210 includes a sample switch 500, a sample and hold capacitor 502, a sense (or column enable) switch 504, and a differential analog output bus 506. The differential analog output bus 506 is connected to the AFE circuit 212 shown in fig. 2.

Fig. 5 depicts an exemplary arrangement of output circuitry that permits a row of pixels to be sampled concurrently with readout of a previously sampled row of pixels. This is referred to as a simultaneous sample and read operation. Each column output (N +0_ PIXOUT, N +1_ PIXOUT,. or..) in pixel array 202 is connected to the inputs of four sampling switches 500 in a respective output circuit 210. The output of each sampling switch 500 is connected to a sample and hold capacitor 502. Each sample and hold capacitor 502 is connected to an input of a readout switch 504. The output of the readout switch 504 is connected to an output bus 506.

In the illustrated embodiment, output bus 506 includes two SIGNAL lines, one for the RESET SIGNAL and one for the SIGNAL SIGNAL. The outputs of the two sense switches in each group of four sense switches are connected to the RESET signal in output bus 506. The outputs of the other two sense switches in each group of four sense switches are connected to SIGNAL lines in output bus 506.

Each column output is selectively connected to one of four sample and hold capacitors 502 in a respective output circuit 210 via a respective sample switch 500. Two sample and hold capacitors 502 in each output circuit 210 are provided to sample and hold the reset signal from a pixel while the other two sample and hold capacitors 502 sample and hold the image signal from the pixel. The sampling switch 500, which is connected to two sample and hold capacitors 502 for the reset signal, is controlled by a Sample and Hold Reset (SHR) signal. The sampling switch 500 connected to two sample and hold capacitors 502 for the image signal is controlled by a Sample and Hold Signal (SHS).

Although internal details of the pixel array 202 are not shown in fig. 5, those skilled in the art will recognize that individual pixel readout circuits in the array may be shared by two or more pixels. For example, a physical row of pixels in the pixel array 202 may comprise pairs of pixels, with each pair sharing a common output signal. In this case, each of the signals provided on outputs (N +0_ PIXOUT, N +1_ PIXOUT,..) would represent the output of only one of each pair of pixels or the combined output of both pixels of each pair. Thus, to read out each individual pixel in a physical row, two sampling and readout operations are used; one sampling and readout operation is used for each of the two pixels in the pair that make up the row. Accordingly, references to sampling or reading a row of pixels should be understood to include full physical rows of pixels, alternating pixels from physical rows, combined pairs of pixels from physical rows, or other alternatives depending on the details of the pixel structure and readout circuitry sharing arrangement within the pixel array.

The signal held in the sample and hold capacitor 502 is read out by sequentially connecting the sample and hold capacitor 502 to the output bus 506 by means of the readout switch 504. Each output in the column decoder 204 is electrically connected to a respective sense switch 504 in each four sense switch groups via a logic gate (e.g., and gates 514, 520). The column decoder 204 decodes the column address COLADDR to selectively enable the two sense switches 504 in each group of four sense switches and selects one differential sample and hold capacitor 502 pair for sensing.

The select signal determines which sample and hold capacitors 502 are available for sampling and which sample and hold capacitors 502 are available for readout. For example, when selected low, the and gate 508 permits the SHR signal to operate the leftmost sampling switch (e.g., switch 510) in each group of four sampling switches 500 to allow the reset signal to be stored in the leftmost sample and hold capacitor (e.g., capacitor 512). And gate 514 permits the N + x _ COLEN signals (i.e., N +0_ COLEN, N +1_ COLEN,..) to select the right pair of each group of four sampling capacitors 502 for readout.

When selected high, AND gates 516 permit sampling into the third from the left side of each group of four sample and hold capacitors 502 (e.g., capacitor 518), while AND gates 520 permit the N + x _ COLEN signal to select the left pair of each group of four sample and hold capacitors 502. The and gate ensures that the sampling and readout operations are mutually exclusive with respect to the use of sampling capacitor 502.

The SHS signal operates similar to the SHR signal. For example, when selected low, the and gate 522 permits the SHS signal to operate the sampling switches 524 in each group of four sampling switches 500 to allow the image signal to be stored in the sample and hold capacitor 526. And gate 514 permits the N + x _ COLEN signal to select the right pair of each group of four sampling capacitors 502 for readout.

When selected high, AND gate 528 permits sampling into the rightmost sample and hold capacitor 502 (capacitor 530), while AND gate 520 permits the N + x _ COLEN signal to select the left pair of each group of four sample and hold capacitors 502.

Referring now to fig. 6, an exemplary timing diagram for the non-simultaneous sample and read operations of the sample and sense output circuit 210 shown in fig. 2 and 5 is shown. The select line is held low during sampling and high during readout, so only one set of sample and hold switches 500, corresponding set of sample and hold capacitors 502, and corresponding set of readout switches 504 are used. At the time of sampling (time t)₀And time t₂The time period in between), the column address COLADDR remains in the intended state X, which does not address any active columns for readout. SHR and SHS signal operation to sampleAnd holds the pixel RESET signal (time t)₀To time t₁) Followed by a SIGNAL of the pixel SIGNAL (time t)₁To time t₂). After sampling all of the RESET and SIGNAL SIGNALs in a row of pixels (time t)₂Later time period), the COLADDR begins providing sequential addresses to read out the sampled signals.

Fig. 7 depicts an exemplary timing diagram for simultaneous sample and read operations of the sample and sense out output circuit 210 shown in fig. 2 and 5. Assuming that the previous sampling operation had stored the signal in the sample and sense capacitor for readout, the COLADDR immediately begins reading out the signal from the right sample and sense capacitor pair in each group of four sample and sense capacitors 502 (see time t)₃) And SHR (time t)₃To time t₄) And SHS (time t)₄To time t₅) Sampling is to the left sampling and readout capacitor pair in each group of four sampling and readout capacitors 502. An X in COLADDR means that the addressing sequence has been completed and COLADDR is set to a value that does not address any active column for readout.

When the sampling and reading operation is at time t₆When completed, the select lines switch the function of two sampling and sense capacitor sets in each group of four sampling and sense capacitors 502. In each group of four sample and sense capacitors 502, COLADDR then begins sensing the left sample and sense capacitor pair while SHR and SHS sample into the right sample and sense capacitor pair. In the FIG. 7 embodiment, the sense activity is occurring at the critical falling edge of SHR and SHS. This increases the likelihood that the sampling capacitor can be sampled along with system noise in the desired pixel reset or signal.

Referring now to FIG. 8, shown is a flow diagram of a method for suspending column addressing in an embodiment in accordance with the invention. Initially, as shown in block 800, a simultaneous sampling and read operation is initiated. Both sampling of signals from rows of pixels and column readout of previously sampled signals begin substantially simultaneously such that sampling and column readout are performed simultaneously (e.g., time t in fig. 7)₃)。

Next, as shown in block 802, during the SHR period (in FIG. 7, the SHR period is time t)₃To time t₄) The column addressing sequence supplied to the column decoder 204 is suspended N clock cycles before the end. Value N is specified in a programmable control register, such as, for example, control register 214, or fixed by design in embodiments in accordance with the invention. For example, the value N is selected for the shortest possible abort. If N is too short, there may still be system noise captured by the sampling. If N is too long, performance will be degraded because completion of the addressing sequence will be delayed.

When the SHR cycle completes at the falling edge of the SHR signal, the supply of the column addressing sequence to the column decoder is restarted (block 804). In an embodiment of the present invention, the column address sequence is restarted where it was paused in block 802.

FIG. 9 is a timing diagram that diagrammatically shows the operations described in blocks 802 and 804. The SH signal in fig. 9 corresponds to the SHR signal or the SHs signal in fig. 7. FIG. 9 is a graph showing the time t in FIG. 7₄SHR of (a) or time t in fig. 7₅The falling edge of the SHS at (a) provides additional detail and shows an embodiment of the invention. When considered in the context of blocks 802 and 804, the SH signal should be considered an SHR signal. As shown in FIG. 9, some time before the end of the SHR sampling period (time t in FIG. 9)_sAt) pause the COLADDR as described in block 802. Shortly after the end of SHR (at time t in FIG. 9)_RAt) restart the COLADDR as described in block 804.

Next, as shown in block 806, during the SHS period (in FIG. 7, the SHS period is time t)₄To time t₅) The column addressing sequence supplied to the column decoder is suspended M clock cycles before the end. Value M is specified in a programmable control register, such as, for example, control register 214, or fixed by design in embodiments in accordance with the invention.

When the SHS cycle completes at the falling edge of the SHS signal, the supply of the column addressing sequence to the column decoder is restarted (block 808). In an embodiment of the present invention, the column address sequence is restarted where it was paused in block 806.

Like blocks 802 and 804, FIG. 9 shows the operations described in blocks 806 and 808 graphically. When considered in the context of blocks 806 and 808, the SH signal should be considered an SHs signal. As shown in FIG. 9, some time before the end of the SHS sampling period (time t in FIG. 9)_sAt) pause the COLADDR as described in block 806. Shortly after the end of SHS (at time t in fig. 9)_RAt) restart the COLADDR as described in block 808.

The suspension of the column address sequence may be repeated until all of the signals have been sampled from the pixel array and read out. As described in more detail in connection with fig. 10 and 11, the pixel data output from each output circuit may be stored while the sequence of column addresses is suspended. The storage of the pixel data selectively delays the output of the pixel data to affect an uninterrupted output data stream of the pixel data.

Fig. 9 illustrates an exemplary timing diagram for the method shown in fig. 8. In this embodiment, the sequence of column addresses COLADDR to the column decoder (FIGS. 2 and 5) is suspended for one or more clock cycles, shown here by sample and hold signal SH, at approximately the end of the sample time. In an embodiment in accordance with the invention, this suspension of the column address COLADDR sequence occurs at the end of each sample period. For example, the column address sequence pauses at the end of the SHR and again pauses at the end of the SHS.

When the column address COLADDR changes during the column address sequence, each new column address propagates through the column read decoder 204 (FIG. 5), effectively eliminating one column output circuit and selecting a different column output circuit. The newly selected column output circuit causes the RESET and SIGNAL lines in the differential analog output bus 506 (fig. 5) to change. This switching activity generates system noise that can be sampled by the sampling process that occurs during this time. By pausing the sequence of column addresses to the column decoder at about the end of the sampling time, system noise caused by switching activity associated with changing column addresses is eliminated, thereby reducing system noise at this critical sampling time.

In one or more embodiments in accordance with the invention, the output of the image sensor can be received by an imaging system or processing system that may not handle the discontinuity in data flow caused by the suspension of the AFE clock signal. FIG. 10 depicts a block diagram of circuitry to keep the intermittent data stream from FIG. 9 continuous with the use of a digital buffer. Fig. 11 illustrates an exemplary timing diagram for the circuit shown in fig. 10.

The circuit 1000 receives the discontinuous ADC output ADC OUT (see fig. 9) and outputs an uninterrupted data stream DOUT from the image sensor (see fig. 10 and 11). The ADC OUT output from ADC 400 is received at digital logic 208 (fig. 2) through AFE interface 220. This data output stream will have one or more breaks therein due to one or more pauses in the column addressing sequence. Data captured by AFE interface 220 is stored in digital buffer 222 as it is received. The read out of each row of data from the digital buffer 222 begins a number of clock cycles after the first data is written into the buffer, where the number of clock cycles is greater than or equal to the total number of clock cycles that the column address sequence is paused during each read out row as shown in 11. In an embodiment in accordance with the invention, the digital buffer 222 is comprised of a first-in-first-out (FIFO) memory having a selectable depth, but those skilled in the art will recognize that other implementations are possible.

Although fig. 11 shows recovery from a single discontinuity in the column addressing sequence, multiple discontinuities may occur when sampling rows of pixels. For example, multiple discontinuities may occur when pixel reset and signal levels are sampled separately (using SHR and SHS signals, for example). In the case of multiple discontinuities, the start of output data from DOUT must be delayed by a total combination time sufficient to anticipate all column addressing discontinuities. The digital buffer 222 stores the discontinuous ADC output ADC OUT during all of the discontinuities in the same row.

While the invention has been described in detail with particular reference to certain preferred embodiments thereof, it will be understood that variations and modifications can be effected within the spirit and scope of the invention. For example, embodiments in accordance with the invention have been described herein with respect to simultaneous sampling and readout of reset and image signals. Other embodiments according to the invention are not limited to these signals. Embodiments of the present invention can read out and sample any signal and any number of signals simultaneously.

In addition, the illustrated embodiments have been described with reference to specific components and circuits. Other embodiments according to the invention are not limited to these specific components. For example, logic gates and different types of switches other than and gates may be used in the embodiment shown in fig. 5.

Although specific embodiments of the present invention have been described herein, it should be noted that the present application is not limited to these embodiments. In particular, any feature described with respect to one embodiment may also be used in other embodiments, where compatible. And features of different embodiments may be interchanged when compatible.

Parts list

100 image capturing apparatus

102 light of

104 imaging stage

106 image sensor

108 processor

110 memory

112 display

114 input/output (I/O) element

200 pixels

202 pixel array

204 column decoder

206 row decoder

208 digital logic

210 sampling and readout circuit

212 Analog Front End (AFE)

214 control register

216 timing generator

218 analog front end clock controller

220 analog front-end interface

222 digital buffer

300 region of action

302 photo-activated pixel column

304 rows of light activated pixels

306 lines of reference area

Reference area of 308 columns

400A/D converter (ADC)

402 Analog Signal Processor (ASP)

404 variable gain amplifier

406 variable gain amplifier

408 signal summary node

410 digital-to-analog converter (DAC)

500 sampling switch

502 sample and hold capacitor

504 read out switch

506 differential analog output bus

508 AND gate

510 sampling switch

512 sample and hold capacitor

514 and gate

516 AND gate

518 sample and hold capacitor

520 AND gate

522 AND gate

524 sampling switch

526 sample and hold capacitor

528 AND gate

530 sample and hold capacitor

1000 uninterrupted data flow output circuit

Claims (9)

1. An image sensor, comprising:

a two-dimensional array of pixels, the array including a plurality of column outputs;

output circuitry connected to each column output, wherein each output circuitry is configured to operate simultaneous sample and read operations;

a column decoder electrically connected to each output circuit; and

a timing generator for outputting a column address sequence received by the column decoder, wherein the timing generator pauses the column address sequence during a sampling operation and restarts the column address sequence simultaneously with or after an end of the sampling operation.

2. The image sensor of claim 1, further comprising a digital buffer configured to selectively store at least a portion of pixel data output from the output circuit.

3. The image sensor of claim 1, further comprising a plurality of sampling switches connected to each column output.

4. The image sensor of claim 3, further comprising a sample and hold capacitor connected to each sampling switch.

5. The image sensor of claim 4, further comprising a readout switch connected to each sample and hold capacitor.

6. The image sensor of claim 5, wherein a select signal is used to activate respective readout switches, and the column decoder selects individual output circuits in a sequence to readout previously sampled pixel signals.

7. The image sensor of claim 1, wherein the timing generator pauses the sequence of column addresses for a predetermined number of clock cycles.

8. The image sensor of claim 7, further comprising a control register for storing one or more values collectively representative of the predetermined number of clock cycles.

9. The image sensor of claim 1, wherein the image sensor is included in an image capture device.