HK1172762B - A method for processing an image captured by an image sensor - Google Patents

Abstract

The present application relates to a method for processing an image captured by an image sensor having a charge multiplication output channel and a charge sensing output channel. An image sensor includes a horizontal shift register electrically connected to a pixel array for receiving charge packets from the pixel array. A non-destructive sense node is connected to an output of the horizontal shift register. A charge directing switch is electrically connected to the non-destructive sense node. The charge directing switch includes two outputs. A charge multiplying horizontal shift register is electrically connected to one output of the charge directing switch. A discharging element is connected to the other output of the charge directing switch.

Description

Method for processing images captured by an image sensor

Technical Field

The present invention relates to image sensors for use in digital cameras and other types of image capture devices, and more particularly, to Charge Coupled Device (CCD) image sensors. Still more particularly, the present invention relates to charge multiplication in CCD image sensors.

Background

Fig. 1 depicts a simplified block diagram of a first CCD image sensor performing charge multiplication according to the prior art. The pixel array 100 includes a vertical Charge Coupled Device (CCD) shift register (not shown) that shifts charge packets from a row of pixels 102 into a low voltage horizontal CCD (hccd) shift register 105, one row at a time. The low voltage HCCD shift register 105 serially shifts the charge packets into the high voltage charge multiplying HCCD shift register 110. Charge multiplication occurs in the charge multiplying HCCD shift register 110 via application of a large electric field to the gate electrode (not shown) of the overlying HCCD shift register 110 during charge transfer. The large electric field produces a signal that is larger than the signal that would otherwise be collected in the pixels in the pixel array 100. A large electric field is generated by overdriving the gate electrode above the extended HCCD shift register 402 with a sufficiently large voltage. In general, the charge multiplying HCCD shift register 110 may multiply the number of charge carriers in each charge packet by a factor of 2 to 1000. The multiplied charge packets output at the ends of the charge multiplying HCCD shift register 110 are sensed by an output amplifier 120 and converted to a voltage signal.

A conventional output amplifier may have a minimum noise level of eight charge carriers, meaning that the output amplifier cannot detect a signal when the charge contains less than eight charge carriers. One advantage of multiplying the HCCD shift register 110 is the ability to amplify or multiply charge packets that would normally not be detectable by the output amplifier. For example, a charge multiplying HCCD shift register may take an input of only one non-detectable charge carrier (e.g., electron) and convert it into a larger detectable group of 1000 charge carriers. The output amplifier is now able to detect the charge packets and convert them into a voltage signal.

One major drawback of the charge multiplying HCCD shift register is its dynamic range. If a charge packet entering the multiplying HCCD shift register has 200 charge carriers and if the gain is 1000, then 200 charge carriers multiply to 200,000 charge carriers. Many charge multiplying HCCD shift registers cannot hold 200,000 or more than 200,000 charge carriers, so the charge carriers diffuse (diffuse) into pixels adjacent to the HCCD shift register. When the capacity of the charge multiplying HCCD shift register is 200,000 charge carriers and the gain is 1000, the maximum signal that the charge multiplying HCCD shift register can measure is 200 charge carriers at the noise floor with one charge carrier. This is a dynamic range of 200 to 1. To illustrate the badness of the dynamic range, an output amplifier with a minimum noise level of eight electrons can easily measure charge packets containing 32,000 charge carriers over a dynamic range of 4000 to 1.

To overcome this limitation, prior art CCD image sensors (see fig. 2) have added a second output amplifier 200 to the HCCD shift register 105. If the image is known to contain charge packets that are too large for the charge multiplying HCCD shift register 110, the charge packets are serially shifted through the HCCD shift register 105 to the output amplifier 200 rather than toward the charge multiplying HCCD shift register 110. One disadvantage of this embodiment is that the entire image must be read out of either output amplifier 200 or output amplifier 120. If an image contains both bright and dark regions, the image must be read out of the output amplifier 200 so that the bright regions do not fringe (flood) the charge multiplying HCCD shift register 110. But when the entire image is read out of the output amplifier 200, dark areas in the image are not shifted through the charge multiplying HCCD shift register and do not receive the benefit of the charge multiplying HCCD shift register 110.

Disclosure of Invention

An image sensor includes a horizontal shift register electrically connected to a pixel array for receiving charge packets from the pixel array. A non-destructive sense node is connected to an output of the horizontal shift register. A charge directing switch is electrically connected to the non-destructive sense node. The charge directing switch includes two outputs. A charge multiplying horizontal shift register is electrically connected to one output of the charge directing switch. A discharge element is connected to the other output of the charge directing switch.

A pipeline delay horizontal shift register may be connected between the non-destructive sense node and the charge directing switch. An extended horizontal shift register may be connected between the charge directing switch and an input of the charge multiplying horizontal shift register. An amplifier may be connected to the non-destructive sense node and an output of the charge multiplying shift register.

The image sensor may be included in an image capture device. The image capture device may include a Correlated Double Sampling (CDS) unit connected to the output of the amplifier. The CDS units may each include an analog-to-digital converter. A computing device receives a digital pixel signal generated by the non-destructive sense node for each charge packet output from the horizontal shift register. The computing device generates a switch signal that is received by the charge directing switch and that causes the charge directing switch to direct a charge packet to the charge multiplying horizontal shift register when the number of charge carriers in the charge packet will not saturate the charge multiplying horizontal shift register. The charge directing switch directs a packet of charge to the discharge element connected to another output of the charge directing switch when the packet of charge will saturate the charge multiplying horizontal shift register.

The amplifier connected to the non-destructive sense node and the CDS cell connected to the amplifier combine to form a charge sensing output channel having a combined charge-to-voltage conversion gain value G1. The amplifier connected to the output of the charge multiplying horizontal shift register and the CDS unit connected to the amplifier combine to form a charge multiplying output channel having a combined charge to voltage conversion gain value G2. A method for generating an image includes selecting a pixel signal generated by the charge sensing output channel or the charge multiplying output channel. If the pixel signal generated by the charge sensing output channel is selected, a gain ratio (G2/G1) is applied to each pixel signal selected from the charge sensing output channel. The image is generated by combining the selected pixel signals.

A method for making an image sensor includes providing a horizontal shift register electrically connected to a pixel array for receiving charge packets from the pixel array. A non-destructive sense node is provided that is connected to an output of the horizontal shift register. A charge directing switch electrically connected to the non-destructive sense node is provided. The charge directing switch includes a first output and a second output. Providing a charge multiplying horizontal shift register electrically connected to the first output of the charge directing switch. Providing a discharge element connected to the second output of the charge directing switch. A method for making an image capture device further includes providing a computing device electrically connected to the charge directing switch, wherein the computing device is operable to transmit a switch signal to the charge directing switch in response to a signal received from the non-destructive sense node.

Drawings

Embodiments of the invention are better understood with reference to the following drawings. The elements of the drawings are not necessarily to scale relative to each other.

Fig. 1 depicts a simplified block diagram of a first CCD image sensor performing charge multiplication according to the prior art;

FIG. 2 depicts a simplified block diagram of a second CCD image sensor performing charge multiplication according to the prior art;

FIG. 3 is a simplified block diagram of an image capture device in an embodiment in accordance with the invention;

FIG. 4 is a simplified block diagram of a CCD image sensor suitable for use as image sensor 306 shown in FIG. 3 in an embodiment in accordance with the invention;

FIG. 5 depicts a simplified top view of the charge directing switch 414 shown in FIG. 4 in an embodiment in accordance with the invention;

FIG. 6 illustrates a first exemplary timing diagram for the charge directing switch 414 shown in FIG. 5;

FIG. 7 illustrates a second exemplary timing diagram for the charge directing switch 414 shown in FIG. 5;

FIG. 8 is a flow chart of a method for operating an image sensor in an embodiment in accordance with the invention;

FIG. 9 is a flow chart of a method for generating an image that may be used in conjunction with the embodiment shown in FIG. 4;

FIG. 10 is an exemplary diagram for illustrating how signals output from three output channels are combined to generate an image in an embodiment in accordance with the invention; and

FIG. 11 is a flow chart of a method for fabricating an image sensor in an embodiment in accordance with the invention.

Detailed Description

Throughout the specification and claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meaning of "a, an" and "the" includes plural references, and the meaning of "in … …" includes "in … …" and "on … … (on)". The term "coupled" means either a direct electrical connection between the items coupled, or an indirect connection through one or more passive or active intermediary devices. The term "circuit" means either an active or passive component or components that are connected together to provide a desired function. The term "signal" means at least one current, voltage, charge or data signal.

Additionally, the term "substrate layer" should be understood to mean a semiconductor-based material, including, but not limited to, silicon-on-insulator (SOI) technology, silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers or well regions formed on a semiconductor substrate, and other semiconductor structures.

Referring to the drawings, like numbers indicate like parts throughout the views.

FIG. 3 is a simplified block diagram of an image capture device in an embodiment in accordance with the invention. The image capture device 300 is implemented as a digital camera in fig. 3. Those skilled in the art will recognize that a digital camera is but one example of an image capture device that may utilize an image sensor incorporating the present invention. Other types of image capture devices may be used with the present invention, such as, for example, cell phone cameras and digital video camcorders.

In the digital camera 300, light 302 from a subject scene is input to an imaging stage 304. Imaging stage 304 may include conventional elements such as lenses, neutral density filters, diaphragms, and shutters. Light 302 is focused by imaging stage 304 to form an image on image sensor 306. Image sensor 306 captures one or more images by converting incident light into electrical signals. The digital camera 300 further includes a processor 308, memory 310, a display 312, and one or more additional input/output (I/O) elements 314. Although shown as separate elements in the embodiment of fig. 3, imaging stage 304 may be integrated with image sensor 306 and possibly one or more additional elements of digital camera 300 to form a compact camera module.

For example, processor 308 may be implemented as a microprocessor, Central Processing Unit (CPU), Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), or other processing device, or a combination of multiple such devices. The various elements of imaging stage 304 and image sensor 306 may be controlled by timing signals or other signals supplied from processor 308.

Memory 310 may be configured as any type of memory such as, for example, Random Access Memory (RAM), Read Only Memory (ROM), flash memory, disk-based memory, removable memory, or other types of storage elements in combination. A given image captured by image sensor 306 may be stored by processor 308 in memory 310 and presented on display 312. The display 312 is typically an active matrix color Liquid Crystal Display (LCD), although other types of displays may be used. For example, the additional I/O elements 314 may include various on-screen controls, buttons or other user interfaces, network interfaces, memory card interfaces, and the like.

It should be understood that a digital camera as shown in fig. 3 may include additional or alternative elements of a type well known to those skilled in the art. Elements not explicitly shown or described herein may be selected from those known in the art. As previously described, the present invention may be implemented in a wide variety of image capture devices. Moreover, certain aspects of the embodiments described herein may be implemented, at least in part, in the form of software executed by one or more processing elements of an image capture device. As will be appreciated by those skilled in the art, in view of the teachings provided herein, such software may be implemented in a straightforward manner.

Referring now to fig. 4, there is shown a simplified block diagram of a CCD image sensor suitable for use as image sensor 306 shown in fig. 3, in an embodiment in accordance with the invention. Image sensor 400 may be implemented as any type of CCD image sensor including, but not limited to, an interline CCD image sensor and a full frame image sensor.

Image sensor 400 includes a pixel array 402 having a vertical shift register (not shown) that shifts charge packets from each row of pixels to a horizontal shift register 404. Horizontal shift register 404 is implemented as a low voltage horizontal Charge Coupled Device (CCD) shift register in an embodiment in accordance with the invention. Horizontal shift register 404 serially shifts each charge packet toward non-destructive sense node 406. In an embodiment in accordance with the invention, non-destructive sense node 406 is implemented as a non-destructive floating gate sense node.

The voltage on non-destructive sense node 406 is input into amplifier 408. The output of the output amplifier 408 is connected to an output circuit 410. Output amplifier 408 forms a "charge sensing output channel" with output circuit 410. Output circuit 410 is implemented as a Correlated Double Sampling (CDS) unit in an embodiment in accordance with the invention. The CDS unit may be configured in any of various circuit implementations. By way of example only, the CDS unit may be configured to subtract the double samples (e.g., reset and image samples) in the analog domain and pass the result to the analog-to-digital converter. As another example, a CDS unit available from Andriod Devices, part number AD9824, can be used for the CDS unit. The CDS unit may also be configured to digitally convert the two samples and subtract the double samples in the digital domain, as in U.S. patent application 5,086,344.

Typically, output circuits that include analog-to-digital converters have pipeline processing delays. When the output circuit receives the analog pixel signal output from the output amplifier 408, the corresponding digital pixel signal is not output from the output circuit 410 until a given number of clock cycles have elapsed. Pipeline delay horizontal shift registers are used in some embodiments according to the invention to compensate for pipeline processing delays of output circuit 410. In the illustrated embodiment, pipeline delay horizontal shift register 412 has a length corresponding to the pipeline processing delay of output circuit 410. The length of the pipeline delay horizontal shift register 412 is determined such that charge packets sensed by the non-destructive sense node 406 and passed to the pipeline delay horizontal shift register 412 are output from the pipeline delay horizontal shift register 412 and arrive at the charge directing switch 414 at the same time or at a later time as the digitized pixel signal is output from the CDS unit 410. In other embodiments according to the invention, the pipeline delay horizontal shift registers 412 may have different lengths.

A computing device (e.g., processor 308 in fig. 3) analyzes the digital pixel signals output from output circuit 410 and transmits a switch signal on signal line 413 to charge directing switch 414. In embodiments according to the invention, the computing device is constructed external to the image sensor die or chip. In another embodiment according to the invention, the computing device may be constructed on an image sensor die or chip.

If the digital pixel signal output from the output circuit 410 represents a small or fractional number of charge carriers, the switch signal on the signal line 413 causes the charge directing switch 414 to pass a packet of charge onto the charge multiplying horizontal shift register 416. The charge packets are then shifted through charge multiplying horizontal shift register 416 and input into output amplifier 418. The output amplifier 418 outputs an analog pixel signal representative of the amount of charge carriers in the charge packet.

The output circuit 420 is connected to the output of the output amplifier 418. The output amplifier 418 forms a "charge multiplying output channel" with the output circuit 420. The output circuit 420 converts the analog pixel signal into a digital pixel signal. In some embodiments according to the invention, the output circuit 420 may perform additional processing on the pixel signals. In an embodiment in accordance with the invention, the output circuit 420 is implemented as a CDS unit. The CDS unit may be configured in any of a number of implementations.

If the digital pixel signal output from the output circuit 410 represents a number of charge carriers that can saturate the multiplying horizontal shift register 416, the switch signal on signal line 413 causes the charge directing switch 414 to direct a charge packet to the discharge element 422. The discharge element 422 is used to dump or discharge charge packets that will not be input into the charge multiplying horizontal shift register 416. In an embodiment according to the present invention, the discharge element 422 is implemented as a drain.

The extended horizontal shift register 424 serves as a connecting horizontal shift register between the charge directing switch 414 and the charge multiplying horizontal shift register 416. The extended horizontal shift register 424 operates at a low voltage level in an embodiment in accordance with the invention. The extended horizontal shift register 424 may be omitted in other embodiments in accordance with the invention.

The image sensor 400 generates one pixel signal for a charge packet that is not input into the charge multiplying output channel. The pixel signal is generated by a charge sensing output channel. Image sensor 400 generates two pixel signals for charge packets directed into the charge multiplying output channel. The digital pixel signals generated by output circuits 410 and 420 may be asynchronous in terms of the time at which the digital pixel signals are output from the output circuits and the location of charge packets in the image. For each charge packet, output circuit 410 will typically output a digital pixel signal faster than output circuit 420 because it takes more time to shift the charge packet via charge multiplying horizontal shift register 416. In an embodiment in accordance with the invention, the digital pixel signals output from output circuits 410 and 420 are synchronized or reordered by a computing device (e.g., processor 308 in FIG. 3). The computing device may store the state of the switch signal for each charge packet and use the data to reorder the digital pixel signals to render an image.

Referring now to fig. 5, shown is a simplified top view of the charge directing switch 414 shown in fig. 4 in an embodiment in accordance with the invention. A pipeline delay horizontal shift register 412 and an extended horizontal shift register 428 are shown connected to the charge directing switch 414. In an embodiment in accordance with the invention, the charge directing switch 414 includes gates 500, 502, 504 disposed over the charge shifting elements. The charge directing switch 414 includes two outputs, one associated with gate 502 and the other associated with gate 504.

In the illustrated embodiment, pipeline delay horizontal shift register 412 and extended horizontal shift register 424 are each depicted as two-phase CCD shift registers. Other embodiments according to the invention are not limited to two-phase CCD shift registers. CCD shift registers having three or more phases may be implemented in other embodiments.

The exemplary first timing diagram depicted in FIG. 6 is used to direct charge from the pipeline delay horizontal shift register 412 to the extended horizontal shift register 424. In embodiments omitting the extended horizontal shift register 424, the timing diagram may be used to direct charge from the pipeline delay horizontal shift register 412 to the charge multiplying horizontal shift register 416. And finally, in embodiments omitting the pipeline delay horizontal shift register 412, the timing diagram may be used to direct charge from the non-destructive sense node 406 to either the extended horizontal shift register 424 or the charge multiplying horizontal shift register 416.

At time T₀Here, gate 500 is clocked low while the signal on gate 504 remains low and the signal on gate 502 is clocked high. When the signals on gates 500 and 504 are at low and gate 50 is atWhen the signal on 2 is high, charge flows out of the charge shifting element under gate 500 and into the charge shifting element under gate 502. The signals applied to the gates 506, 508 in the extended horizontal shift register 424 are then clocked as shown in fig. 6 to shift charge packets through the extended horizontal shift register.

Referring now to FIG. 7, another exemplary timing diagram for the charge directing switch 414 shown in FIG. 5 is shown. In an embodiment in accordance with the invention, the exemplary timing diagram illustrated in FIG. 7 is used to direct charge from the pipeline delay horizontal shift register 412 to the discharge element 422. When at time T₀₀At this point, when gate 500 is clocked to a given level (e.g., low), the signal on gate 502 remains low and the signal on gate 504 is clocked high. When the signals on gates 500 and 502 are at a low level and the signal on gate 504 is at a high level, charge flows out of the charge shifting element disposed below gate 500 and into discharge element 422.

Fig. 8 is a flow chart of a method for controlling the flow of charge packets in an embodiment in accordance with the invention. Initially, at block 800, charge packets are shifted to a non-destructive sense node. Charge packets are converted to a digital pixel signal representative of an amount or number of charge carriers in the charge packet while the charge packet is sent to a charge directing switch (block 802). In an embodiment in accordance with the invention, a horizontal shift register is delayed through a pipeline to shift charge packets to send them to a charge directing switch.

A determination is then made at block 804 as to whether the number of charge carriers in a charge packet will saturate the charge multiplying horizontal shift register. If the charge packet will saturate the charge multiplying horizontal shift register, the process proceeds to block 806, where the charge packet is directed to a discharge element. If the charge carriers will not saturate the charge multiplying horizontal shift register, then charge packets are directed to the charge multiplying horizontal shift register and shifted through the charge multiplying horizontal shift register (block 808).

The method depicted in fig. 8 is repeated for each pixel read out of the pixel array. Only charge packets that do not cause blooming are input and shifted through the charge multiplying horizontal shift register. The larger charge packets causing dispersion are directed to the discharge element.

Referring now to FIG. 9, there is shown a flow chart of a method for generating an image that may be used in conjunction with the embodiment shown in FIG. 4. The value G1 represents the combined charge-to-voltage conversion gain of the amplifier 408 and the output circuit 410. The value G2 represents the combined charge-to-voltage conversion gain of the output amplifier 418 and the output circuit 420.

Initially, a determination is made at block 900 as to whether the number of charge carriers in a charge packet will saturate the charge multiplying horizontal shift register. If not, the charge packet is directed to and shifted through a charge multiplying horizontal shift register and the digital pixel signal generated by an output amplifier and output circuit connected to the charge multiplying horizontal shift register is selected as the digital pixel signal (block 902). Next, as indicated in block 904, the digital pixel signals are stored. By way of example only, the digital pixel signals may be stored in the memory 310 shown in fig. 3.

Next, as shown in block 906, a determination is made as to whether the image sensor will produce another charge packet. If so, the method returns to block 900. When the number of charge carriers in a charge packet will saturate the charge multiplying horizontal shift register, the process proceeds to block 906, where the charge packet is directed to a discharge element. The digital pixel signal generated by the amplifier connected to the non-destructive sense node is selected as the digital pixel signal (block 908). Then, at block 910, the selected digital pixel signal is multiplied by a gain ratio (G2/G1) and the modified digital pixel signal is stored at block 904. By way of example only, the gain ratio (G2/G1) may be applied to the selected digital pixel signal by a computing device (e.g., the processor 308 shown in FIG. 3).

When all charge packets have been processed and there are no more charge packets (block 906), the method proceeds to block 914, where the stored or modified pixel signals are combined to generate an image. Embodiments in accordance with the invention may combine blocks 904 and 914 such that the pixel signals are stored in locations corresponding to the locations of the pixels in the image. Thus, when the image sensor has produced all charge packets, the memory or storage unit stores the completed image.

One process for determining the gain ratio G2/G1 used in the method shown in FIG. 9 will now be described. The G2/G1 gain ratio may be determined from the charge packets directed to the charge multiplying horizontal shift register 418 and the output circuit 420. The charge packets are processed by both output circuits 410 and 420. In one embodiment according to the present invention, a running average of (the digital pixel signal generated by output circuit 420)/(the digital pixel signal generated by output circuit 410) is determined. This running average is equal to the gain ratio G2/G1. The running average is used in embodiments because as the camera temperature changes, the gain ratio G2/G1 will likely also change.

Embodiments according to the invention are not limited to the use of running averages. In another embodiment according to the invention, a running least squares fit average may be used. Those skilled in the art will appreciate that running a least squares fit average will also correct for offset errors.

Fig. 10 is an exemplary diagram for illustrating how signals output from two output channels are combined to generate an image in an embodiment according to the present invention. Line 1000 represents the output of the charge multiplying output channel for a charge packet having a number of charge carriers from 0 to S1. Line 1002 represents the output of the charge sensing output channel for a charge packet having a number of charge carriers from 0 to S2. The slope of each line 1000 and 1002 is the output gain G2 and G1, respectively.

Line 1004 represents the saturation levels of amplifiers in different output channels, such as amplifiers 408 and 418. The pixel intensity of all output channels will not exceed this saturation level. Thus, the maximum pixel intensity of the image is limited to the intensity level represented by line 1004.

The output amplifier 418 saturates at a low charge carrier number S1 and the output amplifier 408 saturates at a charge carrier number S2. If the number of charge carriers is between S1 and S2, the output of the charge sensing output channel is multiplied by the ratio of the slopes of output lines 1000 and 1002 (i.e., gain ratio G2/G1).

The pixel signals output from the charge sensing output channels are multiplied by a gain ratio to produce an image with a larger range of intensity values. When a gain ratio is applied to charge packets having a number of charge carriers between S1 and S2, the gain ratio modifies the pixel intensity values such that the intensity values fall along line 1006.

By way of example only, charge packets having a number of charge carriers corresponding to the number of points 1008 along line 1002 are output from the charge sensing output channel. When the charge packet is multiplied by the gain ratio (G2/G1), the modified pixel intensity value corresponds to point 1008' along line 1006. Thus, the gain ratio produces modified pixel intensities that fall or substantially fall on line 1006, thereby providing an image with a larger range of pixel intensity values.

Referring now to FIG. 11, shown is a flow chart of a method for fabricating an image sensor in an embodiment in accordance with the invention. Initially, an array of pixels is fabricated, as shown in block 1100. The photodetector pixel array may be fabricated using techniques known in the art. For example, a masking layer may be deposited over the substrate and each patterned to provide openings at locations where respective components (e.g., photodetectors) in each pixel are to be formed. Dopants of a particular conductivity type are then implanted into the substrate to fabricate the component.

Next, as shown in block 1102, a horizontal CCD shift register is fabricated on one side of the pixel array. Horizontal CCD shift registers can be fabricated using techniques known in the art. For example, a masking layer may be deposited over the substrate and patterned to provide openings at locations where each shift register element or phase in each shift register element is to be formed. Dopants of a particular conductivity type are then implanted into the substrate to fabricate the shift register elements or phases. Barrier implants may also be formed between shift register elements or phases. Furthermore, electrodes are fabricated over each shift register element or phase and electrically connected to respective voltage clocking signals for shifting charge packets through the horizontal CCD shift register. Typically, the electrodes are formed in several electrode layers. In a two-phase CCD shift register, alternate electrodes (every other electrode) form one electrode layer and the remaining electrodes form a second electrode layer. In a four-phase CCD shift register, the electrodes disposed above the first and third phases (or the second and fourth phases) form one electrode layer and the remaining electrodes form a second electrode layer.

Next, as shown in blocks 1104 and 1106, charge sensing output channels and charge multiplying output channels are fabricated. The output channels may be fabricated using techniques known in the art. For example, a masking layer may be deposited over the substrate and patterned to provide openings at locations where each shift register element or phase in each shift register element is to be formed. Dopants of a particular conductivity type are then implanted into the substrate to fabricate the shift register elements or phases. Barrier implants may also be formed between shift register elements or phases. Further, an electrode or gate is fabricated over each shift register element or phase and electrically connected to a respective voltage clocking signal for shifting charge packets through the horizontal shift register. Typically, the gate is formed in several layers. In a two-phase shift register, alternate gates (every other gate) form one layer and the remaining gates form the second electrode layer. In a four-phase shift register, the gates disposed over the first and third phases (or the second and fourth phases) form one layer and the remaining gates form a second electrode layer.

A discharge element is formed at block 1108. The discharge elements may be formed using techniques known in the art. And finally, a charge directing switch is made at block 1110. The charge directing switch may be fabricated using techniques known in the art. For example, a masking layer may be deposited over the substrate and patterned to provide openings at locations where each shift register element or phase in each shift register element is to be formed. Dopants of a particular conductivity type are then implanted into the substrate to fabricate the shift register elements or phases. Barrier implants may also be formed between shift register elements or phases. Further, a gate is fabricated over each shift register element or phase and electrically connected to a respective voltage timing signal for directing charge packets through respective outputs of the charge directing switches.

Those skilled in the art will recognize that the order of the blocks shown in figure 10 may be modified in accordance with other embodiments of the invention. For example, multiple components included in a pixel array, horizontal shift register, charge sensing output channel, or charge multiplying output channel may be fabricated simultaneously by appropriately patterning masking layers. Embodiments including a pipeline delay horizontal shift register or an extended horizontal shift register can fabricate these elements when fabricating the desired output channels. In addition, other components in the image sensor may be fabricated between the processes shown in FIG. 10.

The invention has been described in detail with particular reference to certain embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention. For example, signal levels other than those shown in fig. 7 and 8 may be used. In other embodiments according to the invention, the charge directing switch may be implemented in a different manner. The image capture device may include additional components compared to those shown in fig. 3.

Also, even though specific embodiments of the invention have been described herein, it should be noted that the application is not limited to such embodiments. In particular, any feature described with respect to one embodiment may also be used in other embodiments, where compatible. Also, features of different embodiments may be interchanged, if compatible.

Parts list

100 pixel array

102 pixel

105 horizontal charge coupled device shift register

110 charge multiplying horizontal charge coupled device shift register

120 output amplifier

200 output amplifier

300 image capturing apparatus

302 light

304 imaging stage

306 image sensor

308 processor

310 memory

312 display

314 other input/output (I/O)

400 image sensor

402 pixel array

404 horizontal charge coupled device shift register

406 non-destructive sense node

408 amplifier

410 output circuit

412 pipeline delay horizontal shift register

414 charge directing switch

416 Charge multiplying horizontal shift register

418 amplifier

420 output circuit

422 discharge element

424 extended horizontal charge coupled device shift register

500 grid

502 grid

504 grid

506 grid

508 grid

1000 represents a line of output of a charge multiplying output channel

1002 represents a line for the output of a charge sensing output channel

1004 represents the line of saturation level

1006 represents a line of pixel intensity values

1008 pixel intensity values

1008' modified pixel intensity values

S1 represents the value of the number of charge carriers

S2 represents the value of the number of charge carriers

Claims (6)

1. A method for processing an image captured by a pixel array in an image sensor, the method comprising:

transferring charge packets from the pixel array to a horizontal shift register;

shifting each charge packet to a non-destructive charge sensing output channel;

non-destructively sensing each charge packet and generating a signal representative of a number of charge carriers in the charge packet;

directing a respective charge packet to a charge multiplying output channel when the signal representative of the number of charge carriers in each charge packet indicates that the charge packet will not saturate the charge multiplying horizontal shift register; and

when the signal representative of the number of charge carriers in each charge packet indicates that the charge packet will saturate the charge multiplying horizontal shift register, the respective charge packet is directed to a discharge element.

2. The method of claim 1, wherein the charge multiplying output channel has an associated charge-to-voltage conversion gain value of G2 and the charge sensing output channel has an associated charge-to-voltage conversion gain value of G1.

3. The method of claim 2, further comprising applying a gain ratio G2/G1 to each pixel signal generated by the charge sensing output channel.

4. The method of claim 1, wherein directing a respective charge packet to a charge multiplying output channel when the signal representative of the number of charge carriers in each charge packet indicates that the charge packet will not saturate the charge multiplying horizontal shift register comprises: a charge directing switch is configured to direct a respective charge packet to a charge multiplying output channel when the signal representative of the number of charge carriers in each charge packet indicates that the charge packet will not saturate the charge multiplying horizontal shift register.

5. The method of claim 1, wherein directing a respective charge packet to a discharge element when the signal representative of the number of charge carriers in each charge packet indicates that the charge packet will saturate the charge multiplying horizontal shift register comprises: a charge directing switch is configured to direct each charge packet to a discharge element when the signal representative of the number of charge carriers in the respective charge packet indicates that the charge packet will saturate the charge multiplying horizontal shift register.

6. A method for generating an image captured by an image sensor, wherein the image sensor includes at least two output channels: a charge multiplying output channel having an associated gain value of G2 and a charge sensing output channel having an associated gain value of G1, the method comprising:

selecting, for each charge packet, a pixel signal generated by the charge multiplying output channel or a pixel signal generated by the charge sensing output channel;

applying a gain factor (G2/G1) to each pixel signal selected from the charge sensing output channel if the pixel signal generated by the charge sensing output channel is selected; and

the selected pixel signals are combined to produce the image.