HK1171870B - Reduced pixel area image sensor - Google Patents

Description

Image sensor with reduced pixel area

The present application is a divisional application of the chinese patent application with application number 200880008428.3 and invention name "image sensor with reduced pixel area" filed on 9, 15/2009.

Technical Field

The present invention relates generally to the field of CMOS active pixel image sensors and, more particularly, to reducing the size of pixels.

Background

Fig. 1 shows a typical CMOS active pixel image sensor 100. The basic component of image sensor 100 is an array of light sensitive pixels 130. The row decoder circuit 105 selects an entire row of pixels 130, which will be sampled by a Correlated Double Sampling (CDS) circuit 125. The analog-to-digital converter 115 scans through (scan across) column decoders and digitizes the signals stored in the CDS 125. The analog-to-digital converter 115 may be of the type having one converter per column (parallel) or of the type having one high-speed converter to digitize each column serially. The digitized data may be output directly from the image sensor 100 or there may be integrated image processing 120 for defect correction, color filter interpolation, image scaling, and other special effects. A timing generator 110 controls the row and column decoders to sample the entire pixel array or only a portion of the pixel array.

Fig. 2 shows one of many different possible schematics for a CMOS image sensor. Four pixels 130 of the pixel array are shown (only one labeled for clarity). Each pixel 130 has circuitry shared between two photodiodes 150 and 151. This type of pixel and other variations can be found in U.S. patents 5,625,210, 5,841,159, 5,949,061, 6,107,655, 6,160,281, 6,423,994, and 6,657,665.

Photodiodes 150 and 151 are connected to a common shared floating diffusion 155 through transfer gates 152 and 153, respectively. The process of sampling the photodiode 150 begins with turning on the power supply (VDD) 158 and also turning on the reset transistor 154 to set the floating diffusion 155 voltage to the voltage of the power supply 158. Then, the reset transistor 154 is turned off, and the signal level sampled by the output transistor 156 is driven onto the output signal line 157. The transfer gate 153 is then turned on to transfer photo-generated signal charges from the photodiode 150 to the floating diffusion 155. The output transistor 156 will now drive the signal level voltage onto the output signal line 157. The difference of the first signal just after reset minus the signal after the transfer gate 153 is pulsed (pulse) is proportional to the number of electrons in the photodiode 150.

The second photodiode 151 is sampled in the same manner by a transfer gate 152. The pixel 130 is shown as a shared pixel because the two photodiodes 150 and 151 share a common floating diffusion 155. An example of how a pixel shared by both can be physically fabricated on a silicon substrate is shown in figure 3. The numbered components in fig. 3 correspond to the schematic symbols in fig. 2. Polysilicon transistor transfer gates are 152 and 153; the reset transistor gate is 154 and the output transistor gate is 156. Metal lines connect the floating diffusion contacts 155 together. The reset 154 and output 156 transistors share a common diffusion connection 158 to the power supply line.

A disadvantage of the pixel layout of fig. 3 is how to reduce the size of the pixels. The gap 160 between two adjacent pixels cannot be further reduced without risk of electron leakage between adjacent pixels. The transistor gates 154 and 156 cannot be scaled down in size because the operating voltage of the power supply determines their size. Reducing the supply voltage is not an attractive option as this will also reduce the maximum number of photoelectrons that can be collected by the photodiode.

This and other disadvantages are addressed by the present invention, which discloses a method of reducing the size of a pixel without reducing the size of the reset and output transistor gates (gates).

Disclosure of Invention

The present invention is directed to overcoming one or more of the problems set forth above. Briefly summarized, according to one aspect of the present invention, the present invention resides in an image sensor including a plurality of pixels disposed on a substrate, each pixel including: at least one photosensitive region that collects charge in response to incident light; a charge-to-voltage conversion node for sensing charge from the at least one photosensitive region and converting the charge to a voltage; an amplifier transistor having a source connected to the output node, a gate connected to the charge-to-voltage conversion node, and a drain connected to at least a portion of the power supply node; and a reset transistor connecting the output node and the charge-to-voltage conversion node.

Advantageous effects

The invention allows the image sensor pixel size to be reduced without reducing the size of the transistor geometry.

Drawings

FIG. 1 is a prior art active pixel image sensor;

FIG. 2 is a schematic diagram of the pixel of FIG. 1;

fig. 3 is a plan view (top view) of fig. 1;

FIG. 4 is a schematic diagram of a plurality of pixels of the present invention;

fig. 5 is a plan view (top view) of fig. 4;

fig. 6 is a horizontal cross-section through the transistor of fig. 5;

FIG. 7 is an image sensor of the present invention having the pixel of FIG. 4; and

fig. 8 is a camera having an image sensor of the present invention.

Detailed Description

Before discussing the present invention in detail, it is helpful to note that the present invention is preferably used in, but not limited to, CMOS active pixel sensors. Active pixel sensors refer to the active electrical elements in a pixel, more specifically an amplifier, and CMOS refers to the complementary metal oxide silicon type of electrical components, such as transistors, associated with a pixel but not normally in a pixel, and formed when the source/drain of a transistor is one dopant type (e.g., p-type) and the transistor to which it is mated is the opposite dopant type (n-type). CMOS devices include several advantages, one of which is that less power is consumed.

In order to reduce the pixel size, it is necessary to change the operation of the transistors in the pixel. A schematic diagram of a pixel of the present invention is shown in fig. 4. The main difference of this pixel 235 from the prior art is that the reset transistor 212 is connected between the floating diffusion 218 and the output signal line 242. The prior art connects the reset transistor to the power supply line (VDD) 234. Although this schematic does not reduce the total number of transistors, it does allow the power supply line (VDD) 234 diffusion to be shared between the two pixels 235 and 236. This is more clearly shown in fig. 5.

Referring back to fig. 4, each pixel will now be described in detail. The pixel 235 will be used as a representative pixel. In this regard, the pixel 235 includes two photosensitive regions or photodiodes 232 and 233, each for collecting charge in response to incident light. It should be noted for clarity that pin (pinned) photodiodes may also be used, as it should be understood that the functional block primarily needs to collect charge only in response to light. The transfer gate 214 transfers charge from the photodiode 232 to a charge-to-voltage conversion node or sensing node 218. An output transistor or amplifier 210, preferably a source follower, is connected to the sense node 218 via its gate, and the amplifier 210 senses the signal on the sense node 218 and outputs the signal onto an output bus 242 via its source. The drain of amplifier 210 is connected to a power supply (VDD) 234. The connection includes connecting the drain to at least a portion of power supply node 234. This portion preferably comprises one half or substantially one half of power supply node 234. Amplifier 220 is connected in the same manner and to the remainder of power supply 234. The pixel 235 shares the sensing node 218, the amplifier 210, and the reset transistor 212, but includes a separate photodiode 233 that collects charge in response to incident light and a transfer gate 216 that transfers charge to the sensing node 218.

The adjacent pixel 236 includes the same components as the pixel 235, but is indicated by a different number for clarity. In this regard, the pixel 236 includes a photodiode 237, a transfer gate 224, a sense node or floating diffusion 228, an amplifier 220, and a reset transistor 222. Pixel 236 shares floating diffusion 228, amplifier 220, and reset transistor 222, but includes a separate photodiode 238 and transfer gate 226.

In fig. 5, the reference numerals correspond to those in fig. 4. The VDD diffusion 234 is shared between the two output transistors 210 and 220. The reset transistor gates 212 and 222 allow the floating diffusions 218 and 228 to be reset to a voltage through outputs 242 and 243. The pixels 235 (shown in FIG. 4) comprise a sequential spatial order as follows: charge-to-voltage conversion node 218, the reset gate of reset transistor 212, output node 242, the gate of amplifier transistor 210, and at least a portion of power supply node 234. The adjacent pixels 236 (also shown in FIG. 4) comprise a sequential spatial order as follows: the remainder of power supply node 234, the gate of amplifier transistor 220, output node 243, the reset gate of reset transistor 222, and charge-to-voltage conversion node 228.

Referring back to fig. 4, the process of reading out charge from a row of photodiodes 232 and 237 begins by activating floating diffusions 218 and 228. This is accomplished by turning off constant current sink load transistors 240 and 241 (see bottom of fig. 4). The load transistors 240 and 241 are turned off and the switches 230 and 231 can be set to the VHigh voltage setting. Now, when the reset transistors 212 and 222 are turned on, the floating diffusions 218 and 228 will be set to the VHigh voltage. Next, the reset transistors 212 and 222 are turned off, and the switches 230 and 231 are set to the off setting. Then, current dissipating load (current sink load) transistors 240 and 241 are turned on, so that output transistors 210 and 220 will drive output lines 242 and 243 to a voltage representing a floating reset level corresponding to zero electrons of the photo signal. Transfer gates 214 and 224 are then pulsed on and off to transfer the photo-generated charge from photodiodes 232 and 237 to floating diffusions 218 and 228. Now, the output transistors 210 and 220 will drive the output lines 242 and 243 to a voltage level corresponding to the number of electrons generated in the photodiodes 232 and 237. The difference between this voltage level and the reset voltage level is proportional to the amount of charge in the photodiode.

To read out the next row of photodiodes 233 and 238, the process is repeated by activating the floating diffusions 218 and 228. This is done by turning off the constant current dissipating load transistors 240 and 241. The load transistors 240 and 241 are turned off and the switches 230 and 231 can be set to the VHigh voltage setting. Now, when the reset transistors 212 and 222 are turned on, the floating diffusions 218 and 228 will be set to the VHigh voltage. Next, the reset transistors 212 and 222 are turned off, and the switches 230 and 231 are set to the off setting. The current dissipating load transistors 240 and 241 are then turned on so that the output transistors 210 and 220 will drive the output lines 242 and 243 to a voltage representing a floating reset level corresponding to zero electrons of the photo signal. Transfer gates 216 and 226 are then pulsed on and off to transfer the photo-generated charge from photodiodes 233 and 238 to floating diffusions 218 and 228. Now, the output transistors 210 and 220 will drive the output lines 242 and 243 to a voltage level corresponding to the number of electrons generated in the photodiodes 233 and 238. The difference between this voltage level and the reset voltage level is proportional to the amount of charge in the photodiode.

Then, the transistors in pixels 235 and 236 must be deactivated (deactivated) before proceeding to read out another row of pixels. Holding the reset transistors 212 and 222 on sets the gate and source voltages of the output transistors 210 and 220 to be equal. When the gate and source voltages are equal in a surface channel transistor, the transistor will be in an off state. When the output transistors 210 and 220 are in the off state, they will not interfere with the readout of the photodiodes of other image sensor rows.

By sharing a common power supply (VDD) diffusion 234, the amount of area occupied by the transistors in fig. 5 is reduced. There is one less contact and one less isolation region between the transistors compared to the prior art of fig. 3. This allows the overall pixel size to be reduced while maintaining the same transistor gate size and maintaining a reasonably sized photodiode.

Fig. 6 shows a cross-section through lines of transistor gates 212, 210, 220, and 222. These transistors are fabricated on a silicon substrate 250.

The pixel 235 in fig. 4 shows two photodiodes 232 and 233 sharing a common floating diffusion 218. Those skilled in the art of CMOS image sensors will readily observe that the invention may be applied to any number of photodiodes, including those that do not share a photodiode, with or without sharing a common floating diffusion.

Fig. 4 also shows VDD power supply line 234 oriented in a vertical direction. The power lines 234 may also be oriented horizontally or in both directions as a square grid. Furthermore, if the VDD power supply line 234 is oriented horizontally, it may be used to select or deselect rows to be read out, as in U.S. Pat. nos. 5,949,061 and 6,323,476.

Fig. 7 shows a pixel 330 of the present invention incorporated in an image sensor 300. The image sensor 300 has a row decoder 305 to select and deselect rows to be read out. It also has a column decoder 325 for sampling the output line (line) of each column and an analog-to-digital converter 315 for digitizing the signals on the output lines. Timing generator 310 controls the scanning of the row 305 and column 325 decoders. An image processor 310 is used to correct row and column gains and offsets, as well as defect correction, color filter interpolation, or other image processing functions.

Fig. 8 is a digital camera 400 having the image sensor 300 of the present invention.

Parts list

100 image sensor

105 row decoder circuit

110 timing generator

115 analog-to-digital converter

120 image processing

125 Correlated Double Sampling (CDS) circuit

130 light sensitive pixel

150 photodiode

151 photodiode

152 transmission gate

153 transmission gate

154 reset transistor gate

155 floating diffusion

156 output transistor gate

157 output signal line

158 power line (VDD)

160 gap

210 output transistor or amplifier

212 reset transistor gate

214 transmission gate

216 transmission gate

218 floating diffusion or sense node

220 output transistor or amplifier

222 reset transistor gate

224 transmission gate

226 transmission gate

228 floating diffusion or sense node

230 switch

231 switch

232 photoelectric diode

233 photodiode

234 power supply line (VDD)

235 pixels

236 pixel

237 photodiode

238 photodiode

240 dissipative load transistor

241 dissipative load transistor

242 output signal line

243 output signal line

250 silicon substrate

300 image sensor

305 row decoder

310 timing generator

315 analog-to-digital converter

320 image processor

325 row decoder

330 photosensitive pixel

400 digital camera.

Claims (3)

1. A method for reading out charge from a row of pixels in an image sensor, wherein each pixel in the row includes a photodetector, a floating diffusion, and each column output line in the image sensor is connected to a load transistor, the method comprising:

turning off the load transistor;

setting the column output line to a first voltage level by setting a switch connected to the column output line to a high level voltage, wherein the first voltage level is a high level voltage;

resetting the floating diffusion by pulsing a reset transistor in a pixel in the row to be read out, wherein pulsing the reset transistor transfers a first voltage level on the column output line to the floating diffusion;

turning on the load transistor and setting the column output line to a second voltage level by turning the switch to an off setting and driving the column output line using an output transistor having a gate coupled to the floating diffusion, wherein the second voltage level is a voltage representing a floating reset level corresponding to zero electrons of a photo signal; and

signals are read out from the pixels in the row.

2. The method of claim 1, wherein reading out signals from pixels in the row comprises:

reading out a reset signal on the floating diffusions in the row;

transferring charge from the photodetector to the floating diffusion in the row by pulsing a transfer gate in the row;

reading out image signals on the floating diffusions in the row; and

turning on the reset transistors in the pixels in the row.

3. The method of claim 1, wherein the output transistor shares a power supply node with one of the output transistors in the row.