HK1171571B - Solid-state image pickup device and method for manufacturing same - Google Patents

Description

Solid-state image pickup device and method of manufacturing the same

Technical Field

The present invention relates to a solid-state image pickup device. More particularly, the present invention relates to a solid-state image pickup device in which each pixel has a charge holding portion.

Background

In recent years, for higher performance of a solid-state image pickup device, a configuration in which each pixel has a charge holding portion separated from a photoelectric conversion portion and a floating diffusion (hereinafter, FD) is considered. A charge holding portion is provided in each pixel in order to realize a global electronic shutter (global electronic shutter) as described in PTL 1 and PTL 2, or in order to expand a dynamic range as described in PTL 3. Further, as described in PTL 4, a charge holding portion is also provided in each pixel in a configuration in which each pixel has an analog-to-digital (AD) converter.

PTL 1 discloses a configuration in which a P-type semiconductor region is provided on a surface portion so as to separate an electrode TX1 on an electric charge holding portion formed of an N-type semiconductor region and an electrode TX2 for transferring electric charges in the electric charge holding portion from each other. Such a configuration prevents dark current from flowing to the accumulation region.

CITATION LIST

Patent document

PTL 1: U.S. Pat. No.7414233

PTL 2: japanese patent laid-open No.2008-004692

PTL 3: japanese patent laid-open No.2006-197383

PTL 4: japanese patent laid-open No.2009-038167

Disclosure of Invention

Technical problem

However, according to the configuration of PTL 1, the P-type semiconductor region is provided to separate the two transfer gate structures from each other, and the N-type semiconductor region constituting the charge holding portion is provided thereunder. Therefore, it is difficult to control the charge transfer efficiency in the charge path under the P-type semiconductor region provided as the structure separating the two transfer gates regardless of the impurity concentration of the charge holding portion. Therefore, if a high priority is given to the performance of the charge holding portion, it is difficult to improve the transfer efficiency in the charge path extending from the charge holding portion to the sense node.

The present invention has been made in view of this problem, and aims to improve the charge transfer efficiency from the charge holding portion to the FD regardless of the impurity concentration of the charge holding portion.

Solution to the problem

In view of the above-described problems, according to the present invention, there is provided a solid-state image pickup device including a plurality of pixels. Each of the plurality of pixels includes: a photoelectric conversion portion configured to generate electric charges according to incident light; a charge holding portion configured to include a first conductivity type first semiconductor region that holds charges generated by the photoelectric conversion portion in a portion different from the photoelectric conversion portion; and a transfer portion configured to include a transfer gate electrode that controls an electric potential between the charge holding portion and the sense node. The charge holding portion includes a control electrode disposed over the first semiconductor region through an insulating film. A second-conductivity-type second semiconductor region is provided on a surface of the semiconductor region between the control electrode and the transfer gate electrode, the second semiconductor region having an impurity concentration higher than that of the first semiconductor region. A third semiconductor region of the first conductivity type is disposed in a charge path extending from the charge holding portion to the sense node under the second semiconductor region. The third semiconductor region has an impurity concentration higher than that of the first semiconductor region.

The invention has the advantages of

According to the present invention, the charge transfer efficiency from the charge holding portion to the FD can be improved regardless of the impurity concentration of the charge holding portion.

Drawings

Fig. 1 is a schematic diagram of a cross section of a pixel of a solid-state image pickup device according to a first embodiment.

Fig. 2 is a schematic diagram of a cross section of a pixel of a solid-state image pickup device according to a second embodiment.

Fig. 3 is a schematic diagram of a cross section of a pixel of a solid-state image pickup device according to a third embodiment.

Fig. 4 is a schematic diagram of an upper surface of a pixel of a solid-state image pickup device according to a third embodiment.

Fig. 5 is a conceptual diagram illustrating the distribution of the impurity concentration in the Y-Y' section in fig. 3.

Fig. 6 includes a cross-sectional view of a pixel, which shows an example of a method for manufacturing a solid-state image pickup device according to the present invention.

Fig. 7 is an equivalent circuit diagram of a solid-state image pickup device according to the present invention.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail. Regarding the conductivity type of the semiconductor, a description will be given on the assumption that the first conductivity type is an N-type and the second conductivity type is a P-type, but the opposite is also acceptable. The difference depends on whether the signal charge is an electron or a hole. The cross-sectional view of each pixel shows a part of one pixel, but a plurality of pixels are provided in an actual device.

(first embodiment)

Fig. 1 is a schematic diagram of a cross section of a pixel of a solid-state image pickup device according to an embodiment of the present invention.

Reference numeral 101 denotes a photoelectric conversion portion. For example, a photodiode configured to include a P-type semiconductor region and an N-type semiconductor region is used. Reference numeral 102 denotes a charge holding portion. The charge holding portion 102 is configured to include an N-type semiconductor region (first semiconductor region) capable of holding the charge generated by the photoelectric conversion portion. Reference numeral 103 denotes a transmission section. The transfer portion 103 transfers the electric charge held by the charge holding portion to the sensing node. Reference numeral 104 denotes a sensing node. The sensing node is, for example, a Floating Diffusion (FD) electrically connected to a gate of a Metal Oxide Semiconductor (MOS) transistor for pixel amplification. The sensing node may be electrically connected to a vertical signal line (not shown) instead of being electrically connected to a gate of a MOS transistor for pixel amplification.

Next, specific configurations of the foregoing respective members will be described. In the present embodiment, the photoelectric conversion portion 101, the charge holding portion 102, the transfer portion 103, and the sense node 104 are arranged in a P-type well 107. A P-type well 107 is formed on the surface side of the N-type substrate 116 by ion implantation or epitaxial growth. A P-type semiconductor substrate may be used instead of the N-type substrate 116 on which the P-type well 107 is formed.

Reference numerals 105 and 106 denote N-type semiconductor regions. The N-type semiconductor region 105 is formed in the N-type semiconductor region 106, and has an N-type impurity concentration higher than that of the N-type semiconductor region 106. The N-type semiconductor region 105 forms a PN junction together with the P-type semiconductor region 108. The N-type semiconductor region 106 forms a PN junction together with the P-type well 107.

Reference numeral 108 denotes a high concentration P-type semiconductor region. Providing the P-type semiconductor region 108 enables reduction of dark current generated on the surface of the semiconductor. In this embodiment, the aforementioned photoelectric conversion portion 101 is constituted by the N-type semiconductor regions 105 and 106, the P-type well 107, and the high-concentration P-type semiconductor region 108.

Reference numeral 110 denotes an N-type semiconductor region. In this embodiment, the N-type semiconductor region 110 is a first semiconductor region that holds electric charges in a portion different from the photoelectric conversion portion. Reference numeral 112 denotes a control electrode. The aforementioned charge holding portion 102 is configured to include an N-type semiconductor region 110 and a control electrode 112.

In the charge holding portion 102 according to the present embodiment, the control electrode 112 is provided above the N-type semiconductor region 110 through the insulating film 109. The control electrode 112 controls the potential of the semiconductor surface side of the N-type semiconductor region 110. A negative voltage may be applied to the control electrode in order to suppress the influence of the dark current generated in the charge holding portion.

Reference numeral 113 denotes a transfer gate electrode. A bias voltage applied to the transfer gate electrode 113 causes an electron transfer path to be formed in a portion of the P-type well 107 adjacent to the N-type semiconductor region 110. The transfer gate electrode 113 is switched between a transfer path formation state and a transfer path non-formation state according to a bias voltage supplied thereto, and controls electrical connection between the charge holding portion and the PD.

The N-type semiconductor region 114 is an FD. In the present embodiment, the FD 114 serves as a sensing node. The sensing node may be a semiconductor region from which a signal is output according to the amount of charge accumulated therein.

Reference numeral 115 denotes a light shielding member. The light shielding member 115 reduces incident light of the charge holding portion 102, the transmission portion 103, and the sensing node 104, and more preferably, completely shields incident light of the charge holding portion 102, the transmission portion 103, and the sensing node 104.

Reference numeral 116 denotes a P-type semiconductor region (second semiconductor region). The P-type semiconductor region 116 is disposed in a surface portion between the control electrode 112 and the transfer gate electrode 113. Providing the P-type semiconductor region enables suppression of dark current in a charge transfer path for transferring charges to the FD 114.

Reference numeral 117 denotes an N-type semiconductor region (third semiconductor region). An N-type semiconductor region 117 is disposed below the P-type semiconductor region 116. In a step different from the step of providing the N-type semiconductor region 110 constituting the charge holding portion, the N-type semiconductor region 117 is provided in a configuration separated from the N-type semiconductor region 110. The P-type semiconductor region 116 and the N-type semiconductor region 117 form a PN junction. The N-type semiconductor region 117 has an impurity concentration higher than that of the N-type semiconductor region 110.

According to such a configuration, the transfer characteristic can be determined not according to the impurity concentration of the N-type semiconductor region 110, and therefore the amount of saturated charge in the charge holding portion can be designed independently. In particular, in order to improve the charge transfer efficiency, the impurity concentration of the N-type semiconductor region 117 is preferably high to some extent. However, if the N-type semiconductor region 117 is configured as an extended portion of the N-type semiconductor region 110 constituting the charge holding portion, the impurity concentration of the entire N-type semiconductor region 110 is too high. In such a configuration, the voltage for transferring most of the electric charges (preferably, all of the electric charges) from the charge holding portion is high. In contrast, the impurity concentration of the N-type semiconductor region 110 is preferably set low to a certain degree so that the voltage for transfer is not so high. However, if the N-type semiconductor region 117 is configured as an extension of the N-type semiconductor region 110 constituting the charge holding portion, the impurity concentration of the N-type semiconductor region 117 is low, and the charge transfer efficiency is lowered. Therefore, as in the present embodiment, the N-type semiconductor regions 110 and 117 are formed as regions separated from each other, and the impurity concentration of the N-type semiconductor region 117 is set higher than that of the N-type semiconductor region 110, so that the transfer efficiency can be improved without increasing the voltage for transfer.

Further, according to the present embodiment, dark current and saturation variation caused by displacement of the charge holding portion of each pixel due to process variation can be reduced.

(second embodiment)

Fig. 2 is a schematic diagram of a cross section of a pixel according to the present embodiment. Portions having the same functions as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

The present embodiment is different from the first embodiment in that the depth of the N-type semiconductor region 117 is set. In the first embodiment, the N-type semiconductor region 117 is provided at almost the same depth as the N-type semiconductor region 110. In the present embodiment, the N-type semiconductor region 117 is provided at a depth greater than the depth at which the N-type semiconductor region 110 is provided.

According to the present embodiment, the effects obtained in the first embodiment can be obtained. In addition, charge accumulation in a charge path extending from the charge holding portion to the sense node can be suppressed.

(third embodiment)

Fig. 3 is a cross-sectional view of a cross-section of a pixel according to the present embodiment, and fig. 4 is a top view of the pixel. Fig. 5 is a conceptual diagram of impurity distribution in the section Y-Y' in fig. 3. Fig. 3 is a sectional view of a portion a-B in fig. 4. Parts having the same functions as those in the first and second embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted.

The present embodiment differs from the first and second embodiments in that a P-type semiconductor region 301 (fourth semiconductor region) is provided below an N-type semiconductor region 110. Another difference is that a P-type semiconductor region 302 (fifth semiconductor region) including a plurality of semiconductor regions is provided below the P-type semiconductor region 301. Here, the P-type semiconductor region 302 includes four P-type semiconductor regions 302a to 302 d. The number of P-type semiconductor regions is not limited thereto.

Reference numeral 301 denotes a high concentration P-type semiconductor region. The impurity concentration of the P-type semiconductor region 301 is higher than that of the P-type well 107. Preferably, the P-type semiconductor region 301 forms a PN junction directly with the N-type semiconductor region 110 without passing through the P-type well 107. The distribution of the impurity concentration in the depth direction of the P-type semiconductor region 301 may be a distribution having a peak of the impurity concentration at a certain depth. Preferably, the peak of the impurity concentration of the P-type semiconductor region 301 is at a position shallower by 0.5 μm than the surface. This is because if the peak is at a position shallower by 0.5 μm than the surface, a region of low impurity concentration is not provided between the N-type semiconductor region 110 and the high concentration P-type semiconductor region 301. With this configuration, it is possible to transfer charge from the charge holding portion to the sensing node at a low voltage. This will be described in detail.

First, a mechanism of transferring charge from the charge holding portion to the sense node will be described. Before the signal charges generated in the photoelectric conversion portion 101 are held in the N-type semiconductor region 110, a reset voltage is supplied to the N-type semiconductor region 110 through the sense node. Then, after the potential of the sense node floats, the electric charges in the photoelectric conversion portion 101 are transferred to the N-type semiconductor region 110. Then, the charges are sequentially transferred from the charge holding portion to the sensing node. The transfer is performed in units of pixel lines or in units of a plurality of pixel lines. At this time, the N-type semiconductor region 110 is in a state where a reverse bias is supplied through the transfer portion 103. The reverse bias causes the N-type semiconductor region 110 to be depleted so that charges are transferred. In order to transfer most of the electric charges (preferably, all of the electric charges) held in the N-type semiconductor region 110 to the sensing node, most of the area (preferably, the entire area) of the N-type semiconductor region 110 needs to be depleted. In order to suppress the expansion of the depletion layer at this time, the N-type semiconductor region 110 preferably forms a PN junction together with the high concentration P-type semiconductor region 111 without passing through the P-type well 107. This is because, since the impurity concentration of the P-type semiconductor region forming the PN junction together with the N-type semiconductor region 110 is high, the expansion of the depletion layer to the P-type semiconductor region can be suppressed. Therefore, even if the reverse bias supplied through the transmission portion is low, most of the region (preferably, the entire region) of the N-type semiconductor region 110 can be depleted.

Further, in the present embodiment, the impurity concentration of the high concentration P-type semiconductor region 301 is higher than that of a region at the same depth as the P-type semiconductor region 301 below the transfer path. In other words, the high concentration P-type semiconductor region 301 does not extend below the transfer gate electrode 113. With this configuration, a transfer path can be formed in the P-type well below the transfer gate electrode 113 without increasing the bias voltage supplied to the transfer gate electrode 113.

Further, in the present embodiment, the P-type semiconductor region 302 is disposed below a part of the P-type semiconductor region 301. The P-type semiconductor region 302 extends below the transfer gate electrode 113 and below the FD 114.

The P-type well 107 includes two regions 107a and 107 b. However, the P-type semiconductor region 302 may extend only under at least a portion of each of the P-type semiconductor region 301, the transfer gate electrode 113, and the FD 114. In addition, ion implantation may be further performed on the region 107b to form a P-type semiconductor region.

With the end of the charge holding portion as a reference, the end of all or some of the plurality of semiconductor regions included in the P-type semiconductor region 302 is deviated from the photoelectric conversion portion side in the same pixel. An N-type semiconductor region 106 constituting a part of the photoelectric conversion portion is provided in the offset portion.

In this embodiment, in each of the plurality of pixels, the end portions on the photoelectric conversion portion side of the P-type semiconductor regions 302 and 303 are deviated from the photoelectric conversion portions. This configuration may have sensitivity to light entering in an oblique direction. Such an arrangement may be utilized in all or some of the pixels.

Next, a description will be given with reference to fig. 4. Reference numeral 401 denotes a portion where circuits constituting pixels are arranged. Specifically, the circuit includes an amplifying MOS transistor, a reset MOS transistor, and the like. Examples of equivalent circuits thereof will be described below. Reference numeral 402 denotes an element separating region. The region is provided to separate the active regions from each other. Any one of a field region composed of an insulating film and diffusion separation composed by PN junction separation is set. Reference numeral 403 denotes a contact plug electrically connected to the FD. The contact plug 403 electrically connects the FD with the gate of the amplifying MOS transistor. Reference numeral 404 denotes an active region where elements are disposed.

In fig. 4, a region in which the P-type semiconductor region 302 is disposed is indicated by a dotted line, and a region in which the P-type semiconductor region 116 and the N-type semiconductor region 201 are disposed is indicated by a dashed-dotted line. As can be understood from fig. 4, the end of the P-type semiconductor region 302 is offset from the photoelectric conversion portion in the same pixel with reference to the end of the charge holding portion. As described above, the N-type semiconductor region 106 constituting a part of the photoelectric conversion portion is provided in the offset portion.

Fig. 5 shows the distribution of the impurity concentration in the Y-Y' section in fig. 3. The vertical axis indicates the net impurity concentration (net concentration) compensated by impurities of the relative conductivity type. The horizontal axis indicates a depth from one main surface of the light receiving portion in which the semiconductor substrate is disposed. The P-type semiconductor regions 302a to 302d each have a peak of the impurity concentration. The P-type semiconductor regions 301 and 302 have a configuration in which the peak is highest in a region closest to the surface.

As described above, according to the present embodiment, in addition to the effects of the first embodiment and the second embodiment, an effect of improving the sensitivity of the photoelectric conversion portion can be obtained.

(method for manufacturing solid-state image pickup device)

Fig. 6 includes a schematic diagram of a cross section of a pixel for explaining a process of manufacturing a solid-state image pickup device according to the present invention. Parts having the same functions as those in each of the embodiments described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

A first feature of the manufacturing method is that the N-type semiconductor region 110 and the P-type semiconductor region 301 are formed using the same mask (first mask). The second feature is that the P-type semiconductor region 116 and the N-type semiconductor region 201 provided in the gap portion between the control electrode 112 and the transfer gate electrode 113 are formed using the same mask.

A detailed description will be given with reference to fig. 6. Fig. 6 shows only a portion related to the present embodiment. The transistors and the like in the other portions can be manufactured using a known manufacturing method. Fig. 6(a) is a schematic view of a cross section of a pixel in a state where a P-type semiconductor region 301 is formed. Reference numeral 601 denotes a mask pattern formed of photoresist.

First, a photoresist is formed over the entire surface of the substrate. Then, the photoresist is exposed to light so that an opening is formed in a region where the N-type semiconductor region 110 in the charge holding portion is to be disposed.

As a first impurity implantation step of forming the N-type semiconductor region 110, N-type impurity ions are implanted using a photoresist pattern formed in an exposure step as a mask pattern (first mask pattern). Arsenic or phosphorus may be used as impurities.

Subsequently, without a step of removing the photoresist mask, as a second impurity implantation step of forming the high-concentration P-type semiconductor region 301, P-type impurities are implanted. At this time, boron or the like may be used as the impurity. Then, heat treatment is performed to recover crystal defects and the like occurring during ion implantation. In this way, the N-type semiconductor region 110 and the P-type semiconductor region 301 are formed using the same mask pattern.

The first impurity implantation step of forming the N-type semiconductor region and the second impurity implantation step of forming the P-type semiconductor region may be performed in reverse order.

After the N-type semiconductor region 110 and the P-type semiconductor region 301 are formed, the photoresist mask 601 is removed.

Then, the P-type semiconductor region 302 is formed to be offset from the photoelectric conversion portion using a mask different from the aforementioned first mask. Then, the control electrode 112 and the transfer gate electrode 113 are formed.

Next, a step of forming the P-type semiconductor region 116 and the N-type semiconductor region 201 will be described with reference to fig. 6 (b).

First, a photoresist is formed over the entire surface of the substrate. Then, the photoresist is exposed to light to form a photoresist mask (second mask) so that the semiconductor substrate is covered except for a gap portion between the control electrode 112 and the transfer gate electrode 113. In order to perform ion implantation so as to achieve self-alignment with respect to the control electrode 112 and the transfer gate electrode 113, a photoresist is formed to cover at least a part of the control electrode 112 and the transfer gate electrode 113 and other regions.

Then, ion implantation of P-type impurities is performed in a self-aligned manner with respect to the control electrode 112 and the transfer electrode 113, so that a P-type semiconductor region 116 is formed (third impurity implantation step). Then, ion implantation of N-type impurities is performed without removing the second mask, so that the N-type semiconductor region 201 is formed (fourth impurity implantation step). As a condition of this ion implantation, the dose of the impurity ions is set higher than that in the first impurity implantation step so that the impurity concentration of the N-type semiconductor region 201 is higher than that of the N-type semiconductor region 110 at least. Then, heat treatment is performed to recover crystal defects and the like occurring during ion implantation.

According to the above manufacturing method, the P-type semiconductor regions 301 and 116 and the N-type semiconductor region 201 can be formed without largely increasing the manufacturing steps. Further, the displacement of the N-type semiconductor region 110 and the P-type semiconductor region 301 in the direction horizontal to the substrate surface can be reduced. Therefore, a portion in which the N-type semiconductor region 110 and the P-type semiconductor region 301 directly form a PN junction can be enlarged. Further, the displacement of the P-type semiconductor region 116 and the N-type semiconductor region 201 can be suppressed, and the transfer variation of each pixel can be suppressed.

Any one of the first and second impurity implantation steps and the third and fourth impurity implantation steps may be performed using the same mask.

(equivalent circuit of solid-state image pickup device)

Fig. 7 is an equivalent circuit diagram of a solid-state image pickup device applicable to all the foregoing embodiments. The solid-state image pickup device having the equivalent circuit can perform an overall electronic shutter operation.

Reference numeral 801 denotes a photoelectric conversion portion. Here a photodiode is used. Reference numeral 802 denotes a charge holding portion that holds signal charges generated by the photoelectric conversion portion. Reference numeral 803 denotes a sensing node of the amplifying section. For example, the FD and the gate electrode of the amplifying transistor electrically connected to the FD correspond to a sensing node. Reference numeral 804 denotes a first transfer portion which transfers the charge in the charge holding portion to a sensing node of the amplifying portion. Reference numeral 805 denotes a second transmission section provided as necessary. The second transfer portion may also function as a control electrode of the charge holding portion. The second transfer portion may have no transfer function and may have only a function as a control electrode in the charge holding portion. The second transfer portion functions to transfer the electric charges in the photoelectric conversion portion to the charge holding portion. Reference numeral 808 denotes a reset portion which supplies a reference voltage to at least the input portion of the amplification portion. Further, the reset portion may supply a reference voltage to the charge holding portion. Reference numeral 807 denotes a selection section provided as necessary. The selecting portion 807 causes the signal lines to output signals of the respective pixel rows. Reference numeral 806 denotes an amplifying transistor constituting the amplifying section. The amplification transistor 806 constitutes a source follower circuit together with a constant current source supplied to a signal line. Reference numeral 809 denotes a charge output control section which controls connection between the photoelectric conversion section and a power supply line serving as an overflow drain (hereinafter, OFD).

The equivalent circuit is not limited thereto, and a part of the configuration may be shared by a plurality of pixels. Further, the equivalent circuit is applicable to a configuration in which the control wiring of each element is fixed at a certain voltage and conduction control is not performed.

The second transfer portion may have a buried channel MOS transistor configuration so that the electric charges generated by the photoelectric conversion portion immediately flow into the charge holding portion. In this configuration, even in a non-conductive state, at a portion deeper than the surface, there is a portion where the energy barrier portion is lower. In this case, the charge transfer portion may be brought into a state in which a certain voltage is supplied without performing active control. That is, a fixed potential barrier may be provided, rather than functioning as a transmission section.

According to such a configuration, most of the signal charges generated by photoelectric conversion when light enters the photoelectric conversion portion are not accumulated in the photoelectric conversion portion, and can be transferred to the charge holding portion. Therefore, the charge accumulation time can be made uniform in the photoelectric conversion portions of all the pixels. Further, when the MOS transistor is in a non-conductive state, holes are accumulated on the surface of the channel, and a configuration for transporting charges exists at a predetermined depth with respect to the surface. Therefore, the influence of dark current on the interface of the insulating film can be reduced.

From another point of view, during a period when signal charges are accumulated in the photoelectric conversion portion and the charge holding portion, the potential of the charge path between the photoelectric conversion portion and the charge holding portion is lower than the potential of the charge path between the photoelectric conversion portion and the OFD region. Here, the electric potential refers to an electric potential with respect to signal charges.

Further, from the viewpoint of driving, the electric charges moved from the photoelectric conversion portion to the first electric charge holding portion within one exposure period are held in the first electric charge holding portion and used as an image signal. That is, after one exposure period in the photoelectric conversion portion starts, a signal is read to the outside of the pixel without passing through the reset operation of the charge holding portion. Note that when one frame image is captured, one exposure period is determined in each photoelectric conversion portion collectively.

In such a pixel configuration, electric charges can be transferred from the photoelectric conversion portion to the charge holding portion at a low voltage, which is more preferable from the viewpoint of improving charge transfer efficiency at a low voltage in combination with the embodiment of the present invention.

In such a configuration, the entire exposure can be performed relatively easily, but the charges in the photoelectric conversion portion are released to the OFD region during the transfer from the charge holding portion to the FD region. Thus, the image is intermittent. In the case where continuity of images is particularly necessary in such a configuration, continuous images can be obtained by performing exposure. Both can be switched if necessary.

Further, the present invention can also be realized in a solid-state image pickup device in which a charge holding portion is provided in each pixel to increase a dynamic range, and charges are transferred from the charge holding portion to a sensing node.

The present invention is not limited to the respective embodiments, and various modifications are acceptable without departing from the concept of the present invention. For example, the present invention may be applied to a configuration that does not include the control electrode 112. For example, the N-type semiconductor region 110 may be selectively connected to a power source through a contact plug and a switch.

List of reference symbols

101 photoelectric conversion part

102 charge holding part

114 control electrode

113 transfer gate electrode

116P-type semiconductor region

117, 201N type semiconductor region

Claims (7)

1. A solid-state image pickup device comprising a plurality of pixels, characterized in that each of the plurality of pixels comprises:

a photoelectric conversion portion configured to generate electric charges according to incident light;

a charge holding portion configured to include a first conductivity type first semiconductor region that holds charges generated by the photoelectric conversion portion in a portion different from the photoelectric conversion portion; and

a transfer portion configured to include a transfer gate electrode that controls a potential between the charge holding portion and a sense node,

wherein the charge holding portion includes a control electrode provided over the first semiconductor region through an insulating film,

wherein a second conductivity type second semiconductor region is provided on a surface of a semiconductor region between the control electrode and the transfer gate electrode, the second semiconductor region having an impurity concentration higher than that of the first semiconductor region,

wherein a first conductivity type third semiconductor region is disposed below the second semiconductor region in a charge path extending from the charge holding portion to the sense node,

wherein an impurity concentration of the third semiconductor region is higher than an impurity concentration of the first semiconductor region, and

wherein an area of the control electrode (112) is larger than an area of the transfer gate electrode (113) in a cross-sectional view.

2. The solid-state image pickup device according to claim 1, wherein a second conductivity type fourth semiconductor region is provided below the first semiconductor region so as to form a PN junction together with the first semiconductor region.

3. The solid-state image pickup device according to claim 2, wherein the sense node includes a floating diffusion, and wherein a second conductivity type fifth semiconductor region is provided at a position deeper than the fourth semiconductor region, the fifth semiconductor region extending under at least a part of the floating diffusion, the transfer gate electrode, and the fourth semiconductor region.

4. The solid-state image pickup device according to claim 3, wherein the fifth semiconductor region is configured to include a plurality of second conductivity type semiconductor regions at different depths.

5. The solid-state image pickup device according to claim 4,

wherein in the each pixel, an end portion on the photoelectric conversion portion side of the fifth semiconductor region is at a position close to the photoelectric conversion portion as compared with an end portion on the photoelectric conversion portion side of the second semiconductor region, and

wherein a first conductivity type semiconductor region constituting a part of the photoelectric conversion portion is disposed below at least a part of the second semiconductor region.

6. A solid-state image pickup device according to any one of claims 1 to 5, wherein a charge path extending between the photoelectric conversion portion and the charge holding portion is a buried channel.

7. A method for manufacturing the solid-state image pickup device according to claim 1, wherein the second semiconductor region and the third semiconductor region are formed using the same mask in a self-aligned manner with respect to the control electrode and the transfer gate electrode.