HK1170345B - Low rate radio frequency signal receiver for frequency shift keying fsk modulation - Google Patents

Description

Low-rate radio frequency signal receiver for frequency shift keying FSK modulation

Technical Field

The invention relates to a low rate and direct conversion radio frequency signal receiver for FSK modulation.

Background

In a conventional radio frequency signal receiver for FSK modulation, as shown in fig. 1a, direct frequency conversion may be performed in two different orthogonal branches to obtain a baseband signal. Each branch comprises a mixer 4, 5 for performing a frequency conversion of the oscillating signal provided by a local oscillator 7. In the first branch, a first high-frequency mixer 4 combines the FSK signal extracted by the antenna 2 and amplified by a low-noise amplifier ("LNA") 3 of the receiver with an in-phase oscillator signal S_lMixed to provide an intermediate in-phase signal I_INT. In the second branch, a second high-frequency mixer 5 combines the FSK signal extracted by the antenna 2 and amplified by the LNA 3 with the quadrature oscillator signal S_QMixed to provide an intermediate quadrature signal Q_INT. These quadrature oscillator signals are obtained via a 90 ° phase shifter 6 connected to a local oscillator 7. The intermediate signal I is then filtered in respective low-pass filters 8 and 9_INTAnd Q_INTTo provide a filtered signal. Each filtered signal is then passed through respective limiters 10 and 11 and then data demodulated in a conventional demodulator 12 to provide a data signal D_OUT. For the demodulation stage, two intermediate in-phase signals II_NTAnd quadrature signal Q_INTIt is necessary to be able to identify the sign of the frequency shift of the incoming FSK signal and to analyse the incoming FSK signal data.

According to another variant of the conventional FSK radio frequency signal receiver shown in fig. 1b, a 90 ° phase shifter may be configured in one of the branches before frequency conversion. First, an oscillation signal S is provided via a local oscillator 7_lMixing the FSK radio frequency signal in a first high frequency mixer 4 to provide an intermediate in-phase signal I_INT. Then, the same oscillation signal S is passed through the local oscillator 7_lAt the second placeFSK radio frequency signals phase shifted by 90 DEG by a phase shifter 6 are mixed in a high frequency mixer 5 to provide an intermediate quadrature signal Q_INT。

According to the first and second variants described above with reference to fig. 1a and 1b, the receiver 1 is able to extract a carrier frequency f that may have about 2.45GHz₀Conventional FSK radio frequency signals. Around f₀May be about 250kHz, or less. Since the high frequency direct conversion is performed in the two mixers 4 and 5, then filtered in the two low pass filters and amplitude limited in the two displays, the receiver consumes a high level of electric power, which is a drawback.

To avoid the use of two mixers during direct conversion of the high frequency of the input radio frequency signal, reference may be made to us patent No.5,293,408, which discloses an FSK data signal receiver. This receiver has a single mixer for directly converting the incoming FSK signal to a baseband signal. To this end, according to a first variant, the single mixer is supplied with an oscillation signal from a local oscillator via a phase control circuit, which alternates during phase switching, such as a 90 ° phase shifter. The phase control circuit alternately supplies the in-phase oscillation signal and the quadrature oscillation signal to the single mixer over time to convert the frequency of the FSK radio frequency signal extracted by the receiver antenna. The intermediate signal provided by the mixer is thus a series of alternating intermediate in-phase and intermediate quadrature signals. These intermediate signals are filtered in a low-pass filter and then subjected to a data demodulation operation.

According to a second variant of the FSK radio frequency signal receiver, a phase control circuit acting alternately during phase switching as a 90 ° phase shifter is arranged between the receiver antenna and the single mixer. This phase control circuit alternately supplies the single mixer with the in-phase FSK radio frequency signal and the quadrature FSK radio frequency signal of the phase control circuit over time. The local oscillator provides an oscillating signal directly to the mixer so that it provides alternating intermediate in-phase and quadrature signals. These intermediate signals are filtered in a low-pass filter and then subjected to a data demodulation operation.

In the FSK signal receiver of us patent No.5,293,408, switching between the in-phase signal and the quadrature signal is performed very abruptly. This results in high frequencies. Under these conditions, a low-pass filter with a very wide bandwidth is required after the single mixer, which is a drawback, because very high speed switching is required. This also means that FSK signal receivers have low practical sensitivity and poor reception channel efficiency, but have high electrical power consumption. This receiver can only be used to control devices in a precise location, but not in the field of communications with several transmit and receive channels. Further, a phase control circuit that directly controls a change from the communication signal to the quadrature signal and an inverse change based on the first baseband signal at the output of the low-pass filter. Switching from one phase to another occurs with very steep flanks, which requires the use of hysteresis components. Thus, all spurious frequencies at the center frequency pass through the filter to maintain fast switching between phases. These spurious frequencies may even be higher than the frequency of the input radio frequency signal, which results in high power consumption of the receiver input stage.

Reference is also made to us patent No.6,038,268, which discloses a receiver for FSK radio frequency signals. This receiver also uses a single mixer for converting the frequency of the radio frequency signal to a baseband signal. A phase control circuit is provided at the output of the local oscillator to provide either an in-phase or quadrature signal to the mixer. A pulse control generator is provided for controlling the clock of the phase control circuit at the output of the local oscillator. For the previous document, the first low-pass filter at the mixer output has a very high bandwidth, since the phase switching must also be very fast. This is a drawback because a second low-pass filter with a narrow bandwidth must be provided before the data demodulation stage to remove all spurious frequencies that have not been filtered out by the first low-pass filter. A high power consumption in the input stage (in particular the phase control circuit) is therefore observed and an additional component is provided between the frequency conversion and the data demodulation, which is another drawback.

Disclosure of Invention

It is therefore an object of the present invention to provide a direct conversion radio frequency signal receiver for FSK modulation having a high level of sensitivity and low power consumption in a low rate mode to overcome the above-mentioned drawbacks of the state of the art.

The present invention therefore relates to an FSK radio frequency signal receiver comprising the features defined in the independent claim 1.

Particular embodiments of the receiver are defined in the dependent claims 2 to 14.

One advantage of the radio frequency signal receiver for FSK modulation according to the present invention is that the phase switching is performed at a low frequency compared to the data modulation frequency drift in the incoming FSK radio frequency signal. However, the phase switching frequency is higher than the data rate frequency in the FSK radio frequency signal. Therefore, the data modulation frequency deviation is higher than the low data rate of the intermediate signal to be demodulated, which ensures that a narrow-band low-pass filter can be used. As a result of the low frequency phase switching of the FSK signal receiver and the single synthesizer for frequency conversion, the electrical power consumption of the receiver is greatly reduced. Furthermore, the slower phase switching does not affect the data demodulation in the demodulation stage.

Another advantage of the FSK radio frequency signal receiver according to the invention is that in the demodulation stage, when the other branches are selected for demodulation in the demodulator, the selected intermediate in-phase and quadrature signals are reconstructed in each branch.

Drawings

The objects, advantages and features of an FSK radio frequency receiver will be more apparent from the following description, based on non-limiting embodiments shown in the accompanying drawings, in which:

fig. 1a and 1b cited above show simplified views of two embodiments of an FSK radio frequency receiver according to the prior art;

fig. 2a and 2b show simplified views of two embodiments of a direct conversion, low-rate, FSK radio frequency signal receiver according to the present invention;

fig. 3 shows a time diagram of intermediate in-phase and quadrature signals with phase selection signals of a demodulation stage of a receiver for radio frequency signals by FSK according to the invention;

fig. 4a shows a first simplified embodiment of a frequency synthesizer using sigma-delta synthesis, forming a local oscillator with an integrated phase shifting circuit of the FSK radio frequency signal receiver of fig. 2 a;

fig. 4b shows two time diagrams illustrating the frequency programming of a binary word provided via a sigma-delta modulator of the synthesizer of fig. 4a of the FSK radio frequency signal receiver of fig. 2;

fig. 5 shows a second simplified embodiment of a frequency synthesizer with two switchable delay units forming an integrated phase shifted local oscillator with the FSK radio frequency signal receiver of fig. 2 a;

fig. 6 shows a second simplified embodiment of a frequency synthesizer with two switchable delay units forming an integrated phase shifted local oscillator with the FSK radio frequency signal receiver of fig. 2 a; and

fig. 7 shows an embodiment of a phase shifter arranged at the input of the FSK radio frequency signal receiver of fig. 2 b.

Detailed Description

In the following description, only those components of a radio frequency signal modulation receiver (FSK) known to a person skilled in the art will be described in a simplified manner. The FSK radio frequency signal receiver is arranged primarily for performing a direct conversion of a low data rate radio frequency signal to a baseband signal via a single mixer.

The FSK radio frequency signal receiver 1 as shown in fig. 2a and 2b is configured to be capable of operating in a low rate data or control reception mode. Due to the fact thatHere, the data or control rate of the modulation in the FSK signal is below 10 kbit/s, for example about 1 kbit/s. Under these conditions, the power of the radio-frequency signal extracted by the antenna 2 of the receiver 1 is generally concentrated at the carrier frequency f of the FSK signal₀The relative (positive and negative) modulation frequency drift or deviation af. This carrier frequency f₀May be greater than 300MHz, for example, about 2.45 GHz. The modulation frequency drift or deviation must theoretically be high enough, for example higher than or equal to 100kHz, preferably 250kHz, to avoid being affected by the high level 1/f of noise close to 0Hz after the frequency conversion. Generally, in input signal frequency modulation, by modulating the carrier frequency f₀Adding to the modulation frequency drift Δ f to define a "1" modulation state, which gives f₀+ Δ f, by a slave carrier frequency f₀Subtracting the modulation frequency drift Δ f to define the "0" modulation state, which gives f₀- Δ f. Of course, it is contemplated to define the "0" modulation state as the carrier frequency f₀But f is₀+ Δ f and f₀A data modulation frequency of-af is preferred.

A first embodiment of an FSK radio frequency signal receiver 1 is shown in fig. 2 a. The receiver of fig. 2a first comprises an FSK radio frequency signal receiver antenna 2 and a LAN 3, the latter being used for amplification and filtering of conventional FSK signals. The receiver further comprises a local oscillator 7 for providing an oscillating signal to the phase shifting circuit 16. Generating an oscillation signal LO having a carrier frequency f corresponding to the input FSK signal₀The equivalent frequency. The phase shift circuit 16 is controlled by a phase selection signal SEL to phase shift the oscillation signal LO provided by the local oscillator 7 from 0 ° to 90 ° and back in each half of the phase switching cycle 1/fs. This enables the single mixer 4 to be supplied alternately with an in-phase oscillating signal and a quadrature oscillating signal, the quadrature signal being phase-shifted by 90 ° with respect to the in-phase oscillating signal.

For example, an in-phase oscillation signal is provided when the signal SEL is in a "0" state, whereas a quadrature oscillation signal is provided when the signal SEL is in a "1" state, for example. However, an inverse selection by the signal SEL is also conceivable. The frequency fs of the phase switching period is designed to be lower than the frequency deviation Δ f but much larger than the frequency of the data rate D of the modulation in the FSK radio frequency signal. The frequency fs of the switching period may be set to be 10 to 20 times lower than the frequency deviation Δ f, for example between 10 and 25kHz, while the frequency deviation Δ f may be between 100 and 250 kHz. However, the phase switching period frequency is 10 to 20 times higher than the data rate frequency D, e.g. 1 kbit/s.

Thus, an input FSK signal frequency conversion is performed in the mixer 4 via the oscillation signal to provide the intermediate baseband signal INT. Since the oscillation signal LO supplied to the mixer 4 is an alternating and continuous in-phase oscillation signal and a quadrature oscillation signal, the intermediate signal INT generated at the output of the single mixer 4 is an alternating and continuous intermediate in-phase and quadrature signal.

These intermediate signals INT are then filtered by a low-pass filter 8, the low-pass filter 8 having a low bandwidth, considering that the receiver 1 is configured to receive low-rate FSK radio frequency signals and that the phase switching frequency is advantageously low. The filtered intermediate signal INT is likewise amplified in the amplitude limiter 10 before entering the demodulation stage 20. Based on the filtered and amplified intermediate signal, this demodulation stage is able to provide a data signal D at the output after demodulation_OUT. These data signals D_OUTCan be used immediately by a processing unit (not shown), for example for controlling the functions of the device in which the receiver is arranged.

The demodulation stage 20 comprises at its input a demultiplexer 13 which receives the filtered and amplified intermediate signal INT. This demultiplexer 13 is controlled by a phase selection signal SEL, providing a selected intermediate in-phase signal Im at a first output when the signal SEL is in the "0" state and a selected quadrature intermediate signal Qm at a second output when the signal SEL is in the "1" state. This does not lead to high spurious frequencies, such as jitter, during phase switching, since the phase switching is performed relatively slowly with a switching cycle frequency fs, e.g. equal to 10 kHz. Only switching transients occur, but at low frequencies, data demodulation is not affected.

Since the demultiplexer 13 provides the intermediate in-phase signal Im with a time lag of 1/(2 · fs) and the intermediate quadrature signal Qm with a time lag of 1/(2 · fs), a "hole" remains in the signal of each demodulation branch at the demultiplexer output. This therefore reduces the size and power consumption of the receiver relative to a conventional receiver with two conversion branches, but also reduces the sensitivity of the receiver by about 3dB, which is not disadvantageous. However, in order to allow continuous data demodulation in the demodulation stage 20, first and second circuits, called "magic circuits" 14 and 15, are used in each respective branch.

The first magic circuit 14 receives the selected intermediate in-phase signal Im and the second magic circuit 15 receives the selected intermediate quadrature signal Qm. The task of each magic circuit is to reconstruct the in-phase Im or quadrature Qm signal during the pause time of each branch from the phase selection signal SEL. Thus, each magic circuit 14, 15 reconstructs the signal on the basis of the image of the input signal for the entire duration of the pause, before the de-multiplexer controlled via the phase selection signal SEL provides the new in-phase signal Im or the quadrature signal Qm. As a result of these magic circuits, the selected intermediate in-phase signal Im and the quadrature signal Qm are supplied to the data demodulator, importantly continuously, at the output of the demodulation stage.

Each magic circuit 14, 15 advantageously comprises a known pseudo-digital phase-locked loop (PLL) which successively generates, before the selection of the other branch, an in-phase signal Im or a quadrature signal Qm representative of the received signal. In the phase of acquisition of the selected intermediate in-phase signal Im or Qm at the output of the demultiplexer 13 via the selection signal SEL, a magic circuit counter, clocked by the clock in the receiver, measures the average period of said intermediate signal received before switching off. The clock frequency may be, for example, about 26 MHz. Based on this measurement, a digital PLL (NCO synthesizer) that calculates the clock from the receiver clock goes through a frequency adjustment once per switching operation and starts at a phase equal to the average measured phase. Accordingly, the register of each digital PLL can store the phase and frequency of the reception signal to generate an image signal of the reception signal at the time of the pause or cut-off. Thus, the demodulator 12 receives the intermediate in-phase and quadrature signals Im and Qm successively.

The demodulator 12 of the demodulation stage 20 may be a simple D flip-flop, for example receiving the intermediate in-phase signal Im at the D input and calculating the clock at its clock terminal CLK by means of the intermediate quadrature signal Qm. By means of this flip-flop and depending on the state of each data bit, the flip-flop is in the data signal D_OUTThe output of (1) is level 1 or level 0.

Fig. 3 shows a simplified diagram of a time diagram of the intermediate in-phase and quadrature signals Im and Qm with filtering of the phase selection signal SEL through a demodulation stage of the FSK radio frequency signal receiver. It should be noted that there is a "hole" in the signals Im or Qm in each half of the switching cycle 1/fs, but as a result of each magic circuit, an image of these signals is reconstructed, as indicated by each arrow below the signals Im and Qm. Thus, the intermediate in-phase signals Im and Qm at the output of the magic circuit are uninterrupted for continuous data demodulation in the demodulator.

Fig. 2b shows a second embodiment of the FSK radio frequency signal receiver 1. This second embodiment differs from the first embodiment of the receiver of fig. 2a described above only in that the phase shifting circuit 26 is located in the path of the FSK radio frequency signal extracted by the antenna 2. This phase shift circuit 26 is arranged between the LNA 3 and the single mixer 4. The phase shift circuit calculates a clock by a phase selection signal SEL to alternately generate an in-phase FSK radio frequency signal and a quadrature FSK radio frequency signal every successive phase switching period. These in-phase and quadrature FSK signals are frequency-converted in the mixer 4 via the oscillation signal LO to generate the intermediate baseband signal INT. These intermediate signals INT comprise alternately intermediate in-phase signals and intermediate quadrature signals. These intermediate signals INT are processed in the demodulation stage 20 in the same way as in the first embodiment of the receiver 1 described with reference to fig. 2 a.

For the first and second embodiments of the FSK radio frequency signal receiver of fig. 2a and 2b, the phase selection signal SEL may advantageously be obtained by a programmable or multimode frequency divider connected to the reference quartz oscillator of the local oscillator 7. For calculating the clock time for the magic circuits 14 and 15The clock frequency may also be provided by a quartz oscillator of the local oscillator. This local oscillator 7 may be a conventional frequency synthesizer. This synthesizer includes a reference quartz oscillator that generates a reference frequency for the phase and frequency detectors. This controls the VCO in the synthesizer PLL, which generates the oscillation signal LO for the mixing operation in the single mixer 4. A programmable divider between the output of the VCO and the phase and frequency detectors determines the frequency f of the oscillating signal LO₀。

Due to the low frequency fs of the switching period of the phase selection signal SEL, it is possible for the FSK signal receiver to have a standard structure. The use of a single branch by the single frequency conversion mixer 4 reduces the electrical power consumption compared to existing receivers. Furthermore, as indicated above, the sensitivity (at-3 dB) of this type of receiver is substantially the same as a conventional receiver with two frequency-converted branches for FSK.

Fig. 4a depicts a first simplified embodiment of a local oscillator incorporating a phase shifting circuit for the FSK radio frequency signal receiver of fig. 2 a. This local oscillator is preferably a frequency synthesizer using sigma-delta synthesis.

This frequency synthesizer therefore comprises a quartz reference oscillator 30 which is able to provide a reference frequency signal Fref to a phase and frequency detector 31 in the PLL. The frequency Fref may be about 26 MHz. In the PLL this phase and frequency detector 31 also receives a divided frequency signal. These divided frequency signals are derived from the oscillation signal LO provided at the output of the VCO34, which are the frequencies divided by the programmable divider 35. The division factor of the divider 35 is programmed by a conventional sigma-delta modulator 36.

This frequency synthesizer further comprises a charge pump 32 receiving the comparison signal from the phase and frequency detector, a low pass filter 33 for filtering the signal provided at the output of the charge pump, and a VCO 34. This VCO34 is controlled by a determined voltage supplied at the output of the low-pass filter 33 to generate an oscillation signal at a predetermined frequency. This predetermined frequency may be, for example, frequency f₀Match it withAt the carrier frequency of the incoming FSK radio frequency signal.

This first embodiment of the frequency synthesizer may generate at the frequency synthesizer output a binary programming word Fn according to the sigma-delta modulator 36 at a predetermined frequency f₀The oscillation signal LO. Via a specific time programming of the sigma-delta modulator 36, a 90 ° phase shift may be performed to change the in-phase oscillating signal to a quadrature signal at the output of the VCO 34. A-90 ° reverse phase shift may also be performed to change the quadrature oscillator signal to an in-phase oscillator signal.

It is also shown in the simplified diagram of fig. 4b that the modulator 36 is programmed by a specific first binary word Fn in order to change the in-phase oscillation signal to a quadrature oscillation signal. According to this first binary word, the desired frequency of the oscillation signal LO is equal to the frequency f at the period Δ t₀With a low compensation frequency f₁And (4) adding. At the end of this period Δ t, the modulator is programmed again by the base binary word Fn to obtain again the frequency f in the oscillation signal LO₀. During this period Δ t, a 90 ° phase shift is performed to change the in-phase oscillation signal to a quadrature oscillation signal at the output of the VCO 34. To perform this phase switching, a phase selection signal (not shown) provides a first binary word Fn to the modulator 36 when changing from a "0" state to a "1" state.

To change the quadrature oscillator signal to an in-phase oscillator signal, the modulator is programmed with a second specific binary word Fn. According to this second binary word, the desired frequency of the oscillating signal is equal to the desired frequency at the period Δ t from the frequency f₀Subtracting the low compensation frequency f₁. At the end of this period Δ t, the modulator is programmed again by the base binary word Fn to obtain again the frequency f in the oscillation signal LO₀. During this period at the oscillator signal phase shift is again changed by 90 deg. to 0 deg. to provide an in-phase oscillator signal at the output of the VCO. To perform this phase switching, a phase selection signal (not shown) provides a second binary word Fn to the modulator 36 when changing from a "1" state to a "0" state, for example. Since this phase shifting method is known, no additional details will be given. It should be noted that with this type of frequency synthesizer, the phase shifting circuit is advantageously integrated in the local oscillator.

It should also be noted that instead of providing the first and second binary words Fn to the sigma-delta modulator 36 during the short period at, it is also conceivable to provide a multiplexer at the synthesizer output. The multiplexer inputs (not shown) receive in-phase and quadrature oscillator signals provided by different types of VCOs. This multiplexer can advantageously be controlled by a phase selection signal SEL to provide an in-phase oscillation signal, or a quadrature oscillation signal, at the output.

Fig. 5 depicts a second simplified embodiment of a local oscillator incorporating a phase shifting circuit for the FSK radio frequency signal receiver of fig. 2 a. This local oscillator is preferably a frequency synthesizer with two delay units 46 and 47 (switchable by a phase selection signal SEL). Since several components of the frequency synthesizer of this second embodiment are identical to those described with reference to fig. 4a, the description thereof will not be repeated for the sake of simplicity.

The difference between this second embodiment of the frequency synthesizer and the first embodiment described above with reference to fig. 4a is therefore that two switchable delay units 46 and 47 are used instead of the sigma-delta modulator. The oscillation signal LO generated by the VCO34 is divided as necessary in a standard N-divider or multi-mode divider 45, and then the divided signals are directed to the input terminals of the first delay unit 46 and the second delay unit 47. The output of each delay cell is connected to an input of a multiplexer 48, wherein the divided output signal of the multiplexer 48 is supplied to the phase and frequency detector 31. The phase select signal SEL causes selection of the split signal to be provided at the output of the multiplexer 48. During the first half of the phase switching period 1/fs, a divided "in-phase" signal is provided to the detector 31 to perform a comparison with the reference signal Fref. During the second successive half of the phase switching period, the detector 31 is provided with a divided "quadrature" signal. Therefore, the VCO34 alternately and continuously generates an in-phase oscillation and a quadrature signal LO at the output terminal in each switching period.

Each delay cell 46, 47 may be implemented by placing an inverter and a voltage controlled delay transmission gate in series. This voltage is controlled to establish the necessary delay provided to the detector 31. The delay can be controlled by m inverters in series, followed by m variable control voltage transmission gates. This therefore forms a ring oscillator which is phase locked to the reference frequency Fref generated by the quartz oscillator 30, for example. In the second delay control unit 47, the ring oscillator comprises n inverters followed by n variable control voltage transmission gates, which are phase locked to the reference frequency Fref. The delay difference between the components of the two delay cells is precisely set by the formula ((1/Fref)/m) - ((1/Fref)/n). In the case where m equals 37 and n equals 31, the reference frequency Fref equals 26MHz, the delay difference is about 100 ps. Frequency f of 2.45GHZ in oscillation signal LO₀The time difference in the split signals provided by the delay units is therefore about 100 ps.

Fig. 6 depicts a third simplified embodiment of a local oscillator incorporating a phase shifting circuit for the FSK radio frequency signal receiver of fig. 2 a. This local oscillator is preferably a frequency synthesizer with two delay units 56 and 57 (switchable by the phase selection signal SEL). Since several components of the frequency synthesizer of this third embodiment are identical to those described with reference to fig. 4a and 5, the description thereof will not be repeated for the sake of simplicity.

This third embodiment of the frequency synthesizer is very similar to the second embodiment shown in fig. 5. In this third embodiment, two delay units 56, 57 are now provided between the reference oscillator 30 and the phase and frequency detector 31. The oscillation signal LO generated by the VCO34 is divided only by the programmable or multi-mode divider 55. This programmable divider 55 provides a divided signal to the phase and frequency detector 31 in the PLL.

Each delay unit 56 and 57 receives a reference signal Fref. The output of each delay cell is connected to the input of a multiplexer 58, so that the reference signal Fref at the output of the multiplexer 58 is supplied to the phase and frequency detector 31. One of the delay units that has to provide the reference signal to the detector 31 is selected in the multiplexer 58 by a phase selection signal SEL. During the first half 1/fs of the phase switching period, an "in-phase" reference signal is provided to the detector 31 to perform a comparison with the split signal from the programmable splitter 55. During the second successive half of the phase switching period, a "quadrature" reference signal is provided to the detector 31. Thus, the VCO34 alternately and continuously generates an in-phase oscillation and a quadrature signal LO at the output terminal every switching period.

The delay units 56, 57 of this third embodiment are similar to the units 46 and 47 described above, as in the second embodiment. Therefore, the description of these delay units 56 and 57 will not be repeated.

It should also be noted that in addition to all the frequency synthesizer embodiments described with reference to fig. 4a, 5 and 6, it is conceivable to first provide a VCO with in-phase oscillation and quadrature signals, the frequency of which is still applicable to the input radio frequency signal. In a first variant, the VCO34 may generate an oscillating signal whose frequency is the frequency f of the FSK radio frequency signal₀Half of that. In this case, a frequency doubler must be provided at the VCO output. By a phase shift of 45 deg. at the VCO output, a phase shift of 90 deg. can be obtained at the doubler output. In a second variation, the VCO may generate an oscillating signal having twice the frequency of the FSK radio frequency signal. In this case, a divider is provided at the VCO output. By a 180 ° phase shift at the VCO output this means a 90 ° phase shift at the output of the splitter.

Fig. 7 shows an embodiment of a phase shift circuit 26 arranged at the input of the FSK radio frequency signal receiver of the second embodiment shown in fig. 2 b. Fig. 7 shows only the input part of the receiver.

The phase shift circuit 26 essentially comprises an array of differently connected switchable capacitors. This array of switchable capacitors is arranged in parallel with the inductor L and the antenna 2 via the LNA 3 to form a resonant circuit. As described below, this resonant circuit must be calibrated so that the FSK radio frequency signal picked up by the antenna is an alternating in-phase FSK radio frequency signal and quadrature FSK radio frequency signal in each successive phase switching cycle. A phase selection signal SEL is applied to this phase shift circuit 26 to perform phase switching in the resonance circuit.

Since this array of switchable capacitors is of a different type, the LNA 3 has two outputs with opposite phases. Thus, an array of switchable capacitors is connected to both outputs of the LNA 3, and to both inputs of the single mixer 4. The array of switchable capacitors thus comprises n capacitor banks connected in parallel to the two output lines of the LNA 3. Each capacitor bank comprises two capacitors C1, C1 ', C2, C2 ', Cn ' and a switch, for example a MOS transistor N1, N2, Nm in series between the two capacitors. The MOS transistors are preferably of NMOS type. The capacitance values of each pair of capacitors of the array are weighted to powers of 2. To select one pair of capacitors or another pair of capacitors from the bank of capacitors to be arranged in parallel with the inductor L, the NMOS transistors N1, N2 to Nm are controlled across gates 1c, 2c to nc so that the transistors conduct via the N-bit configuration word provided by the self-calibration logic circuit 29.

In the first phase, the resonant circuit has to be calibrated by an array of switchable capacitors. This is achieved by basing the switchable phase shifting circuit 26 on properties associated with the amplitude and phase of the parallel resonant circuit. This requires an accurate determination of two points at-3 dB from the maximum resonant gain. These two points (at-3 dB from maximum gain) have a phase difference of exactly 90 deg.. Furthermore, this difference is relatively constant for frequencies within the bandwidth limits, depending on the quality factor of the FSK radio frequency signal receiver. The resonant circuit formed by the capacitor bank simply needs to be calibrated by two binary words sent by the self-calibration logic circuit 29 alternately according to the phase selection signal that controls the self-calibration logic circuit. Due to the two binary words alternately transmitted to the array of switchable capacitors, the phase shift circuit alternately provides the mixer 4 with an in-phase radio frequency signal and a quadrature radio frequency signal.

This calibration takes place by introducing and measuring the test oscillation signal LO. These oscillating test signals LO are supplied via a local oscillator 7To the input of the LNA 3, in particular via a capacitor Cc. Of course, once the array of switchable capacitors is calibrated, the local oscillator no longer needs to provide the oscillation test signal LO to the LNA 3 input. To this end, a switch (not shown) may be provided between the local oscillator output and the LNA 3 input before the capacitor Cc. The other oscillator signal LO from the local oscillator 7, preferably a frequency synthesizer, is supplied directly to the mixer 4 for frequency conversion of the FSK radio frequency signal into the intermediate baseband signal INT. For this direct conversion, the oscillation signal frequency is set equal to the frequency f of the incoming FSK radio frequency signal₀。

To perform the amplitude measurement, first a first measurement circuit 27 is configured, which is connected to the LNA 3 output and the array of switchable capacitors. The purpose of this first measurement circuit 27 is to determine the maximum gain point via the self-calibration logic circuit 29. This self-calibration logic circuit successively makes a certain number of NMOS transistors conductive to place one or several pairs of capacitors of the capacitor bank in parallel until the first measurement circuit determines the maximum gain. Once the maximum gain is determined, a second measurement circuit 28 in parallel with the first measurement circuit 27 receives (e.g., using an attenuator such as a capacitive divider) the signal attenuated by-3 dB. A comparison is made between the second measurement circuit measurement and the first measurement circuit measurement. This allows two points-3 dB from the maximum gain to be determined so that the self-calibration logic circuit 29 provides two binary calibration words in succession to the array of switchable capacitors.

It should be noted that at least the first measurement circuit 27 may be configured to perform well-known enhanced Bessel amplitude measurements. This is achieved by using the exponential characteristic of a weakly inverting MOS transistor coupled with the FSK radio frequency signal to be measured. The sine function is exponential to a zero order Bessel function whose output voltage value decreases as the amplitude of the coupled FSK radio frequency signal increases. To obtain a larger change in terms of amplitude, the known enhanced Bessel detector couples two similar behaviors by placing two complementary NMOS and PMOS transistors and a current source in series between the two terminals of the voltage supply. The output voltage signal is provided to a PMOS transistor source, which is connected to a current source. This detector has a different configuration to exploit the associated virtual quality.

The FSK radio frequency signal receiver described above comprises an integrated circuit in which most of the receiver components are integrated. This integrated circuit may be formed by, for example, 0.18um CMOS technology.

From the given description, a person skilled in the art may devise several variants of a receiver for FSK radio frequency signals without departing from the scope of the invention as defined by the claims. A phase shift circuit may be provided between the antenna and the low noise amplifier. The array of switchable capacitors of the phase shift circuit may be formed by a bank of capacitors having a single capacitor in series with a bipolar or MOS transistor, connected between a single output line of the LAN and a ground terminal. This array of switchable capacitors may also be connected directly to the antenna.

Claims (13)

1. Receiver (1) for frequency shift keying, FSK, modulated low-rate radio frequency signals, said receiver comprising:

an antenna (2) for receiving an FSK radio frequency signal;

a low noise amplifier (3) for amplifying and filtering the signal extracted by the antenna;

a local oscillator (7) for providing an oscillating signal (LO) having the same frequency as the carrier frequency of the incoming FSK radio frequency signal;

a phase shift circuit (16, 26) for performing a 0 ° to 90 ° phase shift and a reverse phase shift of the oscillation signal (LO) or the input FSK radio frequency signal in each half of the phase switching period (1/fs) to alternately and continuously generate an in-phase oscillation signal and a quadrature oscillation signal or an in-phase input FSK radio frequency signal and a quadrature input FSK radio frequency signal;

a mixer (4) for mixing the in-phase and quadrature signals with the filtered and amplified input FSK radio frequency signal or mixing the oscillation signal (LO) with the in-phase and quadrature FSK radio frequency signals to alternately generate intermediate in-phase and intermediate quadrature baseband signals;

at least one low-pass filter (8) for filtering the intermediate in-phase signal and the intermediate quadrature signal; and

a demodulation stage (20) for demodulating data (Dout) from the filtered intermediate in-phase signal (Im) and the filtered intermediate quadrature signal (Qm);

characterized in that the receiver is arranged such that the phase shifting circuit (16, 26) is switched by a phase selection signal to a phase switching cycle frequency (fs) which is between 10 and 20 times lower than the frequency deviation (Δ f) of the modulated data in the FSK radio frequency signal and between 10 and 20 times higher than the data rate.

2. The receiver (1) of claim 1, characterized in that the demodulation stage (20) input comprises a demultiplexer (13) for receiving the filtered intermediate in-phase signal and the filtered intermediate quadrature signal, the demultiplexer (13) being controlled by a phase selection Signal (SEL) to periodically provide the filtered intermediate in-phase signal (Im) at a first output and the filtered intermediate quadrature signal (Qm) at a second output, the demodulation stage (20) input further comprising a data demodulator (12) for receiving the filtered intermediate in-phase signal and the filtered intermediate quadrature signal from the demultiplexer (13) to provide the data signal (D)_OUT)。

3. Receiver (1) according to claim 2, characterized in that said demodulation stage (20) comprises a first magic circuit (14) between the first output of said demultiplexer (13) and said data demodulator (12), and a second magic circuit (15) between the second output of said demultiplexer (13) and said data demodulator (12), each magic circuit comprising a pseudo-digital phase-locked loop for continuously generating an in-phase signal or a quadrature signal to reconstruct an intermediate in-phase signal or an intermediate quadrature signal after any interruption caused by the phase switching produced in the demultiplexer (13) by the phase selection Signal (SEL).

4. A receiver (1) as claimed in claim 3, characterized in that each magic circuit (14, 15) comprises a counter for measuring the period of the selected filtered intermediate signal; and a digital phase-locked loop, which undergoes a frequency adjustment once per switching operation, the adjusted phase being equal to the average phase measured during the duration of the filtered intermediate signal before any interruption due to the phase switching, to continuously generate, after the interruption, an intermediate in-phase signal or an intermediate quadrature signal to be supplied to the demodulator (12) for continuously demodulating the filtered intermediate in-phase signal and the intermediate quadrature signal from the two magic circuits (14, 15).

5. A receiver (1) as claimed in claim 2, characterized in that the data demodulator (12) is a D flip-flop for receiving at one input the filtered intermediate in-phase signal (Im) or the filtered intermediate quadrature signal (Qm) and for calculating the clock from the other filtered intermediate quadrature signal or intermediate in-phase signal.

6. Receiver (1) according to claim 1, characterized in that the phase shift circuit (16) is integrated in a local oscillator, which is a frequency synthesizer, to provide alternately and continuously an in-phase oscillator signal and a quadrature oscillator signal.

7. The receiver (1) of claim 6, wherein the frequency synthesizer comprises: a quartz reference oscillator (30) capable of supplying a reference frequency signal (Fref) to a phase and frequency detector (31) in a phase-locked loop; the quartz reference oscillator comprises a charge pump (32) connected to the output of the detector (31); a low-pass filter (33); a voltage controlled oscillator (34) receiving the filtered signal to generate an oscillation signal (LO); a programmable or multi-mode divider (35) for frequency dividing the oscillating signal in combination with a sigma-delta modulator (36) to provide a divided signal to the phase and frequency detector (31), said sigma-delta modulator being programmed with a binary word (Fn) at each phase switching period, whereby the voltage controlled oscillator (34) alternately and continuously provides an in-phase oscillating signal and a quadrature oscillating signal.

8. The receiver (1) of claim 6, wherein the frequency synthesizer comprises: a quartz reference oscillator (30) capable of supplying a reference frequency signal (Fref) to a phase and frequency detector (31) in a phase-locked loop; the quartz reference oscillator comprises a charge pump (32) connected to the output of the detector (31); a low-pass filter (33); a voltage controlled oscillator (34) receiving the filtered signal to generate an oscillation signal (LO); a multi-mode divider or N-divider (45) for frequency dividing the oscillation signal; two delay units (46, 47) for receiving the divided signals from the divider (45); and a multiplexer (48) connected to the two delay units and controlled by a phase selection Signal (SEL) to alternately supply the divided signals to the phase and frequency detector (31) via the first delay unit (46) and the second delay unit (47), so that the voltage controlled oscillator (34) alternately and continuously generates the in-phase oscillation signal and the quadrature oscillation signal.

9. The receiver (1) of claim 6, wherein the frequency synthesizer comprises: a quartz reference oscillator (30) capable of supplying a reference frequency signal (Fref) to two delay units (56, 57) connected to a multiplexer (58) controlled by a phase selection Signal (SEL) to alternately supply the reference signal to a phase and frequency detector (31) in a phase locked loop via a first delay unit (56) and a second delay unit (57); the quartz reference oscillator comprises a charge pump (32) connected to the output of the detector (31); a low-pass filter (33); a voltage controlled oscillator (34) receiving the filtered signal to alternately generate an in-phase oscillation signal and a quadrature oscillation signal; an N-divider or multi-mode divider (55) for frequency dividing the oscillation signal and providing the divided signal to the phase and frequency detector (31).

10. A receiver (1) as claimed in claim 1, characterized in that the phase shift circuit (26) is arranged between the low noise amplifier LNA (3) and the single mixer (4).

11. The receiver (1) of claim 10, wherein the phase shift circuit (26) comprises: an array of switchable capacitors arranged in parallel with the inductor (L) and the antenna (2) via a low noise amplifier (3) to define a resonant circuit; a self-calibration logic circuit (29), controlled by a phase selection Signal (SEL), for alternately providing two binary configuration words to the array of switchable capacitors to provide an in-phase radio frequency signal and a quadrature radio frequency signal to the mixer (4).

12. The receiver (1) of claim 11, wherein the phase shift circuit (26) comprises: a first measurement circuit (27) for determining a maximum gain point of the resonant circuit via a self-calibration logic circuit (29); and a second measurement circuit (28) for determining two points of attenuation-3 dB relative to a point of maximum gain to configure a self-calibration logic circuit that alternately and successively provides two configuration words to the array of switchable capacitors to perform a phase shift of 0 ° to 90 ° and a reverse phase shift in the input FSK radio frequency signal.

13. A receiver (1) as claimed in claim 12, wherein the local oscillator (7) is arranged to provide an oscillating signal to the low noise amplifier (3) during a calibration period in which the array of switchable capacitors is calibrated.