HK1169746B - High-efficiency solar cell structures and methods of manufacture - Google Patents

Description

High efficiency solar cell structure and method of manufacture

Information of related applications

The present application claims priority from U.S. provisional application No. 61/171,194 entitled "High-Efficiency solar cell Structures and Methods of Manufacture" filed on 21/4/2009, the entire contents of which are hereby incorporated by reference. All aspects of the invention may be combined with any of the above applications.

Technical Field

The present invention relates to a solar cell. More particularly, the present invention relates to improved solar cell structures having increased cell efficiency and methods of making the same.

Background

Solar cells provide a wide range of benefits to society by converting a substantially unlimited amount of solar energy into usable electrical energy. As their use increases, certain economic factors become important, such as high volume manufacturing and efficiency.

High volume manufacturing is generally considered to achieve a high degree of cost effectiveness and efficiency if the number of manufacturing steps, and the complexity of each step, can be minimized.

There is a great need in the industry for completed solar cells to have efficiencies of 20% or more, however, it is known that cells implementing such efficiencies often suffer from complexity in cell structure and/or complexity in manufacturing.

Therefore, there is a need for solar cells that achieve high operating efficiency and that can be manufactured in a cost-effective manner.

Disclosure of Invention

The shortcomings of the prior art are overcome and additional advantages are provided by the present invention which, in one aspect, provides any one or combination of the solar cell structures disclosed below, which generally include a central substrate, a conductive layer, an anti-reflective layer, a passivation layer, and/or an electrode. The multiple functional layers provide a combination of passivation, transparency, sufficient conductivity for the longitudinal carrier flow, junction (junction), and/or varying degrees of anti-reflection. Improved manufacturing methods are also disclosed, including single-sided CVD deposition processes and thermal treatments for layer formation and/or conversion.

In one aspect, the invention includes a method of making these structures, the method comprising: providing a wafer as a central substrate; depositing or growing an interface passivation layer on the substrate; depositing a conductive layer on the passivation layer; providing a heat treatment; optionally depositing an antireflective layer (possibly including a back mirror); and providing metallization as an electrode.

In one embodiment, the invention includes applying a thermal treatment to produce a multifunctional film that is separated into a surface passivating interfacial layer and a highly doped polycrystalline passivation layer with high transparency.

In one embodiment, the invention includes depositing an amorphous silicon-containing compound and initiating crystallization into a polycrystalline film using a thermal process.

In one embodiment, the invention includes depositing an amorphous silicon-containing compound and utilizing a thermal treatment to crystallize the film and increase optical transmission.

In one embodiment, the invention includes depositing an amorphous silicon-containing compound and utilizing a thermal treatment to activate the dopant atoms in the compound.

In one embodiment, the invention includes depositing an amorphous silicon-containing compound and utilizing a heat treatment greater than 500 ℃ to activate the dopant atoms in the compound and diffuse the dopant atoms into the substrate wafer to provide a high-low junction or p-n junction.

System and computer program products corresponding to the above-described methods are also described and claimed herein.

Further, additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.

Drawings

The subject matter of the invention is clearly described in the claims of the present application. The above and other objects, features, and advantages of the present invention will become apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:

fig. 1 is an energy band diagram of an n-type crystalline silicon solar cell having a doped polysilicon layer and a passivated interface;

FIG. 2 is a partial cross-sectional view of a solar cell depicting one minority and majority carrier flow for a front-side junction, p-type wafer;

FIG. 3 is a partial cross-sectional view of a solar cell depicting one minority and majority carrier flow for a back-junction, p-type wafer;

FIG. 4 is a partial cross-sectional view of a solar cell depicting one minority and majority carrier flow for a front-side junction, n-type wafer;

FIG. 5 is a partial cross-sectional view of a solar cell depicting one minority and majority carrier flow for a back-junction, n-type wafer;

FIG. 6 is a partial cross-sectional view of a solar cell having an n-type front side, an n-or p-type wafer, and a p-type back side;

FIG. 7 is a partial cross-sectional view of a solar cell having an n-type front side, an n-or p-type wafer, a p-type back side in a double sided configuration;

FIG. 8 is a partial cross-sectional view of a solar cell having an n-type front side, an n-type wafer, a p-type back side and including an isolated anti-reflective coating;

FIG. 9 is a partial cross-sectional view of a solar cell having an n-type front side, an n-type wafer, a p-type back side and including a multifunctional transparent conductive highly doped silicon compound layer;

FIG. 10 is a partial cross-sectional view of a solar cell having an n-or p-type wafer, a modified n-type front side including some front side layers, and a p-type back side;

FIG. 11 is a partial cross-sectional view of a solar cell having a p-type front side, an n-or p-type wafer, and an n-type back side;

FIG. 12 is a partial cross-sectional view of a solar cell having a p-type front side, an n-or p-type wafer, an n-type back side in a double sided configuration;

FIG. 13 is a partial cross sectional view of a solar cell having a p-type front side, a p-type wafer, an n-type back side and including an isolated anti-reflective coating;

FIG. 14 is a partial cross sectional view of a solar cell having a p-type front side, a p-type wafer, an n-type back side and including a multifunctional transparent conductive highly doped silicon compound layer;

FIG. 15 is a partial cross-sectional view of a solar cell having an n-or p-type wafer, a modified p-type front side including some front side layers, and an n-type back side;

FIG. 16 is a partial cross-sectional view of a solar cell in which a glass or other transparent film with embedded electrodes is pressed or bonded onto the cell;

FIG. 17 is a partial cross sectional view of a solar cell in which a glass or other transparent film with embedded electrodes is pressed or bonded onto the cell, which includes a partial electrode on the back side; and

FIG. 18 is a partial cross sectional view of a solar cell in which an additional silicon buffer layer is formed;

all of these figures are in accordance with the present invention.

Detailed Description

Referring to the band diagrams and partial cross-sectional views of the solar cell shown in fig. 1-5, it is assumed that solar radiation preferentially strikes one surface of the solar cell, which is commonly referred to as the front side. In order to achieve high energy conversion efficiency of incident photons into electrical energy, efficient absorption of photons within the silicon substrate material forming the cell is important. This can be achieved by low parasitic optical absorption of photons within all layers except the substrate itself.

For simplicity, the geometric surface shape of the layer surface is not depicted in these figures (e.g., surface textures such as pyramids, or other surface textures may be formed on the layer surface), however, it should be understood that the geometric shapes and/or surfaces may be configured in any shape that is beneficial for improving solar cell efficiency and that such shapes and/or surfaces are within the scope of the present invention.

An important parameter for high solar cell efficiency is surface passivation. Surface passivation inhibits recombination of electrons and holes at or near certain physical surfaces within the solar cell. Surface recombination can be reduced by applying a dielectric layer. These layers reduce the interface energy state density and thus the number of recombination centers. Two examples are thermally grown silicon oxide and PECVD deposited silicon nitride. Another example of a surface passivation layer is intrinsic amorphous silicon. These layers may also provide charge that reduces the number of carriers of opposite polarity and reduces the rate of recombination by this principle. Two examples are silicon nitride and aluminum oxide.

Another way to reduce the number of carriers of a type close to the surface is to diffuse doping atoms of the same doping type as the layer or of opposite doping. In this case, a doping level exceeding the doping of the layer is necessary to obtain a high-low junction (also commonly referred to as back surface field or front surface field) or a p-n junction. This can be combined with other methods of surface passivation as described above.

Surface passivation may play an important role in achieving high efficiency solar cells. In most solar cell structures according to the present invention as described below, the multilayer or multifunctional layer can provide excellent surface passivation. This can be achieved by a very steep doping profile and additional passivation of the interface with layers having a low interface energy state density and a high band gap, creating a tunnel barrier for passage of substrate minority carriers. The corresponding band diagram is shown in fig. 1. The solid line represents the case of an n-type crystalline silicon wafer with a passivated interface and a doped polysilicon passivation layer. The dashed line represents the case of an n-type crystalline silicon wafer and a bilayer structure of intrinsic amorphous silicon and subsequent doped amorphous silicon layers, sometimes referred to as a heterojunction cell.

These structures provide another benefit for high efficiency solar cells: recombination in the area under the contact may be as low as the area without the contact. The contacts may be shielded by passivation. Thus, the contact area of the optical properties can be optimized, minimizing the loss of resistance, but the recombination of carriers is decoupled.

The disclosed cell structures can be classified as either front-junction or back-junction cells, depending on the materials selected, and the type and concentration of doping. In a front junction cell, minority carriers (in the case of a p-type wafer, these are electrons) are collected on the illuminated side. In the case of a back junction cell, minority carriers are collected on the side opposite to the irradiated side. The current profiles for the p-type and n-type wafers are shown in the partial cross-sectional views of the solar cell of fig. 2-5.

Fig. 2 shows the carrier flow of the solar cell 20, wherein minority carriers (solid lines) flow from the p-type wafer 25 with the front-side junction towards the front electrode 21. These electrons need to take advantage of the lateral flow within the thin n-type emitter 22 to reach the electrode 21, and the lateral sheet resistance of the emitter 22 increases the resistive losses. The majority carriers (dashed lines) can take the shortest geometric path to the full-area back electrode 29.

Fig. 3 shows the carrier flow from a solar cell 30 with a back-junction p-type wafer 35. The majority carriers (dashed lines) can exploit the conductivity of the entire wafer to reach the front electrode 31. Minority carriers (solid lines) can take the shortest geometric path to the back n-type emitter 38 and their migration within the emitter is longitudinal rather than predominantly lateral. This back junction structure reduces the lateral conductivity requirements of the emitter layer.

Fig. 4 shows the carrier flow of the solar cell 40, wherein minority carriers (solid lines) flow from the n-type wafer 45 with the front-side junction towards the front electrode 41. These holes need to reach the electrode 41 by means of lateral flow within the thin p-type emitter 42, and the lateral conductivity of this emitter determines the resistive losses. The majority carriers (dashed lines) can take the shortest geometric path to the full area back electrode 49.

Fig. 5 shows the carrier flow from a solar cell 50 with an n-type wafer 55 having a back junction. The majority carriers (dashed lines) can reach the front electrode 51 using the conductivity of the entire wafer. Minority carriers (solid lines) can take the shortest geometric path to the back p-type emitter 58 and their migration within the emitter is longitudinal rather than predominantly lateral. This back junction structure reduces the lateral conductivity requirements of the emitter layer.

Back junction cells with full area back contacts have the advantage that minority carriers do not have to flow through the emitter laterally to reach the contacts, their migration within the emitter being predominantly vertical. This reduces losses due to lateral migration of minority carriers within the emitter. Because coverage of the full contact area is a requirement that benefits from this property of the structure, shielding contacts are important, for example, because metal is in contact with the layer everywhere ("full area contact coverage"), and therefore minority carriers are not required to flow laterally to the nearest contact, as they are shown in the emitter in, for example, fig. 4. Exemplary cell structure: n-type front side, n-or p-type wafer, p-type back side:

fig. 6 is a partial cross-sectional view of a solar cell 60 having an n-type front side, an n-or p-type wafer, and a p-type back side.

Metal electrodes 61 and 69 are located on outer layers 62 and 68, respectively. This has the advantage that the metal does not need to pass through the underlying layers before it contacts the wafer. The silicon bulk wafer (silicon bulk wafer)65 is also shielded from the contact interface, thereby minimizing contact interface carrier recombination. This structure has an n-type front surface on which minority carriers (electrons) are collected for a p-type wafer 65. Thus, the composite layers 62, 63, and 64 are required to have a maximum lateral sheet resistance of, for example, 500 Ohm/sq. For an n-type wafer, this structure collects minority carriers (holes) on the back side. Thus, the current patterns in the solar cell are different and the requirements for lateral conductivity of layer 62 are less stringent. The layers of exemplary battery 60 include the following:

61: and a front metal electrode.

62: the refractive index of the transparent conductive film is more than 1.4 and less than n and less than 3; the thickness is more than 20nm and less than 110 nm; the sheet resistance of the p-type wafer (front junction solar cell) is less than 500Ohm/sq and the specific resistance of the n-type wafer (back junction solar cell) is rho < 1000Ohm cm. Examples include transparent conductive oxides such as indium tin oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, tantalum oxide, antimony tin oxide, germanium oxide, zirconium oxide, titanium oxide, gallium oxide, cadmium antimony oxide.

63: electrically passivated electrically conductive thin film, highly n-doped 1e18cm^-3＜N_D＜5e21cm^-3(ii) a The thickness is more than 2nm and less than 50 nm; the specific resistance is rho < 1000Ohm cm. Examples include:

● n-type amorphous or polycrystalline silicon carbide: phosphorus doped silicon carbide, nitrogen doped silicon carbide;

● n-type amorphous or polycrystalline silicon: phosphorus-doped amorphous silicon, nitrogen-doped amorphous silicon;

● n-type amorphous or polycrystalline diamond-like carbon: nitrogen doped diamond-like carbon.

Any of the above listed examples may include oxygen and hydrogen (n-doped SiC)_xO_yH_z(ii) a n-doped SiN_xO_yH_z)。

64: electrically passivating the interfacial layer; the thickness is less than 10 nm; because of the small thickness, there is no requirement for conductivity; due to the small thickness, there is no absorption limitation. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

65: an n-type or p-type crystalline silicon wafer; the thickness is w < 300um, the base resistance of the n-type wafer is 0.5Ohm cm < rho < 20Ohm cm, and the base resistance of the p-type wafer is 0.1Ohm cm < rho < 100Ohm cm.

66: electrically passivating the interfacial layer; the thickness is less than 10 nm; because of the small thickness, there is no requirement for conductivity; due to the small thickness, there is no absorption limitation. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

67: electrically passivated electrically conductive thin films, highly p-doped 1E18-5E21cm³(ii) a The specific resistance is rho < 1000Ohm cm. Examples include:

● p-type amorphous or polycrystalline silicon carbide: boron-doped silicon carbide, aluminum-doped silicon carbide, gallium-doped silicon carbide;

● p-type amorphous or polycrystalline silicon: boron-doped silicon, aluminum-doped silicon, gallium-doped silicon;

● p-type amorphous or polycrystalline diamond-like carbon: boron doped diamond-like carbon, aluminum doped diamond-like carbon.

[0058]Any of the above examples may include oxygen and hydrogen (p-doped SiC)_xO_yH_z(ii) a p-doped SiN_xO_yH_z)。

68: the refractive index of the transparent conductive film is more than 1.4 and less than n and less than 3; the specific resistance is rho < 1000Ohm cm. Examples include conductive oxides such as indium tin oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, tantalum oxide, antimony tin oxide, germanium oxide, zirconium oxide, titanium oxide, gallium oxide, cadmium antimony oxide.

69: and a back metal electrode.

Fig. 7 is a partial cross-sectional view of a solar cell 70 having an n-type front side, an n-or p-type wafer, and a p-type back side in a double-sided configuration. Battery 70 is similar to battery 60, but includes a local electrode 79 on the back side. Due to the local structure on this backside, photons impinging from the rear of the solar cell can be absorbed and electron-hole pairs are generated within the wafer 75. This may increase the power output generated by the solar cell in outdoor operation, wherein the reflectivity may be used with low manufacturing and installation costs of the auxiliary module.

Fig. 8 is a partial cross-sectional view of a solar cell 80 having an n-type front side, an n-type wafer, a p-type back side, and including an isolated anti-reflective coating. This structure is particularly advantageous for material combinations in which the conductive layer on the front side of the cell structures 60 and 70 has a high absorption. By placing the electrode 81 directly on the contact layer 83, the conductivity requirement for the layer 82 can be eliminated and a conventional anti-reflective coating film (which is an insulator) can be used. The layers of exemplary battery 80 include the following:

81: and a front metal electrode.

82: the refractive index of the anti-reflection film is more than 1.4 and less than n and less than 3; the thickness is more than 20nm and less than 110 nm. Examples include silicon nitride, silicon carbide, silicon oxide, transparent conductive oxides.

83: an electrically passivated conductive film; the thickness is less than 110 nm; highly n-doped 1e18cm^-3＜N_D＜5e21cm^-3The specific resistance is rho < 1000Ohm cm. Examples include:

● n-type amorphous or polycrystalline silicon carbide: phosphorus doped silicon carbide, nitrogen doped silicon carbide;

● n-type amorphous or polycrystalline silicon: phosphorus-doped amorphous silicon, nitrogen-doped amorphous silicon;

● n-type amorphous or polycrystalline diamond-like carbon: nitrogen doped diamond-like carbon.

Any of the above examples may include oxygen and hydrogen (n-doped SiC)_xO_yH_z(ii) a n-doped SiN_xO_yH_z)。

84: electrically passivating the interfacial layer; the thickness is less than 10 nm; because of the small thickness, there is no requirement for conductivity; due to the small thickness, there is no absorption limitation. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

85: an n-type crystalline silicon wafer; the thickness is w < 300um, and the base resistance of the n-type wafer is 0.5Ohm cm < rho < 20Ohm cm.

86: electrically passivating the interfacial layer; the thickness is less than 10 nm; because of the small thickness, there is no requirement for conductivity; due to the small thickness, there is no absorption limitation. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

87: electrically passivated conducting film, highly doped p-doped 1e18cm^-3＜N_A＜5e21cm^-3(ii) a The specific resistance is rho < 1000Ohm cm. Examples include:

● p-type amorphous or polycrystalline silicon carbide: boron-doped silicon carbide, aluminum-doped silicon carbide, gallium-doped silicon carbide;

● p-type amorphous or polycrystalline silicon: boron-doped silicon, aluminum-doped silicon, gallium-doped silicon;

● p-type amorphous or polycrystalline diamond-like carbon: boron doped diamond-like carbon, aluminum doped diamond-like carbon.

Any of the above examples may comprise oxygen and hydrogen (p-doped)SiC_xO_yH_z(ii) a p-doped SiN_xO_yH_z)。

88: the refractive index of the transparent conductive film is more than 1.4 and less than n and less than 3; the specific resistance is rho < 1000Ohm cm. Examples include transparent conductive oxides such as indium tin oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, tantalum oxide, antimony tin oxide, germanium oxide, zirconium oxide, titanium oxide, gallium oxide, cadmium antimony oxide.

89: and a back metal electrode.

Fig. 9 is a partial cross-sectional view of a solar cell 90 having an n-type front side, an n-type wafer, a p-type back side, and including a multifunctional transparent, conductive, highly doped silicon compound layer. This aspect of the invention is an improvement over the others described above in that, for example, the role of layers 62 and 63 of solar cell 60 of fig. 6 (and any other similar layers in any of the other embodiments disclosed herein) is incorporated into a multifunctional layer 93a as described in fig. 9. This layer may be electrically passivated, transparent, and have sufficient conductivity to allow longitudinal carrier flow to the electrodes (back junction solar cells), which provides a junction with the wafer 95 and/or reduces the reflectivity of incident light (e.g., anti-reflection coating). On the back side, layer 97a may incorporate layers 67 and 68 of solar cell 60 of fig. 6, for example (and any other similar layers in any other embodiments disclosed herein). Layer 97a provides a junction with wafer 95 having a refractive index such that photons of wavelengths greater than 900nm produce high reflectivity and an electrical conductivity sufficient to allow longitudinal carrier flow from wafer 95 to metal electrode 99. The layers of exemplary battery 90 include the following:

91: and a front metal electrode.

93 a: the refractive index of the electrically passivated transparent conductive film is more than 1.4 and less than n and less than 3; the thickness is more than 20nm and less than 110 nm; the specific resistance of the n-type wafer is rho < 1000Ohm cm; highly doped n-doped 1e18cm^-3＜N_D＜5e21cm^-3. Examples include:

● n-type amorphous or polycrystalline silicon carbide: phosphorus doped silicon carbide, nitrogen doped silicon carbide;

● n-type amorphous or polycrystalline silicon: phosphorus-doped amorphous silicon, nitrogen-doped amorphous silicon;

● n-type amorphous or polycrystalline diamond-like carbon: nitrogen doped diamond-like carbon.

Any of the above examples may include oxygen and hydrogen (n-doped SiC)_xO_yH_z(ii) a n-doped SiN_xO_yH_z)。

94: electrically passivating the interfacial layer; the thickness is less than 10 nm; because of the small thickness, there is no requirement for conductivity; due to the small thickness, there is no absorption limitation. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

95: an n-type or p-type crystalline silicon wafer; the thickness is w less than 300um, the base resistance of the n-type wafer is 0.5Ohm cm < rho < 20Ohm cm, and the base resistance of the p-type wafer is 0.1Ohm cm < rho < 100Ohm cm.

96: electrically passivating the interfacial layer; the thickness is less than 10 nm; because of the small thickness, there is no requirement for conductivity; due to the small thickness, there is no absorption limitation. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

97 a: the specific resistance of the electrically passivated transparent conductive film is rho < 1000Ohm cm. Examples include:

● p-type amorphous or polycrystalline silicon carbide: boron-doped silicon carbide, aluminum-doped silicon carbide, gallium-doped silicon carbide;

● p-type amorphous or polycrystalline silicon: boron-doped silicon, aluminum-doped silicon, gallium-doped silicon;

● p-type amorphous or polycrystalline diamond-like carbon: boron doped diamond-like carbon, aluminum doped diamond-like carbon.

Any of the above examples may include oxygen and hydrogen (p-doped SiC)_xO_yH_z(ii) a p-doped SiN_xO_yH_z)。

99: and a back metal electrode.

Fig. 10 is a partial cross-sectional view of a solar cell 100 having an n-or p-type wafer, a modified n-type front side including certain front side layers, and a p-type back side. The latter surface structure (omitted for convenience) may be accomplished according to any other structure described herein.

This structure is particularly advantageous for material combinations where the layers x3 and x4 on the front surface of the structure such as disclosed above have unacceptably high absorbency. (the x3 and x4 symbols, which denote the above-mentioned layers ending with reference numerals 3, 3a, 4a, respectively, are explained further below). In cell 100, by disposing layers 103 and 104 only under the contacts, their optical properties (refractive index, absorption) are not important for cell efficiency. Resistive losses occur only by the flow of longitudinal carriers to the contacts 101. Layers 102, 104b and 105b also do not have to shield contacts so they can optimize transmittance and surface passivation. This will facilitate the flow of current to the contacts and also may place the contact structures at a large distance from each other if they provide lateral conductivity. This reduces optical shielding losses. This structure works best with a back junction because the requirement for lateral conductivity of layers 102, 104b and 105b is eliminated. The layers of the exemplary battery 100 include the following:

101: and a front metal electrode.

102: the refractive index of the anti-reflection film is more than 1.4 and less than n and less than 3; the thickness is less than 150 nm. Examples include silicon nitride, silicon carbide, silicon oxide, titanium oxide, transparent conductive oxides.

103: an electrically passivated conductive film; for example, it has a thickness of < 50 nm; for example, the specific resistance is rho < 1000Ohm cm. Examples include:

● n-type amorphous or polycrystalline silicon carbide: phosphorus doped silicon carbide, nitrogen doped silicon carbide;

● n-type amorphous or polycrystalline silicon: phosphorus-doped amorphous silicon, nitrogen-doped amorphous silicon;

● n-type amorphous or polycrystalline diamond-like carbon: nitrogen doped diamond-like carbon.

Any of the above examples may include oxygen and hydrogen (n-doped SiC)_xO_yH_z(ii) a n-doped SiN_xO_yH_z)。

104: electrically passivating the interfacial layer; the thickness is less than 10 nm; because of the small thickness, there is no requirement for conductivity; due to the small thickness, there is no absorption limitation. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

104 b: electrically passivating the interfacial layer; the thickness is less than 110 nm. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polysilicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride, silicon carbide, or a stack of two or more of these materials.

105: an n-type or p-type crystalline silicon wafer; the thickness is w less than 300um, the base resistance of the n-type wafer is 0.5Ohm cm < rho < 20Ohm cm, and the base resistance of the p-type wafer is 0.1Ohm cm < rho < 100Ohm cm.

105 b: a phosphorus diffused silicon layer (optionally present) having a sheet resistance > 70 Ohm/sq.

The above structures are not mutually exclusive and any feature of one structure may be applied to any other structure in accordance with the invention.

Exemplary cell structure: p-type front side, n-or p-type wafer, n-type back side:

fig. 11 is a partial cross-sectional view of a solar cell 110 having a p-type front side, an n-or p-type wafer, and an n-type back side.

In this cell, metal electrodes 111 and 119 are disposed on outer layers 112 and 118, respectively. This has the advantage that the metal does not need to penetrate the underlying layer before contacting the wafer. The bulk silicon wafer 115 is also shielded from the contact interface, thereby minimizing contact interface carrier recombination. This structure has a p-type front surface, which for an n-type wafer collects minority carriers (holes) on the front surface. Thus, the bonding layers 112, 113 and 114 are allowed to have a maximum lateral sheet resistance of 500 Ohm/sq. For a p-type wafer, this structure collects minority carriers (electrons) on the back side. Thus, the current patterns in the solar cell are different and the requirements on the lateral conductivity of the layer 112 are less stringent. The layers of the exemplary battery 110 include the following:

111: and a front metal electrode.

112: the refractive index of the transparent conductive film is more than 1.4 and less than n and less than 3; the thickness is less than 110 nm; the sheet resistance of the n-type wafer is less than 500Ohm/sq, and the specific resistance of the p-type wafer is rho < 1000Ohm cm. Examples include transparent conductive oxides such as indium tin oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, tantalum oxide, antimony tin oxide, germanium oxide, zirconium oxide, titanium oxide, gallium oxide, cadmium antimony oxide.

113: electrically passivated conducting film, highly doped p-doped 1e18cm^-3＜N_A＜5e21cm^-3(ii) a The specific resistance is rho < 1000Ohm cm. Examples include:

● p-type amorphous or polycrystalline silicon carbide: boron-doped silicon carbide, aluminum-doped silicon carbide, gallium-doped silicon carbide;

● p-type amorphous or polycrystalline silicon: boron-doped silicon, aluminum-doped silicon, gallium-doped silicon;

● p-type amorphous or polycrystalline diamond-like carbon: boron doped diamond-like carbon, aluminum doped diamond-like carbon.

Any of the above examples may include oxygen and hydrogen (p-doped SiC)_xO_yH_z(ii) a p-doped SiN_xO_yH_z)。

114: electrically passivating the interfacial layer; less than 10 nm; because of the small thickness, there is no requirement for conductivity; due to the small thickness, there is no absorption limitation. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

115: an n-type or p-type crystalline silicon wafer; the thickness is w less than 300um, the base resistance of the n-type wafer is 0.5Ohm cm < rho < 20Ohm cm, and the base resistance of the p-type wafer is 0.1Ohm cm < rho < 100Ohm cm.

116: electrically passivating the interfacial layer; the thickness is less than 10 nm; because of the small thickness, there is no requirement for conductivity; due to the small thickness, there is no absorption limitation. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

117: an electrically passivated transparent conductive film; highly doped n-doped 1e18cm^-3＜N_D＜5e21cm^-3(ii) a For example, a thickness of 2nm < thickness < 50nm or greater; the specific resistance is rho < 1000Ohm cm. Examples include:

● n-type amorphous or polycrystalline silicon carbide: phosphorus doped silicon carbide, nitrogen doped silicon carbide;

● n-type amorphous or polycrystalline silicon: phosphorus-doped amorphous silicon, nitrogen-doped amorphous silicon;

● n-type amorphous or polycrystalline diamond-like carbon: nitrogen doped diamond-like carbon.

Any of the above examples may comprise oxygen and hydrogen (n-doped SiC)_xO_yH_z(ii) a n-doped SiN_xO_yH_z)。

118: the refractive index of the transparent conductive film is more than 1.4 and less than n and less than 3; the specific resistance is rho < 1000 Ohmcm. Examples include transparent conductive oxides such as indium tin oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, tantalum oxide, antimony tin oxide, germanium oxide, zirconium oxide, titanium oxide, gallium oxide, cadmium antimony oxide.

119: and a back metal electrode.

Fig. 12 is a partial cross-sectional view of a solar cell 120 having a p-type front side, an n-or p-type wafer, and an n-type back side in a double-sided configuration. Cell 120 is similar to cell 110, but includes a local electrode 129 on the back side. Due to the local structure on the backside, photons impinging from the rear of the solar cell can be absorbed and electron-hole pairs are generated within the wafer 125. This may improve the efficiency of solar cell formation in outdoor operating conditions, wherein the reflectivity may be used with low manufacturing and installation costs of the auxiliary module.

Fig. 13 is a partial cross-sectional view of a solar cell 130 cell having a p-type front side, a p-type wafer, an n-type back side, and including an isolated anti-reflective coating. This structure is particularly advantageous for material combinations in which the conductive layer on the front side of the cell structures 110 and 120 has a high absorption. By placing the electrode 131 directly on the contact layer 133, the conductivity requirement for the layer 132 is eliminated and a conventional anti-reflective coating film (which is an insulator) can be used. This structure works best with the back side junction because the lateral conductivity requirements of layers 133 and 134 are not critical. The layers of exemplary battery 130 include the following:

131: and a front metal electrode.

132: the refractive index of the anti-reflection film is more than 1.4 and less than n and less than 3; less than 150 nm. Examples include silicon nitride, silicon carbide, silicon oxide, aluminum oxide, titanium oxide, transparent conductive oxide.

133: an electrically passivated transparent conductive film; the thickness is less than 110 nm; the specific resistance is rho < 1000 Ohmcm. Examples include:

● p-type amorphous or polycrystalline silicon carbide: boron-doped silicon carbide, aluminum-doped silicon carbide, gallium-doped silicon carbide;

● p-type amorphous or polycrystalline silicon: boron-doped silicon, aluminum-doped silicon, gallium-doped silicon;

● p-type amorphous or polycrystalline diamond-like carbon: boron doped diamond-like carbon, aluminum doped diamond-like carbon.

Any of the above examples may include oxygen and hydrogen (p-doped SiC)_xO_yH_z(ii) a p-doped SiN_xO_yH_z)。

134: electrically passivating the interfacial layer; the thickness is less than 10 nm; because of the small thickness, there is no requirement for conductivity; due to the small thickness, there is no absorption limitation. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

135: a p-type crystalline silicon wafer; the thickness is w < 300um, and the base resistance of the p-type wafer is 0.1Ohm cm < rho < 100Ohm cm.

136: electrically passivating the interfacial layer; the thickness is less than 10 nm; because of the small thickness, there is no requirement for conductivity; due to the small thickness, there is no absorption limitation. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

137: an electrically passivated transparent conductive film; highly doped n-doped 1e18cm^-3＜N_D＜5e21cm^-3(ii) a The specific resistance is rho < 1000Ohm cm. Examples include:

● n-type amorphous or polycrystalline silicon carbide: phosphorus doped silicon carbide, nitrogen doped silicon carbide;

● n-type amorphous or polycrystalline silicon: phosphorus-doped amorphous silicon, nitrogen-doped amorphous silicon;

● n-type amorphous or polycrystalline diamond-like carbon: nitrogen doped diamond-like carbon.

Any of the above examples may include oxygen and hydrogen (n-doped SiC)_xO_yH_z(ii) a n-doped SiN_xO_yH_z)。

138: a transparent conductive film having a refractive index in the range of 1.4 < n < 3; the specific resistance is rho < 1000Ohm cm. Examples include transparent conductive oxides such as indium tin oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, tantalum oxide, antimony tin oxide, germanium oxide, zirconium oxide, titanium oxide, gallium oxide, cadmium antimony oxide.

139: and a back metal electrode.

Fig. 14 is a partial cross-sectional view of a solar cell 140 having a p-type front side, a p-type wafer, an n-type back side, and including a multifunctional transparent, conductive, highly doped silicon compound layer. This aspect of the invention is an improvement over the others described above in that, for example, the role of layers 112 and 113 of solar cell 110 of fig. 11 (and any other similar layers in any of the other embodiments disclosed herein) is incorporated into the multifunctional layer 143a described in fig. 14. This layer may be electrically passivated, transparent, and have sufficient conductivity to allow longitudinal carrier flow to the electrodes (back junction solar cells), which provides a junction with the wafer 145 and/or reduces the reflectivity of incident light (e.g., anti-reflection coating). On the back side, layer 147a may incorporate layers 117 and 118 of solar cell 110 of fig. 11, for example (and any other similar layers in any other embodiments disclosed herein). Layer 147a provides a junction with wafer 145 having a refractive index such that photons of wavelengths greater than 900nm produce high reflectivity and an electrical conductivity sufficient to allow longitudinal carrier flow from wafer 145 to metal electrode 149. The layers of the exemplary battery 140 include the following:

141: and a front metal electrode.

143: the refractive index of the electrically passivated transparent conductive film is more than 1.4 and less than n and less than 3; the thickness is less than 150 nm; the specific resistance is rho < 1000Ohm cm. Examples include:

● p-type amorphous or polycrystalline silicon carbide: boron-doped silicon carbide, aluminum-doped silicon carbide, gallium-doped silicon carbide;

● p-type amorphous or polycrystalline silicon: boron-doped silicon, aluminum-doped silicon, gallium-doped silicon;

● p-type amorphous or polycrystalline diamond-like carbon: boron doped diamond-like carbon, aluminum doped diamond-like carbon.

Any of the above examples may include oxygen and hydrogen (p-doped SiC)_xO_yH_z(ii) a p-doped SiN_xO_yH_z)。

144: electrically passivating the interfacial layer; the thickness is less than 10 nm; because of the small thickness, there is no requirement for conductivity; due to the small thickness, there is no absorption limitation. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

145: an n-type or p-type crystalline silicon wafer; the thickness is w less than 300um, the base resistance of the n-type wafer is 0.5Ohm cm < rho < 20Ohm cm, and the base resistance of the p-type wafer is 0.1Ohm cm < rho < 100Ohm cm.

146: electrically passivating the interfacial layer; the thickness is less than 10 nm; because of the small thickness, there is no requirement for conductivity; due to the small thickness, there is no absorption limitation. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

147 a: an electrically passivated transparent conductive film; for highly doped n-doped 1E18cm^-3＜N_D＜5E21cm^-3The specific resistance is rho < 1000Ohm cm. Examples include:

● n-type amorphous or polycrystalline silicon carbide: phosphorus doped silicon carbide, nitrogen doped silicon carbide;

● n-type amorphous or polycrystalline silicon: phosphorus-doped amorphous silicon, nitrogen-doped amorphous silicon;

● n-type amorphous or polycrystalline diamond-like carbon: nitrogen doped diamond-like carbon.

Any of the above examples may include oxygen and hydrogen (n-doped SiC)_xO_yH_z(ii) a n-doped SiN_xO_yH_z)。

149: a back metal.

Fig. 15 is a partial cross-sectional view of a solar cell 150 having an n-or p-type wafer, a modified p-type front side including certain front side layers, and an n-type back side. The latter surface structure (omitted for convenience) may be accomplished according to any other structure described herein.

This structure is particularly beneficial for material combinations where the layers xx3 and xx4 on the front surface of the structure such as disclosed above have unacceptably high absorbency. In cell 150, by disposing layers 153 and 154 only under the contacts, their optical properties (refractive index, absorption) are not important for cell efficiency. Resistive losses occur only by the flow of longitudinal carriers to the contacts 151. Layers 152, 154b, and 155b also do not have to shield the contacts so they can optimize transmittance and surface passivation. This will facilitate the flow of current to the contacts and also may place the contact structures at a large distance from each other if they provide lateral conductivity. This reduces optical shielding losses. This structure works best with the back junction because the lateral conductivity requirements for layers 152, 154b and 155b are eliminated. The layers of exemplary battery 150 include the following:

151: and a front metal electrode.

152: the refractive index of the anti-reflection film is more than 1.4 and less than n and less than 3; the thickness is less than 110 nm. Examples include silicon nitride, silicon carbide, silicon oxide, titanium oxide.

153: electrically passivating the conductive film, wherein the thickness of the conductive film is less than 110 nm; the specific resistance is rho < 1000Ohm cm. Examples include:

● p-type amorphous or polycrystalline silicon carbide: boron-doped silicon carbide, aluminum-doped silicon carbide, gallium-doped silicon carbide;

● p-type amorphous or polycrystalline silicon: boron-doped silicon, aluminum-doped silicon, gallium-doped silicon;

● p-type amorphous or polycrystalline diamond-like carbon: boron doped diamond-like carbon, aluminum doped diamond-like carbon.

Any of the above examples may include oxygen and hydrogen (p-doped SiC)_xO_yH_z(ii) a p-doped SiN_xO_yH_z)。

154: electrically passivating the interfacial layer; the thickness is less than 10 nm; because of the small thickness, there is no requirement for conductivity; due to the small thickness, there is no absorption limitation. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

154 b: electrically passivating the interfacial layer; the thickness is less than 10 nm. Examples include silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride, silicon carbide.

155: an n-type or p-type crystalline silicon wafer; the thickness is w less than 300um, the base resistance of the n-type wafer is 0.5Ohm cm < rho < 20Ohm cm, and the base resistance of the p-type wafer is 0.1Ohm cm < rho < 100Ohm cm.

155 b: a phosphorus diffused silicon layer (optionally present) with a sheet resistance > 70 Ohm/sq.

The above structures are not mutually exclusive and any feature of one structure may be applied to any other structure in accordance with the invention.

Exemplary battery structure-alternative electrode structure:

fig. 16 is a partial cross-sectional view of a solar cell 160, the solar cell 160 having glass or other transparent film embedded electrodes that are pressed or bonded to the cell. This alternative structure applies to any of the above structures and may include an n-or p-type front side, an n-or p-type wafer, and a p-or n-type back side. As an alternative to metal electrodes deposited directly on the cell, the metal electrodes 161 and 169 are embedded in glass or other laminate films 161a and 169 a. When the glass or laminate film is pressed or laminated under pressure, the embedded electrodes contact on top of the outer layers 162 and 168, respectively. This has the advantage that the metal does not need to be deposited directly on the cell itself, thereby eliminating typical sources of thin film stress that can cause cell bowing. This is particularly useful when processing very large area wafers such as thin film silicon plates and/or very thin wafers. In many of the above embodiments, the metal electrode need not pass through the underlying layers before contacting the cell. Also, various conductive materials may be used to increase the conductivity between the metal electrodes 161 and 169 and the surfaces of the outer layers 162 and 168. These conductive materials may include, but are not limited to, Anisotropic Conductive Film (ACF), conductive epoxy, or spring-like contact probes. The layers of exemplary battery 160 include the following (which may be formed of any of the above materials, omitted here for simplicity):

161 a: a glass plate or a transparent film with embedded metal electrodes.

161: and a front metal electrode.

162: a transparent conductive film.

163: and electrically passivating the conductive film.

164: and electrically passivating the interfacial layer.

165: an n-type or p-type crystalline silicon wafer; the thickness of the film is w less than 300 um.

166: and electrically passivating the interfacial layer.

167: and electrically passivating the conductive film.

168: a transparent conductive film.

169: and a back metal electrode.

169 a: a glass plate or a transparent film with embedded metal electrodes.

Fig. 17 is a partial cross-sectional view of a solar cell 170 having glass or other transparent film with embedded electrodes pressed or bonded to the cell and having local electrodes 179 on its back side. Due to the local electrode structure on the backside, photons impinging from the back of the solar cell can be absorbed within the wafer 175 and electron-hole pairs are generated in this double-sided structure. This may improve the efficiency of the solar cell in outdoor operation conditions, wherein the reflectivity may be used with low manufacturing and installation costs of the auxiliary module.

This alternative structure applies to any of the above structures and may include an n-or p-type front side, an n-or p-type wafer, and a p-or n-type back side. As an alternative to metal electrodes deposited directly on the cell, the metal electrodes 171 and 179 are embedded in glass or other laminate films 171a and 179 a. When the glass or laminate film is pressed or laminated under pressure, the embedded electrodes contact on the top surfaces of the outer layers 172 and 178, respectively. This has the advantage that the metal does not need to be deposited directly on the cell itself, thereby eliminating typical sources of thin film stress that can cause cell bowing. This is particularly useful when processing very large area wafers, such as thin film silicon plates and/or very thin wafers. In many of the above embodiments, the metal electrode need not pass through the underlying layers before contacting the cell. Also, various conductive materials may be used to increase the conductivity between the metal electrodes 171 and 179 and the surfaces of the outer layers 172 and 178. These conductive materials may include, but are not limited to, Anisotropic Conductive Film (ACF), conductive epoxy, or spring-like contact probes. The layers of exemplary battery 170 include the following (which may be formed of any of the above materials, omitted here for simplicity):

171 a: a glass plate or a transparent film with embedded metal electrodes.

171: and a front metal electrode.

172: a transparent conductive film.

173: and electrically passivating the conductive film.

174: and electrically passivating the interfacial layer.

175: an n-type or p-type crystalline silicon wafer; the thickness of the film is w less than 300 um.

176: and electrically passivating the interfacial layer.

177: and electrically passivating the conductive film.

178: transparent and electrical films.

179: and a back metal electrode.

179 a: a glass plate or a transparent film with embedded metal electrodes.

The above structures are not mutually exclusive and any feature of one structure may be applied to any other structure in accordance with the invention.

The manufacturing method comprises the following steps:

the following production flow is a method of producing the structures disclosed herein; other approaches are possible without departing from the scope of the invention. Initially, an incident wafer is obtained without surface damage, which can be structured or altered in geometry, and with a clean surface. As noted above, the geometric surface shapes of the layer surfaces are not depicted in these figures for simplicity (e.g., surface structures such as pyramids, or other surface structures may be formed on the layer surfaces), however, it should be understood that the geometric shapes and/or surfaces may be configured in any shape that is beneficial for improving solar cell efficiency and that such shapes and/or surfaces are within the scope of the present invention.

The subsequent processing steps may be as follows (using a notation such as "xx 4" or any other similar notation consistent with any of the above-described structures of fig. 1-18 ending in a "4" or "4 a" such as 4, 14, 134, 4a, 14a, 134a, etc.):

● deposition or growth of interfacial passivation layers xx4 and xx 6;

● deposition of layers xx3 and xx 7;

● heat treatment;

● optional deposition of layers xx2 and xx8 (to provide a good internal mirror on the back, possibly including low reflectivity layers — refractive indices substantially less than 3.0, less than 2.6, less than 2.0, less than 1.5); and

● metallization.

In any of the structures described above, these layers (e.g., xx2, xx3, xx4, xx6, xx7, and xx8) are electrically conductive, i.e., metallization may be placed directly on the outer layer. (in typical high efficiency solar cells this is not the case because surface passivation is usually achieved using materials that are also electrical insulators.) this allows innovative metallization schemes, e.g., solar cells can be laminated into assemblies that have electrodes already embedded in the glass or in the laminate. Furthermore, conductive sheets may also be applied in order to mechanically strengthen the battery. Another method of metallization may include depositing fine lines of metal. Due to the conductivity of the surface, the need for metal pastes is reduced, since they are in direct contact with the outer layer, without the need to corrode through the insulating layer to contact the solar cell. Another example is the direct evaporation or sputtering of metal on a conductive surface.

Most of the layers within the solar cell structure as described above may be deposited or grown by methods such as PECVD, APCVD, LPCVD, PVD, electroplating, etc. For some layers or combinations of layers, innovative methods of producing these layers and structures can be used. For example, thermal oxidation or plasma deposition or plasma assisted oxidation may be used to form the interfacial passivation layer.

For example, in order to achieve very efficient solar cells with cost-effective production methods, it is advantageous to deposit thin films of different properties on one side only. Although this may be difficult to achieve, (e.g., for standard tube furnace deposition of polysilicon, such as LPCVD deposition), PECVD deposition may be performed on one side of the wafer, with no deposition on the other side. PECVD equipment is available on an industrial scale, but it can only work under temperature conditions that enable the deposition of amorphous or microcrystalline silicon layers. In the cell structure, the amorphous silicon layer may be converted into a polycrystalline silicon layer by a heat treatment. This also applies to doped amorphous silicon layers or compounds of amorphous silicon carbide and the like. This crystallization adversely affects the passivation properties of the silicon/amorphous silicon interface layer (if present in the cell structure). However, starting from a crystallized polysilicon layer, layers xx4 and xx6 buffer the wafer surface. Thus, the interface remains passivated after the heat treatment and the underlying system is stable at the heat treatment temperature.

According to the invention, many properties of the layer are changed during the crystallization: the donor or acceptor is activated, increasing light transmission, hydrogen diffusion out of the layer. The thermal treatment may activate the dopant atoms in the compound, causing the dopant atoms to diffuse into the substrate wafer to provide a high-low junction or p-n junction.

According to the present invention, good passivation of layers xx4 and xx6 is sustained and/or improved after high temperature heat treatment. Passivation may be sufficient after deposition, but high temperature heat treatment may improve its properties. Because of the composition of the layers, the passivation is temperature stable (from 500 ℃, or 600 ℃, or 700 ℃ to 1100 ℃ or higher). Thus, a heat treatment above 500 ℃ constitutes one aspect of the present invention. Other possible benefits of this structure may include: the heat treatment may not change the crystallinity of the silicon substrate, at least at the interface, because the first interface layer is amorphous SiO₂And/or because the conductive layer is SiC. It is therefore contemplated that another aspect of the present invention is to provide a thermal treatment without changing the crystallinity of the silicon substrate, and/or the interface passivation layer serves as a buffer layer for recrystallization during the thermal treatment.

If the composition of the layers is chosen correctly, the layers deposited in a single process can be divided into two (or more) layers. The oxygen introduced in the amorphous deposited layer migrates to the silicon interface and a thin oxide can be grown. If this principle is studied using oxide-containing films xx3 and xx7, it is not necessary to produce passivation interface layers xx4 and xx6 before layers xx3 and xx7, so all described structures can work without layers xx4 and xx 6. At the same time, the film crystallizes and the dopants can be activated. This effect can be utilized to produce the batteries 90 and 140 whose structures are as disclosed above in an extremely short production flow, but is not limited to this application. Thus, layers xx3 and xx7 in all structures can be used to take advantage of this principle if they contain a small amount of oxygen and embodiments are developed with the same layers containing oxygen.

In the case of depositing or growing passivating interfacial layers xx4 and xx6 and highly doped layers xx3 and xx7 under internal stress, or in the case of stress generated by the heat treatment used for crystallization as described above, this can adversely affect the passivation properties of wafer surface xx 5. To prevent this adverse effect, referring to the partial cross-sectional view of the solar cell 180 of fig. 18, thin silicon films 1831 and 1871 may be deposited as buffer layers over the passivation films 184 and 186. Fig. 18 illustrates this concept of silicon buffer layers 1831 and 1871 between passivation layers 184 and 186 and layers 183a and 187a, respectively. This concept is particularly advantageous for the batteries 90 and 140 disclosed above, but its application is not limited to these configurations.

This silicon buffer layer may be, for example, undoped polysilicon. In this case, a standard tube furnace can be used, since this film can be deposited on both sides. In a process sequence where passivation layers 184 and 186 are thin thermal oxide, polysilicon may be deposited directly after the oxidation process in the same furnace but in a different tube (saving processing of the wafer) or even in the same tube. The doping required for passivation can be produced by doping the thin films 183a and 187a with a dopant by a heat treatment for crystallization while making them passivated and conductive from the layers 183a and 187a into the layers 1831 and 1871, respectively. The allowable thickness of the buffer layer depends on the doping level of the doped layer deposited on the top surface and the time/temperature profile for crystallizing this doped top layer. The undoped layers are doped with doped layers 183a and 187a during this thermal treatment. Buffer layers 1831 and 1871 may also be comprised of multiple layers of silicon.

Another effect of the thermal treatment is to reorganize the passivation interface layers 184 and 186. Depending on their thickness, heat treatment, and the layers above them, the layers shrink and open (e.g., perforated) so that adjacent layers 1831 and 1871 may be in direct contact with wafer 185. A very small portion of the interface allows carriers to bypass layers 184 and 186. If the thermal treatment is chosen to be non-open or insufficiently open, then layers 184 and 186 need to be sufficiently thin to allow tunneling of carriers.

Other aspects of the invention include improved methods of metallization fabrication. In one example, the Method may be performed according to U.S. provisional application No. 61/171,187 entitled "Method for Forming structures in an aerosol Cell" filed on 21/4/2009; and co-filed international patent application "Method for Forming structures in a Solar Cell" attorney docket No. 3304.002AWO to form metallization of any of the above structures. These applications are incorporated by reference herein in their entirety. According to these applications, the metallization may be formed in accordance with a method of forming a conductive contact/heterogeneous contact pattern on a surface of a solar cell, including forming a thin conductive layer on an underlying layer of at least one solar cell, and ablating a majority of the thin conductive layer with a laser beam, thereby leaving the conductive contact/heterogeneous contact pattern. Self-aligned metallization may be formed on the conductive contact pattern. The bottom layer may comprise a passivation layer and/or an anti-reflection layer below the thin conductive layer, wherein the conductive contact pattern forms an electrical contact with the semiconductor layer of the solar cell through the at least one bottom layer.

In another example, the method may be performed in accordance with U.S. provisional application No. 61/171,491 entitled "Localized Metal Contacts By Localized Laser Assisted Reduction Of Metal-Ions in functional Films, And added solvent Cell Applications therof, filed on 22.4.2009; and co-filed international patent application entitled "Localized Metal Contacts By Localized Laser Assisted Conversion of functional Films In Solar Cells", attorney docket number 3304.003 AWO. These applications are hereby incorporated by reference in their entirety. According to these applications, metallization may be formed in accordance with methods of forming at least one electrical contact in a layer of a solar cell, including forming a layer in a solar cell comprising a material that can be selectively modified to make electrical contact upon laser irradiation; and applying selective laser irradiation to at least one region of the layer to form at least one electrical contact in said region of the layer. The remaining regions of the layer may comprise functional layers of the solar cell and need not be removed: such as transparent conductive films, and antireflective films, and/or passivation as described above.

The present invention extends to any one or combination of the solar cell structures disclosed above, typically including a central substrate, a conductive layer, an anti-reflective layer, a passivation layer and/or an electrode. The above structures are not mutually exclusive and any feature of one structure may be applied to any other structure herein in accordance with the invention.

The invention includes methods of making these structures, comprising: providing a wafer as a central substrate; depositing or growing interfacial passivation layers xx4 and xx6 on the substrate; depositing conductive layers xx3 and xx7 over the passivation layer; providing a heat treatment; optionally depositing antireflective layers xx2 and xx8 (possibly including a low reflectivity layer to provide good internal mirror on the backside); and providing metallization as an electrode.

In one embodiment, the invention includes applying a thermal treatment to produce a multifunctional film that is separated into a surface passivating interfacial layer and a highly doped polycrystalline passivation layer with high transparency.

In one embodiment, the invention includes depositing an amorphous silicon-containing compound and using a thermal treatment to induce crystallization to make it a polycrystalline film.

In one embodiment, the invention includes depositing an amorphous silicon-containing compound and utilizing a thermal treatment to cause crystallization of the film and increase optical transmission.

In one embodiment, the invention includes depositing an amorphous silicon-containing compound and utilizing a thermal process to activate dopant atoms in the compound.

In one embodiment, the invention includes depositing an amorphous silicon-containing compound and utilizing a thermal treatment greater than 500 ℃ to activate the dopant atoms in the compound and diffuse the dopant atoms into the substrate wafer to provide a high-low junction or p-n junction.

One or more process control aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code for providing and facilitating the capabilities of the present invention. The article of manufacture may be part of a computer system or sold separately.

Additionally, at least one program storage device readable by an apparatus embodying at least one instruction program executable by the apparatus to perform the potential capabilities of the present invention can be provided.

The flow diagrams and steps described herein are merely examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For example, the steps may be performed in a differing order, or steps may be added, deleted or changed. All of these variations are considered a part of the claimed invention.

Although preferred embodiments have been depicted and described in detail herein, it will be apparent to those skilled in the relevant art that various modifications, additions, substitutions and the like can be made without departing from the spirit of the invention and these are therefore considered to be within the scope of the invention as defined in the following claims.

Claims (17)

1. A method of fabricating a solar cell, comprising:

providing a wafer as a central substrate;

depositing or growing at least one interface passivation layer on the substrate;

depositing at least one conductive passivation layer on the at least one interfacial passivation layer, the at least one conductive passivation layer comprising a dopant;

providing a thermal treatment at a temperature of 500 ℃ or more that at least partially crystallizes the at least one conductive passivation layer and promotes diffusion of the dopant from the at least one conductive passivation layer throughout the at least one interfacial passivation layer; and

providing metallization as an electrode on the at least one conductive passivation layer after the heat treatment, wherein the dopant diffused throughout the at least one interfacial passivation layer shortens a path of charge carriers between the substrate and the electrode through the at least one conductive passivation layer and the at least one interfacial passivation layer.

2. The method of claim 1, further comprising depositing at least one anti-reflective layer, and/or a low reflectivity layer that forms a good internal mirror on the back side of the solar cell.

3. The method of claim 1, comprising applying a thermal treatment to produce a multifunctional film that is separated into a surface passivating interfacial layer and a highly doped polycrystalline passivation layer with high transparency.

4. The method of claim 3, wherein the thermal treatment causes the passivating interfacial layer to perforate, thereby allowing carrier transport through the perforation.

5. The method of claim 1 or 2, wherein the at least one conductive passivation layer comprises an amorphous silicon-containing compound, and wherein the thermal treatment induces crystallization of the at least one conductive passivation layer into a polycrystalline thin film.

6. The method of claim 1 or 2, wherein the at least one conductive passivation layer comprises an amorphous silicon-containing compound, and wherein the thermal treatment causes the at least one conductive passivation layer to crystallize and increase optical transmittance.

7. The method of claim 1 or 2, wherein the at least one conductive passivation layer comprises an amorphous silicon-containing compound, and wherein the thermal treatment activates dopant atoms in the compound.

8. A method of forming a solar cell comprising depositing an amorphous silicon-containing compound and utilizing a thermal treatment greater than 500 ℃ to activate and diffuse dopant atoms in the compound through at least one interfacial passivation layer into a substrate to provide a high-low junction or a p-n junction.

9. A solar cell formed according to the method of claim 1.

10. A solar cell, comprising:

a wafer as a central substrate;

at least one interface passivation layer formed on the substrate;

at least one conductive passivation layer on the at least one interfacial passivation layer, the at least one conductive passivation layer comprising a crystalline structure formed with a thermal treatment at a temperature of 500 ℃ or more and comprising a dopant that has diffused at least partially from the at least one conductive passivation layer throughout the at least one interfacial passivation layer as a result of the thermal treatment; and

a metallization as an electrode on the at least one conductive passivation layer, the metallization provided after heat treating the at least one conductive passivation layer, wherein the dopant diffused throughout the at least one interfacial passivation layer shortens a path of charge carriers between the substrate and the electrode through the at least one conductive passivation layer and the at least one interfacial passivation layer.

11. The solar cell of claim 10, further comprising at least one anti-reflection layer, and/or a low reflectivity layer that forms a good internal mirror on the back side of the solar cell.

12. The solar cell of claim 10 or 11, wherein the at least one conductive passivation layer comprises an amorphous silicon-containing compound, and wherein the thermal treatment induces crystallization of the at least one conductive passivation layer into a polycrystalline thin film.

13. The solar cell of claim 10 or 11, wherein the at least one conductive passivation layer comprises an amorphous silicon-containing compound, and wherein the thermal treatment causes the at least one conductive passivation layer to crystallize and increase optical transmittance.

14. The solar cell of claim 10 or 11, wherein the at least one conductive passivation layer comprises an amorphous silicon-containing compound, and wherein the thermal treatment activates dopant atoms in the compound.

15. The solar cell of claim 10 comprising a multifunctional film that separates upon thermal treatment into a surface passivating interfacial layer and a highly doped polycrystalline passivation layer with high transparency.

16. The solar cell of claim 15, wherein the interfacial passivation layer comprises perforations to allow carrier transport therethrough, the perforations being formed by heat treating the multifunctional thin film.

17. A solar cell comprising an amorphous silicon-containing compound treated with a thermal treatment at greater than 500 ℃ to activate dopant atoms in the compound to diffuse the dopant atoms through at least one interfacial passivation layer into a substrate to provide a high-low junction or a p-n junction.