HK1169744B - An integrated circuit assembly and assembly method thereof - Google Patents

Description

Integrated circuit package and assembling method thereof

Technical Field

The invention relates to the assembly of integrated circuit packages.

Background

Integrated Circuit (IC) chips or dies are typically coupled to other circuits (interfaces) using packages that may be attached to (attach) circuit boards. One such type of IC die package is the Ball Grid Array (BGA) package. BGA packages provide smaller footprint than many other packaging solutions available today. One type of BGA package contains one or more IC dies attached to a first surface of a package substrate and contains an array of solder ball pads located on a second surface of the package substrate. The solder balls are connected to the solder ball pads. The solder balls are reflowed to attach the package to the circuit board.

One advanced type of BGA package is the wafer level BGA package. Wafer level BGA packages are known in the industry by several names, including Wafer Level Chip Scale Packages (WLCSP), and the like. In wafer-level BGA packages, solder balls are directly attached to the IC chip while the IC chip has not been singulated from its fabrication wafer. Thus, a wafer level BGA package does not include a package substrate. Accordingly, the wafer level BGA package can be made small with a high pin count (highpin out) relative to other IC package types including conventional BGA packages.

For IC chips used in wafer-level BGA packages, the wiring is typically formed directly on the chip. Wires are formed on the surface of the wafer to route signals from the wafer pads to the locations where solder balls are attached to the wafer as routed. Fan-in (fan-in) and fan-out (fan-out) wiring are two different types of wiring that can be formed on a wafer. Fan-in wiring is a type of wiring that is formed only within the area of each semiconductor wafer. Fan-out routing is a type of routing that extends outside the area of the semiconductor die. For example, for each wafer, a material may be used around the semiconductor material of the wafer, the material used being a solid. The fan-out wiring may then be applied to the wafer, extending outside the area of the wafer through the material used. In this way, fan-out routing provides advantages, including enabling signals to be passed over a larger area, thereby providing more space for signal traces. However, current fan-out wiring techniques require expensive capital investment. While such capital investment may provide capital benefits in the long term, it may not provide cost benefits in the short term. Furthermore, current fan-out routing technology is limited in its capabilities due to the current trend in the industry to move more and more devices to wafer level packaging. Thus, while the cost of fan-out wafer level manufacturing is decreasing, it is difficult for fan-out wafer level manufacturing to keep up with the increasing pressures to reduce prices and maintain profit margins.

Disclosure of Invention

A method, system, and apparatus for fabricating an integrated circuit package, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

According to an aspect of the invention, there is provided a method comprising:

forming a substrate panel (substrate panel) including a plurality of substrates, each of the substrates including a wiring;

dividing (singulating) the substrate panel to separate the plurality of substrates;

attaching at least a subset of the separated substrates to a surface of a carrier;

mounting one or more wafers to each of the substrates on the carrier;

encapsulating the die and the substrate with a molding compound (molding compound) on the carrier;

detaching the carrier from the packaged die and substrate to form a molded assembly comprising the molding compound used to package the die and substrate;

connecting a plurality of interconnects (interconnects) to each of the substrates on a surface of the mold assembly; and

the molded assembly is singulated to form a plurality of integrated circuit packages, each integrated circuit package including at least one of the die and the substrate.

Preferably, the method further comprises:

the substrate in the substrate panel is plated using a plunger (stud) to form conductive contacts for attaching the wafer to the substrate.

Preferably, the forming a substrate panel including a plurality of substrates each including a wiring includes:

forming the substrate panel to include the substrates in an array that fills the substrate panel except for a peripheral edge region of the substrate panel around the array.

Preferably, the attaching at least a subset of the separated substrates to a surface of a carrier comprises:

positioning the separated substrates to be spaced apart on the surface of the carrier.

Preferably, the encapsulating the die and the substrate with the molding compound on the carrier includes:

filling spaces between the separated substrates with the molding compound.

Preferably, said singulating said molded assembly to form a plurality of integrated circuit packages comprises:

the molded assembly is singulated such that each integrated circuit package includes a peripheral ring of molding compound around an outer edge of the included substrate.

Preferably, the interconnect is a bump interconnect.

Preferably, the method further comprises:

testing the substrate in the substrate panel to determine a set of working substrates;

wherein attaching at least a subset of the separated substrates to a surface of a carrier comprises:

attaching the separated substrates of the set of work substrates to the surface of the carrier.

According to an aspect of the invention, there is provided a method comprising:

receiving a plurality of separated substrates;

attaching the substrate to a surface of a carrier;

mounting one or more wafers to each of the substrates on the carrier;

encapsulating the die and the substrate with a molding compound on the carrier;

detaching the carrier from the packaged die and substrate to form a molded assembly comprising the molding compound used to package the die and substrate;

attaching a plurality of interconnects to each of the substrates on a surface of the mold assembly; and

the molded assembly is singulated to form a plurality of integrated circuit packages, each integrated circuit package including at least one of the die and the substrate.

Preferably, the attaching the substrate to the surface of the carrier includes:

the substrates are positioned to be spaced apart on the surface of the carrier.

Preferably, the encapsulating the die and the substrate with the molding compound on the carrier includes:

filling the space between the substrates with the molding compound.

Preferably, said singulating said molded assembly to form a plurality of integrated circuit packages comprises:

the molded assembly is singulated such that each integrated circuit package includes a perimeter ring of molding compound around an outer edge of the contained substrate.

Preferably, the interconnect is a bump interconnect.

Preferably, the method further comprises:

testing the substrate in the substrate panel to determine a set of working substrates;

wherein attaching at least a subset of the substrates to a surface of a carrier comprises:

attaching the substrates of the set of working substrates to the surface of the carrier.

According to one aspect of the invention, there is provided an integrated circuit package comprising:

a substrate having opposing first and second surfaces;

a wafer attached to the first surface of the substrate; and

a molding compound for encapsulating the die on the first surface of the substrate and forming a peripheral ring around an outer edge of the substrate.

Preferably, the integrated circuit package comprises:

a plurality of interconnect bumps attached to the second surface of the substrate.

Preferably, the integrated circuit package comprises:

a plurality of plungers connecting the terminals of the die to conductive features on the first surface of the substrate.

Preferably, the integrated circuit package comprises:

a plurality of solder bumps for coupling terminals of a die to conductive features on the first surface of the substrate.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.

FIG. 1 is a flow chart of forming an integrated circuit package substrate according to an embodiment of the present invention;

FIG. 2 is a top view of an example of a substrate panel comprising a plurality of substrate strips;

FIG. 3 is a schematic diagram of a process of forming an integrated circuit package substrate according to an embodiment of the invention;

FIGS. 4 and 5 are schematic views of a substrate panel substantially filled with a substrate according to an embodiment of the invention;

fig. 6 is a side view of first and second divided substrates according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a process of testing a substrate of a substrate panel according to an embodiment of the invention;

FIG. 8 is a schematic diagram of a process of singulating a wafer to form integrated circuit chips in accordance with an embodiment of the present invention;

FIG. 9 is a top view of an example of a wafer;

FIG. 10 is a cross-sectional view of the wafer of FIG. 9 showing first and second integrated circuit regions;

FIG. 11 is a cross-sectional view of an integrated circuit region being singulated into separate wafers according to embodiments of the invention;

FIG. 12 is a flow chart of forming an integrated circuit package according to an embodiment of the present invention;

fig. 13 and 14 are schematic diagrams of examples of carrier substrates according to embodiments of the invention;

fig. 15 is a schematic view of a surface of a carrier with an attached substrate according to an embodiment of the invention;

FIG. 16 is a schematic view of the substrate on wafer of FIG. 15 according to an embodiment of the present invention;

FIGS. 17 and 18 are cross-sectional views of a substrate attaching a wafer to a carrier according to an embodiment of the present invention;

fig. 19 is a cross-sectional view of a carrier with a substrate and a wafer mounted thereon, wherein the substrate and the wafer are encapsulated using an encapsulation material applied to the carrier, in accordance with an embodiment of the present invention;

fig. 20 is a cross-sectional view of the carrier of fig. 19 separated from the encapsulation material, the substrate, and the wafer, in accordance with an embodiment of the present invention;

FIG. 21 is a cross-sectional view of a mold assembly having bump interconnections applied to a package substrate according to an embodiment of the present invention;

FIG. 22 is a side cross-sectional view of an integrated circuit package singulated from the mold assembly of FIG. 21 in accordance with an embodiment of the present invention;

fig. 23 is a side cross-sectional view of an integrated circuit package including encapsulation material around the edge of a package substrate according to an embodiment of the invention.

The present invention will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears.

Detailed Description

Introduction to the design reside in

The present specification discloses one or more embodiments that incorporate the features of this invention. The disclosed embodiments are merely illustrative. The scope of the invention is not limited to the disclosed embodiments. The invention is defined by the appended claims.

References in the specification to "one embodiment," "an example embodiment," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

Furthermore, it should be understood that spatial descriptions (e.g., "above …," "below …," "up," "left," "right," "down," "top," "bottom," "vertical," "horizontal," etc.) used herein are for purposes of illustration only. Embodiments of the structures described herein may be spatially arranged in any orientation or manner.

Examples

Embodiments of the invention enable efficient and economical assembly of Integrated Circuit (IC) packages, such as Ball Grid Array (BGA) packages. In an embodiment, forming the IC package includes encapsulating the one or more dies and the substrate in an encapsulation material (e.g., a molding compound). In an IC package, one or more dies are attached to a package substrate, and bump interconnections or other types of interconnections are attached to the package substrate to attach the package connections to a circuit board.

IC package embodiments may be assembled using existing substrate manufacturing facilities without the need for fan-out routing, expanding the area of the die by using additional area around the die based on the fan-out routing, and routing the fan-out routing out with additional material. However, the manufacturing process for enlarging the area of the wafer and using fan-out wiring is expensive and time consuming. Embodiments of the present invention significantly alleviate capital investment constraints by not requiring expensive equipment for fan-out wiring. In embodiments of the present invention, substrate utilization is improved to significantly improve throughput, improve feedstock utilization, and reduce cost. In such embodiments, the number of packages produced per substrate panel is increased. Furthermore, there is no need to mark the non-working substrates in the substrate panel/strip.

In one embodiment of the present invention, the substrate formed may be undersized, which may be compensated for by the molding compound. For example, a package size of 7mm by 7mm may be required. A 6.6mm substrate may be formed and the molding compound around the outer edges of the substrate may have a thickness of 0.2mm to allow for encapsulation with dimensions of 7 mm. This way the utilization of the substrate panel can be further improved.

In embodiments of the invention, existing or established reconstruction procedures may be used. For example, the panel may be reconstructed using pick and place techniques to place known good substrates and wafers on a carrier and using established techniques to package the substrates and wafers.

In embodiments of the invention, existing fan-out wafer level packaging assembly techniques may be utilized, but a multi-layer substrate may be used in place of the redistribution layer, enabling the step of avoiding the redistribution layer formation process (and associated expensive equipment) to be converted into a more cost-effective solution.

Such an embodiment is cost effective and producible and enables the manufacture of small-sized packages containing a large number of pins. The described embodiments of the present invention are intended to be illustrative only and not to be limiting. Although primarily illustrated in the following description as ball grid array packages, embodiments of the present invention may be adapted to a variety of different types of integrated circuit package types, and such packages may include more than one integrated circuit die. Further structural and operational embodiments, including modified/altered embodiments, will be apparent to those skilled in the art in view of the teachings of the present invention.

(1) Example substrate fabrication embodiments

According to embodiments of the present invention, a substrate for use in an IC package may be formed in a substrate panel. For example, fig. 1 shows a process 100 for forming a package substrate according to an embodiment of the invention. For illustrative purposes, the process 100 is described below in conjunction with FIGS. 2-6. Further structural and operational embodiments will be apparent to those skilled in the art from the discussion provided herein.

The process 100 begins at step 102. In step 102, a substrate panel is formed comprising a plurality of substrates, each substrate comprising wiring. In an embodiment of the present invention, the substrate panel may be formed to include a plurality of regions corresponding to the package substrate. The substrate panel is formed to include one or more wiring layers and one or more insulating layers, and conductive holes are formed through the insulating layers. Conductive pads (for transmitting signals of the wafer) on the first surface of the substrate panel pass through the wiring layer and the hole, penetrate through the substrate panel, and are connected to the solder ball pads on the second surface of the substrate panel. One skilled in the art will appreciate that the substrate panel may be manufactured according to standard or proprietary substrate panel manufacturing techniques.

For example, fig. 2 shows a surface view of an example substrate panel 200, the substrate panel 200 including a plurality of substrate strip portions 202 a-2021. Each substrate strip portion 202a-2021 includes a plurality of substrates 204. Although the substrate panel 200 shown in fig. 2 includes 12 substrate strip portions 202a-2021(2 by 6 array), in other embodiments, the substrate panel 200 may include other numbers of substrate strip portions 202. Further, although each base strip portion 202a-2021 shown in fig. 2 includes 24 substrates 204(2 by 12 array), each base strip portion 202 may include other numbers of substrates 204.

According to one type of assembly technique for IC packages, the substrate panel 200 may be separated (e.g., saw cut, etc.) to form separate substrate strips, each comprising a plurality of substrates 204. The substrates 204 in each substrate strip may be tested and any non-working substrates 204 (failed test substrates) marked. For a particular substrate strip, die connections may be attached to the active substrate 204 (substrates not marked as failed in the substrate strip), die may be packaged on the substrate strip, bump interconnects may be connected to the substrate strip, and the substrate strip may be singulated into separate integrated circuit packages.

However, such IC assembly techniques also have drawbacks. For example, as shown in FIG. 2, additional portions of the substrate panel 200 between and around the substrate strip portions 202a-2021 are unutilized. After the substrate panel 200 is separated, the unused portion of the substrate panel 200 is discarded, resulting in wasted material and cost. Furthermore, during testing, if a certain base-strip is determined to include a certain number of non-working substrates 204 (e.g., greater than 10% of the total number of substrates in the base-strip, greater than 20% of the total number of substrates in the base-strip, etc.), the entire base-strip may be discarded as being invalid for further processing. In this way, any working substrate in the discarded substrate strip is also discarded, resulting in further wasted material and cost.

Embodiments of the present invention enable a reduction in waste of substrate panels. For example, in one embodiment, step 102 of flow 100 may include step 302 shown in FIG. 3. In step 302, a substrate panel is formed such that it is substantially filled with a plurality of substrates. In such embodiments, the unused portion of the substrate panel is substantially reduced or completely eliminated. In this manner, little or no substrate material is discarded, saving material and cost and increasing the utilization of the substrate panel.

For example, fig. 4 and 5 illustrate substrate panels 400 and 500, respectively, that are substantially filled with substrate 204, in accordance with embodiments of the present invention. In fig. 4, a substrate panel 400 includes an array 402 of substrates 204, and a peripheral edge portion 404 of the substrate panel surrounding the array 402. The substrates 204 in the array 402 are adjacent to each other such that no unused portions of the substrate panel 400 are present between the substrates 204. When the substrate 204 is separated from the substrate panel 400, the edge portion 404 is the only significant portion of the substrate panel 400 that is discarded. The substrate panel 400 shown in fig. 4 is rectangular, but may have other shapes in other embodiments. Further, the array 402 shown in fig. 4 is an 18 by 26 array of substrates 204(208 substrates 204), however, in other embodiments, there may be other sizes and/or other numbers of substrates 204.

In fig. 5, a substrate panel 500 includes an array of substrates 204. There is no substrate panel edge portion in the substrate panel 500. The substrates 204 in the substrate panel 500 are adjacent to each other such that there are no unused portions of the substrate panel 500 between or around the substrates 204. When the substrate 204 is separated from the substrate panel 500, no significant portion of the substrate panel 500 is discarded. The substrate panel 500 shown in fig. 5 is rectangular, but may have other shapes in other embodiments. Further, the substrate panel 500 shown in fig. 5 is an 18 by 26 array of substrates 204(208 substrates 204), however, in other embodiments, there may be other sizes and/or other numbers of substrates 204.

Substrate panels, such as substrate panels 200, 400, and 500, are formed such that each of substrates 204 includes one or more conductive layers separated by one or more insulating layers. The conductive layers may include traces/wires, bond fingers (bond fingers), contact pads, and/or other conductive characteristics. For example, a BGA substrate may be formed that contains one conductive layer, two conductive layers, or four conductive layers. The conductive layer may be made of a conductive material such as a metal or a combination/alloy of metals including copper, aluminum, tin, nickel, gold, silver, and the like. In embodiments, the substrate panel may be rigid or may be flexible (e.g., a "flexible" substrate or flexible circuit). The insulating material may be made of ceramic, glass, plastic, tape, and/or other suitable materials. For example, the insulating layer of the substrate panel may be made of an organic material such as BT (bismaleimide triazine) laminate/resin, a flexible tape material such as polyimide, a flame retardant fiberglass composite substrate material (e.g., FR-4), and the like. The conductive and non-conductive layers may be stacked and laminated together, or otherwise coupled together, to form the substrate 204 in a substrate panel, in a manner known to those skilled in the art.

In step 104, the substrate panel is singulated to separate into a plurality of substrates. In an embodiment, a substrate panel, such as substrate panels 200, 400, and 500, may be divided in any manner known to those skilled in the art to form separate substrates 204. For example, the substrate panel may be singulated using a saw (e.g., saw cut), a laser, or according to any other singulation technique. Fig. 6 shows a side view of a first substrate 204a and a second substrate 204b separated from a substrate panel according to an embodiment of the present invention.

In an embodiment, the process 100 of FIG. 1 may include a further step 702 shown in FIG. 7. In step 702, a substrate may be tested in a substrate panel to determine a set of working substrates. In an embodiment, the substrate 204 may be tested in a substrate panel, such as one of the substrate panels 200, 400, and 500, to determine a working substrate (substrate 204 that passes the test) and a non-working substrate (substrate 204 that fails the test). One skilled in the art will appreciate that any type and number of tests may be performed on the substrate 204. For example, functional testing (e.g., contacting conductive features of the substrate 204 with probes to provide test signals and measure test results), environmental testing, etc. may be performed.

In an embodiment, the substrate panels that were determined to be non-working substrates 204 in step 702 are marked. For example, non-working substrates may be marked using ink, laser marking, or other types of marking to indicate that they are non-working. In this manner, any non-working substrates are identified so that they are not further processed/used. It should be noted that instead of processing the substrate 204 to form an IC package within a substrate strip (e.g., as described in connection with substrate panel 200 of fig. 2) by singulating the substrate 204 from the substrate panel (at step 104 of fig. 1), individual non-working substrates may be removed from further processing/use rather than potentially discarding the entire substrate strip containing some working substrates. In this way, the work substrate is not wasted.

(2) Wafer processing embodiments

As described above, an IC package may include one or more IC dies. Those skilled in the art will appreciate that IC chips may be fabricated in a wafer and separated from the wafer in any manner.

Such a wafer may be produced, for example, according to step 802 shown in fig. 8. In step 802, the wafer is singulated into a plurality of integrated circuit dies, each integrated circuit die including an integrated circuit region. For example, fig. 9 shows a top view of an example wafer 900. The wafer 900 may be silicon, gallium arsenide, or other wafer types. As shown in fig. 9, the wafer 900 has a surface defined by a plurality of integrated circuit regions 902 (the small rectangles shown in fig. 9). Each integrated circuit region 902 is packaged in an IC package, such as a ball grid array package. Many integrated circuit regions 902 may be included in the wafer 900, including 10s, 100s, 1000s, and even greater numbers.

Fig. 10 shows a cross-sectional view of the wafer 900 showing a first integrated circuit region 902a and a second integrated circuit region 902 b. As shown in fig. 10, each of the integrated circuit regions 902a and 902b includes a plurality of terminals 1002 (e.g., terminals 1002a-1002c), the terminals 1002 being access points (e.g., also referred to as "wafer pads", "I/O pads", etc.) for electrical signals (e.g., input-output signals, power signals, ground signals, test signals, etc.) of the integrated circuit region 902. There may be any number of terminals 1002 on the surface of the wafer 900 suitable for each integrated circuit region 902, including 10s, 100s, or even greater numbers of terminals 1002.

The wafer 900 may optionally be thinned by back grinding. For example, if desired and/or necessary, a back grinding process may be performed on the wafer 900 to reduce the thickness of the wafer 900 to obtain a desired amount. However, it is not necessary that the thinning process of the wafer 900 be performed in all implementations. One skilled in the art will appreciate that the wafer 900 may be thinned in any manner. The wafer 900 may be made as thin as possible to help minimize the thickness of the resulting package, which includes the integrated circuit region 902. In addition, each integrated circuit region 902 may be tested in the wafer 900. For example, test probes contact terminals 1002 in the wafer 900 to provide test input signals and receive test result signals to test each of the integrated circuit regions 902.

One skilled in the art will appreciate that wafer 900 may be diced/diced in any suitable manner such that the integrated circuit regions are physically separated from each other, in accordance with step 802 of fig. 8. For example, a saw, router, laser, etc. may be used to dice the wafer 900 in a conventional or other manner. Fig. 11 shows a cross-sectional view of integrated circuit regions 902a and 902b that have been singulated from each other to form wafers 1102a and 1102b, respectively. Depending on the number of integrated circuit regions 902 of the wafer 900, the wafer 900 may be divided into 10s, 100s, 1000s, or even a larger number of dies 1102.

(3) IC Package Assembly/fabrication embodiments

In an embodiment, an assembled/fabricated IC package includes a substrate (e.g., substrate 204) and an IC die (e.g., die 1102). It should be noted that the substrate and/or wafer used to fabricate the IC package may be formed and/or singulated in the same facility as the facility in which the IC package is fabricated. Alternatively, the substrate and/or wafer used to fabricate the IC package may also be formed and/or singulated in a facility separate/distinct from the facility in which the IC package is fabricated. If the substrate and wafer are singulated in a facility different from the facility in which the IC package is manufactured, only the singulated substrates and/or wafers (i.e., the working substrate and/or the working wafer) that pass the test need be transported to the facility in which the IC package is manufactured. In this manner, the manufacturing process of the IC package does not require a resource-consuming process, avoiding the use of non-working substrates and/or wafers. For example, when forming IC packages in a base strip, some of the substrates in the strip are non-working, and the manufacturing process of the IC packages avoids wasting working wafers, and connecting working wafers to non-working substrates in the base strip. In the described embodiment of the invention, this avoidance is not required in the case where, when the substrate has already been singulated, the non-working singulated substrate is discarded before the wafer is attached to the singulated substrate.

In embodiments, the IC package may be manufactured in a variety of different ways. For example, fig. 12 shows a flow 1200 for assembling an IC package according to an embodiment of the invention. For illustrative purposes, the process 1200 is described below in conjunction with FIGS. 13-23. Other structural and operational embodiments will be apparent to those skilled in the art from the discussion provided herein. Further, the steps of flow 1200 need not necessarily be performed in the order shown, but may be performed in other orders. The process 1200 is described below.

The process 1200 begins at step 1202 by attaching at least a subset of the separated substrates to a surface of a carrier at step 1202. In one embodiment, package substrates, such as substrate 204, singulated from the substrate panel described above are attached to the surface of the carrier. In one embodiment, a subset of substrates that pass the test (e.g., the working substrates as described in connection with fig. 7) that are singulated from the substrate panel are attached to a carrier. Substrates that fail the test (e.g., non-working substrates) are not attached to the carrier.

Any suitable type of carrier, including carriers composed of ceramic, glass, plastic, semiconductor materials (e.g., silicon, gallium arsenide, etc.), metals, or other materials, may be used to receive the separated substrates. The carrier may have a flat surface for receiving the substrate 204. Such a carrier may have any profile including circular, rectangular or other shapes. For example, fig. 13 and 14 illustrate an example carrier substrate according to an embodiment of this disclosure. Fig. 13 shows a circular carrier 1302. In one embodiment, the carrier 1302 may be a semiconductor wafer (e.g., silicon or gallium arsenide) or may be composed of other materials such as plastic, ceramic, glass, metal, and the like. Fig. 14 shows a square carrier 1402. For example, in one embodiment, the carrier 1402 may be composed of a material such as plastic, ceramic, glass, metal, and the like.

Fig. 15 shows a schematic view of a carrier 1302 according to an embodiment of the invention, the carrier 1302 having a planar surface 1502 connecting a plurality of substrates 204. For illustrative purposes, fig. 15 (and additional figures) shows the carrier 1302, but in other embodiments, the carrier 1402 of fig. 14 or other carriers may be used. The substrate 204 may be placed and/or positioned on the surface 1502 of the carrier 1302 in any manner, including by utilizing pick-and-place equipment, a self-aligning process, or other techniques. An adhesive material may be used to adhere the substrate 204 to the surface 1502 and/or to the surface of the substrate 204 prior to placing the substrate 204 on the surface 1502 to adhere the substrate 204 to the surface 1502. Any suitable adhesive material may be used, including epoxy, glue film, and the like.

In the example of fig. 15, 21 substrates 204 are shown attached to the surface 1502 of the carrier 1302. However, in embodiments, any number of substrates 204 may be attached to the surface of the carrier, including 10, 100, or even thousands of substrates 204. In one embodiment, the substrates 204 may be positioned adjacent to each other (in contact with each other) on the surface 1502 of the carrier 1302. In another embodiment, the substrates 204 may be positioned spaced apart on the surface 1502 of the carrier 1302, as shown in fig. 15. The substrates 204 may be spaced apart at any distance, depending on the particular application, which is determined for a particular application.

Referring back to fig. 12, in step 1204, one or more wafers are mounted to each substrate on the carrier. In an embodiment, one or more wafers, such as wafer 1102a and/or wafer 1102b of fig. 11, may be attached to each substrate 204 attached to the carrier. For example, fig. 16 shows a schematic view of a carrier 1302 attached to substrates 204 and each substrate 204 attached to an IC wafer 1102, according to one embodiment of the invention. The wafer 1102 may be placed and/or positioned on the substrate 204 in any manner, including by utilizing pick-and-place equipment, automated alignment processes, or other techniques. Terminals of die 1102 may be aligned with conductive pad pads on substrate 204 to couple signals of die 1102 to the wiring of substrate 204. For example, solder or other conductive materials (e.g., metals or metal compositions/alloys) may be used to couple the terminals to the conductive pads. An adhesive material is used to adhere to the surface of the substrate 204 and/or the non-active surface of the wafer 1102 prior to placing the wafer 1102 on the substrate 204. An adhesive material may be used to adhere the wafer 1102 to the substrate 204. Any suitable adhesive material may be used, including conventional lens attachment materials, epoxies, glue films, and the like.

For example, fig. 17 shows a cross-sectional view of a portion of a carrier 1302 in accordance with an embodiment of the present invention. As shown in fig. 17, substrates 204a and 204b are attached to a surface 1502 of carrier 1302. Each of the substrates 204a and 204b has opposing first 1702 and second 1704 surfaces, where the second surface 1704 is attached to the surface 1502 of the carrier 1302. Wafer 1102a is attached to first surface 1702 of substrate 204a and wafer 602b is attached to first surface 1702 of substrate 204b in the process. In the example of fig. 17, a plurality of plungers 1708 are used as interconnects between each wafer 1102 and the substrate 204. For example, as shown in fig. 17, a plurality of plungers 1708 are formed (e.g., plated) on conductive features (e.g., conductive pads, wires, etc.) on the first surface 1702 of the substrate 204 b. The plungers 1708 form conductive contacts for connecting the wafers 1102a and 1102b to the substrates 204a and 204 b. The terminals 1706 of the wafer 1102b are positioned in contact with the plungers 1708, and the plungers 1708 may be reflowed to connect the terminals 1706 of the wafer 1102b to conductive features (alternatively, an adhesive material) on the first surface 1702 of the substrate 204 b. As shown in fig. 17, terminals 1706 of wafer 1102a contact and connect to plungers 1708 on first surface 1702 of substrate 204a to connect terminals 1706 of wafer 1102a to conductive features on first surface 1702 of substrate 204 a. The plunger 1708 can be made of any suitable conductive material including metals (e.g., gold (Au), copper (Cu), etc.), metal compositions/alloys (e.g., solder, etc.), polymeric forms of conductive coating materials, etc.

Further, it should be noted that terminals 1706 of wafer 1102 include signal pads of wafer 1102 and may include one or more metal layers formed on the wafer pads, referred to as Under Bump Metallurgy (UBM) layers. The UBM layer is typically formed of one or more metal layers (e.g., metal deposition-plating, sputtering, etc.) that provide a robust interface between the wafer pad and additional wiring and/or package interconnect mechanisms such as plungers or solder balls.

Fig. 18 shows a cross-sectional view of a portion of a carrier 1302 according to another embodiment of the invention. As shown in fig. 18, substrates 204a and 204b are attached to a surface 1502 of carrier 1302. Each of the substrates 204a and 204b has opposing first 1702 and second 1704 surfaces, where the second surface 1704 is attached to the surface 1502 of the carrier 1302. Wafer 1102a is attached to first surface 1702 of substrate 204a and wafer 602b is attached to first surface 1702 of substrate 204b in the process. In the example of fig. 18, a plurality of bump interconnections (solder bumps) are used as interconnections between each wafer 1102 and the substrate 204. For example, as shown in fig. 18, a plurality of bump interconnects 1802 are formed on terminals 1706 of wafer 1102 b. Terminals 1706/bump interconnects 1802 of wafer 1102b are positioned to contact conductive features (alternatively, adhesive material) on first surface 1702 of substrate 204b, and bump interconnects 1802 may be reflowed to connect terminals 1706 to conductive features on first surface 1702 of substrate 204 b. As shown in fig. 18, terminals 1706 of wafer 1102a are connected to conductive features on first surface 1702 of substrate 204a by solder reflow bump interconnects 1802.

It should be noted that the structure shown in fig. 16-18, formed by the substrate 204 and the wafer 1102 attached to a carrier (e.g., carrier 1302 or 1402) may be referred to as a "reconstruction panel". This is at least in part because the substrate 204 mounted on the carrier can be considered a reconstituted form of a substrate panel, such as substrate panels 200, 400, and 500 (fig. 2, 4, and 5).

Further, it should be noted that steps 1202 and 1204 are performed in the order shown in FIG. 12, or in the reverse order, such that step 1204 is performed before step 1202. For example, wafer 1102 shown in fig. 16 is attached to substrate 204 prior to attaching substrate 204 (and wafer 1102) to surface 1502 of carrier 1302. In one embodiment, the wafer 1102 may be attached to the singulated substrates 204 (i.e., substrates 204 that have been separated from each other). Alternatively, in another embodiment, the wafer 1102 may be attached to the substrate 204 while the substrate 204 is still in panel form (i.e., the substrates 204 are still attached to each other in a panel of substrates).

Referring back to fig. 12, in step 1206, the wafer and substrate are encapsulated with a molding compound on a carrier. For example, fig. 19 shows a side cross-sectional view of a carrier 1302 containing packaged wafers and substrates according to an embodiment of the invention. As shown in fig. 19, a plurality of substrates 204a-204e are attached to the surface 1502 of carrier 1302 and a plurality of wafers 1102a-1102e are attached to the substrates 204a-204 e. Further, on the carrier 1302, a molding compound 1902 encapsulates the substrates 204a-204e and the dies 1102a-1102 e. Molding compound 1902 is an example of an encapsulation material that may be used to encapsulate substrates 204a-204e and wafers 1102a-1102e on carrier 1302. The molding compound 1902 may be applied to the carrier 1302 in any manner, including according to a vacuum forming process or the like. For example, in one embodiment, a mold is positioned on a surface 1502 of carrier 1302 (with the substrate and wafer attached) and molding compound 1902 may be inserted into the mold (e.g., in liquid form) and cured to encapsulate substrates 204a-204e and wafers 1102a-1102e on carrier 1302. Suitable encapsulating materials, including molding compounds, are known to those skilled in the art and include resins, epoxies, and the like.

In step 1208, the carrier is detached from the packaged die and substrate to form a molded assembly including a molding compound for encapsulating the die and substrate. For example, fig. 20 shows a side cross-sectional view of carrier 1302 that has been removed or detached from the packaged wafers and substrates, in accordance with an embodiment of the present invention. In FIG. 20, substrates 204a-204e, wafers 1102a-1102e, and molding compound 1902 form a molded assembly 2002 that is disassembled from carrier 1302. The second surfaces 1704 of the substrates 204a-204e are flush with and exposed to the surface of the mold assembly 2002 (the bottom surface in FIG. 20). Otherwise, the dies 1102a-1102e and substrates 204a-204e are encapsulated by the molding compound 1902 in the mold assembly 2002. The carrier 1302 may be removed from the mold assembly 2002 in any manner. For example, the mold assembly 2002 may be peeled from the carrier 1302, the mold assembly 2002 and/or the carrier 1302 may be heated or cooled, the carrier 1302 may be caused or enabled to detach from the mold assembly 2002, and/or the like. In one embodiment, molding compound 1902 is attached to substrates 204a-204e more securely than the attachment to carrier 1302 (e.g., more securely than the adhesive material that attaches substrates 204a-204e to carrier 1302) to enable substrates 204a-204e to be removed from carrier 1302 with molding compound 1902, rather than leaving substrates 204a-204e on carrier 1302 after removal.

In step 1210, a plurality of interconnects are attached to each substrate on a surface of a mold assembly. For example, in an embodiment, a plurality of interconnects are attached to the second surface 1704 of the substrate 204 in the mold assembly 2002. The interconnects may be used to enable mounting of the molded assembly 2002 to a circuit board (e.g., a printed circuit board, etc.) to produce an IC package. Examples of such interconnects include bump interconnects (e.g., solder balls) of BGA packages, pins (e.g., of array pin Packages (PGAs)), posts (posts), or other types of interconnects. The substrate 204 of the mold assembly 2002 may employ these interconnections in any manner, including according to conventional and proprietary techniques.

For example, fig. 21 illustrates a side cross-sectional view of the molded assembly 2002 of fig. 20 with solder balls 2102 attached, in accordance with an embodiment of the invention. As shown in fig. 21, a plurality of solder balls 2102 are attached to the second surface 1704 of each of the substrates 204a and 204 b. Each solder ball 2102 is attached to a corresponding solder ball pad. Thus, the signal at the terminal of each IC die 1102 is electrically connected to the solder ball 2102 via interconnections (e.g., plungers or bumps) between the IC die 1102 and the substrate 204, wiring on the surface 1702 of the substrate 204, vias to conduct through the substrate 204, additional wiring optionally present in further wiring layers of the substrate 204, and wiring from the surface 1704 of the substrate 204 to the solder ball pad.

Referring back to fig. 12, in step 1212, the mold assembly is singulated to form a plurality of integrated circuit packages, each integrated circuit package including at least one die and a substrate. For example, fig. 22 shows a first IC package 2202a and a second IC package 2202b singulated from the molded assembly 2002 of fig. 21. Many IC packages 2202, including 10s, 100s, and even thousands of IC packages 2202, may be singulated from a molded assembly. As shown in fig. 22, IC package 2202a includes a die 1102a attached to substrate 204a, a molding compound 1902 encapsulating die 1102a on substrate 204a, and solder balls 2102 attached to second surface 1704 of substrate 204 a. In addition, the IC package 2202b includes a die 1102b attached to the substrate 204b, a molding compound 1902 encapsulating the die 1102b on the substrate 204b, and solder balls 2102 attached to the second surface 1704 of the substrate 204 b.

Those skilled in the art will appreciate that IC package 2202 may be singulated from molded assembly 2002 in any suitable manner such that they are physically separated from each other. For example, a saw, router, laser, etc. may be used to singulate the IC package 2202 in a conventional or other manner. The IC packages 2202a and 2202b of fig. 22 can be singulated from the molded assembly 2002 of fig. 21 by cutting through the molding compound 1902 to separate the IC packages 2202a and 2202b from each other and from other IC packages 2202 (not shown in fig. 21). In one embodiment, the dicing may be performed directly adjacent to the perimeter edges of the substrates 204a and 204b, such that the molding compound 1902 does not remain around (i.e., exposes) the perimeter edges of the substrates 204a and 204b in the IC packages 2202a and 2202 b. Alternatively, as shown in fig. 22, the dicing may be performed at a distance from the peripheral edges of the substrates 204a and 204b such that some molding compound 1902 remains around the peripheral edges of the substrates 204a and 204b in the IC packages 2202a and 2202b (i.e., the peripheral substrate edges are not exposed).

For example, fig. 23 shows a side cross-sectional view of an IC package 2202a singulated from a molded assembly 2002. As shown in fig. 23, the space 2302 adjacent to the outer edge of the substrate 204a is filled with the molding compound 1902 (e.g., the peripheral edge of the substrate 204 a), forming a ring of the molding compound 1902 surrounding the substrate 204 a. In this manner, only the second surface 1704 of the substrate 204a is exposed (i.e., not covered by the molding compound 1902). This enables the outer edge of the substrate 204a to be protected from the environment by the molding compound 1902.

In addition, the peripheral ring of molding compound 1902 enables undersized substrates 204 to be formed at will, with the molding compound 1902 compensating for the reduced size. For example, a 7mm by 7mm sized IC package 2202a is required. Thus, the IC package 2202a may be sized at 7mm by forming the substrate 204a at 6.6mm by 6.6mm, and cutting (during or after singulation) the molding compound 1902 in the space 2302 around the substrate 204a to have a thickness of 0.2 mm. In this manner, the utilization rate of the substrate panel is further improved by including a smaller substrate in the substrate panel, and therefore, a large number of substrates can be included in the substrate panel. Furthermore, when the substrate 204a does not extend completely to the edge of the IC package 2202a, the IC package 2202a includes less of the substrate 204a and more of the molding compound 1902, reducing the overall cost of the IC package 2202a (since the same volume of molding compound 1902 is less expensive than the substrate 204 a).

Third, conclusion

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims appended hereto and their equivalents.

Claims (10)

1. A method of assembling an integrated circuit package, the method comprising:

forming a substrate panel including a plurality of substrates, each of the substrates including a wiring;

testing the substrate in the substrate panel to determine a set of working substrates;

dividing the substrate panel to separate into the plurality of substrates;

attaching a subset of the separated substrates to a surface of a carrier, the subset of separated substrates being the set of working substrates;

attaching one or more wafers to each of the substrates on the carrier;

encapsulating the die and the substrate with a molding compound on the carrier;

detaching the carrier from the packaged die and substrate to form a molded assembly comprising the molding compound used to package the die and substrate;

attaching a plurality of interconnects to each of the substrates on a surface of the mold assembly; and

the molded assembly is singulated to form a plurality of integrated circuit packages, each integrated circuit package including at least one of the die and the substrate, with a perimeter ring of the molded assembly surrounding an outer edge of the substrate.

2. The method of assembling an integrated circuit package of claim 1, further comprising:

electroplating the substrate in the substrate panel using a plunger to form conductive contacts for attaching the wafer to the substrate.

3. The method of assembling an integrated circuit package of claim 1, wherein forming a substrate panel comprising a plurality of substrates, each substrate comprising wiring, comprises:

forming the substrate panel to include the substrates in an array that fills the substrate panel except for a peripheral edge region of the substrate panel around the array.

4. The method of assembling an integrated circuit package of claim 1, wherein said attaching the separated subset of substrates to a surface of a carrier comprises:

positioning the separated substrates to be spaced apart on the surface of the carrier.

5. The method of assembling an integrated circuit package of claim 4, wherein said encapsulating said die and said substrate with a molding compound on said carrier comprises:

filling a space between the separated substrate and the molding compound.

6. The method of assembling an integrated circuit package of claim 5, wherein said singulating the mold assembly to form a plurality of integrated circuit packages comprises:

the molded assembly is singulated such that each integrated circuit package includes a perimeter ring of molding compound around an outer edge of the contained substrate.

7. A method of assembling an integrated circuit package, the method comprising:

receiving a plurality of separated substrates tested as working substrates divided from a substrate panel;

attaching the substrate to a surface of a carrier;

mounting one or more wafers to each of the substrates on the carrier;

encapsulating the die and the substrate with a molding compound on the carrier;

detaching the carrier from the packaged die and substrate to form a molded assembly comprising the molding compound used to package the die and substrate;

attaching a plurality of interconnects to each of the substrates on a surface of the mold assembly; and

the molded assembly is singulated to form a plurality of integrated circuit packages, each integrated circuit package including at least one of the die and the substrate, with a perimeter ring of the molded assembly surrounding an outer edge of the substrate.

8. The method of assembling an integrated circuit package of claim 7, wherein said attaching said substrate to a surface of a carrier comprises:

the substrates are positioned to be spaced apart on the surface of the carrier.

9. The method of assembling an integrated circuit package of claim 8, wherein said encapsulating said die and said substrate with a molding compound on said carrier comprises:

filling the space between the substrates with the molding compound.

10. An integrated circuit package according to the method of claim 1 or 7.