HK1168909A - Low power inversion scheme with minimized number of output transitions - Google Patents

Description

Low power inversion scheme with minimized number of output transitions

Technical Field

The present disclosure relates generally to control of a display in a device.

Background

This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present disclosure that are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.

Liquid Crystal Displays (LCDs) are commonly used as screens or displays for a wide variety of electronic devices, including consumer electronic devices such as televisions, computers, and handheld devices (e.g., cellular telephones, audio and video players, gaming systems, etc.). Such LCD devices typically provide flat panel displays in a relatively thin package, which is suitable for use in a variety of electronic goods. Furthermore, such LCD devices typically use less power than comparable display technologies, making them suitable for use in battery-powered devices or in other environments where it is desirable to minimize power usage.

LCDs typically include an LCD panel having therein a layer of liquid crystals and various circuits for controlling the orientation of the liquid crystals within the layer to modulate the amount of light passing through the LCD panel and thereby render an image on the panel. If a voltage of a single polarity is applied to the liquid crystal layer all the time, a bias (polarization) of the liquid crystal layer occurs, so that the light transmission characteristics of the liquid crystal layer may be disadvantageously changed.

To help prevent such a bias of the liquid crystal layer, periodic inversion (inversion) of an electric field applied to the liquid crystal layer may be employed. Also, various inversion techniques may be used to reduce visual artifacts caused by slight differences in the values of the positive and negative voltages applied during the periodic inversion of the electric field applied to the liquid crystal layer. For example, the dot inversion (dot inversion) method may cause each adjacent (adjacent) pixel location in the liquid crystal layer to be driven with an opposite voltage to its neighboring (neighbor) pixel location within a given time frame. This technique may greatly reduce the generation of visual artifacts on the LCD, however, it may require a large amount of power to perform. Therefore, there is a need for low power inversion techniques that minimize the generation of visual artifacts on LCDs.

Disclosure of Invention

The following sets forth a summary of certain embodiments disclosed herein. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these particular embodiments, and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects that may not be set forth below.

A method and system for driving a matrix of pixels in a display with alternating positive and negative voltages is provided. A column driver of the display may drive a first voltage, e.g., a positive voltage, to a selected row along a column of a pixel array (matrix) in the display during a first time period of a frame (i.e., the first half of the time required to update data for the entire pixel matrix). The column driver may then drive an inverted voltage (invert voltage) of the first voltage to the remaining rows along the columns of the pixel array during a second time period of the frame. That is, the row driver may alternately activate, for example, even rows followed by odd rows (or alternatively, activate odd rows followed by even rows) during the first period and the second period. In this manner, for example, odd rows driven with a first voltage may be scanned during a first period of time of a frame, and even rows driven with an inverse voltage of the first voltage may be scanned during a second period of time of the frame. In addition, since the rows are scanned alternately in two steps, the image data can be pre-arranged before being scanned into the display. That is, each of the odd and even lines of data may be grouped such that first the even lines are scanned into the display, then the odd lines are scanned into the display, and vice versa.

Drawings

Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings in which:

FIG. 1 is a block diagram of an electronic device in accordance with aspects of the present disclosure;

FIG. 2 is a perspective view of a computer according to aspects of the present disclosure;

FIG. 3 is a perspective view of a handheld electronic device in accordance with aspects of the present disclosure;

FIG. 4 is an exploded view of a Liquid Crystal Display (LCD) according to aspects of the present disclosure;

FIG. 5 illustrates circuitry that may be found in the LCD of FIG. 4 in accordance with aspects of the present disclosure;

FIG. 6 is a block diagram representing how the LCD of FIG. 4 receives data and drives a pixel array of the LCD, in accordance with aspects of the present disclosure;

FIG. 7 is another block diagram of the electronic device of FIG. 1 in accordance with aspects of the present disclosure;

FIG. 8 is a diagram of a liquid crystal display of the electronic device of FIG. 7;

FIG. 9 is a diagram of a pixel matrix of the liquid crystal display of FIG. 8;

FIG. 10 is a second diagram of a pixel matrix of the liquid crystal display of FIG. 8;

FIG. 11 is a second diagram of a liquid crystal display of the electronic device of FIG. 7;

fig. 12 is a timing chart illustrating an operation of elements of the liquid crystal display of fig. 11; and

FIG. 13 is a second timing diagram illustrating the operation of the elements of the liquid crystal display of FIG. 11

Detailed Description

One or more specific embodiments are described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

Certain embodiments of the present disclosure generally relate to reducing power consumption of an electronic display (e.g., an LCD) by driving a matrix of pixels in the display with alternating positive and negative voltages to help prevent biasing of the pixels in the display. For example, a column driver of a display may drive a first voltage (e.g., a positive voltage) to a selected row of a pixel array in the display during a first time period of a frame (i.e., the time required to update data for the entire pixel matrix), and may then drive a second (inverted) voltage of the first voltage to the remaining rows of the pixel array during a second time period of the frame. That is, the row driver may alternately activate, for example, even rows and odd rows during the first period and the second period in conjunction with the first voltage and the second voltage. In this manner, for example, odd rows driven with a first voltage may be scanned during a first period of time of a frame, and even rows driven with an inverse voltage of the first voltage may be scanned during a second period of time of the frame. Alternatively, for example, even rows driven with a first voltage may be scanned during a first period of time of one frame, and odd rows driven with an inverse voltage of the first voltage may be scanned during a second period of time of the frame. In addition, the data for display on the display may be arranged such that the data is sent to the activated rows of the pixels of the matrix in conjunction with the alternating activation of the rows as described above. In view of the above, a general description of an electronic device including a display that can use the presently disclosed technology follows.

It will be appreciated that an electronic device may include various internal and/or external components that contribute to the functionality of the device. For example, FIG. 1 is a block diagram illustrating components that may be present in one such electronic device 10. Those of ordinary skill in the art will appreciate that the various functional blocks shown in fig. 1 may include hardware elements (including circuitry), software elements (including computer code stored on a computer-readable medium such as a hard drive or system memory), or a combination of hardware and software elements. Fig. 1 is only one example of a particular implementation and is intended merely to illustrate the types of components that may be present in electronic device 10. For example, in the presently illustrated embodiment, these components may include a display 12, input/output (I/O) ports 14, input structures 16, one or more processors 18, one or more memory devices 20, a non-volatile storage device 22, expansion cards 24, networking devices 26, and a power supply 28.

The display 12 may be used to display various images generated by the electronic device 10. The display 12 may be any suitable display, such as a Liquid Crystal Display (LCD) or an Organic Light Emitting Diode (OLED) display. Additionally, in particular embodiments of electronic device 10, display 12 may be provided in conjunction with a touch-sensitive element (e.g., a touch screen) that may be used as part of a control interface for device 10.

The I/O ports 14 may include ports configured to connect to a variety of external devices, such as a power supply, headphones or earphones, or other electronic devices (e.g., handheld devices and/or computers, printers, projectors, external displays, modems, docking stations, etc.). The I/O ports 14 may support any interface type, such as a Universal Serial Bus (USB) port, a video port, a serial connection port, an IEEE-1394 port, an Ethernet or modem port, and/or an AC/DC power connection port.

Input structures 16 may include various devices, circuits, and pathways that provide user input or feedback to processor 18. Such input structures 16 may be configured to control functions of the electronic device 10, applications running on the device 10, and/or any interfaces or devices connected to the device 10 or used by the device 10. For example, the input structures 16 may allow a user to navigate a displayed user interface or application interface. Non-limiting examples of input structures 16 include buttons, sliders, switches, control pads, keys, knobs, scroll wheels, keyboards, mice, touch pads, and the like. Additionally, in certain embodiments, one or more input structures 16 may be provided with the display 12, such as in the case of a touch screen in which a touch sensitive mechanism is provided in conjunction with the display 12.

The processor 18 may provide processing capabilities for executing an operating system, programs, user and application interfaces, and any other functions of the electronic device 10. The processor 18 may include one or more microprocessors, such as one or more "general purpose" microprocessors, one or more special purpose microprocessors or ASICs, or some combination of these processing components. For example, the processors 18 may include one or more Reduced Instruction Set (RISC) processors, as well as graphics processors, video processors, audio processors, and so forth. It should be understood that the processor 18 may be communicatively coupled to one or more data buses or chip sets for transferring data and instructions between the various components of the electronic device 10.

The programs or instructions executed by the processor 18 may be stored in any suitable article of manufacture including one or more tangible computer-readable media (which at least collectively store the executed instructions or routines), such as, but not limited to, the memory devices and storage devices described below. Also, the programs (e.g., operating systems) encoded on such computer program products may also include instructions executable by processor 18 to enable device 10 to provide various functionality, including the functionality described herein.

Instructions or data to be processed by the one or more memories 18 may be stored in a computer readable medium, such as the memory 20. The memory 20 may include volatile memory (e.g., Random Access Memory (RAM)) and/or non-volatile memory (e.g., Read Only Memory (ROM)). The memory 20 may store various information and may be used for various purposes. For example, the memory 20 may store firmware of the electronic device 10, such as a basic input/output system (BIOS), an operating system, and various other programs, applications, or routines that may be executed on the electronic device 10. Further, the memory 20 may be used for buffering or caching during operation of the electronic device 10.

The components of device 10 may also include other forms of computer-readable media, such as non-volatile storage 22 for persistent storage of data and/or instructions. The non-volatile storage 22 may include, for example, flash memory, a hard drive, or any other optical, magnetic, and/or solid-state storage medium. The non-volatile storage device 22 may be used to store firmware, data files, software programs, wireless connection information, and any other suitable data.

The embodiment illustrated in fig. 1 may also include one or more card slots or expansion slots. The card slot may be configured to receive one or more expansion cards 24, which expansion cards 24 may be used to add functionality to the electronic device 10, such as additional memory, I/O functionality, or networking capabilities. Such expansion cards 24 may connect to device 10 through any type of suitable connector, and may be accessed inside or outside the housing of electronic device 10. For example, in one embodiment, expansion card 24 may include a flash memory card, such as a Secure Digital (SD) card, a mini or micro SD, compact flash, multimedia card (MMC), or the like. Additionally, expansion card 24 may include one or more processors 18 of device 10, such as a video graphics card having a GPU to facilitate graphics rendering by device 10.

The components shown in FIG. 1 also include a network device 26, such as a network controller or a Network Interface Card (NIC). In one embodiment, network device 26 may be a wireless NIC providing wireless connectivity over any 802.11 standard or any other suitable wireless networking standard. The device 10 may also include a power supply 28. In one embodiment, the power source 28 may include one or more batteries, such as lithium ion polymer batteries or other types of suitable batteries. Additionally, the power source 28 may include AC power, such as provided by an electrical outlet, and the electronic device 10 may be connected to the power source 28 via a power adapter. The power adapter may also be used to charge one or more batteries of the device 10.

The electronic device 10 may take the form of a computer system or some other type of electronic device. Such computers may include computers that are generally portable (e.g., laptop, notebook, tablet, and handheld computers), as well as computers that are generally used in one location (e.g., conventional desktop computers, workstations, and/or servers). In particular embodiments, electronic device 10 in the form of a computer may include a model number available from apple Inc. of Kubinuo, CalifPro、MacBookmini orPro. For example, FIG. 2 illustratesAn electronic device 10 according to one embodiment is in the form of a laptop computer 30. The illustrated computer 30 includes a housing 32, a display 12 (e.g., in the form of an LCD34 or some other suitable display), I/O ports 14, and input structures 16.

The display 12 may be integral with the computer 30 (e.g., the display of a laptop computer as shown), or may be a separate display connected with the computer 30 using one of the I/O ports 14, such as via a displayport, Digital Video Interface (DVI), high-definition multimedia interface (HDMI), or analog (D-sub) interface. For example, in particular embodiments, the stand-alone display 12 may be a model Apple Cinema available from Apple Inc

Although the electronic device 10 is generally illustrated in fig. 2 in the context of a computer, the electronic device 10 may also take the form of other types of electronic devices. In some embodiments, the various electronic devices 10 may include mobile telephones, media players, personal data organizers, handheld game platforms, cameras, and combinations of these devices. For example, as generally shown in FIG. 3, the device 10 may be provided in the form of a handheld electronic device 36, the handheld electronic device 36 including various functions (e.g., the ability to take pictures, make telephone calls, access the Internet, communicate via email, record audio and video, listen to music, play games, and connect to a wireless network). By way of further example, handheld device 36 may be a model available from apple IncOr

The handheld device 36 of the presently illustrated embodiment includes a display 12, which display 12 may take the form of an LCD 34. The LCD34 may display various images generated by the handheld device 36, such as a Graphical User Interface (GUI)38 having one or more icons 40. The device 36 may also include various I/O ports 14 to facilitate interaction with other devices and user input structures 16 to facilitate interaction with a user.

FIG. 4 illustrates one example of an LCD display 34 according to one embodiment. The illustrated LCD display 34 includes an LCD panel 42 and a backlight unit 44 that may be assembled within a frame 46. It is understood that the LCD panel 42 may include an array of pixels configured to selectively modulate the amount and color of light passing from the backlight unit 44 through the LCD panel 42. For example, the LCD panel 42 may include a liquid crystal layer, one or more Thin Film Transistor (TFT) layers configured to control the orientation of liquid crystals in the liquid crystal layer via an electric field, and polarizing films that cooperate to enable the LCD panel 42 to control the amount of light emitted by each pixel. In addition, the LCD panel 42 may include color filters that allow light of specific colors (e.g., red, green, and blue) to be emitted from the pixels.

The backlight unit 44 includes one or more light sources 48. Light from the light source 48 passes through portions of the backlight unit 44 (e.g., the light guide and the optical films) and is generally emitted toward the LCD panel 42. In various embodiments, the light source 48 may include a Cold Cathode Fluorescent Lamp (CCFL), one or more Light Emitting Diodes (LEDs), or any other suitable light source. Further, although the LCD34 is generally shown with an edge-lit backlight unit 44, it is noted that other configurations (e.g., direct backlight) may be used in accordance with the present techniques.

Referring now to fig. 5, an example of a circuit diagram of a pixel drive circuit found in LCD34 is provided. For example, the circuit shown in FIG. 5 may be implemented on the LCD panel 42 as described above with reference to FIG. 4. The pixel drive circuit includes an array or matrix 54 of unit pixels 60 driven by a data (or source) line drive circuit 56 and a scan (or gate) line drive circuit 58. As shown, the matrix 54 of unit pixels 60 forms the image display area of the LCD 34. In such a matrix, each unit pixel 60 may be defined by the intersection of a data line 62 and a scan line 64, the data line 62 and the scan line 64 also being referred to as a source line 62 and a gate (or video scan) line 64. The data line driving circuit 56 may include one or more driver integrated circuits (also referred to as column drivers) for driving the data lines 62. The scan line driver circuit 58 may also include one or more driver integrated circuits (also referred to as row drivers).

Each unit pixel 60 includes a pixel electrode 66 and a Thin Film Transistor (TFT)68 for switching the pixel electrode 66. In the illustrated embodiment, the source electrode 70 of each TFT68 is electrically connected to the data line 62 extending from the corresponding data line drive circuit 56, and the drain electrode 72 is electrically connected to the pixel electrode 66. Similarly, in the illustrated embodiment, the gate 74 of each TFT68 is electrically connected to a scan line 64 extending from a corresponding scan line driver circuit 58.

In one embodiment, the column drivers of the data line driving circuit 56 send image signals to the pixels via the respective data lines 62. Such image signals may be applied line-sequentially, i.e., the data lines 62 may be activated sequentially during operation. The scan line 64 may apply a scan signal from the scan line driver circuit 58 to the gate 74 of each TFT 68. Such a scanning signal may be applied in a line sequence at a predetermined timing or in a pulse manner.

Each TFT68 functions as a transistor that can be activated and deactivated (i.e., turned on and off) for a predetermined period of time based on the presence or absence of a scan signal at its gate 74. The TFT68, when activated, may store an image signal received via the corresponding data line 62 as an electric charge in the pixel electrode 66 at a predetermined timing.

The image signals stored at the pixel electrodes 66 may be used to generate an electric field between the corresponding pixel electrodes 66 and the common electrode. Such an electric field may align liquid crystals in the liquid crystal layer to modulate light transmission through the LCD panel 42. The unit pixel 60 may operate in conjunction with various color filters, such as red, green, and blue color filters. In such embodiments, a "pixel" of the display may actually include a plurality of unit pixels, such as a red unit pixel, a green unit pixel, and a blue unit pixel, each of which may be modulated to increase or decrease the amount of light emitted, to enable the display to present multiple colors via additive mixing of colors.

In some embodiments, a storage capacitor may be disposed in parallel with a liquid crystal capacitor formed between the pixel electrode 66 and the common electrode to prevent leakage of the image signal stored at the pixel electrode 66. Such a storage capacitor may be provided between the drain 72 of the respective TFT68 and a separate capacitor line, for example.

In block diagram 80 of FIG. 6, certain components for processing image data and rendering an image based on such data on LCD34 are shown, according to one embodiment. In the illustrated embodiment, a Graphics Processing Unit (GPU) in block 82 or some other processor 18 sends the data in block 84 to a timing controller in block 86 of the LCD 34. This data typically includes image data that may be processed by the circuitry of LCD34 to drive pixels 60 of LCD34 and render an image on LCD 34. The timing controller in block 86 may then send signals to and control the operation of one or more column drivers (or other data line driver circuits 56) in block 88 and one or more row drivers (or other scan line driver circuits 58) in block 90. These column and row drivers may generate analog signals for driving the individual pixels 60 of the pixel array of the LCD34 in block 92. In addition, in one embodiment, data line driver circuit 56 may include a single column driver that may be switched to drive each of a plurality of columns in LCD34, while scan line driver circuit 58 may include a single row driver that may be switched to drive each of a plurality of rows in LCD 34.

FIG. 7 illustrates an embodiment that may be used to implement the steps described above with reference to block diagram 80. FIG. 7 includes an illustration of device 10, which device 10 includes a Graphics Processing Unit (GPU)94 that may be coupled to display 12 via path 96. GPU 94 may include one or more microprocessors, such as one or more "general purpose" microprocessors, one or more special purpose microprocessors or ASICs, or some combination of such processing components. In one embodiment, GPU 94 may be separate from processor 18. Alternatively, GPU 94 may be one of a plurality of processors included in processor 18. As indicated, GPU 94 may be coupled to display 12 via path 96. Path 96 may allow data transfer between GPU 94 and display 12, and control signal transfer between GPU 94 and display 12. For example, frame data for display on the LCD34 of the display 12 may be sent from the GPU 94 to the display 12. The frame data may be stored in frame buffer 98 before being sent to display 12. The data stored in the frame buffer 98 may be transmitted as an entire frame of data to be displayed on the LCD34 at a specified time (i.e., data to be displayed during a time period required to transmit data to all pixels of the display 12). Alternatively, a portion of a frame of data to be displayed on LCD34 at a specified time may be sent from frame buffer 98 to display 12.

As noted above, data may be sent from GPU 94 to display 12, which may include image data that may be processed by the circuitry of LCD34 to drive pixels 60 of LCD34 and render an image on LCD 34. The data may be received by the timing controller 100. In one embodiment, the timing controller 100 is operable to control the timing of the data line driving circuit 56 or the scan line driving circuit 58 of the LCD 34. Control of the data line drive circuits 56 or the scan line drive circuits 58 (which may include a single-switch column driver or multiple column drivers in each data line drive circuit 56 and a single-switch row driver or multiple row drivers in each scan line drive circuit 58) may be achieved by generating and sending display signals (e.g., via the drivers 102). These display signals may be based on data received along path 96 and/or based on control signals received along path 96 and may include column driver signals sent to column drivers 104 in data line drive circuit 56 and gate pulse signals sent to gate drivers 106 in scan line drive circuit 58 of LCD 34.

Column driver 104 and row driver 106 may generate analog signals for driving individual pixels 60 of a pixel array of LCD 34. In some implementations, the timing controller 100 can send data and timing signals to the column driver 104 via, for example, one or more flex circuits 108. The column driver 104 or other circuitry in the data line driver circuitry 56 may then forward the appropriate timing or data information to the row driver 106. In other implementations, the timing controller 100 may provide timing information directly to each of the column driver 104 and the row driver 106.

Additionally, display 12 may include a frame buffer 110 that may be used in place of frame buffer 98. The frame buffer 110 may be coupled to the timing controller 100 and may be used to store data related to a single frame (i.e., a period of time to send data to all pixels 60 in the display 12) to be displayed on the LCD34 at a specified time. The data stored in the frame buffer 110 may be retrieved by the timing controller 100 in a particular order, for example. For example, the timing controller 100 may acquire data or timing signals related to the even-numbered video scan lines 64 for a given frame to transmit the data or timing signals to the LCD 34. Next, the timing controller 100 may acquire data or timing signals related to the odd-numbered video scan lines 64 for a given frame to transmit the data or timing signals to the LCD 34. In this manner, frame buffer 110 local to timing controller 100 may be used to make changes to the transmission of data or timing signals to LCD 34. It should be noted that the same processing described above for modified retrieval of data from frame buffers 110 may be performed alternately by GPU 94 in conjunction with frame buffers 98. For example, instead of sending an entire frame of data to display 12, GPU 12 may retrieve and send data related to even numbered video scan lines 64 for a given frame, and may then retrieve and send data related to odd numbered video scan lines 64 of LCD 34.

To help prevent biasing of the liquid crystal layer of the LCD panel 42, periodic inversion of the electric field applied to the liquid crystal layer may be employed. For example, the dot inversion method may cause each neighboring unit pixel 60 in the liquid crystal layer to be driven at a voltage opposite to that of its neighboring unit pixel 60 within a given time frame. Fig. 8 illustrates such a dot inversion technique.

FIG. 8 illustrates column drivers 104a-104l and row drivers 106a-106e, as well as a plurality of unit pixels 60a-60 e. Each of the unit pixels 60a-60e may be coupled to a particular column driver 104l via a source line 62l and to a particular row driver 106a-106e via a particular video scan line 64a-64 e. As previously indicated, each of the column drivers 104a-104l may be driven with a signal generated by the timing controller 100 and sent from the driver 102. Also, the column driver outputs 112a-112l illustrate the outputs of the column drivers 104a-104l resulting from signals received from the timing controller 100.

As shown in FIG. 8, the column driver outputs 112a-112l for each column driver 104a-104l are alternating signals that alternate between positive and negative values to help prevent biasing of the LCD 34. Also, the column driver outputs 112a-112l may be sent to the unit pixels 60 in a sequential manner. For example, the column driver output 112l may first be a negative voltage, e.g., -5 volts. This value may be output from the column driver 104l for a first time period within one frame. When this negative voltage is sent from column driver 104l along source line 62l, a strobe signal may be sent from row driver 106a along video scan line 64 a. This may cause the unit pixel 60a to be driven with the value sent from the column driver 104l (represented in fig. 8 as directional arrow 114 and a negative value in the unit pixel 60 a). The output 112l of the column driver 104l may then be switched to a positive voltage, for example 5 volts. This value may be output from column driver 104l during a second time period immediately following the first time period within the same frame. When this positive voltage is sent from the column driver 104l along source line 62l, a strobe signal may be sent from the row driver 106b along video scan line 64 b. This may cause the unit pixel 60b to be driven with the value sent from the column driver 104l (represented in fig. 8 as directional arrow 116 and a positive value in the unit pixel 60 b). Additionally, the example output voltages described above may not necessarily be absolute positive or negative values. That is, the output values may all be positive, while the relative voltages may be negative when they are applied to a pixel electrode having a particular reference voltage level. For example, if the absolute pixel voltage is 5 volts and the reference voltage is 1 volt, then the relative voltage across the liquid crystal layer is-4 volts.

This process may be repeated for each unit pixel 60c-60e, as indicated by directional arrows 118, 120 and 122, until each unit pixel 60a-60e has been updated with a value corresponding to the corresponding output of the column driver 104 l. Also, this process may be applied simultaneously to each of the column drivers 104a-104l and row drivers 106a-106 e. When each unit pixel 60 is updated with a column driver output 112a-112l, a frame (i.e., the update of the entire matrix 54 of unit pixels 60) is completed. These frames may occur, for example, at a rate of 30, 60, or more frames per second.

Once a frame is complete, the column driver outputs 112a-112l may be inverted by inverting the oscillation signals sent to the column drivers 104a-104l during a second frame that immediately follows the first frame. That is, in the second frame, the unit pixels 60a, 60c, 60e, etc. receive positive values, and the unit pixels 60b, 60d, 60f, etc. receive negative values. Fig. 9 and 10 illustrate the results.

FIG. 9 illustrates the matrix 54 of unit pixels 60 after a first frame, with the column driver outputs 112a-112l for each column driver 104a-104l illustrated in FIG. 8. Similarly, FIG. 10 illustrates the matrix 54 of unit pixels 60 immediately following the second frame of the first frame, with the column driver outputs 112a-112l for each column driver 104a-104l being the inverse of that illustrated in FIG. 8. Also, the matrix 54 of unit pixels 60 in fig. 9 may represent a subsequent odd frame, while the matrix 54 of unit pixels 60 in fig. 9 may represent a subsequent even frame. In this manner, unit pixels 60 may oscillate between positive and negative values from one frame to the next to help prevent biasing of LCD 34.

While the oscillation of the polarity of the unit pixels 60 in subsequent frames is desirable to help prevent biasing of the LCD34, the use of the oscillation signals sent to the column drivers 104a-104l to generate the column driver outputs 112a-112l may require a significant amount of power to drive the liquid crystals in each unit pixel to alternating voltage polarities in a periodic manner. That is, the individual transitions (transitions) of the column drivers 104a-104l (the individual generations of oscillations of the column driver outputs 112a-112 l) consume power at a higher rate than if positive or negative voltages were sent from the column drivers 104a-104l at a lower rate. It is therefore beneficial to drive the unit pixels 60 of the matrix 54 with reduced transitions by the column drivers 104a-104l, as shown in fig. 9 and 10.

FIG. 11 illustrates a second set of column driver outputs 124a-124l for each of the column drivers 104a-104 l. As shown, the column driver outputs 124a-124l oscillate only once per frame, i.e., the column driver outputs 124a-124l are driven to a positive voltage once and a negative voltage once per frame. In this manner, transitions from positive to negative voltages (or negative to positive) occur only once per frame, and therefore require less power consumption than that used to generate column driver outputs 124a-124 l. However, instead of sending each column driver output 124a-124l to each unit pixel 60 in a sequential manner, the unit pixels 60 to be driven to negative values may, for example, receive a negative voltage column driver output (e.g., a negative voltage from the column driver output 124 l), followed by the unit pixels 60 to be driven to positive values may, for example, receive a positive voltage column driver output (e.g., a positive voltage from the column driver output 124 l).

For example, the column driver output 124l may first be a negative voltage, e.g., -5 volts. This value may be output from the column driver 104l for a first time period within one frame. When this negative voltage is sent from column driver 104l along source line 62l, a gate signal may be sent from row driver 106a along gate line 64 a. This may cause the unit pixel 60a to be driven with the value sent from the column driver 104l (represented in fig. 11 as the directional arrow 126 and the negative value in the unit pixel 60 a). While the column driver 104l maintains this negative voltage along output 124l of source line 62l, a gate signal may be sent from row driver 106c along gate line 64c during a second time period of the same frame, immediately following the first time period. This may cause the unit pixel 60c to be driven with the value sent from the column driver 104l (represented in fig. 11 as the directional arrow 128 and the negative value in the unit pixel 60 c). This process may continue for all odd rows in the matrix 54 (e.g., according to directional arrow 130 and a negative value in the unit pixel 60e) until all odd rows of the source line 62l are driven to a negative voltage with the negative drive column driver output 124 l.

After all odd rows of source line 62l have been driven to a negative voltage by the negatively charged column driver output 124l, the column driver output 124l may be driven to a positive voltage, e.g., 5 volts. This value may be output from the column driver 104l for a period of time immediately following the last unit pixel 60 in an odd row of the matrix 54 being driven with the column driver output 124 l. When this positive voltage is sent from column driver 104l along source line 62l, a gate signal may be sent from row driver 106b along gate line 64 b. This may cause the unit pixel 60b to be driven with a positive value sent from the column driver 104l (represented in fig. 11 as directional arrow 132 and the positive value in the unit pixel 60 b). This process may be repeated for unit pixel 60d (as indicated by directional arrow 134) and all remaining even rows of unit pixels 60 until each unit pixel 60 in matrix 54 has been updated with a value corresponding to a respective output of column driver 104 l. Also, this process may be applied simultaneously to each of the column drivers 104a-104l and row drivers 106a-106 e. In addition, the process may be modified by first driving the odd rows of matrix 54 to positive values during a first time period of a frame, and driving the even rows to negative voltages during a second time period of a frame, and then reversing for the next frame. Alternatively, for example, the even rows of matrix 54 may be driven to a first voltage (either positive or negative) first during a first time period of a frame, while the odd rows are driven to the opposite voltage (either negative or positive) of the first voltage during a second time period of the frame, and then reversed for the next frame.

When each unit pixel 60 is updated with a column driver output 124a-124l, a frame (i.e., data update for the entire matrix 54 of unit pixels 60) is completed. These frames may occur, for example, at a rate of 30, 60, or more frames per second. This may occur for each of the column drivers 104a-104l such that each unit pixel 60 included in the matrix 54 is driven to the opposite polarity of the immediately adjacent row and column of that unit pixel 60. Also, the image data to be displayed may be pre-arranged before being scanned into the display 34. That is, each of the odd and even lines of data may be grouped in such a way that the even lines are scanned into the display 34 first, followed by the odd lines into the display 34, to match the order of gate line driving, so that the final image displayed is correct.

Once a frame is completed, the column driver outputs 124a-124l may be switched back to negative values sent to the even rows of the matrix 54 (e.g., including unit pixels 60b and 60d), followed by negative values sent to the odd rows of the matrix 54 (e.g., including unit pixels 60a, 60c, and 60e) during the next frame following the first frame. Alternatively, once the first frame is completed, the column driver outputs 124a-124l may continue to transmit positive values that may be read into odd rows of the matrix 54 (e.g., including unit pixels 60a, 60c, and 60e), followed by negative values that may be transmitted into even rows of the matrix 54 (e.g., including unit pixels 60b and 60d), during the next frame immediately following the first frame. In either case, in the second frame, unit pixels 60a, 60c, 60e, etc. receive positive values, while unit pixels 60b, 60d, 60f, etc. receive negative values. Thus, the column driver outputs 124a-124l may be used to generate the same results illustrated in the matrix 54 in FIGS. 9 and 10, with reduced transitions for the column drivers 104a-104 l.

Fig. 12 illustrates a timing diagram corresponding to fig. 11. For example, output 136 may correspond to a column driver output, e.g., column driver output 124 l. In the first half 138 of the frame 140, the output 136 may be a negative value, e.g., -5 volts. This value may be sent to a column driver, such as column driver 104 l. In the first half 138 of the frame 140, the various gates may be activated sequentially, as represented by the strobe output signals 144, 146, and 148. For example, gate output signal 144 may correspond to a signal sent from row driver 106a along gate line 64a, gate output signal 146 may correspond to a signal sent from row driver 106c along gate line 64c, and gate output signal 148 may correspond to a signal sent from row driver 106e along gate line 64 e.

At the end of the first half 138 of the frame 140, the output 138 may switch to a positive value, e.g., 5 volts. This value may also be sent to a column driver, such as column driver 104 l. Thus, in the second half 142 of the frame 140, the various gates may be activated sequentially, as represented by the gated output signals 150 and 152. For example, gate output signal 150 may correspond to a signal sent from row driver 106b along gate line 64b, while gate output signal 152 may correspond to a signal sent from row driver 106d along gate line 64 d.

However, a potential problem may be that when the output 136 switches from a negative value to a positive value, the voltage of the output 136 may not settle to a suitable (positive) level. This may cause, for example, insufficient charging of one unit pixel 60 that is driven while the output 136 is switching. Fig. 13 illustrates a timing diagram illustrating a scheme that allows all unit pixels 60 to be driven after the output 136 has settled to its desired level. Similar to fig. 12, output 136 in fig. 13 may correspond to a column driver output, e.g., column driver output 124 l. During a first time period 154 of frame 140, output 136 may be a negative value, e.g., -5 volts. This value may be sent to a column driver, such as column driver 104 l. During the first half period 154 of the frame 140, the various gates may be activated sequentially, as represented by the strobe output signals 144, 146, and 148. For example, gate output signal 144 may correspond to a signal sent from row driver 106a along gate line 64a, gate output signal 146 may correspond to a signal sent from row driver 106c along gate line 64c, and gate output signal 148 may correspond to a signal sent from row driver 106e along gate line 64 e.

At the end of the first time period 154 of the frame 140, but before the last time period 156 of the frame 140, there may be an intermediate time period 158, which intermediate time period 158 may be equal to, for example, the activation time of the gated-out signal (e.g., signal 144). During this intermediate period 158, the gate may not be activated and dummy data (i.e., a data value not displayed on the display 12) or no data may be sent to the LCD 34. Instead, during this intermediate period 158, the output 136 may be allowed to settle at a positive value, such as 5 volts.

After the end of the intermediate period 158, the last period 156 of the frame 140 may begin, during which last period 156 the gates may be sequentially activated, as shown by the gated output signals 150 and 152. For example, gate output signal 150 may correspond to a signal sent from row driver 106b along gate line 64b, while gate output signal 152 may correspond to a signal sent from row driver 106d along gate line 64 d. This process may be repeated for the second frame and any subsequent frames and for each of the column drivers 104a-104 l.

The particular embodiments described above have been shown by way of example, but it should be understood that these embodiments may be susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.

Claims (18)

1. A display, the display comprising:

a liquid crystal display panel including a pixel array formed as a plurality of odd-numbered rows, a plurality of even-numbered rows, a plurality of odd-numbered columns, and a plurality of even-numbered columns;

a column driver coupled to the liquid crystal display panel and configured to drive a plurality of output signals to the plurality of odd columns of the pixel array; and

a timing controller configured to transmit a first column driver control signal to the column driver, wherein the column driver is configured to generate a first output signal of the plurality of output signals based on the column driver control signal such that the first output signal is driven to a first voltage when the first output signal is transmitted to the plurality of odd rows of the plurality of odd columns of the pixel array and then driven to a second voltage having a polarity opposite to the first voltage when the first output signal is transmitted to the plurality of even rows of the plurality of odd columns of the pixel array.

2. The display of claim 1, wherein the timing controller is configured to send a second column driver control signal to the column driver, wherein the column driver is configured to generate a second output signal based on the second column driver control signal such that the second output signal is driven to the second voltage when the second output signal is sent to the plurality of odd rows of the even columns of the pixel array and subsequently driven to the first voltage when the second output signal is sent to the plurality of even rows of the even columns of the pixel array.

3. The display of claim 2, wherein at some time after transmitting the first and second column driver control signals, the timing controller is configured to retransmit the first and second column driver control signals to the column drivers, wherein the column drivers are configured to generate the first output signals and transmit the first output signals to the odd columns of the pixel array and generate the second output signals and transmit the second output signals to the even columns of the pixel array.

4. The display of claim 2, wherein the timing controller is configured to transmit the first column driver control signal and the second column driver control signal simultaneously.

5. The display of claim 2, wherein the timing controller is configured to transmit the second column driver control signal immediately after transmitting the first column driver control signal.

6. A display as claimed in claim 2, comprising a column driver for each of the odd and even columns of the pixel array respectively.

7. The display of claim 2, comprising a frame buffer coupled to the timing controller and configured to store image data for transmission to the liquid crystal display panel to generate an image on the display.

8. The display of claim 7, wherein the timing controller is configured to retrieve first image data from the frame buffer corresponding to pixels in the plurality of odd rows of the plurality of odd columns and subsequently retrieve image data from the frame buffer corresponding to pixels in the plurality of even rows of the plurality of odd columns.

9. The display of claim 8, wherein the timing controller is configured to retrieve second image data from the frame buffer corresponding to pixels in the plurality of odd rows of the plurality of even columns and subsequently retrieve image data from the frame buffer corresponding to pixels in the plurality of even rows of the plurality of even columns.

10. An electronic device, comprising:

a graphics processing unit comprising a processor configured to generate image data and control signals; and

a display coupled to the graphics processing unit and configured to receive the image data and control signals and display the image data, wherein the display comprises:

a liquid crystal display panel including a pixel array formed as a plurality of odd-numbered rows, a plurality of even-numbered rows, a plurality of odd-numbered columns, and a plurality of even-numbered columns; and

a plurality of column drivers, wherein each column driver is coupled to a respective one of the columns of the pixel array, wherein a plurality of column drivers coupled to the plurality of odd columns are configured to transmit a first output signal of a first voltage to the plurality of odd rows of the plurality of odd columns of the pixel array followed by a second output signal of a voltage of opposite polarity to the first voltage to the plurality of even rows of the plurality of odd columns of the pixel array.

11. The electronic device of claim 10, wherein a plurality of column drivers coupled to the plurality of even columns are configured to send the second output signals to the plurality of odd rows of the plurality of even columns of the pixel array followed by sending the first output signals to the plurality of even rows of the plurality of even columns of the pixel array.

12. The electronic device of claim 10, wherein the plurality of column drivers are configured to receive the control signal from the graphics processing unit and generate the first output signal and the second output signal based on the control signal.

13. The electronic device of claim 10, comprising a frame buffer coupled to the graphics processing unit and configured to store the image data prior to transmission to the display.

14. The electronic device of claim 13, wherein the graphics processing unit is configured to retrieve first image data from the frame buffer corresponding to pixels in the plurality of odd rows of the plurality of odd columns and subsequently retrieve image data from the frame buffer corresponding to pixels in the plurality of even rows of the plurality of odd columns.

15. The electronic device of claim 14, wherein the graphics processing unit is configured to retrieve the stored pseudo image data from the frame buffer after retrieving image data from the frame buffer corresponding to pixels in the plurality of odd rows of the plurality of odd columns and before retrieving image data from the frame buffer corresponding to pixels in the plurality of even rows of the plurality of odd columns.

16. A method, the method comprising:

a first output signal of a first voltage is sent from a first column driver to a plurality of odd rows of a first column of a liquid crystal display pixel array, followed by a second output signal of a voltage of opposite polarity to the first voltage from the first column driver to a plurality of even rows of the first column of the liquid crystal display pixel array.

17. The method of claim 16, comprising: sending the second output signal to odd rows of an immediately adjacent column of the first column of the liquid crystal display pixel array and sending the first output signal to even rows of the immediately adjacent column of the first column.

18. The method of claim 16, comprising: the first output signal is then transmitted from the first column driver to the plurality of even rows of the first column of the plurality of odd columns, and the second output signal is then transmitted from the first column driver to the plurality of odd rows of the first column of the plurality of odd columns.