HK1166549A - Storage components and memory structures - Google Patents

Description

Storage element and memory structure

Technical Field

The present invention relates generally to memory elements.

Background

Conventional fuse and anti-fuse elements provide one-time programmable memory elements. In other words, the element starts in a default or initial state and is programmed to a final state only once. Once programmed to the final state, the element may not be reprogrammed to other states.

Typically, to enable multiple programmability, the fuse or anti-fuse element is duplicated based on the desired programmability. Therefore, conventional fuse and anti-fuse elements may be an area inefficient solution when mass storage is required.

Therefore, a multi-time programmable storage element is required.

Disclosure of Invention

According to an aspect of the present invention, there is provided a memory element including:

a first terminal coupled to an N-region (N-gated region) of the memory element;

a second terminal coupled to the P-region of the memory element; wherein the N-region and P-region create a polysilicon diode anti-fuse; and

a silicide layer overlying the N-region and the P-region, wherein in an initial programmed state of the memory element, the silicide layer produces a polysilicon fuse (poly fuse) in parallel (in parallel with) the polysilicon diode antifuse.

Preferably, the storage element is multi-time programmable.

Preferably, the storage element is at least three times programmable.

Preferably, in the initial programming state, the polysilicon fuse in parallel with the polysilicon diode antifuse provides a very low impedance.

Preferably, in the initial programmed state, the storage element acts as a short circuit between the first terminal and the second terminal.

Preferably, the storage element provides a first programmed state, wherein a first impedance of the storage element in the first programmed state is higher than an initial impedance of the storage element in the initial programmed state.

Preferably, the first programmed state is achieved by applying a first current between the first terminal and the second terminal of the storage element.

Preferably, the first current opens (open) the silicide layer.

Preferably, said polysilicon diode antifuse provides said first resistance of said storage element in said first programmed state.

Preferably, the storage element provides a second programmed state, wherein a second impedance of the storage element in the second programmed state is lower than the first impedance of the storage element in the first programmed state.

Preferably, the second programmed state is achieved by applying a first voltage of the storage element across the first terminal and the second terminal.

Preferably, the first voltage causes the polysilicon diode antifuse to a highly reverse biased state.

Preferably, in the second programmed state, the polysilicon diode antifuse acts as a resistive element having a low impedance and provides the second impedance of the storage element.

Preferably, the storage element provides a third programmed state, wherein a third impedance of the storage element in the third programmed state is higher than the second impedance of the storage element in the second programmed state.

Preferably, the third programmed state is achieved by applying a second current between the first and second terminals of the storage element.

Preferably, the second current open forms an N-P junction by the N-region and P-region of the memory element.

Preferably, in the third programmed state, the storage element acts as an open circuit between the first and second terminals.

According to one aspect of the invention, a memory structure comprises:

a plurality of programmable storage elements, each storage element of the plurality of storage elements comprising:

a first terminal coupled to the N-region;

a second terminal coupled to the P-region; and

a silicide layer overlying the N-region and the P-region;

wherein each of the plurality of memory cells is programmable independently of the other memory cells of the plurality of programmable memory cells.

Preferably, the memory structure requires a complete rewrite only when one of the plurality of programmable storage elements has exhausted all of its available programmed states.

Preferably, each of the plurality of programmable storage elements is at least three times programmable.

Preferably, the N-region and the P-region create a polysilicon diode antifuse.

Preferably, in an initial programmed state of the memory element, the silicide layer creates a polysilicon fuse in parallel with the polysilicon diode antifuse.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.

FIGS. 1-4 are schematic diagrams of various one-time programmable memory elements;

FIG. 5 is a schematic diagram of an example of a storage element, according to an embodiment of the invention;

6A-D are schematic diagrams of examples of programmed states of memory cells according to embodiments of the invention;

the present invention will be described with reference to the accompanying drawings. In general, the drawing in which an element first appears is representatively illustrated by the leftmost digit(s) in the corresponding reference number.

Detailed Description

Fuse and antifuse elements may be used as memory elements. Typically, an anti-fuse element is an element that is initially in an open or high impedance state, and can be programmed to a short or low impedance state at one time. A fuse element is an element that is initially in a short or low impedance state and can be programmed to an open or high impedance state at one time. Thus, fuse and antifuse elements are typically one-time programmable memory elements. The initial or default state may correspond to a logic 0 or a logic 1, with the subsequent programmed state corresponding to a logic 1 or a logic 0, respectively.

FIG. 1 is a schematic diagram of an example of an NMOS antifuse element. The NMOS antifuse element is a gate oxide that starts in an open or high impedance state and can be programmed to a short or low impedance state. The programming of the NMOS antifuse element is accomplished by providing a high voltage across its terminals N1 and N2. The high voltage insulation breaks down the oxide, turning it into a resistive short between N1 and N2. Other descriptions of NMOS antifuse elements may be found in commonly owned u.s. patent 7,649,798, which is incorporated herein by reference in its entirety.

FIG. 2 is a schematic diagram of an example of a polysilicon diode antifuse element. The polysilicon diode antifuse element is polysilicon with a non-salicide having a high N-region and a high P-region, which creates a reverse biased junction (or effectively a diode). The polysilicon diode antifuse starts out in an open or high-impedance state and can be programmed to a short or low-impedance state. Programming of the polysilicon diode antifuse is accomplished by providing a high voltage across its terminals N1 and N2 to bring it to a highly reverse biased state that ultimately shorts out the element.

Fig. 3 is a schematic diagram of an example of a 3T (three-transistor) antifuse. Like the NMOS antifuse and the polysilicon diode antifuse, the 3T antifuse starts with an open or high impedance state and can be programmed to a short or low impedance state.

Fig. 4 is a schematic diagram of an example of a polysilicon fuse element. The polysilicon fuse element is a polysilicon resistor with a top layer of salicide (salicide). The polysilicon fuse element starts with a short or low impedance state and can be programmed to an open or high impedance state. Programming of the polysilicon fuse element is accomplished by applying a high current through it which causes melting of the top layer of salicide, thus causing a change in the resistance of the polysilicon fuse element (from low to high resistance). Other descriptions of programmable polysilicon fuse elements can be found in commonly owned U.S. patent 7,561,456, which is incorporated herein by reference in its entirety.

Conventional fuse and antifuse elements, such as those illustrated in fig. 1-4, provide one-time programmable memory elements. In other words, the element starts in a default or initial state and can be programmed to a final state only once. Once programmed to the final state, the element may not be reprogrammed to other states.

Typically, to enable multiple programmability, the fuse or anti-fuse element is duplicated based on the desired programmability. For example, to enable a twice programmable k-bit antifuse memory structure, two k-bit storage locations for the antifuse elements are required, a first location corresponding to an initial state of the memory structure and a second location corresponding to a final state. Thus, conventional fuse and anti-fuse elements may be an area inefficient solution when large capacity memory is required. In addition, to enable multiple programmability, control circuitry, such as including multiplexing and/or logic circuitry, is required to determine which location of the element should be read at any given time to enable reading of the location being programmed. Furthermore, because each additional programmed state of the memory structure (after the first programming) corresponds to a separate cell location, even when the unit data of a k-bit memory structure is being modified (i.e., a single fuse or anti-fuse cell is being programmed), the entire k-bit memory structure must be rewritten into the locations corresponding to the additional programmed states.

Embodiments extend the ability of fuse elements, anti-fuse elements, and combinations thereof to enable multi-time programmable memory elements. At the same time, embodiments significantly reduce area requirements and control circuit complexity. Embodiments may be used, for example, for non-volatile memory and are suitable for use in system-on-a-chip (SoC) products. Exemplary embodiments will be provided below. Based on the teachings herein one skilled in the art will appreciate that the embodiments are not limited to the exemplary embodiments provided herein, but extend to any variations and/or modifications apparent to those skilled in the art.

FIG. 5 is a schematic diagram of an example of a storage element, according to an embodiment of the invention. In particular, FIG. 5 is a schematic diagram of an example of a polysilicon element. The polysilicon elements include N-and P-regions beneath the salicide top layer that create a polysilicon diode.

As described further below, the polysilicon elements are multi-time programmable elements. In an embodiment, the polysilicon elements may be designed as three-time programmable elements. Although the polysilicon element may be slightly larger than a conventional polysilicon fuse or a conventional polysilicon diode antifuse, significant area savings may still be realized by providing multiple programmability (e.g., three times in total). Furthermore, when used in a memory structure (e.g., k-bit memory), the storage elements can be reprogrammed independently of other storage elements, thus eliminating the need to rewrite the entire k-bit memory structure each time a storage element is reprogrammed. Thus, only a rewrite of the k-bit memory structure is required when a given storage element has exhausted its reprogrammability capability.

In an embodiment, the polysilicon elements shown in FIG. 5 provide three-time programmable storage elements, as will be further described with reference to FIGS. 6A-D. Based on the teachings herein one skilled in the art will appreciate that an embodiment may be designed with more than three programmed states.

In its initial or default state (e.g., corresponding to a logic 0), the polysilicon element may be represented schematically as a polysilicon fuse element (salicide) in parallel with a polysilicon diode antifuse element (N-and P-regions), as shown in fig. 6A. The polysilicon element is effectively a short circuit because the polysilicon fuse in parallel with the polysilicon diode antifuse provides very low impedance.

As shown in FIG. 6B, the polysilicon element provides a first programmed state (e.g., reprogramming the element from a logic 0 to a logic 1). To reach the first programmed state, a high current is applied to the polysilicon element between its terminals N1 and N2 to turn off the salicide layer. The salicide layer, which acts as a conductive path between N1 and N2, eliminates and creates a high impedance with the underlying polysilicon diode antifuse. For example, a change from low to high impedance corresponds to a reprogramming of a logic 0 to logic 1 element.

When further reprogramming is required, the polysilicon element provides a second programmed state (e.g., reprogramming the element from a logic 1 to a logic 0) as shown in fig. 6C. The second programmed state is reached by providing a high voltage across terminals N1 and N2, resulting in the polysilicon diode antifuse being highly reverse biased, effectively causing it to act as a resistive element with low impedance.

When further reprogramming is required, the polysilicon elements provide a third and final programmed state (e.g., reprogramming the elements from logic 0 to logic 1) as shown in fig. 6D. By providing a high current through the N-p junction to reach the third programmed state, the junction is effectively disconnected to act as an open circuit or high impedance between N1 and N2.

The embodiments have been described above with the aid of functional means illustrating the implementation of specific functions and relationships thereof. Here, the boundaries of these functional components have been determined for the convenience of description. Alternate boundaries may be determined so long as the specified functions and relationships thereof are appropriately performed.

The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

The breadth and scope of an embodiment of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Cross Reference to Related Applications

This patent application enjoys the benefits of U.S. provisional patent application No.61/364,248, filed on 7/14/2010, which is incorporated herein by reference in its entirety.

Claims (10)

1. A memory element, comprising:

a first terminal coupled to an N-region of the memory element;

a second terminal coupled to the P-region of the memory element; wherein the N-region and P-region create a polysilicon diode antifuse; and

a silicide layer overlying the N-region and the P-region, wherein in an initial programmed state of the memory element, the silicide layer produces a polysilicon fuse in parallel with the polysilicon diode antifuse.

2. The memory element of claim 1, wherein the polysilicon fuse in parallel with the polysilicon diode antifuse provides a very low impedance in the initial programming state.

3. The storage element of claim 2, wherein in the initial programmed state, the storage element acts as a short circuit between the first terminal and the second terminal.

4. The storage element of claim 1, wherein the storage element provides a first programmed state, wherein a first impedance of the storage element in the first programmed state is higher than an initial impedance of the storage element in the initial programmed state.

5. The memory element of claim 4, wherein the first programmed state is achieved by applying a first current between the first terminal and the second terminal of the memory element.

6. The storage element of claim 4, wherein the storage element provides a second programmed state, wherein a second impedance of the storage element in the second programmed state is lower than the first impedance of the storage element in the first programmed state.

7. The storage element of claim 6, wherein the second programmed state is achieved by applying a first voltage of the storage element across the first terminal and the second terminal.

8. The memory element of claim 7, wherein the first voltage causes the polysilicon diode antifuse to a highly reverse biased state.

9. The memory element of claim 8, wherein in the second programmed state the polysilicon diode antifuse acts as a resistive element having a low impedance and provides the second impedance of the memory element.

10. A memory structure, comprising:

a plurality of programmable storage elements, each storage element of said plurality of storage elements comprising:

a first terminal coupled to the N-region;

a second terminal coupled to the P-region; and

a silicide layer overlying the N-region and the P-region;

wherein each of the plurality of memory cells is programmable independently of the other memory cells of the plurality of programmable memory cells.