HK1163992A - System for transmitting and receiving video digital signals for links of the "lvds" type - Google Patents

Abstract

The general field of the invention is that of systems for transmitting and receiving signals of video digital images for links of the "LVDS" type, a system comprising a transmit module, a transmission link and a receive module. The "RGB" video signal comprises the colour and synchronization signals and a clock signal. The "LVDS" video signal transmitted via the transmission link comprises several primary signals, the first primary signal dedicated to the clock signal, the second primary signal comprising the synchronization information, the other primary signals comprising only the colour encoding information. The function of the "LVDS" transmit module is to encode the "RGB" video signal into an "LVDS" video signal and the function of the receive module is to decode the "LVDS" signal into an "RGB" signal. The system comprises the following particular arrangements: the transmission system comprises a means making it possible to inlay a graphic recognition pattern in the "RGB" video signal; the receive means operate in oversampling and comprise test means capable of identifying the synchronization information and the graphic recognition pattern.

Description

System for transmitting and receiving video digital signals for a link of the "LVDS" type

Technical Field

The field of the invention is that of digital links of the "LVDS" type, the abbreviation LVDS meaning "low voltage differential signal". More particularly, the present invention relates to a system for transmitting and receiving transmitted signals and their encoding. The invention can be applied to any field where video information is transmitted using an "LVDS" interface. However, it is designed primarily for aeronautical applications.

Background

These links are typically used for image transmission and have different names. The most common are "FPD-LINK", "Camera-Link", "Channel-Link", "FLATLINK", and the like. As an example, fig. 1 depicts a complete "LVDS" type transmission system. It comprises a transmission interface 1, a transmission line itself 2 and a reception interface 3. Typically, the transmission interface 1 and the reception interface 3 comprise amplifying means 10 and 30 and encoding means 11 and 31. In the case of fig. 1, the system is designed to transmit a 3x 6 bit coded video signal coded of the "RGB" type. The link 2 comprises 4 pairs of twisted wires arranged in parallel. The transmission interface 1 encodes video signals (R, G, B) and synchronization information SYNC, and transmits them through the first three pairs of link lines. The transmission interface 1 also transmits the clock signal CLK through the fourth pair of link lines. At the other end of the link 2, the receiving interface 3 performs the reverse operation, decoding the video signal based on the received signal. If the video information is 3x 8 bit encoded, link 2 requires five twisted wire pairs.

Originally, "LVDS" was originally developed for the link from a graphics component to a flat screen inside a portable microcomputer, and they are well suited for this type of short-range application. This type of link is highly developed and today they are very low cost, many liquid crystal panels have "LVDS" interfaces. In addition, many users attempt to use this technique to make links not only inside devices, but also between devices. In the field of aviation, this technology may be used for certain avionics devices, such as those that perform functions known as "electronic flight bags" or "EFBs" designed to replace on-board manuals or documents. The ARINC 828 standard, which specifies the interface of these "EFB" devices, specifically authorizes the use of the "LVDS" link. This use is valuable because devices based on hardened cards for portable computers have "LVDS" video output from the beginning.

On this type of "LVDS" link, the high frequency clock is reconstructed by the conventional receiving device based on the pixel clock, which is used directly for sampling of the channels containing video data called Rin0, Rin1 and Rin2, as shown in fig. 2, where a phase locked loop 32 or "PLL" controls the "flip-flop" 33. This sampling principle is therefore extremely sensitive to the delay difference (skew) between the lines, which is also referred to as "inter-pair delay difference". When the link length is greater than several meters, depending on the characteristics of the many-pair cable, transmission errors may occur due to delay differences between the individual channels that increase with length. Therefore, the delay difference between the channels must be kept significantly smaller than the "bit" period of the "LVDS" serial transmission, which is equal to one-seventh of the "pixel" period.

As an example, a "XGA" -type video format transmitting images comprising 1024x768 pixels in compliance with the "SPWG" Standard (meaning "Standard Panel Working Group") at a refresh frequency of 60Hz has a "pixel" frequency of 56 MHz. Its serial transmission frequency is 7 times higher and therefore equal to 392 MHz. Thus, a "bit" period or "UI" (Unit Interval) has a duration of about 2.5 ns. Thus, all of the causes for the delay difference (e.g., due to the serializer/deserializer component known as "SERDES", the wire length of the printed circuit, the connector, and the cable) add up to not result in a total error of greater than 1.25 ns. However, the best multi-pair cables, i.e., the multi-pair cables specifically used for this purpose, have a prescribed pair-to-pair delay difference of less than or equal to 50ps/m, which is already the limit for several tens of meters of long cables. For harsh environmental uses, such as avionics, there are no such cables, and for existing avionics, the delay difference between the cable pairs is not controlled.

Furthermore, by using a special wiring harness, standard receiving means of the "LVDS" link can be suitably used for short or very short links in avionics.

To solve the problem of "LVDS" links, the company "Silicon Image" developed a new standard, named "TMDS", adopted by the "DVI" and "HDMI" video standards, meaning "Transition Minimized differential signaling". Video data in "TMDS" format is encoded by an 8-bit to 10-bit encoder that has the following functions:

-generating a so-called "dc-balanced" code, i.e. comprising in practice as many "0" bits as "1" bits. Such encoding can eliminate the transmission of continuous components (continuous components) and can improve the eye diagram;

-limiting the duration of the transition-free (transition), called "run length", which allows to simulate the coupling of a phase-locked loop in order to find the bit phase on each individual channel;

obtain special characters that can find the word phase called "word boundary" and allow the transmission of video synchronization signals such as "data enable", "HSYNC (horizontal synchronization signal)" and "VSYNC (vertical synchronization signal)".

Using this criterion, the tolerance of the delay difference between the channels is in principle no longer really limited. For what has recently been calledOr "PanelBus^TM"is a sufficient pixel clock period. Unfortunately, the "TMDS" link is completely incompatible with the "LVDS" link, and their respective interfaces are not able to communicate with each other. Therefore, the system cannot be improved by replacing the "LVDS" link with the "TMDS" link without compromising compatibility with existing hardware. Another disadvantage of "TMDS" transmission is the increased bandwidth required. For "XGA" type images that conform to the "VESA DMT" standard (meaning "Video Electronics Standards Association Discrete Monitor Timing"), 650Mbaud of transmission speed is required using 10B coding. In the case of "LVDS" transmission, the speed required for the same format to comply with the "SPWG" standard is only 392 Mbaud. Thus, the wiring provided for the "LVDS" transmission cannot support the "TMDS" link.

Disclosure of Invention

The aim of the system according to the invention is to provide, in reception, such as in a "TMDS" receiver, a sufficient tolerance for the inter-delay difference of at least one pixel period for most aeronautical applications, without requiring significant modifications to the "LVDS" transmission standard. The system includes three main functions, allowing:

-recovering (retrieval) bit phase (serial signal);

-recovering the pixel phase (transport word) on the line called "Rin 2" carrying the video synchronization information;

-recovering the pixel phases on the other two channels, in particular by means of decoding a signal called "post-it" embedded on the transmission;

more precisely, the object of the present invention is a system for transmitting and receiving video digital image signals of the "RGB" type for links of the "LVDS" type, comprising at least a transmitting module, a transmission link and a receiving module;

the "RGB" video signal includes three color signals corresponding to color coding of pixels of the transmitted image, three synchronization signals, and one clock signal;

the "LVDS" video signal transmitted over said transmission link comprises at least four primary signals (primary signals), each primary signal being transmitted on its dedicated transmission cable, the first primary signal "CLK" being dedicated as a clock signal, the second primary signal "Rin 2" comprising synchronization information, at least the third primary signal "Rin 0" and the fourth primary signal "Rin 1" comprising only color-coded information;

the LVDS sending module has the function of coding the RGB video signals into LVDS video signals, and the receiving module has the function of decoding the LVDS signals into RGB signals;

the method is characterized in that:

the transmission system comprises means able to embed a graphical recognition pattern in said "RGB" video signal;

the receiving means operate under oversampling, i.e. at a sampling frequency that is an integer multiple of the frequency of said clock signal;

the receiving device includes a testing device capable of identifying synchronization information and the pattern recognition pattern in the second LVDS initial signal.

Advantageously, when the color signal is 6-bit encoded, the transmission link comprises 4 transmission cables, and when the color signal is 8-bit encoded, the transmission link comprises 5 transmission cables.

Advantageously, the graphic pattern is of the "sticky note" type, i.e. corresponds to a portion of an image, always in the same position of said video image, and always superimposed on the initial portion of the video image it replaces. The height of the graphical pattern may be limited to one line of the video image. The pattern is preferably non-periodic.

Advantageously, the sampling frequency is equal to 5 times the frequency of the clock signal.

Drawings

The invention will be better understood and other advantages will appear on reading the following description, given as a non-limiting example and with reference to the accompanying drawings, in which:

fig. 1 depicts the general principle of a system for transmitting and receiving video digital image signals of the "RGB" type for a link of the "LVDS" type;

FIG. 2 depicts a general block diagram of a device for receiving a line or "LVDS" signal according to the prior art;

FIG. 3 depicts the general contents of a line or "LVDS" signal;

FIG. 4 depicts a general block diagram of a receiving module according to the present invention;

fig. 5 depicts a general block diagram of one of the oversampling circuits of the input channel of the receiving module according to the invention, required to recover the "bit" signal;

FIG. 6 depicts a general block diagram of an oversampling circuit of an input channel and a circuit for generating a sampling clock of a receiving module according to the present invention;

FIG. 7 depicts an example of a deformation of the value of the line signal "Rin 2" and the detection of a sequence of features in the signal;

fig. 8 depicts a general block diagram of one of the recognition circuits of the graphical pattern according to the invention, required to recover the "pixel" signal.

Detailed Description

In the following description, definitions and the following terms are used:

video signal, i.e. the object of transmission, comprising:

-a three-color signal corresponding to a color coding of pixels of the transmitted image. These pixels may be 6-bit or 8-bit encoded. In the case of the first 6-bit encoding, the bits corresponding to the "red" pixels are labeled with R0 through R5, the bits corresponding to the "green" pixels are labeled with G0 through G5, the bits corresponding to the "blue" pixels are labeled with B0 through B5,

three synchronization signals, labelled with DE (for "Data Enable", Data Enable), VS (for "Vertical sync", Vertical sync) and HS (for "Horizontal sync", Horizontal sync), each of which is one-bit encoded;

-a clock signal;

when the video signal is 6-bit encoded, the link transmitting the "LVDS" video signal comprises four initial signals, and when the signal is 8-bit encoded, the link comprises 5 initial signals, each initial signal being transmitted over its dedicated transmission cable, each signal comprising a series of 7-bit words arranged serially. Fig. 3 shows such a link in the case of a 6-bit coded video signal according to the "SPWG" standard. The "LVDS" signals are organized in the following way:

-a first initial signal "CLK" dedicated as clock signal;

-a second initial signal "Rin 2" comprising synchronization information DE, VS and HD;

-a third initial signal "Rin 0" and a fourth initial signal "Rin 1" comprising only color-coded information.

In the case of fig. 3, the bits corresponding to the encoding of the color signal are labeled Ri, Gi, and Bi, i varying from 0 to 5. The fifth original signal supports additional least significant color information if the video signal is 8-bit encoded.

Fig. 4 depicts a general block diagram of a receiving module according to the invention in case the video signal is 6-bit encoded. Thus, the "LVDS" link includes 4 initial signals, labeled Rin0, Rin1, Rin2, and CLK. The 3 signals Rin0, Rin1, and Rin2 pass through three substantially identical electronic chains (electronic chains). Each chain essentially comprises an amplification stage (block 300, block 310 and block 320), a deserialization stage (block 301, block 311 and block 321), a basic "bit" phase recovery stage (block 302, block 312 and block 322), and a basic pixel phase recovery stage (block 303, block 313 and block 323). The combination of the three chains is input to a final electronic module 340 for storing the decoded signal and re-formatting the decoded signal, which provides at its output the R, G, B signal, the synchronization signal and the clock signal of the original video signal.

For the sake of clarity, all that is referred to below is a 6-bit encoded signal transmitted over a "LVDS" link comprising 4 transmission lines, but it can be easily converted into an 8-bit encoded signal transmitted over a "LVDS" link comprising 5 transmission lines.

As described above, the various signals of the "LVDS" link may be offset with respect to each other. It is therefore necessary to recover the phase of the fundamental bit on each individual channel, which comprises a different so-called "bit" phase signal.

Since the video data is not encoded, the circuit cannot be recovered using a conventional clock based analog phase locked loop. The duration of no transition (also called "run length") is not limited, the worst case corresponding to a "black" image. In this extreme case, the channels Rin0 and Rin1 are inactive. Thus, images can be thought of as having a "run length" on channels Rin0 and Rin1 that is approximately equal to the image period, e.g., 16.7ms in the case of an image refresh frequency of 60 images per second.

To solve this problem, the receiving device operates at a frequency significantly higher than the clock frequency of the video signal under oversampling of the input channel. This principle applies either to low-speed transmission or to special applications such as the reception of "SDI" signals (meaning "Serial Digital Interface" signals) with programmable logic circuits of the "FPGA" type.

A sampling frequency equal to 5 times the clock frequency may be used. The choice of ratio 5 is sensible, as it gives the ideal central sampling position and two adjacent positions where the tolerance of the high frequency "jitter" is acceptable. But other options are possible.

As an example, fig. 5 shows a functional block diagram of a receiving channel Rin2 comprising synchronization signals DE, VS and HS. The apparatus essentially comprises two modules 321 and 322. The first block 321 performs the function of a deserializer of the Rin2 signal as a serial signal, and the second block 322 recognizes the bit phase. More specifically, the electronic assemblies of Rin2 receiving channels include:

a shift register 3210 that can oversample a stream of 7-bit words from the Rin2 channel at a frequency 5 times higher than the clock frequency and transmit a stream comprising 20 samples;

the same first and second storage registers 3212 and 3221;

an indexing and comparing means 3222 comprising an electronic pointer (electronic pointer) P, the pointer P generally indexing the central sample of these 5 samples. The indexing and comparing means 3222 also includes means for detecting state transitions of these samples. To perform this function, an array of logic gates may be used that perform an exclusive or function, also known as XOR. It is known that the output of an XOR gate is at logic level 1 only if one of the two inputs is at logic level 1. In this way, it is easy to determine the state transition that produces a logic level "1" at the output of the XOR gate;

-an 11-bit third memory register 3223;

-a fourth memory register 3224 of 7 bits;

a conventional parallel signal processing function 323 comprising conventional means for detecting the respective serial signals forming the initial Rin2 signal. At the output of the circuit, the individual components of the Rin2 signal, including the three synchronization components DE, VSn, and HSn, are recovered on 7 parallel lanes. On average, 7 components are extracted at the pixel frequency.

In a typical "SDI" receive type application of this deserialization method, 3, 4, or 5 bits are sampled depending on the frequency shift between the source frequency and the sampling clock. Furthermore, the 11-bit register must be managed in a slightly special way. Depending on the direction of arrival of the data, the location change segment of the pointer may require 5 samples of data to avoid losing any of them, or may allow only 3 samples to avoid repeating any of them.

The detection of the phase of the transition is performed simply by identifying the output of a logic gate performing an exclusive or logic function on 2 adjacent bits, state 1 representing the transition. Sampling of the data is performed by a fixed location of 4 multiplexer components called 1-out-of-5 "MUXs" plus a fifth sample. Depending on the information of the pointer, 3, 4 or 5 samples are transferred. When a sample arrives and has 11 bits, the next register is gradually filled, and 4 samples can be retained when the current 7 samples are taken.

The ability of such devices to operate correctly for the duration of the "run length" (i.e., the maximum duration of the same "0" or "1" state) when in normal use depends on the frequency difference between the source and the sample. Very frequent catch-up (catching-up) of the sampling phase is required due to the frequency shift, but this catch-up can only be caused by the presence of transitions. Thus, if the frequency shift is small, the maximum permitted "run length" will be larger. In our application, the "average sync" sampling of the source is used, so the "run length" is infinite and the device is able to deserialize the uncoded signal.

As shown in fig. 6, a phase locked loop 331 or "PLL" is used to generate the sampling clock, which can provide a delay difference in the clock. It is known that in the worst case, the "run length" can be extremely long, and the device then becomes sensitive to jitter, both to high frequency jitter and to low frequency jitter known as "drift". It has been demonstrated that neither of these situations exists if the phase locked loop is properly programmed.

The other channels Rin0 and Rin1 have the same structure in the electronic part involved in recovering the bit phase.

The electronic implementation of the deserialization stage and the basic "bit" phase recovery stage does not pose a particular problem. As an example, the pixels use a maximum transmission frequency equal to 85MHz, each pixel comprises 7 bits, each bit being sampled by 5 samples, the logic circuit performing the oversampling must operate at a frequency of 2975MHz or 2.975 Gbaud. The serial input produced by ALTERA corporation is capable of using FPGA circuits, up to 3Gbaud, under the brand name "aria GX" or "STRATIX," and is well suited to performing this function.

As mentioned above, it is also necessary to recover the "pixel" phases on the three receive channels. The word output by the 7-bit register of the phase recognition module may include data belonging to two adjacent pixels. On each lane, means for recovering the edge of the parallel word (frontier), also known as a "word aligner using barrel shifters", which means "barrel" registers, are utilized. The "bucket" register consists of a parallel register and 7 1-out-of-7 multiplexers. In order to find the correct multiplex to perform, it is necessary to be able to recognize the special message in the transmitted signal.

As shown in fig. 3, the Rin2 channel has synchronization information, i.e., DE, VS and HS information. As can be seen from fig. 7, which depicts a sequence of 7-bit words on the Rin2 channel, outside the active video area, DE equals 0 and video RGB bits, i.e., B5, B4, B3, and B2. The 10-bit sequence labeled "0110000111" and corresponding to a change in the DE value at its first position "0", at the eighth position "1" therefore characterizes such a transition at the beginning of each active line and not detectable at other times. For 7 possible phases in the receive mode, it is therefore sufficient to run a test of the sequence, also referred to as a "word boundary pattern". When this occurs, the phase is identified, and then the multiplexer of the "barrel shifter" is set to the output word starting with DE.

As can be understood from fig. 3, unfortunately, there is no possibility of finding similar phase information for the Rin0 channel and the Rin1 channel and the additional channels in the case of a 24-bit encoded RGB signal. Furthermore, the apparatus according to the invention needs to be associated with resources used in the receiving module in connection with resources comprised in the transmitter. Such associated resources may be of the hardware type or of the software type.

Hardware solutions are obvious. When the DE value is "0", it is sufficient to modulate the bits of the Rin1 channel and the Rin0 channel in a specific manner during the image transition phase or "blanking". Unfortunately, this solution is difficult to implement, since the transmitter device is in fact in all cases a Component called "COTS" (meaning a finished Component), for example a hardened Component for a "PC" type microcomputer that is difficult to modify in terms of hardware. The "LVDS" output is most commonly the output of a graphics chip that does not allow the necessary modifications.

The associated resources must therefore be able to be generated by software, it being possible to modify the content of the video signal only in the simplest and least disruptive possible way.

A first embodiment is to perform a small marking operation on the image, i.e. a so-called "watermarking" operation hidden at a corner of the image, for example in the upper left corner. The imprint is low density, using the least significant bit or "LSB" of the image pixel. For example, color bits G0 and B0 may be used. The print is visually imperceptible due to its location and its low visual impact. In the case of devices based on cards for PC-type microcomputers, however, it has not previously been easy to perform this type of function with application software programs.

The second embodiment introduces a "sticky note" type identification pattern. In this case, the graphic pattern must be superimposed on the image at any application executed by the transmitting device. This means that it is necessary to generate "small" images that always replace the original video image. The method by which such a pattern can be generated is similar to a small software program called a "sticky note" that makes the "always on top" parameter valid. The main difference in our application compared to the "sticky note" software program is that the position of the image segment must be absolutely fixed and not movable. The height of the pattern may be only one line, preferably to the left of the first line of the screen.

The synchronization of the Rin1 channel and Rin0 channel is based on the recognition of the graphics pattern. Naturally, the detection is verified in the time window against the synchronization information that has been extracted from the Rin2 channel. This avoids the risk of unwanted detection associated with particular image content in which the graphical pattern is accidentally found.

The identification pattern must satisfy the following two conditions:

the pattern cannot be reproduced simply by moving pixels, i.e. it cannot comprise periodicity, in other words it must have a strong autocorrelation;

the pattern must comprise enough pixels to make it very unlikely to be confused with other image parts. In order to make the check more reliable, the presence of the pattern is verified in a time window having a certain duration. If the accepted delay difference is a few pixels, the window must have a sufficiently longer duration than the pattern, in which case it is preferred to work with a very long pattern.

The pattern comprises a certain number of 7-bit words. If the pattern includes a large number of words, it is possible to detect the pattern by recognizing a single bit of each word. In this case, only the special sequence associated with the designated bit may be detected. This simplifies the number of registers required and the size of the combinatorial logic, if the pattern is very long, due to the excessive number of bits in this case.

FIG. 8 presents an exemplary embodiment of stages to recover phases of exemplary pixels based on recognition of a recognition pattern. This stage corresponds to the stage at the appropriate location of the Rin0 lane. Naturally, the amplification stages on the Rin1 channels are the same. One of the functions of this stage is to find the sought sequence or "pattern" corresponding to the designated bit on each bit by a set of recognition modules 3030, each of which includes a shift register 3031 and a pattern detection module 3032. As described above, the detection is performed only during the time window controlled by the module 3033. In this embodiment, for very long patterns, since the phase margin may be larger than one pixel, several 7-bit registers need to be added in the "barrel shifter" functional block to shift the word phase forward or backward with respect to the DE signal from the Rin2 channel. This change in phase is controlled by the time interval between the DE signal and the pattern detection.

For shorter patterns, more common structures may be used, such as a structure for byte alignment of serial signals (also referred to as "byte boundary alignment").

The visual effect of recognizing a pattern is very limited because it is limited to the first line of the image. If the user is aware of its presence, it may not be appropriate to try to convert the pattern into noise by, for example, pseudo-random code conversion, also known as "scrambling". On the other hand, it may be desirable that the pattern be clearly recognizable without ambiguity and thus have a specific length. It is even possible to use a pattern extending over several rows.

It is highly desirable that the receiver will operate even with a source that does not add the appropriate pattern. This may for example allow the use of receivers on standard devices with short cables. Further, when a message is not regularly found on any bits of the Rin0 lane and the Rin1 lane, after acknowledgement, it can be concluded that the source is not sending the message. In this case, the receiving interface is automatically configured in a mode similar to that of a normal "LVDS" receiver, and can tolerate a normal "delay difference" of less than a bit period. In this "no pattern" mode, the Rin0 and Rin1 channels are phase controlled directly on the Rin2 channel, based on the assumption that the delay difference is less than the bit period. For this purpose, it suffices to arrange the "barrel shifter" modules of the RIn0 channel and the RIn1 channel with reference to the RIn2 channel. In this mode, the deserialization units labeled as "SERDES" and "BitSampler" blocks must be rigorously initialized in the same manner. It should be noted that the phase of the clock channels Clk is not important at all, and only the delay difference between Rin channels is critical. Thus, in the "no superimposed pattern" mode, a phase error that may be generated by a structural difference between the clock transmission and the channel transmission is avoided, relative to a normal "LVDS" circuit. The Rin channel operates in the same manner in transmission as in reception, thus minimizing the delay differences associated with the integrated circuit.

The advantages of the transmission system according to the invention are as follows:

by a receiver equipped with the device constituting the invention, the "LVDS" transmission by pairs of lines is insensitive to "inter-delay differences";

the tolerance to "delay differences" enables the addition of equalization circuits to compensate for the high frequency loss of the cable, which allows transmission over greater lengths;

the receiver is still compatible with sources without added patterns, with standard performance.

The disadvantage of this device is modest. The method mainly comprises the following steps:

using a circuit capable of operating at a frequency of the order of 5 times the transmission speed in order to oversample the signal. It has been shown that the use of such an assembly does not pose particular problems;

-adding an overlay pattern on the source image, which pattern has a slight influence from both of its realization and its visual appearance.

Claims (6)

1. A system for transmitting and receiving video digital image signals of the "RGB" type, for links of the "LVDS" type, comprising at least a transmitting module (1), a transmission link (2) and a receiving module (3);

the "RGB" video signal comprises three color signals (R, G, B), three synchronization Signals (SYNC) and one clock signal (CLK) corresponding to the color coding of the pixels of the transmitted image;

the "LVDS" video signals transmitted over the transmission link comprise at least four initial signals (Rin0, Rin1, Rin2, CLK), each initial signal being transmitted over its dedicated transmission cable, a first "LVDS" initial signal being dedicated for use as a clock signal, a second "LVDS" initial signal comprising synchronization information, at least a third "LVDS" initial signal and a fourth "LVDS" initial signal comprising only color-coded information;

the LVDS sending module has the function of coding the RGB video signals into LVDS video signals, and the receiving module has the function of decoding the line signals into RGB signals;

the method is characterized in that:

the transmission system comprises means able to embed a graphical recognition pattern in said "RGB" video signal;

the receiving means operate under oversampling, i.e. at a sampling frequency that is an integer multiple of the frequency of said clock signal;

the receiving device comprises a testing device (301, 302, 311, 312, 321, 322) capable of identifying synchronization information in the second "LVDS" initial signal and the pattern-recognition pattern.

2. System for transmitting and receiving video digital image signals of the "RGB" type for links of the "LVDS" type according to claim 1, characterized in that said transmission link comprises 4 transmission cables when said color signals are 6-bit encoded and 5 transmission cables when said color signals are 8-bit encoded.

3. System for transmission and reception of video digital image signals of the "RGB" type for links of the "LVDS" type according to claim 1, characterized in that the graphic pattern is of the "sticky note" type, i.e. corresponding to a portion of an image, always in the same position of said video image and always superimposed on the initial portion of the video image it replaces.

4. System for transmission and reception of video digital image signals of the "RGB" type for links of the "LVDS" type according to claim 3, characterized in that said graphic pattern has a height limited to one line.

5. System for transmission and reception of video digital image signals of the "RGB" type for links of the "LVDS" type according to claim 3, characterized in that said graphic pattern is non-periodic.

6. System for transmitting and receiving video digital image signals of the "RGB" type for links of the "LVDS" type according to claim 1, characterized in that said sampling frequency is equal to 5 times the frequency of said clock signal.