HK1161933B - Bulk capacitor and method - Google Patents

Description

Bulk capacitor and method

Technical Field

The present invention relates to capacitors. More particularly, the present invention relates to a capacitor capable of achieving a high capacitance density.

Background

The technology for producing capacitors, including electrolytic capacitors and ceramic capacitors, is being pushed to its practical physical limits. Traditionally, high capacitance density is achieved by high surface area, for example in tantalum electrolytic capacitors or carbon double layer capacitors. Alternatively, as used in multilayer ceramic capacitors, high capacitance density can be achieved by thin high dielectric constant (K) dielectric materials. Despite these advances, problems remain. In particular, the demand for high capacitance density is increasing beyond the limits associated with such approaches. High capacitance density is a highly desirable feature for making smaller electronic devices.

There is a need for a capacitor that can achieve a high capacitance density. It is therefore an object, feature, or advantage of embodiments disclosed herein to provide a capacitor and a method of manufacturing a capacitor that can achieve a high capacitance density.

One or more of these aspects will become apparent from the following description and claims.

Disclosure of Invention

According to one aspect of embodiments disclosed herein, a bulk capacitor (bulk capacitor) includes: a metal foil, a semi-conductive porous ceramic body on the metal foil, a dielectric layer on the porous ceramic body (e.g., formed by oxidation), a conductive medium filling the porous body, and a conductive metal layer encapsulating the porous body. According to another aspect of the present invention, there is provided a method of manufacturing a bulk capacitor, comprising: the method includes forming a semi-conductive porous ceramic body on a metal foil, oxidizing the semi-conductive porous ceramic body to form a dielectric layer, filling the porous body with a conductive medium, and encapsulating the porous body with a conductive metal layer.

Drawings

FIG. 1 illustrates one embodiment of a capacitor according to the present invention;

FIG. 2 is a cross-sectional view illustrating a first electrode, a first ceramic layer, and a portion of a porous ceramic body in accordance with an aspect of the present invention;

FIG. 3 shows another embodiment of a capacitor according to the present invention;

FIG. 4 illustrates a mounting substrate according to the present invention;

FIG. 5 shows another embodiment of a capacitor according to the present invention; and

FIG. 6 illustrates a method in accordance with an aspect of the subject invention.

Detailed Description

The present invention provides a capacitor having a high capacitance density. The present invention achieves high capacitance density by creatively combining the high dielectric constant of ceramics with the large surface area of the porous matrix. In particular, capacitors can take advantage of the high dielectric constant of ceramic materials in combination with porous ceramic bodies having large surface areas.

A porous ceramic body is formed on the metal foil. Typically, the metal foil acts as the first electrode. An intermediate ceramic layer may also be provided between the porous ceramic body and the metal foil. The porous ceramic body is then oxidized. The oxidation may be formed by various techniques such as thermal oxidation or electrochemical oxidation. The oxidation forms a thin high-K dielectric layer on the free surface of the porous ceramic body. The porous ceramic body is then filled with a conductive medium, such as a conductive polymer. Typically, the conductive medium forms the second electrode. Subsequent structures can then be added to encapsulate the capacitor structure and form appropriate mounting structures and/or electrical terminals. For example, after filling the porous ceramic body with a conductive medium, the porous ceramic body may be encapsulated with a conductive metal layer, such as silver.

The resulting combination of the large surface area provided by the porous structure and the thin layer of high-K dielectric provided by the dielectric enables the fabrication of small-sized, high capacitance density capacitors.

Fig. 1 shows a simplified embodiment of a capacitor 10. The capacitor 10 includes a first electrode 12, and the first electrode 12 may be formed of various materials including a metal foil. Various metal foils may be used. The metal foil may be selected from the group of elements comprising Ta, Ni, W, Nb, V, Mo, Fe or alloys thereof. Kovar and invar are also preferred because their Coefficient of Thermal Expansion (CTE) matches that of the dielectric and/or ceramic layers. Suitable foils are available from a variety of sources, including but not limited to: wyoissing Campent technologies, Pa., Calif., Boyertown, Pa., and Thailand, Inc. from Newton, MA. As noted above, the CTE of the first electrode 12 is selected to match the dielectric and/or ceramic elements, thereby minimizing thermal stress. In typical embodiments, a CTE of 3-15ppm is used. Various foil thicknesses may be used, for example in the range of 20-250 microns. A more typical range may be the range of 100-.

A semiconductive porous ceramic body 18 is formed on the first electrode 12. It is understood that various geometric configurations (substantially depending on the shape of the first electrode 12) may be used without departing from the scope of the present invention. It should also be understood that the porous ceramic body may be formed and/or deposited using a variety of processes utilizing a variety of ceramic layers and/or compositions. In one embodiment, a thin conductive semi-conductive ceramic layer may be deposited on the first electrode 12 prior to depositing the conductive porous ceramic body 18. Various semiconductive ceramic materials may be used, including Barium Strontium Titanate (BST). Other suitable chemistries may also be used, including, for example, Nb₂O₅、TiO₂、BaCO₃And SrTiO₃The material of (1). Other suitable materials may include lead magnesium niobate (i.e., Pb)₃MgNb₂O₉) Lead titanate and perovskite oxides.

Fig. 2 shows a simplified cross-sectional view of an embodiment with a first electrode 12, a semiconducting first ceramic layer 17 and a semiconducting porous ceramic body 18. It is to be understood that the thicknesses are not shown to scale. The first ceramic layer 17 is relatively thin and is deposited on the first electrode 12 with a thickness of 1-10 microns. The first ceramic layer 17 is typically sintered to full density under a reducing atmosphere. The reducing atmosphere may be selected from various gases. For example, from Ar and H₂The gas is a reducing atmosphere, and the hydrogen concentration is usually between 1 and 10 percent. Other gases may be used, e.g. N₂/H₂. The reduction temperature is typically between 900-1400 degrees C. Typical durations at peak temperature are usually 5-60 minutes. It should be understood that a variety of temperature profiles may be utilized. The first ceramic layer 17 preferably has an electrical conductivity of greater than (or better than) 5 ohm-cm after the reduction sintering process.

A porous ceramic body 18 is deposited as a second ceramic layer onto the first ceramic layer 17. It is also understood that the porous ceramic body 18 may be deposited directly on the first electrode 12. Both the first ceramic layer 17 and the porous ceramic body 18 may be deposited using conventional ceramic deposition techniques, such as screen printing, doctor blading, laminating, spraying, or dip coating. In the present example, the first ceramic layer 17 and the porous ceramic body 18 are deposited using electrophoretic deposition (EPD).

Since the first ceramic layer 17 is semiconductive after reductive sintering, the second layer may be deposited (e.g., to form the porous ceramic body 18) using EPD techniques. Typically, EPDs utilize charged particles that deposit on a counter electrode under the influence of an electric field. EPD can deposit a wide range of particulate materials, almost independent of their chemical composition. EPDs can form separate bodies and layers. The layers may be formed to a thickness in the micrometer range to several mm. The solids content of the powder in suspension, the electric field strength and the time are the main parameters for controlling the weight of deposition during EPD.

The porous ceramic body 18 is from 0.5 to 5m²Large surface area powder per gram, for example BET (specific surface area analysis). The porous ceramic body 18 is typically sintered under a reducing atmosphere, such as the reducing atmosphere disclosed above in connection with the first ceramic layer. Various reduction temperatures may be used. The reduction temperature is typically selected to maintain an open pore structure and avoid densification. The thickness of the porous ceramic body 18 after reduction is typically in the range of 10-250 microns.

The resulting ceramic body has an open cell structure with a porosity of up to 75% by volume. The porous structure may include various pore sizes from 0.1-6 microns. Preferably, the pore size is in the range of 0.3-3 microns. The porous ceramic body 18 may have various geometries, typically depending on the shape of the first electrode 12. For example, the first electrode 12 may be rectangular with a thickness of about 100 microns. The porous ceramic body 18 may be deposited on the first electrode 12 from multiple angles (e.g., from both sides). The first electrode may have other geometrical profiles, such as comb-like and/or simple or complex shapes comprising one or more polygons.

Returning to FIG. 1, a dielectric layer 22 is formed on the porous ceramic body 18 (and the first ceramic layer 17, if present). It is noted that reference numerals 22 and 18 shown in the drawings refer to the same structure. This is because it is difficult to illustrate each thin layer in the drawing. It should be understood that the dielectric layer 17 generally covers the free surface area of the porous ceramic body 18. After deposition of the dielectric layer, the resulting porous ceramic body shape remains substantially unchanged (except for a very small increase in thickness). Dielectric layer 22 may be formed by various processes including thermal oxidation or electrochemical oxidation. In embodiments using thermal oxidation, the porous ceramic body 18 is heated to a temperature between 500 ℃ and 1400 ℃ in an oxygen-containing atmosphere for 5 to 120 minutes. This results in the formation of a thin dielectric layer on the semiconductive porous ceramic body 18 (and the first ceramic layer 17, if present). Pumping and purging cycles may be used during processing and/or at peak temperatures to ensure that oxygen is present in the voids of the porous ceramic body 18.

In embodiments using electrochemical oxidation, the porous ceramic body 18 (and the first ceramic layer 17, if any) is interposed in one or more strongly basic solutions (pH greater than 10). This results in the formation of a dielectric layer. For example, the solution may be based on ammonium, St, BaOH₂(barium, strontium hydroxide), optionally with Br, St₈(OH)₂And (4) combining. The porous ceramic body 18 is immersed in a solution that is typically heated to a temperature between 40-130 c. An anodizing electric field is typically applied such that dissolution-reduction occurs on the free surface of the porous ceramic body 18. A voltage of between 2-20V is typically applied for a duration of 1-12 hours. Once the dielectric layer is formed, post processing may be utilized to stabilize the dielectric layer 22 (e.g., heating to 250-1200 ℃ C. in an oxygen atmosphere).

The properties of the dielectric layer can also be altered by dissolving elements such as Mn, Nb, Mg, Si, Zr, Ti, Bi, Cu, Ag in the solution. These elements participate in the electrochemically forming oxidized layer. Post-treatments up to 1200 ℃ may also be applied. For example, a highly stable manganese layer dielectric layer (Mn) may be formed by oxidation and post heat treatment_xO_yX > 2, y > 3). Typically will be dielectricThe layer 22, whether formed by thermal or electrochemical oxidation or other process, is formed to a thickness in the range of 0.1-1 micron and has a thickness typically in the range of 10⁶-10¹¹High Insulation Resistance (IR) in the ohmic range. Once oxidized, the porous ceramic body 18 (and the first ceramic layer 17, if present) is generally characterized by a high dielectric constant (K) in the range of 500-.

The porous ceramic body 18 is filled with a conductive medium 16. Various compositions can be used as the conductive medium, including conductive polymers: PEDT (poly (3, 4-ethylenedioxythiophene)), poly (acetylene), poly (pyrrole), poly (thiophene), polyaniline, polythiophene, poly (p-phenylene sulfide) and poly (para-phenylene vinylene) (PPV) and soluble derivatives thereof, poly (3-alkylthiophene), polyindole, polypyrene, polycarbazole, polyazulene, polyaza, poly (fluorene) and polynaphthalene.

In one embodiment, a commercially available composition of PEDT (Clevios (PEDT)) is utilized, available from Clevios (R) (PEDT) of Thailand, Inc. of Newton, MA. Generally, the conductive medium should have a conductivity greater than 100 Siemens/cm, preferably equal to or greater than 1000 s/cm. The conductive medium may be coated by various processes including dip-coating impregnation. Typically, the porous ceramic body 18 is impregnated with a dilute mixture containing finely dispersed particles (e.g., nano-sized) of a conductive medium.

Typically, the conductive medium 16 forms the second electrode. Subsequent structures can then be added to encapsulate the capacitor structure and form appropriate mounting structures and/or electrical terminals. In this example, the conductive metal layer 20 encapsulates the porous ceramic body 18 (now coated with the dielectric layer 22 and the conductive medium 16) and serves as an electrical terminal for the second electrode. A variety of metals may be used. In one embodiment, a highly conductive silver paste is used. The metal layer may be applied by various techniques including brushing or dipping. Suitable metals are commercially available from a variety of sources, including Lord Corporation of NC Cary, Emerson and Cu, and Du-Pont, of Irvine, CA.

Fig. 3 shows another embodiment according to the invention. The various layers shown in fig. 3 may be formed using the materials and processes described above in connection with fig. 1. In this embodiment, the capacitor 100 has a first electrode 212, which in this example comprises a metal foil. A first ceramic layer 217 is deposited on the metal foil 212. A porous ceramic body 218 is formed on the first ceramic layer 217. It is understood that the porous ceramic body 218 may be formed directly on the first electrode 212. A dielectric layer 222 is formed on the porous ceramic body 218. The conductive medium 216 encapsulates a porous ceramic body 218. The conductive medium 216 essentially forms the second electrode. Suitable conductive media may include the conductive polymers discussed above in connection with fig. 1.

It is noted that reference numerals 222, 218, and 216 shown in the drawings refer to the same structure. This is because it is difficult to illustrate each thin layer in the drawing. It is apparent that the dielectric layer 222 generally covers the free surface area of the porous ceramic body 218. After deposition of the dielectric layer, the resulting porous ceramic body shape remains substantially unchanged (except for a very small increase in thickness). The conductive medium 216 then encapsulates the porous ceramic body, resulting in the generally rectangular shape shown in FIG. 3.

The remaining structure is primarily concerned with forming the electrical terminals and encapsulating the resulting structure. In this example, at least a portion of the conductive polymer layer is covered in a highly conductive silver paste layer 260. A first electrical lead 270 is electrically coupled to the first electrode 212 and a second electrical lead 280 is coupled to the silver paste layer 260. The structure is also encapsulated by layer 290, which layer 290 may comprise various materials such as epoxy, resin, parylene, or various known molding techniques. As discussed in more detail below, the entire capacitor assembly can be attached to the mounting substrate 295.

Fig. 4 shows a detailed view of a mounting substrate 295, such as a typical Printed Circuit (PC) board. The mounting substrate includes a base portion 300 that can be fabricated using conventional PC board technology. First and second metallization layers 302, 304 are formed on the substrate 300. The first and second metallization layers 302, 304 are generally spaced apart so as to align with the first and second electrical leads 270, 280 shown in fig. 3. It will be apparent that the first and second metallization layers may be coupled to one or more circuit traces (not shown). The first and electrical leads 270, 280 are electrically coupled to the first and second metallization layers 302, 304 using a conductive glue 306. A non-conductive glue 308 may be used in the region disposed between the first and second metallization layers 302, 304. Once the capacitor 100 is mounted to the substrate, a soldering operation may then be performed using conventional methods. It is clear that various mounting techniques may be used without departing from the scope of the invention.

Fig. 5 shows another embodiment according to the invention. In this embodiment, the first electrode 512 is disposed along the edge of the structure, as opposed to centrally disposed first electrode 212 as disclosed in fig. 4. The various layers shown in fig. 5 may be formed using the materials and processes described above in connection with fig. 1. In this embodiment, the capacitor 400 has a first electrode 512. A first ceramic layer 517 is deposited on the metal foil 512. A porous ceramic body 518 is formed on the first ceramic layer 517. It is understood that the porous ceramic body 518 may be formed directly on the first electrode 512.

A dielectric layer 522 is formed on the free surface of the porous ceramic body 518. A conductive medium 516, such as a conductive polymer, is infused into the pores of the porous body 518.

It should be noted that reference numerals 522, 518, and 516 shown in the drawings refer to the same structure. This is because it is difficult to illustrate each thin layer in the drawing. It should be appreciated that the dielectric layer 522 generally covers the free surface area of the porous ceramic body 518. After deposition of the dielectric layer, the resulting porous ceramic body shape remains substantially unchanged (except for a very small increase in thickness). The conductive medium 522 then encapsulates the porous ceramic body, resulting in the generally rectangular shape shown in FIG. 5.

A typical thickness of layer 516 is 1-10 microns. Fully impregnating all of the open cells in the porous ceramic body 518 is preferred because it provides the greatest capacitance. The conductive polymer preferably adheres well to the dielectric layer 522 to ensure good electrical performance. An insulating layer 513 is disposed between the first electrode and the remaining layers, which is coupled to the second electrode to provide electrical insulation between the two electrodes. A wide range of insulating materials can be used for this purpose.

The remaining structure relates primarily to the formation of the electrical terminals for the second electrode and the packaging of the resulting structure. A conductive metal paste layer 560 (e.g., silver paste) is applied over a portion of the conductive medium 516. The first electrical lead 570 is electrically coupled to the first electrode 512 and the second electrical lead 580 is coupled to the conductive metal paste layer 560. The structure is also encapsulated by a layer 590. the layer 590 may comprise various materials such as epoxy, resin, parylene coated by various known techniques. It is understood that various electrical terminals and packaging techniques may be used without departing from the scope of the present invention. It is also understood that additional layers may be added to the structure without departing from the scope of the invention.

Figure 6 illustrates one embodiment of a method of manufacturing the bulk capacitor of the present invention. The various process steps set forth in fig. 6 are performed as generally discussed above. In step 600, a suitable ceramic material is prepared. The ceramic particles are then placed in an appropriate suspension for deposition (e.g., by EPD), as shown at block 602. As shown in block 604, a first electrode (e.g., kovar foil) is formed into a desired geometry using conventional methods.

A first (thin) ceramic layer is then deposited over the first electrode, as shown in block 606. Then, as shown in block 608, in a reducing atmosphere (e.g., Ar/H)₂) The first ceramic layer is then sintered to full density. The reduction temperature is typically between 900-1400 degrees C. Typical durations at peak temperature are usually 5-60 minutes. A porous ceramic body is next deposited on the first ceramic layer, as shown in block 610. As shown in block 612 and as generally discussed above, the porous ceramic body is then sintered in a reducing atmosphere. Various reduction temperatures may be used. The reduction temperature is typically selected to maintain an open pore structure and avoid densification.

The porous ceramic body is then oxidized to form a thin dielectric layer, as shown in block 614. For example, the porous ceramic body may be heated to a temperature of 900 ℃ for about 5 to 120 minutes in an oxygen-containing atmosphere. This results in the formation of a dielectric layer. Pumping and purging cycles may be used during the process to ensure that oxygen is present in the voids of the porous ceramic body.

The porous ceramic body (now covered in a thin dielectric layer) is then infused with a conductive medium (e.g., a conductive polymer as described above) as shown in block 616. In the present example, at least a portion of the porous ceramic body is then coated with a suitable silver compound (e.g., silver paste), as shown in block 618. Electrical leads forming the anode and cathode are attached and the package is sealed, as shown in block 620.

A bulk capacitor and a method of manufacturing a bulk capacitor are disclosed. The disclosure is merely exemplary. Many variations, alternatives and substitutions of the invention are contemplated as falling within the spirit and scope of the claimed invention. Those skilled in the art will recognize that a wide variety of modifications, alterations, and combinations can be made with respect to the above described embodiments without departing from the spirit and scope of the invention, and that such modifications, alterations, and combinations are to be viewed as being within the ambit of the inventive concept. It is intended that the appended claims cover all such changes and modifications as fall within the true spirit and scope of this present invention.

Claims (13)

1. A bulk capacitor, comprising:

a first electrode formed of a metal foil,

a semi-conductive porous ceramic body deposited on the metal foil,

a dielectric layer formed on the porous ceramic body,

a semiconductive ceramic layer disposed between the metal foil and the porous ceramic body, an

A conductive medium overlying the dielectric layer, the conductive medium filling at least a portion of the porous ceramic body and forming a second electrode.

2. The bulk capacitor of claim 1 further comprising a conductive metal layer encapsulating the porous ceramic body.

3. The bulk capacitor of claim 1 wherein the metal foil has a geometric profile.

4. The bulk capacitor of claim 1 wherein the conductive medium comprises a conductive polymer.

5. The bulk capacitor of claim 1 wherein the combination of the porous ceramic body and the dielectric layer has a dielectric constant (K) in the range of 500-.

6. The bulk capacitor of claim 1 wherein the dielectric layer is formed on a porous ceramic body and the metal foil.

7. A method of manufacturing a bulk capacitor, the method comprising:

forming a semiconductive porous ceramic body on a first electrode comprising a metal foil,

oxidizing the porous ceramic body to form a dielectric layer,

forming a semi-conductive ceramic layer between the metal foil and the porous ceramic body, an

A conductive medium is coated on the dielectric layer, the porous ceramic body is filled with the conductive medium and a second electrode is formed.

8. The method of claim 7, comprising encapsulating the porous ceramic body with a conductive metal layer.

9. The method of claim 7, further comprising forming a geometric profile in the metal foil.

10. The method of claim 7, wherein the oxidizing is performed thermally.

11. The method of claim 7, wherein the oxidizing is performed electrochemically.

12. The method of claim 7, wherein the conductive medium comprises a conductive polymer.

13. The method as claimed in claim 7 wherein the combination of the porous ceramic body and the dielectric layer has a dielectric constant (K) in the range of 500-.