HK1159870A - Method and apparatus for power converter for class d audio power amplifiers - Google Patents

Abstract

A method and apparatus for power conversion in a class D amplifier is provided. The power conversion is achieved using synchronous rectifiers in a regulated half bridge power supply, taking the sum of the positive and negative rails as feedback, in order facilitate energy transfer between positive and negative output rails. This minimizes the effects of off side charging and rail sag, as well as achieving good line regulation, while allowing use of very small, low value output capacitors.

Description

Method and apparatus for power converter for class D audio power amplifier

Cross Reference to Related Applications

This patent application claims priority from U.S. provisional patent application No.61/061986 filed on 16/6/2008.

Technical Field

The present invention relates generally to electronic devices for converting power and amplifying signals, and more particularly to methods and devices for providing power to an amplifier.

Background

Fig. 1 is a schematic diagram illustrating an example of a half-bridge class D amplifier. The half-bridge class D amplifier includes a positive supply voltage rail 101, a negative supply voltage rail 102, ground 103, a positive supply voltage filter capacitor 104, a negative supply voltage filter capacitor 105, an upper side driver 106, a lower side driver 107, a low pass output filter inductor 108, a low pass output filter capacitor 109, and a load 110. Class D audio power amplifiers in a half-bridge configuration present a number of problems for power supplies. One example of these problems is offset charging (off-side charging).

Dislocation charging

Class D amplifiers with half-bridge configurations result in "mis-charging" or "rail pumping", where energy is transferred from a loaded converter output to an unloaded converter output. The loaded converter output is the portion of the power supply that provides the first supply voltage to the first supply voltage rail from which the half bridge class D amplifier is currently drawing power. The unloaded converter output is the portion of the power supply that provides the second supply voltage to the second supply voltage rail from which the half bridge class D amplifier is not currently expected to draw power. For example, when the upper side driver 106 is active, power is provided from the power supply to the positive supply voltage rail 101 for the half bridge class D amplifier that includes the upper side driver 106. During this time, the first portion of the power supply circuit that provides the positive supply voltage on the positive supply voltage rail 101 will be the loaded converter output, while the second portion of the power supply circuit that provides the negative supply voltage on the negative supply voltage rail 102 will be the unloaded converter output. As another example, when the low side driver 107 is active, power is provided from the power supply to the negative supply voltage rail 102 for a half bridge class D amplifier that includes the low side driver 107. During this time, the second portion of the power supply circuit that provides the negative supply voltage on the negative supply voltage rail 102 will be the loaded converter output, while the first portion of the power supply circuit that provides the positive supply voltage on the positive supply voltage rail 101 will be the unloaded converter output.

In a half-bridge class D amplifier, a mis-charging or rail pumping condition occurs because the load of the half-bridge class D amplifier is coupled between the loaded converter output and ground, and the filter capacitor of the unloaded converter output is coupled between its corresponding unloaded supply voltage rail and ground. The misaligned charging will result in an increase in the magnitude of the unloaded supply voltage of the unloaded rail, which can easily cause it to exceed the rated voltage of the class D amplifier device and cause distortion by introducing non-linearities in the forward transfer function.

To minimize the effects of mis-charging, larger values of capacitors are typically used on the positive and negative supply voltage rails. However, the required capacitance is not directly proportional to the power output of the amplifier, but inversely proportional to the load impedance. This means that a low power amplifier driving a low impedance load requires a large capacitance value that is not proportional to its lower power output.

Fig. 2 is a waveform diagram illustrating an example of a misaligned discharge of a supply voltage rail due to operation of a half bridge class D amplifier. The duty cycle D is set to 75% so that D' (i.e. not D, the inverse of D) is 25%. In theory, this would result in an output voltage of Vral/2 and an output current of Vral/2R. This makes the dislocation charging current equal to D'. times.Vrail/2R. For the purposes of this example, inductor 108 may be considered to have a value large enough to ignore the ripple and treat it as a constant current source.

Waveform 201 depicts an example of a waveform of a voltage of an enable signal D for enabling the upper side driver 106 of an example half bridge class D amplifier. At time 206, waveform 201 rises to enable voltage 211. Waveform 201 remains high at enable voltage 211 until it drops to inhibit voltage 212 at time 207. Waveform 201 remains at inhibit voltage 212 until it again rises to enable voltage 211 at time 208. Waveform 201 remains high at enable voltage 211 until it again drops to inhibit voltage 212 at time 209. Waveform 201 remains low at inhibit voltage 212 until it is raised again to enable voltage 211 at time 210. Since this example describes a 75% duty cycle, waveform 201 is high at enable voltage 211 75% of the time and low at inhibit voltage 212 25% of the time.

Waveform 202 depicts an example of a waveform of a voltage of an enable signal D' for enabling the lower driver 107 of the example half bridge class D amplifier. At time 206, waveform 202 decreases to inhibit voltage 214. Waveform 202 remains low at inhibit voltage 214 until it rises to enable voltage 213 at time 207. Waveform 202 remains at enable voltage 213 until it again drops to inhibit voltage 214 at time 208. Waveform 202 remains low at inhibit voltage 214 until it again rises to enable voltage 213 at time 209. Waveform 202 remains high at enable voltage 213 before decreasing again to inhibit voltage 214 at time 210. Since this example describes a 75% duty cycle for D, the waveform 202 for D' is high at the enable voltage 213 and low at the inhibit voltage 214 25% of the time.

Waveform 203 depicts an example of the waveform of the voltage at the connection point 111 of the upper driver 106 and the lower driver 107. At time 206, waveform 203 rises to positive supply voltage 216. Waveform 203 remains high at positive supply voltage 216 until it drops to negative supply voltage 217 at time 207. Waveform 203 remains at the negative supply voltage 217 until it rises again to the positive supply voltage 216 at time 208. Waveform 203 remains high at positive supply voltage 216 until it again decreases to negative supply voltage 217 at time 209. Waveform 203 remains low at negative supply voltage 217 until rising again to positive supply voltage 216 at time 210. Since this example depicts a 75% duty cycle, waveform 203 is high at positive supply voltage 216 75% of the time and low at negative supply voltage 217 25% of the time. The inductor 108 and capacitor 109 act as a low pass filter to filter out high frequency switching between the positive supply voltage 216 and the negative supply voltage 217 resulting in a regulated voltage 218, the voltage 218 being at 75% of the way from the negative supply voltage 217 to the positive supply voltage 216 (i.e. at approximately half the positive supply voltage in this example, where the ground 103 has a ground voltage centered between the positive supply voltage 216 and the negative supply voltage 217).

Waveform 204 depicts an example of a waveform of the charging current 112 flowing when the upper driver 106 is active. At time 206, waveform 204 transitions to a negative current level 220. Waveform 204 remains at negative current level 220 until it transitions to zero current level 219 at time 207. Waveform 204 remains at zero current level 219 until it again transitions to negative current level 220 at time 208. Waveform 204 remains at negative current level 220 until it again transitions to zero current level 219 at time 209. Until time 210 again transitions to negative current level 220, waveform 204 remains at zero current level 219. Since this example depicts a 75% duty cycle, the waveform 204 is at the negative current level 220 75% of the time and at the zero current level 219 25% of the time.

Waveform 205 depicts an example of the waveform of the charging current 113 flowing when the lower driver 107 is active. From time 206 to time 207, waveform 205 remains at zero current level 221. At time 207, waveform 205 transitions to positive current level 222. Waveform 205 remains at positive current level 222 until time 208 it again transitions to zero current level 221. Waveform 205 remains at zero current level 221 until it again transitions to positive current level 222 at time 209. Until time 210 again transitions to zero current level 221, waveform 205 remains at positive current level 222. Since this example depicts a 75% duty cycle, the waveform 204 is at the zero current level 221 75% of the time and at the positive current level 222 25% of the time.

The worst case of misaligned charging can be derived by setting the derivative to 0 and solving for D. For example, when Vout ═ 2 ×/Vrail ═ D ═ Vrail, Iout ═ Vout/R, and Ichg ═ 1-D × (Iout) (i.e., offset charging current), Ichg ═ 1-D ═ Iout ═ 1-D) ═ Vout/R ═ 2 × (Vrail ^ D +3 × (D-Vrail)/R. The derivative is set to 0 as follows: dIchg/dD (-2 Vrail (2D) +3 Vrail)/R-0. According to the example of setting the duty cycle D to 75%, the equation is solved for D-3/4 because worst-case mis-aligned charging occurs when D-3/4 and Vout-Vrail/2. Accordingly, solving Ichg for D-3/4 is performed as follows: ichg (-2 × Vrail × 3/4) ^2+3 × Vrail (3/4) -Vrail)/R ═ Vrail/(8 × R). For a typical audio application, the worst case for Ichg is a square wave at 20Hz, where Vout — Vrail/2. Accordingly, Ichg ═ C × dV/dt. Thus, Vrail/(8 × R) ═ C (Vrail/8)/50mS, the desired change in V was set to Vrail/8 to give a 12.5% change. Therefore, C is 1/(20 × R). Thus, for an 8 ohm load, C ═ 6250 uF. As mentioned above, the value of C is a function of output impedance and not output power, and therefore the above calculation is valid for a given percentage fluctuation of Vrail and a given output impedance, regardless of the value of Vrail and output power. If only a sine wave is used, the actual capacitance may be smaller, but the result remains the same because: c is inversely proportional to R rather than proportional to power. The above calculations show that to keep the charge at 1/8 (i.e. 12.5%) of the initial rail voltage during the 20Hz square wave with Vrail/2 peaks, the capacitance needs to be 1/(20 x R) farad, or 6250uF for each rail of 8 ohms. This would require 12,500uF per track at 4 ohms, or 25,000uF per track at 2 ohms. The total capacitance of 50,000uF is very large and impractical for low power designs because large values of capacitors are typically expensive and have large physical dimensions, which runs counter to the low cost and small size that is typically favored in modern electronic devices.

Fig. 3 is a waveform diagram illustrating an example of supply voltage rail fluctuations caused by misaligned charging. The waveform diagram is an example of a waveform that can be obtained using an oscilloscope to view an actual circuit illustrating a problem. Waveform 301 depicts the AC waveform at the output of the transformer secondary winding prior to rectification. Waveform 302 depicts a DC supply voltage rail with a large ripple caused by misaligned charging. In this case, a 50% voltage rise is obtained with 1,000uF per track of 4 ohms in the case of a 20Hz sine wave (the case of a square wave will be worse). To achieve a 3% voltage rise, 15,000uF per track will be assumed.

Regulating

The difficulty of providing power to a half bridge class D amplifier is further compounded by the use of a regulated power supply (typically regulated based on only the positive supply voltage rail). In this case, any increase in the magnitude of the negative supply voltage rail will not enter the feedback loop. Therefore, no correction for such an increase is made. If the positive rail is loaded and the negative rail is charged with misalignment, the amplifier will be subject to possible over-voltages and non-linearities. If the negative rail is loaded, it will always drop to 0 without the feedback loop performing a corrective action. This lack of corrective action results in a reduction in the amplifier output voltage. The reduction in the output voltage of the amplifier results in a lower power output and distortion of the amplified signal, which has an adverse effect on the power rating and good quality of the amplifier output.

If, as an alternative, the sum of the positive and negative output supplies is used to feed back into the regulation circuit, any increase in the "mis-charged" rail will allow a corresponding decrease in the loaded rail, resulting in a drop in the amplifier output voltage. This occurs if the loaded track is positive or negative. Again, the reduced output voltage results in a lower power output and distortion of the amplified signal.

Typical prior art techniques involve larger capacitors and unregulated power supplies to alleviate these problems for half bridge class D amplifiers, but rail droop (i.e., inefficient load regulation) still exists, reduces output power, and does not implement line regulation. In addition, the larger capacitors in the power supply circuit increase the cost and physical size of the amplifier that utilizes these capacitors.

Other prior art techniques utilize full bridge class D amplifiers to avoid these problems. However, the full-bridge class D amplifier has several disadvantages, such as a large DC offset on the output, an inability to operate two channels to one load in a bridge single mode, and the requirement of twice the number of output driver stages and output filters compared to the half-bridge class D amplifier, which increases the cost and physical size of the full-bridge class D amplifier.

Therefore, a solution is needed to avoid the drawbacks of the prior art.

Disclosure of Invention

A method and apparatus for power conversion of a class D amplifier is provided. The power conversion is achieved using a synchronous rectifier in a regulated half-bridge power supply, using the sum of the positive and negative rails as feedback to facilitate energy transfer between the positive and negative output rails. This minimizes the effects of mis-charging and rail droop and enables good line regulation while allowing the use of very small, low value output capacitors.

Drawings

The present invention will be better understood and its features will be apparent to those skilled in the art by reference to the accompanying drawings.

Fig. 1 is a schematic diagram illustrating an example of a half-bridge class D amplifier.

Fig. 2 is a timing diagram showing voltages illustrating an example of a misaligned charging of the supply voltage rail due to operation of the half bridge class D amplifier.

Fig. 3 is a timing diagram showing voltages illustrating an example of power supply voltage rail fluctuations due to misaligned charging.

FIG. 4 is a timing diagram showing voltages illustrating an example of supply voltage rail regulation in accordance with at least one embodiment.

Fig. 5 is a schematic diagram illustrating an example of an apparatus for power conversion of a class D amplifier in accordance with at least one embodiment.

Fig. 6 is a schematic diagram illustrating an example of a power supply for power conversion of a class D amplifier in accordance with at least one embodiment.

Fig. 7 is a schematic diagram illustrating an example of a power supply control circuit for power conversion of a class D amplifier in accordance with at least one embodiment.

Fig. 8 is a schematic diagram illustrating an example of a regulator of a power supply control circuit for power conversion of a class D amplifier in accordance with at least one embodiment.

Fig. 9A and 9B are flow diagrams illustrating a method for power conversion of a class D amplifier in accordance with at least one embodiment.

The use of the same reference symbols in different drawings indicates similar or identical items.

Detailed Description

A method and apparatus for power conversion of a class D amplifier is provided. The power conversion is achieved using a synchronous rectifier in a regulated half-bridge power supply, using the sum of the positive and negative rails as feedback to facilitate energy transfer between the positive and negative output rails. This minimizes the effects of mis-charging and rail droop and enables good line regulation while allowing the use of very small, low value output capacitors.

FIG. 4 is a waveform diagram illustrating an example of supply voltage rail regulation in accordance with at least one embodiment. Waveform 401 depicts the AC waveform at the output of the transformer secondary winding prior to rectification. Waveform 402 depicts a positive supply voltage rail that is substantially free of ripple caused by misaligned charging. Waveform 403 depicts a negative supply voltage rail that is substantially free of ripple caused by misaligned charging. As can be seen from the figure, such an embodiment can achieve a 3% rise in track voltage with only 150uF per track, for example with a 20Hz sine wave going to 4 ohms. If prior art techniques were used, the amount of such voltage rise would require a capacitance that is approximately two orders of magnitude greater.

Although synchronous rectifiers have previously been used in prior art power supply designs to reduce losses in passive output rectifiers, such designs have not been able to take advantage of the bi-directional connectivity of devices such as MOSFETs. However, according to at least one embodiment, synchronous rectifiers with bidirectional connectivity are used to transfer energy between outputs, i.e. from unloaded to loaded rails. This transfer of energy effectively counteracts the mis-charging that occurs in the power supply of prior art half bridge class D power amplifiers.

In prior art power supply designs, synchronous rectifiers are also used to transfer energy from the load back to the source, but the topology that does this typically suffers from large unwanted losses due to circulating currents. However, according to at least one embodiment, efficient energy transfer via the synchronous rectifier provides effective compensation for the mis-aligned charging phenomenon in the class D power amplifier system.

The use of synchronous rectifiers allows feedback to be taken from the sum of the positive and negative rails, as floating and droop are minimized, and protects the class D amplifier from over-voltage.

Fig. 5 is a schematic diagram of an example of an apparatus for power conversion of a class D amplifier, according to at least one embodiment. Primary supply voltage rails, such as a first primary supply voltage rail 506 and a second primary supply voltage rail 507 are provided. For example, the first primary supply voltage rail 506 may be a positive primary supply voltage rail and the second primary supply voltage rail 507 may be a negative primary supply voltage rail. A first primary supply capacitor 508 is connected between the first primary supply voltage rail 506 and a first end of a transformer primary winding 510. A second primary supply capacitor 509 is connected between the second primary supply voltage rail 507 and a first end of the transformer primary winding 510. The first primary switch 511 is connected between the first primary supply voltage rail 506 and the second end of the transformer primary winding 510. A second primary switch 512 is connected between the second primary supply voltage rail 507 and a second end of the transformer primary winding 510.

A first terminal of the transformer first secondary winding 515 is connected to an anode of the first diode 519 and a second terminal of the first switch 523, and to a cathode of the second diode 520 and a first terminal of the second switch 524. A second end of the transformer first secondary winding 515 is connected to ground 503. A first end of the transformer second secondary winding 516 is connected to ground 503. A second terminal of transformer second secondary winding 516 is connected to an anode of third diode 521 and a second terminal of third switch 525, and to a cathode of fourth diode 522 and a first terminal of fourth switch 526. Positive supply voltage rail 501 is connected to a first terminal of first switch 523, a cathode of first diode 519, a cathode of third diode 521, and a first terminal of third switch 525. Negative supply voltage rail 502 is connected to a second terminal of second switch 524, an anode of second diode 520, an anode of fourth diode 522, and a second terminal of fourth switch 526.

The first coupled inductor winding 528 is coupled in series with the positive supply voltage rail 501 and the second coupled inductor winding 529 is coupled in series with the negative supply voltage rail 302. The first coupling inductor winding 528 is inductively coupled to the second coupling inductor winding 529 such that the first coupling inductor winding 528 is coupled in the opposite direction to the second coupling inductor winding 529, as indicated by the dots in the figure. A positive supply filter capacitor 504 is coupled between the positive supply voltage rail 501 and ground 503. A negative supply filter capacitor 505 is coupled between the negative supply voltage rail 502 and ground 503. The positive supply voltage rail 530 and the negative supply voltage rail 531 are coupled to the control system 527. The control system 527 monitors the positive power supply voltage rail 530 and the negative power supply voltage rail 531 and provides a first signal 513 to control the first primary switch 511, the first switch 523, and the fourth switch 526, and provides a second signal 514 to control the second primary switch 512, the second switch 524, and the third switch 525.

Fig. 6 is a schematic diagram illustrating an example of a power supply for power conversion of a class D amplifier in accordance with at least one embodiment. Primary supply voltage rails, such as a first primary supply voltage rail 506 and a second primary supply voltage rail 507 are provided. A capacitor 532 is coupled between the first primary supply voltage rail 506 and the second primary supply voltage rail 507. For example, the first primary supply voltage rail 506 may be a positive primary supply voltage rail and the second primary supply voltage rail 507 may be a negative primary supply voltage rail. A first primary supply capacitor 508 is connected between the first primary supply voltage rail 506 and a first end of a transformer primary winding 510. A second primary supply capacitor 509 is connected between the second primary supply voltage rail 507 and a first end of the transformer primary winding 510. The first primary switch 511 is connected between the first primary supply voltage rail 506 and the second end of the transformer primary winding 510. A second primary switch 512 is connected between the second primary supply voltage rail 507 and a second end of the transformer primary winding 510. The first primary switch control terminal is coupled to a first terminal of a first primary switch control transformer winding 601. A second terminal of the first primary switch control transformer winding 601 is coupled to a second terminal of the transformer primary winding 510. The second primary switch control terminal is coupled to a second terminal of the second primary switch control transformer winding 602. A first end of the second primary switch control transformer winding 602 is coupled to a second primary supply voltage rail 507. The first primary switch control transformer winding 601 and the second primary switch control transformer winding 602 are inductively coupled to the first switch control transformer winding 603, the second switch control transformer winding 604, the third switch control transformer winding 605, the fourth switch control transformer winding 606, and the pulse width modulator output transformer winding 701.

A first terminal of the transformer first secondary winding 515 is connected to an anode of the first diode 519 and a second terminal of the first switch 523, and to a cathode of the second diode 520 and a first terminal of the second switch 524. A second end of the transformer first secondary winding 515 is connected to ground 503. A first end of the transformer second secondary winding 516 is connected to ground 503. A second terminal of transformer second secondary winding 516 is connected to an anode of third diode 521 and a second terminal of third switch 525, and to a cathode of fourth diode 522 and a first terminal of fourth switch 526. Positive supply voltage rail 501 is connected to a first terminal of first switch 523, a cathode of first diode 519, a cathode of third diode 521, and a first terminal of third switch 525. Negative supply voltage rail 502 is connected to a second terminal of second switch 524, an anode of second diode 520, an anode of fourth diode 522, and a second terminal of fourth switch 526.

The first coupled inductor winding 528 is coupled in series with the positive supply voltage rail 501 and the second coupled inductor winding 529 is coupled in series with the negative supply voltage rail 302. The first coupling inductor winding 528 is inductively coupled to the second coupling inductor winding 529 such that the first coupling inductor winding 528 is coupled in the opposite direction to the second coupling inductor winding 529, as indicated by the dots in the figure. A positive supply filter capacitor 504 is coupled between the positive supply voltage rail 501 and ground 503. A negative supply filter capacitor 505 is coupled between the negative supply voltage rail 531 and ground 503. The positive supply voltage rail 530 and the negative supply voltage rail 531 are coupled to the control system 527. The control system 527 monitors the positive power supply voltage rail 530 and the negative power supply voltage rail 531 and provides a first signal 513 to control the first primary switch 511, the first switch 523, and the fourth switch 526, and provides a second signal 514 to control the second primary switch 512, the second switch 524, and the third switch 525.

According to at least one embodiment, the first signal 513 and the second signal 514 may be implemented as Alternating Current (AC) signals applied to the pulse width modulator output transformer windings 701. The pulse width modulator output transformer winding 701 is inductively coupled to a first primary switch control transformer winding 601, a second primary switch control transformer winding 602, a first switch control transformer winding 603, a second switch control transformer winding 604, a third switch control transformer winding 605, and a fourth switch control transformer winding 606.

A first terminal of the first switch control transformer winding 603 is coupled to a first switch control terminal of the first switch 523. A second terminal of the first switch control transformer winding 603 is coupled to a first terminal of a transformer first secondary winding 515 at a node 517. A first end of a second switch control transformer winding 604 is coupled to the negative supply voltage rail 502. A second terminal of the second switch control transformer winding 604 is coupled to a second switch control terminal of the second switch 524. A first end of the third switch control transformer winding 605 is coupled to a second end of the transformer second secondary winding 516 at node 518. A second terminal of the third switch control transformer winding 605 is coupled to a third switch control terminal of the third switch 525. A first terminal of the fourth switch control transformer winding 606 is coupled to a fourth switch control terminal of a fourth switch 526. A second terminal of the fourth switch control transformer winding 606 is coupled to the negative supply voltage rail 502.

Fig. 7 is a schematic diagram illustrating an example of a power supply control circuit for power conversion of a class D amplifier in accordance with at least one embodiment. A first terminal of resistor 704 and a first terminal of resistor 702 are coupled to positive supply voltage rail 530. A second terminal of resistor 704 is coupled to a first terminal of capacitor 705. A second terminal of capacitor 705, a second terminal of resistor 702, and a first terminal of resistor 703 are coupled to a regulator control input of regulator 706. A second terminal of resistor 703 and a negative terminal of regulator 706 are coupled to negative supply voltage rail 531. A first end of resistor 707 and a first end of resistor 711 are coupled to auxiliary voltage source rail 722. A second terminal of resistor 711 is coupled to a first terminal of capacitor 712, a first terminal of capacitor 714, a positive terminal of regulator 706, and a cathode of Light Emitting Diode (LED)709 of opto-isolator 708. A second end of resistor 707 is coupled to the anode of LED 709 of optoisolator 708. A second terminal of capacitor 712 is coupled to a first terminal of resistor 713. A second terminal of resistor 713 and a second terminal of capacitor 714 are coupled to a regulator control input of regulator 706.

The collector of phototransistor 710 of optoisolator 708 is coupled to a first terminal of resistor 715 and a first terminal of resistor 716. A second terminal of the resistor 715 is coupled to a VREF input of a pulse width modulator 717, the pulse width modulator 717 may be, for example, a Texas instruments uc3525A regulating pulse width modulator. A second terminal of the resistor 716 is coupled to the NI INPUT terminal of the pulse width modulator 717. The emitter of the phototransistor 710 of the optocoupler 708 is coupled to a first terminal of a capacitor 718, a first terminal of a resistor 719 and the ground terminal of the pulse width modulator 717. A second terminal of the capacitor 718 is coupled to the CT terminal and DISCHARGE terminal of the pulse width modulator 717. A second terminal of the resistor 719 is coupled to the RT terminal of the pulse width modulator 717. The COMP terminal of the pulse width modulator 717 is coupled to the INV INPUT terminal of the pulse width modulator 717. The OUTB terminal of the pulse width modulator 717 is coupled to a first terminal of a capacitor 720. A second terminal of capacitor 720 is coupled to a first terminal of pulse width modulator output transformer winding 701. The OUTA terminal of the pulse width modulator 717 is coupled to a second terminal of the pulse width modulator output transformer winding 701.

Fig. 8 is a schematic diagram illustrating an example of a regulator 706 of a power supply control circuit for power conversion of a class D amplifier in accordance with at least one embodiment. The regulator control input of regulator 706 is coupled to the non-inverting input of comparator 801. The positive terminal of regulator 706 is coupled to the positive power supply terminal of comparator 801, the collector of NPN transistor 803, and the cathode of diode 804. The negative terminal of regulator 706 is coupled to the negative power terminal of comparator 801, the negative terminal of voltage reference 802, the emitter of NPN transistor 803, and the anode of diode 804. The positive terminal of the voltage reference 802 is coupled to the inverting input of the comparator 801. The output of comparator 801 is coupled to the base of NPN transistor 803. According to at least one embodiment, regulator 706 may be implemented using discrete components or using an integrated device (e.g., a Texas Instrument TLV431B low-voltage tunable precision shunt regulator).

Fig. 9A and 9B are flow diagrams illustrating a method for power conversion of a class D amplifier in accordance with at least one embodiment. The method starts at step 901 where positive and negative supply voltages are applied to a class D power amplifier at step 901. Step 901 may include steps 907 and/or 908. In step 907, the positive and negative supply voltages are coupled to the class D power amplifier via the coupled inductors. The first winding for the positive supply voltage is inductively coupled to the second winding for the negative supply voltage. At step 908, the positive and negative supply voltages are filtered by connecting the first and second capacitors after the coupled inductor. The first capacitor is connected between the positive supply voltage and ground. The second capacitor is connected between the negative supply voltage and ground.

The method continues from step 901 to step 902. At step 902, the difference between the positive and negative supply voltages is compared. The method continues from step 902 to step 903. In step 903, a pulse width modulated control signal is generated based on the difference. The method continues from step 903 to step 904. In step 904, the synchronous rectifier is controlled based on the pulse width modulated signal. Step 904 may include steps 909, 910, and/or 911. In step 909, the first bidirectional conductive device is turned on in response to a first pulse of a first polarity of the pulse width modulated control signal. At step 910, the second bidirectional conductive device is turned on in response to a second pulse of a second polarity of the pulse width modulated control signal. In step 911, the pulse width modulated control signal is coupled to the synchronous rectifier via a transformer.

The method continues from step 904 to step 905. In step 905, current is allowed to pass through the MOSFETs of the synchronous rectifiers in the synchronous rectifiers. The MOSFET is coupled in parallel with a diode. This current appears in the direction blocked by the diode. The method continues from step 905 to step 906. At step 906, charge is transferred through the synchronous rectifier to compensate for the misaligned charging.

Although the control system according to at least one embodiment may be implemented using analog electronics, according to at least one embodiment, the control system may include digital control circuitry. For example, a microcontroller may be used to perform some or all of the above method steps to implement the control system. Any functions not performed by the digital control circuit may be implemented using analog electronics.

Thus, a method and apparatus for power conversion of a class D amplifier is described. While the invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that the inventive features of the present invention are applicable to other embodiments as well, all of which are intended to fall within the scope of the invention.

Claims (20)

1. A method, comprising:

applying positive and negative supply voltages to a class D power amplifier;

comparing the difference between the positive and negative supply voltages;

generating a pulse width modulated control signal based on the difference;

controlling a synchronous rectifier based on the pulse width modulated control signal.

2. The method of claim 1, further comprising:

charge is transferred through the synchronous rectifier to compensate for the misaligned charging.

3. The method of claim 1, further comprising:

a MOSFET that allows current to pass through a synchronous rectifier of the synchronous rectifiers, wherein the MOSFET is coupled in parallel with a diode, the current occurring in a direction that the diode blocks.

4. The method of claim 1, wherein controlling the synchronous rectifier comprises:

turning on a first bidirectional conductive device in response to a first pulse of a first polarity of a pulse width modulated control signal; and

the second bidirectional conductive device is rendered conductive in response to a second pulse of a second polarity of the pulse width modulated control signal.

5. The method of claim 1, wherein applying positive and negative supply voltages to a class D power amplifier comprises:

the positive and negative supply voltages are coupled to a class D power amplifier via a coupled inductor, wherein a first winding for the positive supply voltage is inductively coupled to a second winding for the negative supply voltage.

6. The method of claim 5, wherein applying positive and negative supply voltages to a class D power amplifier further comprises:

the positive and negative supply voltages are filtered by connecting first and second capacitors after the coupled inductor, the first capacitor being connected between the positive supply voltage and ground and the second capacitor being connected between the negative supply voltage and ground.

7. The method of claim 1, wherein controlling the synchronous rectifier comprises:

the pulse width modulated control signal is coupled to a synchronous rectifier via a transformer.

8. An apparatus, comprising:

a power circuit comprising a synchronous rectifier;

a class D amplifier coupled to the power supply circuit; and

a power supply control circuit coupled to the power supply circuit, the power supply control circuit providing a pulse width modulated control signal to control the power supply circuit based on a difference between positive and negative power supply voltages provided by the power supply circuit.

9. The apparatus of claim 8, wherein the pulse width modulated control signal controls a synchronous rectifier of a power supply circuit.

10. The apparatus of claim 9, wherein the charge transfer through the synchronous rectifier compensates for mis-aligned charging of the capacitor on the positive and negative supply voltages due to operation of the class D power amplifier.

11. The apparatus of claim 10, wherein the synchronous rectifier comprises:

a bidirectional conduction device in parallel with the diode.

12. The apparatus of claim 11, wherein the bidirectional conducting means comprises:

a metal oxide semiconductor field effect transistor MOSFET.

13. The apparatus of claim 12, further comprising:

a transformer coupling the pulse width modulated control signal to a gate of a MOSFET.

14. The apparatus of claim 8, further comprising:

a coupled inductor, wherein the coupled inductor couples positive and negative supply voltages from a supply circuit to a class D amplifier, the coupled inductor comprising a first winding in series with the positive supply voltage and a second winding in series with the negative supply voltage, the first winding inductively coupled with the second winding.

15. The apparatus of claim 14, further comprising:

a first capacitor coupled from the first winding to ground; and

a second capacitor coupled from the second winding to ground.

16. An apparatus, comprising:

a regulator including a comparator and a voltage reference, the comparator being coupled to a positive power supply voltage and a negative power supply voltage of the class-D power amplifier to compare a comparison voltage obtained from a difference between the positive power supply voltage and the negative power supply voltage with a reference voltage of the voltage reference; and

a pulse width modulator coupled to the regulator for generating a pulse width modulated control signal to control the positive and negative supply voltages by controlling a synchronous rectifier of a power supply circuit that provides the positive and negative supply voltages.

17. The apparatus of claim 16, further comprising:

a transformer for coupling the pulse width modulated control signal to a synchronous rectifier.

18. The apparatus of claim 17, further comprising:

an optical coupler for coupling the regulator to the pulse width modulator.

19. The apparatus of claim 18, further comprising:

a first capacitor coupled from a positive supply voltage to ground; and

a second capacitor coupled from the negative supply voltage to ground,

wherein the second capacitor is subject to a mis-aligned charging when the class D amplifier is operated from the positive supply voltage.

20. The apparatus of claim 18, further comprising:

a voltage divider for obtaining the comparison voltage from a difference between a positive supply voltage and a negative supply voltage.