HK1158824A - Method of forming a semiconductor die - Google Patents

Description

Method of forming a semiconductor die

Technical Field

The present invention relates generally to electronic devices and, more particularly, to semiconductors, structures of semiconductors, and methods of forming semiconductor devices.

Background

In the past, singulation lines have generally been formed as a plurality of parallel lines, with each singulation line extending in an axial direction, e.g., along a long axis of the singulation line, straight across the wafer from one side of the wafer so as to allow the wafer saw or scribe line to extend in a straight line across the wafer. Each of the existing singulation lines typically extends straight across the wafer without curves, bends, angles, or other shapes other than a continuous straight line. To facilitate the use of straight singulation lines, existing semiconductor dies (die) typically have regular shapes, e.g., all dies have the same total area and the same shape, which is typically a square or rectangular shape. The regularly shaped dies are also arranged in a regular pattern on the wafer so that singulation lines can extend between the dies and singulate the dies. The straight lines of rectangular or square shape and the same area of the die, along with the regular pattern, allow straight singulation lines to be used. These scribe lines force the die to have a regular shape of a square or rectangle in order to use these scribe lines extending in the axial direction.

It is therefore desirable to have a method of forming a semiconductor die that does not require axial singulation lines.

Drawings

FIG. 1 illustrates a reduced plan view of an embodiment of a semiconductor wafer according to the present invention;

FIG. 2 shows an enlarged plan view of an example of an embodiment of a plurality of dies of the wafer of FIG. 1 in accordance with the present invention;

FIG. 3 shows an enlarged plan view of an example of an embodiment of another plurality of dies of the wafer of FIG. 1 in accordance with the present invention;

FIGS. 4-10 show enlarged plan views of examples of various other embodiments of the die of the wafer of FIG. 1 in accordance with the present invention;

FIG. 11 shows an enlarged cross-sectional view of an embodiment of a portion of the semiconductor wafer of FIG. 1 at a stage within an example of an embodiment of a process for singulating dies from a wafer in accordance with the present invention;

fig. 12-14 show the die of fig. 11 at various stages later in time in accordance with an example of an embodiment of a process for singulating dies in accordance with the invention;

FIG. 15 shows an enlarged cross-sectional view of an embodiment of a portion of the semiconductor wafer of FIG. 1 at a stage in an example of another embodiment of a process for singulating dies from a wafer in accordance with the present invention;

FIGS. 16-19 show the die of FIG. 15 at various stages subsequent to an example of an embodiment of a process for singulating dies in accordance with the invention;

FIG. 20 shows an enlarged cross-sectional view of an embodiment of a portion of the semiconductor wafer of FIG. 1 at a stage in an example of another embodiment of a process for singulating dies from a wafer in accordance with the present invention;

FIGS. 21-22 show the die of FIG. 20 at various stages subsequent to an example of an embodiment of a process for singulating dies in accordance with the invention;

FIG. 23 shows an enlarged plan view of an example of an embodiment of a plurality of dies of the wafer of FIG. 1, in accordance with the present invention;

fig. 24 shows a plan view of an embodiment of an example of a semiconductor device having a semiconductor die with a socket in accordance with the present invention;

FIG. 25 shows a cross-sectional view of the device of FIG. 24 in accordance with the present invention;

fig. 26 shows a plan view of an embodiment of an example of a semiconductor device according to the present invention as an alternative embodiment of the device of fig. 24;

fig. 27 illustrates a plan view of a portion of another embodiment of a semiconductor device including a socketed semiconductor device in accordance with the present invention; and

fig. 28 shows an enlarged plan view of a multiply-connected die in accordance with the present invention.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. In addition, descriptions and details regarding well-known steps and elements are omitted for simplicity of the description. As used herein, current carrying electrode means an element of a device that transmits current through the device, such as a source or drain of an MOS transistor or an emitter or collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device, such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-channel devices, or certain N-type or P-type doped regions, one skilled in the art will recognize that complementary devices according to the present invention are equally possible. Those skilled in the art will appreciate that the words used herein in relation to the operation of a circuit are not intended to be precise in the sense that action occurs immediately upon initiation of an initialization action, but rather there may be some small but reasonable delay, such as a transmission delay, between the reactions initiated by the initial action.

The word about or substantially is used to mean that the value of an element has a parameter that is expected to be very close to a starting value or position. However, it is well known in the art that there are always minor differences that prevent the value or position from being exactly at the starting value. It is well established in the art that differences of up to at least ten percent (10%) (and semiconductor dopant concentrations of up to twenty percent (20%)) are reasonable differences from the precisely described ideal target. For clarity of the drawings, the doped regions of the device structure are shown as generally having straight line sides and precisely angled corners. However, it will be appreciated by those skilled in the art that the doped edges of the doped regions may not be generally straight lines and the corners may not be precisely angled due to the diffusion and activation of the dopants.

As used herein, symmetrical shapes means two shapes that correspond one-to-one in at least size, shape, and relative position of portions on opposite sides of a dividing line or media plane or relative position about a center or axis, the shapes being symmetrical if they have not been changed by mapping or rotation. The term asymmetric means an asymmetric shape, which is asymmetric if the shape is changed by mapping or rotation. The term rectangular means a closed planar quadrilateral having opposite sides of equal length and having four right angles. Non-rectangular means a closed geometric shape that is not rectangular. The term multiply-connected means an open set in a plane having holes therein. A shape is multiply connected if it has a hole (e.g., a donut shape) through it.

Detailed Description

Fig. 1 shows a reduced plan view of an example of an embodiment of a semiconductor wafer 30, wherein a plurality of semiconductor dies may be formed on the semiconductor wafer 30. The semiconductor dies on the wafer 30 may all have the same shape or may have different shapes. The dies are separated from each other by portions of the wafer 30 to be removed (e.g., singulation zones) in order to singulate each die. The singulation zone surrounds each die on the wafer 30 such that the singulation zone of the wafer 30 can be removed to singulate the die. As is known in the art, the plurality of semiconductor die on the wafer 30 are generally all separated from each other on all sides by the portions of the wafer 30 that form the singulation zones. The dies on wafer 30 may be formed as any type of semiconductor die, including diodes, vertical transistors, lateral transistors, or integrated circuits including various types of semiconductor devices.

As will be further appreciated below, the dies formed on the wafer 30 generally require the singulated regions of the wafer 30 as portions of the wafer 30 that do not extend axially or straight across the surface of the wafer 30. Those skilled in the art will appreciate that certain portions of the wafer 30 are shown in fig. 1 to have a singulation line that does extend across the wafer 30 in an axial direction, such as from one edge of the wafer to an opposite edge of the wafer 30. An example of this cut line is shown by line 31. Generally, in other embodiments, the wafer 30 may have singulation lines that extend in an axial direction across portions of the wafer 30 and terminate at the boundary of a singulation zone of the wafer 30, such as the singulation line 32 that terminates at the singulation zone as shown by the dashed lines 33 and 112, as will be further appreciated below. In other embodiments, the wafer 30 may not have any singulation lines extending axially across even a portion of the wafer 30.

Fig. 2 shows an enlarged plan view of an example of an embodiment of a plurality of dies having protrusions, such as dies 34-42, formed on the portion of the wafer identified by dashed line 33 in fig. 1 and 2.

The plan view or outer perimeter shape of the top surface of any of the dies 34-42 has a protrusion because at least one side of any of the dies has a protrusion or finger extending from the die. The outer perimeter, e.g., the top surface, of the plan view of any of the dies 34-42 is not only the active area of the die but also the actual perimeter of the die after the die is singulated. For example, die 35 is shown having right side edge 44, bottom edge 45, and top edge 46 each formed as a single straight line. However, the left side of the die 35 has a protrusion rather than a straight line. Thus, the perimeter of die 35 includes a plurality of sides that are not all the same size and dimension. The left side edge of die 35 includes a plurality of projections, such as projections or fingers 183, 184, and 185 that extend outwardly from the left innermost portion (e.g., edge 182) of die 35. Each of the projections or fingers forms a portion of the perimeter of the die 35 and each projection has sides that are a portion of the perimeter, such as sides 180 and 181 of projection 183. The projections form portions of the perimeter, such as edge 180, to project from other peripheral edges or portions (such as from edge 181 or 182). Thus, the die 35 has a protrusion extending outwardly along the perimeter of the die 35. Die 36 has similar protrusions 199, 200, and 201. As can be seen from fig. 2, the size of the die 35 has three or more values depending on where the size is measured. For example, there may be one value along the length of edge 44, but two or more values for the width, such as the width from edge 44 to edge 180 or the width from edge 44 to edge 182. Thus, the width has at least a maximum and a minimum.

Die 34 has a different shape than die 35, but also has protrusions, such as protrusions 196 and 197. In the embodiment shown in fig. 2, protrusion 196 of die 34 extends between protrusions 183 and 184 of die 35 and is positioned within the recess formed between protrusions 183 and 184 of die 35. The spatial or positional relationship between dies 34 and 35 is generally considered to be interdigitated.

Those skilled in the art will appreciate that any of the dies 34-42 is non-rectangular in that none of the dies 34-42 has the shape of the outer perimeter of a plan view of a die that is quadrilateral and has four (4) congruent angles.

Likewise, any of the dies 34-42 has an irregular shape because the outer peripheral shape of the top surface of the die prevents singulation of the dies by using an axial singulation line that extends axially between one of the dies 35-42 and an adjacent one of the dies 35-42. For example, an axial singulation line extending axially through a portion of wafer 30 intermediate dies 36 and 37 cannot be used to singulate die 36 because the outer perimeter of die 36 has protrusions and the portions of wafer 30 intermediate protrusions 200 and 201 of die 36 and the portions intermediate protrusions 199 and 200 cannot be removed by the axial singulation line. Thus, the irregular shape prevents singulation of any of the die 34-42 by using an axial singulation line.

In addition, any of dies 35-42 are considered to be arranged on wafer 30 in an irregular pattern because an axial singulation line extending through at least a portion of singulation zone 49 along an edge of one of dies 35-42 in an axial direction, e.g., parallel to edge 44 of die 35, will intersect an interior portion of an adjacent die, e.g., die 40. Thus, some dies 35-42 cannot be singulated from the wafer 30 using axial singulation lines extending in an axial direction across the portion of the wafer 30 including the die to be singulated, as an irregular pattern would result in such axial singulation lines traversing through the interior of at least one die. Thus, the singulation zone 49 surrounding the dies 35-42 does not form a continuous straight line extending in the axial direction across the portion of the wafer 30 where the dies 51-56 are located.

After the dies 34-42 are formed, portions of the wafer 30 surrounding the dies 36-42, such as the singulation zone 49, are simultaneously removed using a simultaneous singulation process to singulate the dies 36-42 into individual dies. The portion of the wafer 30 that may be generally removed is shown by cross-hatching 48. This type of cross-hatching is only used to show the portions of the wafer 30 that may be removed. Those skilled in the art will appreciate that not all of the area 49 should be removed for severing the die, but only the portion surrounding the outer periphery, as will be further appreciated below.

Because of the protrusions of the dies 34-42, either alternatively because of the irregular shape of the dies 34-42 or because of the irregular pattern of the dies 34-42, the singulation zone 49 surrounding the dies 34-42 does not form a continuous straight line that extends axially across the wafer 30 or even axially through the portion of the wafer 30 where the dies 34-42 are located. Such a continuous straight singulation zone would extend through portions of the dies 34-42 and damage the dies. Alternatively, a portion of wafer 30 would be left along one edge of the die, such as along protrusions 183, 184, and 185 of die 35, so as to have straight singulation lines. Such additional portions of wafer 30 would waste a portion of wafer 30 and reduce the number of dies that can be formed in a given area (e.g., on a given area of wafer 30). However, because a simultaneous singulation process is used to remove at least a portion of singulation zone 49, dies 34-42 may be arranged and positioned on wafer 30 in a configuration that maximizes the use of wafer 30 and increases the number of dies that can be formed on wafer 30.

To maximize the number of dies of this type that can be placed in a given area (e.g., the area of wafer 30), the dies may be arranged in interdigitated locations, such as shown by dies 39 and 40 or dies 37, 38, 41, and 42. As a result of the interdigitated location, the singulation zones 49 surrounding the die protrusions do not form a continuous straight line extending across the wafer 30 in the axial direction. A continuous straight singulation line extending only axially across the portion of the wafer 30 where the dies 34-42 are located would form a line extending from one edge of one die (e.g., along edge 44 of die 35) through a portion of the other die (e.g., through the interior of die 40) and damage the dies.

In addition, dies 34-42 are considered to be arranged on wafer 30 in a non-centered pattern because the center of a first die (e.g., the center of die 35) in the plurality of semiconductor dies is staggered relative to the center of an adjacent semiconductor die (e.g., the center of die 39 or die 40).

The simultaneous singulation process that simultaneously removes at least the portion of region 49 that is the singulation region typically includes the use of a dry etch, as described in U.S. published patent No.2009/0042366 by the inventor Gordon m. The use of a dry etch process to simultaneously singulate dies 34-42 allows for the formation of dies 34-42 having a bumped shape and/or having an irregular shape and/or forming dies 34-42 in an irregular pattern on wafer 30 and/or forming dies 34-42 in a non-central pattern on wafer 30. Other methods of simultaneously singulating dies from a wafer, such as dies 34-42, are described below with reference to fig. 11-22.

Those skilled in the art will appreciate that in some embodiments, region 49 may also have etch enhancement sections 67 that help to increase the etch rate when singulating the semiconductor die. Region 67 is the portion of region 49 that was not removed when dies 34-42 were singulated, and thus belongs to the portion of wafer 30 that was not removed. In certain embodiments, the sections 67 can increase the etch rate of equipment used to sever the dies 34-42. Segments 67 may be formed in any portion of region 49 where space exists between any of dies 34-42.

In an example configuration of dice 34-35, dice 34 and 35 have different shapes. The dies 34 and 35 may be singulated together. After singulation, the dies 34 and 35 may be assembled into a package and positioned in interdigitated locations within the package. Such interdigitated locations can be used to provide low inductance interconnection between two different types of die. In another example, two such dies may be formed on different wafers as two different types of dies (e.g., low power logic circuits and high power transistors). The close proximity of the dies will allow for the use of short interconnects to route interconnects from one die to another. This results in a low inductance connection that can improve the operating characteristics of the two dies.

Fig. 3 shows an enlarged plan view of an example of an embodiment of a plurality of non-rectangular shaped dies (e.g., dies 51-56 formed on the portion of wafer 30 identified by dashed line 50 in fig. 1 and 3). Any die 51-56 is non-rectangular in that the outer perimeter shape of the die in plan view is not a quadrilateral with four (4) congruent angles. In addition, the perimeter of any die 51-56 has at least one curvilinear shape rather than a perimeter formed by straight lines. Thus, the perimeter of any die 51-56 includes a plurality of sides, at least one of which includes a curved, rather than straight, portion. For example, die 54 is shown with side 205 being a straight line. Die 54 also has another edge 206 that includes a curved portion 207, generally identified by an arrow. Thus, the perimeter of the dies 51-56 has a non-rectangular shape and includes at least one side having a curvilinear shape.

Moreover, because die 51-55 form openings, such as holes or openings 58 and 61, through the die, the outer perimeter shape of any die 51-55 is also multiply connected. As used herein, multiply-connected means an open set in a plane having holes therein. Thus, any of the dies 51-55 are multiply connected in that they each have a hole through the die. For example, die 51 has two holes 58 and 59 of different sizes, and die 52 has two holes 61 of the same size. Thus, the die has a multi-connected topology.

After the dies 51-56 are formed, the portions of the wafer 30 surrounding the dies 51-56 are simultaneously removed to singulate the dies 51-56 into individual dies. Some portions of wafer 30 that may typically be removed are shown by cross-hatching 64. Due to the non-rectangular shape, the use of the simultaneous singulation process allows the dies 51-56 to be arranged and positioned on the wafer 30 in a configuration that maximizes the use of the wafer 30 and increases the number of dies that can be formed on the wafer 30. While the singulation process allows the holes through the dies 51-56 to also be formed during singulation. Those skilled in the art will appreciate that the opening formed by any of the dies 51-56 during singulation does not divide the die into pieces (e.g., cut the die in half) but forms an opening through a portion of the die, as shown, for example, in fig. 3, or it may form an opening along the edge of the perimeter of the die, as shown, for example, in fig. 6. Alternatively, the holes may be formed prior to singulation.

In one embodiment (but not necessarily all embodiments), to maximize the number of dies of this type that can be placed in a given area (e.g., the area of wafer 30), the dies may be staggered such that a narrow portion of one die may be positioned adjacent to a wide portion of an adjacent die. The staggered pattern and positioning of the dies 51-56 may cause one edge of one die to intersect an interior portion of at least one adjacent die when extended. For example, an elongated edge 208 of die 54 will cause edge 208 to intersect transversely into the interior of die 52. This staggered positioning can increase the number of non-rectangular shaped die that can be formed in a given area of wafer 30. Due to the staggered position, the singulation zone 65 surrounding the die does not form a continuous straight line extending in the axial direction across the wafer 30. A continuous straight singulation line extending axially across the portion of the wafer 30 where the dies 51-56 are located would form a line extending from one side of one die (e.g., along side 208 of die 54) through a portion of the other die (e.g., through the interior of die 52) and damage the dies.

The dice 51-56 also have an irregular shape because the outer peripheral shape of the dice prevents the dice from being singulated using an axial singulation line that extends axially between one of the dice 51-56 and an adjacent one of the dice 51-56. For example, an axial singulation line extending axially intermediate the dies 51 and 52 cannot be used to singulate the die 52 because a straight singulation line cannot remove a peripheral portion of the curve.

In addition, die 51-56 are considered to be arranged in an irregular pattern on wafer 30 because a singulation line along one edge of one of die 51-56 (e.g., parallel to edge 208 of die 54) would intersect the interior of an adjacent die (e.g., die 52). Thus, some dies 51-56 cannot be singulated from the wafer 30 using axial singulation lines that extend in the axial direction across the wafer 30 or across the portion of the wafer 30 where the dies 51-56 are located, as the irregular pattern will cause such singulation lines to traverse through at least one die. Thus, the singulation zone 65 surrounding the dies 51-56 does not form a continuous straight line extending in the axial direction across the portion of the wafer 30 where the dies 51-56 are located.

Those skilled in the art will appreciate that in some embodiments, region 65 may also have etch enhancement sections 68 that help to improve the etch rate when singulating the semiconductor die. Segment 68 is the portion of region 65 that was not removed when die 51-56 were singulated, similar to segment 67 of fig. 2, and is thus the portion of wafer 30 that was not removed. The segments 68 may be formed in any portion of the space between any of the dies 51-56 in the area 65.

Fig. 4 shows an enlarged plan view of an example of an embodiment (e.g., dies 86-91) having a plurality of dies with bumps formed on the portion of wafer 30 identified by dashed line 185 in fig. 1 and 4. The dies 86-91 have protrusions because at least one edge of the die's plan view perimeter has a protrusion or finger extending from the die. For example, die 88 is shown having top and bottom edges 211 and 212, each formed as a single straight line. However, the left and right sides of the perimeter of the die 88 have projections rather than each being a single straight line. Thus, the perimeter of the die 88 includes a plurality of sides that are not all of the same size and dimension. The left side edge of the die 88 includes a plurality of projections, such as projections or fingers 213 and 217 that extend outwardly from an innermost portion of the left side edge of the die 88, such as edge 216. The projections form portions of the perimeter, such as edge 214 of die 88, to extend from other surrounding or adjacent edges, such as edges 215 or 216. Each of the projections or fingers forms a portion of the perimeter of the die 88 and each projection has sides that are a portion of the perimeter, such as sides 214 and 215 of projection 213. The die 88 also has a similar protrusion on the right side edge of the die 88. Thus, the perimeter of any of the dies 86-91 includes a plurality of edges, at least one of which has a protrusion or finger extending from at least a portion of the die.

To maximize the number of dies of this type that can be placed in a given area (e.g., an area of wafer 30), the dies may be placed in interdigitated locations, such as shown by dies 88 and 89 and dies 88 and 90.

The die 86-91 are also considered to have an irregular shape because the top surface of the die or the outer perimeter shape of the plan view prevents cutting at least a portion of one of the die using an axial cut line extending axially between one of the die 86-91 and an adjacent one of the die 86-91. For example, an axial singulation line extending axially along the edge 214 of the die 88 will not remove portions of the wafer 30 adjacent to the edge 216 of the die 88. The irregular shape thus prevents singulation of any of the die 86-91 by using an axial singulation line.

In addition, die 86-91 are considered to be arranged on wafer 30 in an irregular pattern because a singulation line along one edge of one of die 86-91 (e.g., parallel to edge 214 of die 88) would intersect the interior of an adjacent die (e.g., die 86 or 89). Thus, some of the dies 86-91 cannot be singulated from the wafer 30 using axial singulation lines that extend in the axial direction across the wafer 30, or even the portion of the wafer 30 where the dies 86-91 are located, because the irregular pattern will cause such lateral singulation lines to traverse through at least one die. Thus, the singulation zone 94 surrounding the dies 86-91 does not form a continuous straight line extending in the axial direction across the wafer 30, or even the portion of the wafer 30 where the dies 86-91 are located. Those skilled in the art will also appreciate that any of the dies 86-91 are non-rectangular.

After the dies 86-91 are formed, the portions of the wafer 30 surrounding the dies 86-91 (e.g., the portions of the singulation zones 94) are simultaneously removed to singulate the dies 86-91 into individual dies. The portion of wafer 30 that is typically removed is shown by cross-hatching 93. The singulation zones 94 surrounding the projections of the die do not form a continuous straight line extending across the wafer 30 in the axial direction due to the interdigitated location. A continuous straight singulation line would form a line extending from one edge of one die (e.g., along edge 216 of die 88) through portions of die 88 and through other dies (e.g., through portions of die 91), and damage the dies.

Fig. 5 shows an enlarged plan view of an example of an embodiment of a plurality of multiply-connected die (e.g., die 99-102) formed on the portion of wafer 30 identified by dashed line 108 in fig. 1 and 5. The dies 99-102 are multiply connected in that the perimeter of the top surface of the dies 99-102 has holes through it. The dies 99-102 also have a non-rectangular shape because the outer perimeter of the top surfaces of the dies 71-74 is non-rectangular. A singulation zone 109 of the wafer 30 surrounds the periphery of each die 99-102. The dies 99-102 are shown as parallelograms having at least one opening or aperture through the die. In addition, the die 102 has openings 105 and 106 formed through the die 102. Because the openings 105 and 106 are different shapes, the die 102 is asymmetrical.

After the dies 99-102 are formed, portions of the wafer 30 surrounding the dies 99-102, such as portions of the singulation zone 109, are simultaneously removed to singulate the dies 99-102 into individual dies. The portion of the wafer 30 that is typically removed is shown by cross-hatching 108. Even if the sides of the dies 99-102 are straight, the sides do not intersect at right angles, and thus, the dies 99-102 are arranged in a staggered pattern relative to each other to maximize the number of dies that can be formed in a given area (e.g., on the surface of the wafer 30). The staggered pattern or positioning of the dies 99-102 may cause an edge of one die to intersect the interior of at least one adjacent die when elongated. For example, the elongated edges 209 of the die 99 will cause the edges 209 to intersect or traverse into the interior of the die 101. Due to the staggered pattern, the singulation zones 109 surrounding the dies 99-102 do not form a continuous straight line extending in an axial direction across the portion of the wafer 30 that includes the dies 99-102. A continuous linear singulation zone extending axially across the portion of the wafer 30 where the dies 99-102 are located will extend through the portion of the dies 99-102 and damage the dies. Alternatively, the distance between the dies, for example between the edges of dies 99 and 100, should be increased to allow a straight continuous singulation line to extend between the dies and this would reduce the number of dies that can be formed on the wafer.

In addition, the dies 99-102 are considered to be arranged in an irregular pattern on the wafer 30 because a singulation line along one edge of one of the dies 99-102 (e.g., parallel to the edge 209 of the die 99) would intersect the interior of an adjacent die (e.g., die 101). Thus, some of the dies 99-102 cannot be singulated from the wafer 30 using singulation lines extending axially across the portion of the wafer 30 that includes the dies 99-102, because an irregular pattern would cause the singulation lines to traverse through at least one of the dies. Thus, the singulation zone 109 surrounding the dies 99-102 does not form a continuous straight line extending axially across the wafer 30, or even across only the portion of the wafer 30 that includes the dies 99-102 (e.g., the area 109).

Because a simultaneous singulation process is used to remove the singulation zone 109, the dies 99-102 may be arranged and positioned on the wafer 30 in a configuration that maximizes the use of the wafer 30 and increases the number of dies that can be formed on the wafer 30.

After the dies 99-102 are singulated, the dies may be assembled with other dies, including positioning other dies within openings formed through any of the dies 99-102. For example, die 99 may be formed as a low power logic circuit of a control circuit, while another die may be formed as a high power device such as a power transistor. The power transistor may be positioned within an opening within the die 99 and the two dies can work together. Alternatively, the dies 99-102 may be power transistors and another type of die may be assembled within the opening of any of the dies 99-102. This enables the formation of very close and short interconnects thereby minimizing parasitic resistance and inductance in the connection. Alternatively, a heat sink may be assembled within the opening of the die 99 to help dissipate power generated during operation of the die 99. Alternatively, dielectric or metallic materials may be selectively assembled within the openings to improve device performance, such as to provide a heat sink or to provide direct and low resistance electrical connections from elements formed on the top surface of the die to elements formed on the bottom surface of the die.

Fig. 6 shows an enlarged plan view of an example of an embodiment of a plurality of irregularly-shaped dies (e.g., dies 71-74) formed over the portion of wafer 30 identified by dashed line 70 in fig. 1 and 6. Dies 71-74 also include a curvilinear shape along a portion of the outer perimeter of the top surface of the die. Instead of having the die 71-74 have an opening through the interior of the die 71-74 as does the die 99-102, the die 71-74 has a perimeter that includes a curved portion that may be used in the same application as the opening in the die 99-102. Due to the curved portions of the perimeter of the dies 71-74, the dies 71-74 cannot be singulated by a singulation line extending in an axial direction across the portion of the wafer 30 that includes the dies 71-74. The curved shape of die 71-74 prevents the use of axial singulation lines to remove portions of wafer 30 adjacent to the die. For example, portions of wafer 30 adjacent to edges 77 of die 71 cannot be removed by axial singulation lines. In addition, die 74 has an asymmetric shape because sides 75 are positioned such that the plan view of die 74 or the perimeter of the die top surface is asymmetric. Accordingly, singulation zone 80 is formed to surround the perimeter of dies 71-74 to facilitate singulation of dies 71-74 from wafer 30. The portion of wafer 30 that is typically removed is shown by cross-hatching 79. Due to the curved portion of the perimeter, the singulation zone 80 does not form a continuous straight line that extends in an axial direction across the wafer 30 or even across only the portion of the wafer 30 that includes the dies 71-74. Die 71-74 may be singulated as illustrated in the description of die 99-102.

Fig. 7 shows an enlarged plan view of an example of an embodiment of a plurality of dies 124 and 127 having a perimeter of a die top surface that is non-rectangular in shape. Die 124 and 127 are formed within the portion of wafer 30 identified by dashed line 123 in fig. 1 and 4. Die 124-127 is similar to dies 99-102 of fig. 5 and has the same die shape and similar positioning, except that die 124-127 is not multi-connected. Singulation zone 130 of wafer 30 surrounds the periphery of each die 124 and 127. The portion of the wafer 30 that is typically removed is shown by cross-hatching 129.

Because the sides of the dies 124-127 do not intersect at right angles, a line extending from either side of one of the dies 124-127 will traverse through the other of the dies 124-127. Because of this configuration, die 124-127 cannot be singulated using singulation lines that extend axially across wafer 30, or even the portion of wafer 30 where die 124-127 is located. Thus, the singulation zone 130 surrounding the die 124 and 127 does not form a continuous straight line extending in the axial direction across the portion of the wafer 30 where the die 124 and 127 are located or formed.

In addition, die 124 and 127 are considered to be arranged in an irregular pattern on wafer 30 because a singulation line along one edge of one of die 124 and 127 (e.g., parallel to edge 210 of die 124) would intersect an interior portion of an adjacent die (e.g., die 126). Thus, some of the dies 124-127 cannot be singulated from the wafer 30 using singulation lines that extend axially across the portion of the wafer 30 where the dies 124-127 are formed, because the irregular pattern will cause such singulation lines to traverse through at least one die. Thus, the singulation zone 130 surrounding the die 124 and 127 does not form a continuous straight line extending axially across the wafer 30. Those skilled in the art will appreciate that die 124-127 may be arranged on wafer 30 in different patterns that allow for the use of axial singulation lines to remove die 124-127.

Although die 124 and 127 are shown on wafer 30 in a non-centered pattern, the centers of die 124 and 127 may be aligned in a line or may be positioned non-centered. However, this configuration still prevents singulation of die 124 and 127 using axial singulation lines that extend axially across the portion of wafer 30 where die 124 and 127 are formed.

Fig. 8 shows an enlarged plan view of an example of an embodiment of a plurality of non-rectangular dies (e.g., die 113 and 116) formed on the portion of wafer 30 identified by dashed line 112 in fig. 1 and 8. The dies 113 and 116 are non-rectangular in that the perimeter of the top surface of either die 113 and 116 has a triangular shape rather than a rectangular shape. The singulation zone 119 of the wafer 30 surrounds the periphery of each die 113 and 116.

Although the sides of the die 113 and 116 are straight lines, the sides do not intersect at right angles. To maximize the number of dies of this type that can be placed in a given area (e.g., the area of wafer 30), the dies are arranged in a staggered pattern because the extension of one edge of one die will intersect an adjacent die. For example, extending the edge 117 of the die 114 will cause the extension to intersect the die 113. Also, the dies 114, 115 may be arranged to be non-centered such that centers of the dies 114, 115 along at least one direction are not aligned. For example, die 113 and 116 are shown with the centers of dies 114 and 116 aligned along a horizontal line. However, the centers of die 113 and 114 are not aligned along a vertical line, and a vertical line through the center of die 113 will traverse through die 114, although other die (not shown) of wafer 30 may be aligned along a vertical line with die 114. The singulation zone 119 surrounding the die 113 and 116 does not form a continuous straight line extending axially across the wafer 30 due to the non-rectangular shape or staggered pattern. The dies 114 and 116 are also considered to be positioned on the wafer 30 in an irregular pattern because axial singulation lines extending axially across the portion of the wafer 30 where the dies 113 and 116 are positioned or formed would extend through the interior of some of the dies 113 and 116 and damage the dies. Those skilled in the art will appreciate that the dies 113 and 116 may be arranged on the wafer 30 in different patterns that allow the use of axial singulation lines to remove the dies 113 and 116.

After the dies 113 and 116 are formed, the portion of the wafer 30 surrounding the dies 113 and 116, such as a portion of the singulation zone 119, is simultaneously removed using a dry etching process to singulate the dies 113 and 116 into individual dies. The removed portions of wafer 30 that are typically removed are shown by cross-hatching 118.

Previous die singulation approaches would require that the distance between the dies (e.g., between the edges of the dies 114 and 115) be increased to allow straight, continuous singulation lines to extend between the dies 114 and 115. Thus, the location or spatial layout of the die 114 and 116 improves wafer utilization and allows for an increase in the number of die formed on the wafer.

Fig. 9 shows an enlarged plan view of an example of an embodiment of a plurality of non-rectangular shaped dies (e.g., dies 136 and 142) formed on the portion of wafer 30 identified by dashed line 135 in fig. 1 and 8. The die 136 and 142 have a non-rectangular shape, such as an octagon, because the top surface or perimeter of the die 136 and 142 in plan view has a non-rectangular shape. The octagonal shape is an example of a non-rectangular shape and the die 136 and 142 can have other non-rectangular shapes. The singulation zone 145 of the wafer 30 surrounds the periphery of each die 136 and 142.

To maximize the number of non-rectangular shaped dies that can be disposed within a given area (e.g., the area of wafer 30), dies 136 and 142 are generally positioned on wafer 30 in an irregular pattern. In one example of an irregular pattern embodiment, the dies 136 and 142 are positioned such that the singulation zone 145 surrounding the dies 136 and 142 does not form a continuous straight line extending axially across the portion of the wafer 30 forming the dies 136 and 142.

Likewise, the die 136 and 142 have an irregular pattern because the outer perimeter shape of the die top surface prevents the die from being singulated using axial singulation lines that extend axially between one of the dies 35-42 and an adjacent one of the dies 35-42. For example, an axial singulation line extending axially through a portion of wafer 30 between die 136 and 137 cannot be used to singulate die 136 because the outer periphery of die 136 has an edge 143 that cannot be removed by the axial singulation line. As can be seen, the die 136 has other edges that also contribute to this irregular shape. Thus, the irregular shape prevents the use of an axial singulation line to singulate any of the dies 136 and 142. Thus, the irregular shape prevents the use of axial singulation lines to singulate the die 136 and 142.

In addition, either die 136 and 142 may be positioned in a non-centered position relative to the adjacent die by positioning one die such that the center of the die is not aligned with the adjacent die. Likewise, the dies 136 and 142 may be positioned on the wafer 30 in staggered positions relative to adjacent dies. Such a staggered pattern is typically used because this configuration can increase the number of polygonal-shaped dies that can be formed within a given area of wafer 30. Because of the staggered pattern, lines extending from either side of one of the dies 136, 142 will traverse through the other of the dies 136, 142. Because of this configuration, the dies 136-142 cannot be singulated using singulation lines that extend axially across the portion of the wafer 30 in which the dies 136-142 are formed. Thus, the singulation zone 145 surrounding the dies 136-142 does not form a connecting line extending in an axial direction across the portion of the wafer 30 where the dies 136-142 are formed.

In addition, any of the dies 136-142 is considered to be arranged in an irregular pattern on the wafer 30 because an axial scribe line along a side of one of the dies 136-142 (e.g., parallel to side 221 of die 136) would intersect an interior portion of an adjacent die (e.g., die 138). Thus, some of the dies 136-142 cannot be singulated from the wafer 30 using axial singulation lines that extend axially across the portion of the wafer 30 in which the dies 136-142 are formed. Thus, the singulation zone 145 surrounding the dies 136-142 does not form a continuous straight line extending axially across the wafer 30 or even across the portion of the wafer 30 where the dies 136-142 are formed.

In addition, any of the dies 136-142 is considered to be arranged in an irregular pattern on the wafer 30 because an axial singulation line extending axially along an edge of one of the dies 136-142 through at least a portion of the singulation zone 145 will intersect an interior portion of an adjacent die (e.g., die 40). Thus, some dies 35-42 cannot be singulated from the wafer 30 using axial singulation lines extending in an axial direction across the portion of the wafer 30 including the die to be singulated, as an irregular pattern would result in such axial singulation lines traversing through the interior of at least one die. Thus, the singulation zone 49 surrounding the dies 35-42 does not form a continuous straight line extending in the axial direction across the portion of the wafer 30 where the dies 51-56 are located.

After the dies 136, 142 are formed, the portion of the wafer 30 surrounding the dies 136, 142 (e.g., the singulation zone 145 portion) is simultaneously removed to singulate the dies 136, 142 into individual dies. The portion of the wafer 30 that is typically removed is shown by cross-hatching 144. Since a simultaneous singulation process is used to remove the singulation zone 145 or portions thereof, the dies 136 and 142 may be formed in the described shapes or arranged and positioned on the wafer 30 in the described configuration and maximize the use of the wafer 30 and increase the number of dies that can be formed on the wafer 30.

In prior singulation methods that formed straight singulation lines that extended axially across the wafer, the continuous straight singulation line could extend through portions of the dies 136 and 142 and damage the dies. For example, the continuous straight singulation line can form singulation lines that would extend from one side of one of the dies (e.g., along side 221 of wafer 136) through other die portions (e.g., through interior portions of die 138) and damage die 138. Alternatively, the distance between the dies, such as between the edges of dies 136 and 138, should be increased to allow straight, continuous singulation lines to extend between the dies to reduce the number of dies that can be formed on the wafer.

Fig. 10 shows an enlarged plan view of an example of an embodiment of a plurality of dies (e.g., die 151) formed on the portion of wafer 30 identified by dashed line 150 in fig. 1 and 9. Some of the dies, such as dies 156 and 157, have areas and distances near the periphery of the top surface of the dies that are larger than areas and distances near the periphery of the top surfaces of other dies (such as dies 151 and 154) of wafer 30. The singulation zone 160 of the wafer 30 surrounds the periphery of each die 151 and 157. For the example embodiment shown in fig. 10, the die 151 and 157 are shown as rectangular. Because the dies have different areas and perimeters, the dies are arranged in a staggered pattern with respect to each other to maximize the number of dies that can be formed in a given area (e.g., on the surface of wafer 30). Thus, the area of die 151 is not substantially equal to the area of either of die 154 or 156, and the area of die 154 is not substantially equal to the area of die 156. In addition, the dies 151-157 are considered to be arranged in an irregular pattern on the wafer 30 because singulation lines along one side of one of the dies 151-157 (e.g., parallel to the side 219 of the die 154) would intersect the interior portions of adjacent dies (e.g., the dies 152 and 156). Thus, none of the dies 151-153 or 154-155 or 156-157 can be singulated from the wafer 30 using axial singulation lines that extend axially across the portion of the wafer 30 in which the dies 151-157 are formed, as such axial singulation lines would traverse through at least one of the dies. Thus, the singulation zone 160 surrounding the dies 151-157 does not form a continuous straight line extending in the axial direction across the wafer 30 or even across the portion of the wafer 30 where the dies 151-157 are formed.

Because a simultaneous singulation process is used to remove at least a portion of the singulation zone 160, the dies 151 and 157 may be arranged and positioned on the wafer 30 in a staggered configuration or irregular pattern that maximizes the use of the wafer 30 and increases the number of multi-sized dies that can be formed on the wafer 30.

Those skilled in the art will appreciate that at least two different die sizes, e.g., die having areas like die 153 and 155, and that only one die may have an area different from the area of the other die on wafer 30. In some embodiments, different sized dies are singulated from the wafer 30, wherein the perimeters of the first and second semiconductor dies have the same shape, e.g., rectangular, and wherein both the first and second semiconductor dies are singulated from the wafer 30 into two intact dies. In other embodiments, one of the different sized dies may be a test structure formed on wafer 30 to test process parameters or other parameters during a manufacturing operation. For this embodiment, the dies of the test structure may not be singulated from wafer 30.

Fig. 11 shows an enlarged cross-sectional portion of the wafer 30 of fig. 1 and 2 taken along section line 2-2. This section line 2-2 is shown only across die 36 and a portion of dies 35 and 37 for clarity of the drawing and description. Semiconductor dies 35-37 generally include a semiconductor substrate 318 that may have doped regions formed within substrate 318 to form active and passive portions of the semiconductor die. The cross-sectional portion shown in fig. 11 is taken along contact pads 324 of each die 35-37. Contact pads 324 are generally metal formed on the semiconductor die to provide electrical contact between the semiconductor die and elements external to the semiconductor die. For example, contact pads 324 may be formed to receive bonding wires that may be subsequently attached to pads 324 or may be formed to receive solder balls or other types of interconnect structures that may be subsequently attached to pads 324. Substrate 318 may include a bulk substrate 319 having an epitaxial layer 320 formed on a surface of bulk substrate 319. A portion of epitaxial layer 320 may be doped to form doped regions 321 that are used to form active and passive portions of semiconductor die 35, 36, or 37. Layer 320 and/or region 321 may be omitted in some embodiments or may be within other regions of die 35, 36, or 37.

Typically, a dielectric 323 is formed on the top surface of substrate 318 in order to isolate pads 324 from other portions of a single semiconductor die and to isolate each pad 324 from adjacent semiconductor dies. Dielectric 323 is typically a thin layer of silicon dioxide formed on the surface of substrate 318. Contact pads 324 are typically metal, with a portion of contact pads 324 in electrical contact with substrate 318 and another portion formed on a portion of dielectric 323. After the formation of die 35-37, including the metal contacts and any associated interlayer dielectrics (not shown), dielectric 326 is formed over all of the plurality of semiconductor die to function as a passivation layer for wafer 30 and each individual semiconductor die 35-37. Dielectric 326 is typically formed over the entire surface of wafer 30 by, for example, blanket dielectric deposition (blanket dielectric deposition). The thickness of dielectric 326 is generally greater than the thickness of dielectric 323.

After forming dielectric 326, a singulation mask is formed to facilitate forming openings through substrate 318 without etching the underlying layers (e.g., portions of dielectric 326). In a preferred embodiment, the singulation mask is formed of aluminum nitride (AlN). In the preferred embodiment, an AlN layer 391 is formed over at least dielectric 326. Layer 391 is typically applied to cover the entire wafer 30.

Fig. 12 shows a cross-sectional portion of wafer 30 at a subsequent stage in fig. 11 in an example of a preferred embodiment of a method of singulating irregularly shaped die (e.g., singulating die 35-37 from wafer 30). After AlN layer 391 is formed, mask 332 may be applied to the surface of substrate 318 and patterned to form openings that expose portions of dielectric 326 covering each pad 324 and also portions of wafer 30 where singulation regions (e.g., singulation regions 49) are to be formed.

To form mask 332, a photolithographic masking material is applied to wafer 30 and then exposed to light, such as ultraviolet light, to change the chemical composition of the masking material of the exposed portions to form mask 332 with openings that cover where scribe lines are to be formed and also where pads 324 are to be formed. A developer solution is then used to remove the unexposed portions of the mask material thereby leaving mask 332 with openings 328 and 329 covering the locations where the respective singulation regions (e.g., singulation regions 49) are to be formed. Those skilled in the art will appreciate that openings 328 and 329 are typically two portions of a single opening that surrounds dies 35-37 but are shown as two openings due to the cross-sectional view. It has been found that the use of an ammonium hydroxide based developer solution also results in the developer solution removing the portions of the AlN layer 391 underlying the mask material of the unexposed portions. The removed portion of layer 391 is shown by dashed line 92, while the remaining portion of layer 391 is identified as AlN 393. AlN393 acts as a singulation mask, as will be further understood below.

Fig. 13 shows a cross-sectional portion of wafer 30 in fig. 12 at another subsequent stage in an example of an alternative embodiment of a method of singulating dies 35-37 from wafer 30. Dielectric 326 and 323 are etched through mask 332 and the openings of AlN393 to expose the underlying surfaces of substrate 318 and pad 324. The openings formed in the regions where the singulation regions (e.g., region 49) are to be formed by AlN393 and dielectrics 326 and 323 function as singulation openings 328 and 329. The opening formed over pad 324 by dielectric 326 functions as a contact opening. The etching process is preferably performed by a process that etches the dielectric selectively faster than the metal. The etching process typically etches the dielectric at least ten (10) times faster than it etches the metal. Metal pad 324 acts as an etch stop layer that prevents the etch from removing the exposed portion of pad 324. In a preferred embodiment, a fluorine-based anisotropic reactive ion etching process is used, as explained above.

After forming the openings through dielectrics 326 and 323, mask 332, shown by the dashed lines, is typically removed. Subsequently, the substrate 318 is generally thinned to remove material from the bottom surface of the substrate 318 and reduce the thickness of the substrate 318 as shown by the dashed line 386. Generally, the substrate 318 is thinned to a thickness of no greater than about 25 to 400(25-400) microns and preferably between about 50 to 250(50-250) microns. Such thinning processes are well known to those skilled in the art. After thinning the wafer 30, the back side of the wafer 30 may be metallized to have a metal layer 327. This metallization step may be omitted in some embodiments. Thereafter, the wafer 30 is typically attached to a conveyor or carrier tape 330 that conveniently supports the plurality of dies after they are singulated. In some embodiments, the carrier tape 330 may be omitted or replaced with a different carrier device.

Fig. 14 shows wafer 30 at a subsequent stage in an example embodiment of an alternative method of singulating semiconductor die 35-37 from wafer 30. AlN393 is used as a mask to etch substrate 318 by singulating openings 328 and 329. AlN393 protects dielectric 326 from etching. AlN393 may have a thickness of approximately 50 to 300(50-300) angstroms and still protect dielectric 326. Preferably, AlN393 is about 200(200) angstroms thick. The etching process extends singulation openings 28 and 29 completely through substrate 318 from the top surface of substrate 318 to remove singulation regions 49 from wafer 30 and singulate die 35-37. The etching process is typically performed using a chemical reaction that selectively etches silicon at a much higher rate than the dielectric or metal. The etching process typically etches silicon at least fifty (50) times and preferably one hundred (100) times faster than it etches a dielectric or metal. Typically, a deep reactive ion etching system using a combination of isotropic and anisotropic etching conditions is used to etch openings 328 and 329 from the top surface of substrate 318, e.g., surface 11 of die 36, completely through the bottom surface of substrate 318 to form singulation zone 49. In a preferred embodiment, a process commonly referred to as the Bosch process is used to anisotropically etch the sliced single openings 28 and 29 through the substrate 18. In one example, wafer 30 is etched in a Bosch process within an Alcatel deep reactive ion etch system.

The width of the singulation openings 328 and 329 is typically 5 to 10(5-10) microns. The width is sufficient to ensure that openings 328 and 329 can be formed completely through substrate 318 and is sufficiently narrow to form openings in a short time interval. Typically, openings 328 and 329 can be made to extend through substrate 318 like opening 49 within a time interval of about 15 to 30(15-30) minutes. Since all the singulation zones of the wafer 30 are formed simultaneously, all the singulation zones can be formed across the wafer 30 within the same time interval of about 15 to 30(15-30) minutes.

Thereafter, the dies of wafer 30 may be supported by carrier tape 330 while the dies are transferred to a subsequent assembly operation.

Because AlN393 is a dielectric, it may remain on die 35-37. In other embodiments, AlN393 may be removed after etching through substrate 318 by using, for example, a developer solution; however, this requires additional processing steps. Using a photomask developer to remove the exposed portion of layer 391 saves processing steps and thus reduces manufacturing costs. Using AlN393 as a mask protects dielectric 326 from the etching operation.

In other embodiments, the singulation mask may be formed of other materials than AlN. Other materials for the singulation mask are those that are not substantially etched by the process used to etch the silicon substrate 318. Since the etching process used to etch the substrate 318 etches silicon faster than metal, metal compounds can be used as the material to form the singulation mask. Examples of such metal compounds include: AlN, titanium nitride, titanium oxide, titanium oxynitride, and other metal compounds. In examples where a metal compound other than AlN is used, a layer of the metal compound can be similarly applied to the layer 391. The mask 332 may be used to pattern the metal compound layer to form openings within the metal compound. Thereafter, the mask 332 may be removed and the remaining portion of the metal compound can protect underlying layers, such as dielectric 326, during etching of the substrate 318. The metal compound may be left on the die after singulation or may be removed before singulation is completed (e.g., before the die is separated from the carrier tape 330).

In addition, silicon-metal compounds may also be used to form the singulation mask because the metal in the metal-silicon compound prevents the etch from proceeding into the metal-silicon material. Some examples of silicon-metal compounds include metal silicides, such as titanium silicide and cobalt silicide. For the silicon-metal compound embodiment, the layer of silicon-metal compound may be formed and patterned similarly to the metal compound example. However, the metal-silicon compound is typically a conductor, so it should be removed from the die, for example, before the die from the carrier tape 330 is completely singulated.

Likewise, the polymer may be used to singulate the mask. One example of a suitable polymer is polyimide. Other well known polymers may also be used. The polymer may be patterned similarly to the metal compound and may then be removed or left on the die.

Fig. 15 shows a stage of an example of an embodiment of an alternative method of singulating irregularly shaped semiconductor dies (e.g., dies 35-37) from a semiconductor wafer (e.g., wafer 30). The singulation process forms angled sidewalls on the singulated die. The stage shown in fig. 15 begins after the formation of openings 328-329 (as explained in the description with respect to fig. 12). AlN393 is used as a mask to etch substrate 318 through singulation openings 328 and 329 and to remove singulation regions 49 from wafer 30. After exposing the surface of the substrate 318, the substrate 318 and any exposed pads 324 are etched by an isotropic etch process that selectively etches silicon at a higher rate (typically up to at least fifty (50) times and preferably at least one hundred (100) times faster) than etching the dielectric or metal. Typically, a downstream etcher with a fluorine chemistry is used for etching. For example, wafer 30 may be etched in an Alcatel deep reactive ion etch system using a fully isotropic etch. An etch process is performed to extend openings 328 and 329 into substrate 318 to a depth that laterally expands the opening width while also extending the depth to form opening 400 in substrate 318. Because the process is used to form angled or sloped sidewalls of dies 35-37, multiple isotropic etches will be used to successively increase the width of openings 328 and 329 as the opening depth extends into substrate 318. After the width of opening 400 is greater than the width of openings 328 and 329 at surface 11 of die 36 and substrate 318, the isotropic etch is terminated.

Thereafter, carbon-based polymer 401 is applied to the portion of substrate 318 exposed within opening 400.

Fig. 16 shows a stage following the stage explained in the description of fig. 15. An anisotropic etch is used to remove the portion of polymer 401 at the bottom of opening 400 while leaving the portion of polymer 401 on the sidewalls of opening 400.

Fig. 17 shows a stage following the stage explained in the description of fig. 16. The exposed surface of the substrate 318 within the opening 400, as well as any exposed pads 324, are etched by an isotropic etching process similar to that described in the explanation of fig. 15. The isotropic etch laterally extends the width of the singulation openings 328 and 329 again while also extending the depth to form the opening 404 in the substrate 318. The isotropic etch typically terminates after the width of opening 404 is greater than the width of opening 400 so that the width of the opening becomes wider as the depth increases. The portion of polymer 401 left on the sidewalls of opening 400 protects the sidewalls of opening 400 to prevent the etching of opening 404 from affecting the width of opening 400. Typically, substantially all of polymer 401 is removed from the sidewalls of opening 400 during the etching of opening 404.

Thereafter, a carbon-based polymer 405, similar to polymer 401, is applied to the exposed portion of substrate 318 within opening 404. During the formation of polymer 405, the operation typically again forms polymer 401 on the sidewalls of opening 400.

Fig. 18 shows a stage following the stage explained in the description of fig. 17. An anisotropic etch is used to remove the portion of polymer 405 within opening 404 while leaving a portion of polymer 405 on the sidewalls of opening 404. The process steps are similar to those explained in the description of fig. 16.

Fig. 19 shows that the sequence may be repeated until singulation zones 49 are formed to extend completely through substrate 318. The sequence of anisotropic etches that form the openings (e.g., openings 408 and 412), forming a polymer (e.g., polymer 409) on the sidewalls of the openings, and removing the polymer at the bottom of the openings while leaving a portion of the polymer (e.g., polymer 409) on the sidewalls can be repeated until openings 328 and 329 extend through substrate 318 to remove singulation regions 49 from substrate 30.

After the final isotropic etch (e.g., the etch that forms opening 412), no polymer is typically deposited because a polymer is generally not needed to protect substrate 318 during subsequent operations. Although polymers 401, 405, and 409 are shown on the sidewalls of respective openings 400, 404, and 408, one skilled in the art will appreciate that after all operations are completed, the final isotropic etching step, such as the etching that forms opening 412, substantially removes these polymers from the sidewalls of the corresponding openings. Thus, these polymers are shown for clarity of explanation only.

As can be seen in fig. 19, sidewalls 336 of die 35 and sidewalls 335 and 337 of dies 35 and 37, respectively, slope inward from top surface 11 to the bottom such that the width of the die at the bottom of each die is less than the width of the die at the top of the die. Thus, the outer edge of the die on the top of the substrate 318 extends a distance 316 past the outer edge of the die on the top of the substrate 318 such that the outer edge of the die 35 overhangs the bottom surface by the distance 316. It is believed that distance 316 should be about 5 to 10% (5-10%) of the thickness of die 35-37. In one example embodiment, distance 316 is about 1 to 5(1-5) microns, and thus the width of the bottom of die 35 at the bottom of substrate 318 can be about 2 to 10(2-10) microns less than the width of the top of die 35 at surface 11. Typically, the top of the opening of the singulation zone 49 is about 2 to 40(2-40) microns narrower than the bottom of the opening of the singulation zone 49. In another embodiment, it is believed that the sidewalls 336 should form an angle 417 of about 15 to 40 degrees (15 ° -40 °) between the sidewalls 336 and a vertical line (e.g., a line perpendicular to the top surface of the substrate 318). Thus, the amount of width of the opening 329 expanded per etch should be sufficient to form the corner 417. Those skilled in the art will appreciate that the multiple anisotropic etching operations form the rough sidewalls of each die 35-37 such that the sidewalls have serrated edges along the sidewalls. However, the extent of the jagged edges is exaggerated in the diagrams of FIGS. 15-19 for clarity of explanation. These sidewalls are generally considered to be substantially smooth sidewalls.

Those skilled in the art will appreciate that in an alternative embodiment of the method of singulating die 35-37, the singulation mask layer may be omitted. In this case, the isotropic and/or anisotropic etch process uses an etch that etches silicon faster than dielectric or metal, and thus, dielectric 326 provides protection to the underlying portions of each die 35-37. See U.S. patent publication No.2009/0042366 to Gordon m.grivna, published on 12.2.2009.

Fig. 20 shows a stage of an example embodiment of another alternative method of singulating irregular semiconductor dies (e.g., 35-37) from a semiconductor wafer (e.g., wafer 30). Fig. 20 shows an enlarged cross-sectional portion of dies 35-37 at a stage of fabrication after dielectric 323 is formed over the top surface of substrate 318 and before pads 324 (fig. 11) are formed. For the example singulation method shown in fig. 20, the dies 35-37 have a single isolation trench 379 that surrounds each die on the wafer 30. As will be further appreciated below, trench 379 will be used to form singulation regions 49 and to remove regions 49 from wafer 30.

A trench 379 is formed as an opening within the substrate 30 and a dielectric liner 380 is formed on the sidewalls and bottom of the opening. The dielectric liner is typically a dielectric material such as silicon dioxide. The remainder of the opening is typically filled with a fill material 381. In a preferred embodiment, the bottom of the dielectric liner 380 is removed so that the bottom of the trench 379 is open, as shown by the dashed line 384. One example method of removing the bottom of the liner 380 includes applying a mask 385 having an opening that exposes the trench 379 and performing an isotropic etch, such as a spacer etch, that etches through the bottom of the liner 380. The etch may preferentially etch the dielectric relative to silicon so as to prevent damage to the portion of the substrate 318 under the trench 379. Mask 385 is typically removed after the bottom of liner 380 is removed. After the bottom of the trench 379 is removed, the remaining opening of the trench 379 is filled with a fill material 381. The fill material 381 is typically a silicon-based material, such as polysilicon, to facilitate subsequent processing steps, as will be further appreciated.

Those skilled in the art will recognize that any of dies 35-37 may likewise have other trenches internal to the die, such as trench 378, and that these trenches may be formed using similar process operations to those used to form trench 379. The trenches 378 may leave the bottom oxide or have the bottom oxide removed, depending on the role the bottom oxide is to play. For example, trench 378 may be filled with doped polysilicon and provide a low resistance substrate contact or backside contact, for example to metal layer 327 (not shown in fig. 20) or to another contact on the bottom or backside of substrate 318. However, the preferred embodiment of groove 378 does not have the bottom removed and groove 378 is preferably internal to the die and does not surround the outer perimeter of the die. Thus, the trench 379 may be formed simultaneously with the trench 378 or other similar trenches, thereby reducing manufacturing costs. Those skilled in the art will appreciate that the dies 35-37 may have various active and/or passive components formed on or within the substrate 318.

Trench 379 is formed within singulation zone 49 and preferably in the middle of the singulation zone such that at any point of zone 49, the middle of trench 379 is approximately in the middle of zone 49, e.g., at a point midway between two dies. As will be further appreciated below, singulation will occur approximately through the middle of the trench 379.

Fig. 21 shows wafer 30 at a subsequent stage in an example method of singulating semiconductor dies 35-37 from wafer 30. After trench 379 is formed, other portions of die 35-37 are formed, including forming contact pads 324 and forming dielectric 326 overlying die 35-37. Dielectric 326 typically also covers other portions of wafer 30, including the portions of substrate 318 where singulation zones (e.g., areas 49) are to be formed. Thereafter, a mask 387 is applied and patterned to expose the underlying dielectric 326 where the singulation regions 49 and contact openings are to be formed. Mask 387 is similar to mask 332 shown in fig. 12; however, the mask 387 typically has a slightly different position. The opening in mask 387 where the singulation region 49 is to be formed also covers the trench 379. Dielectric 326 is etched through openings in mask 387 to expose underlying fill material 381 within trenches 379. The etch also typically exposes the underlying pads 324. The openings formed by dielectric 326 in the areas where the singulation regions (e.g., area 49) are to be formed function as singulation openings 382 and 383. The etching process used to form openings 382 and 383 through dielectric 326 is generally the same as the process used to form openings 328 and 329 (fig. 12) in dielectrics 323 and 326. Openings 382 and 383 are typically formed such that dielectric liner 380 on the sidewalls of corresponding trench 379 underlies openings 382 and 383, although dielectric liner 380 need not be exposed so long as material 381 is exposed. Those skilled in the art will appreciate that openings 382 and 383 are typically two portions of a single opening surrounding die 35-37 but are shown as two openings due to the cross-sectional view.

After openings 382 and 383 are formed through dielectrics 326 and 323, mask 387 is removed, as shown by dashed lines, and substrate 318 is thinned, as shown by dashed lines 386. Thinning removes most of substrate 318 under trench 379. The substrate 318 is not generally thinned all the way to the bottom of the trench 379 because the dielectric material of the dielectric liner 380 may damage the tools used to thin the wafer 30 or may cause scratching of the wafer 30. Preferably, the substrate 318 is thinned until the trench 379 is about 2 to 5(2-5) microns from the bottom to the substrate 318. In some embodiments, the substrate 318 may be thinned until the bottom of the trench 379 is exposed. Thereafter, the bottom surface of the substrate 318 may be metallized with a metal layer 327, as explained above in the description of fig. 13. This metallization step may be omitted in some embodiments. Subsequently, the wafers 30 are typically attached to a common carrier substrate or a common carrier, such as the carrier tape 330.

Fig. 22 shows wafer 30 at a subsequent stage in an example of an embodiment of an alternative method of singulating dies 35-37 from wafer 30. A second opening is formed through fill material 381 to form region 49 as an opening through substrate 318. Substrate 318 is preferably etched by singulating openings 382 and 383 using dielectric 326 as a mask. The etching process is typically performed using a chemical reaction that selectively etches silicon at a much faster rate than etching a dielectric or metal, similar to the etching explained in the description of fig. 14. The etching process forms an opening through material 381. Typically, the etch removes substantially all of material 381 to extend singulation regions 49 completely through fill material 381 of trenches 379 from the top surface of substrate 318 and remove regions 49 from wafer 30. Since the etching step is a selective etch of silicon over dielectric, fill material 381 is removed without etching the dielectric liner 380 on the sidewalls of the trench 379. Thus, the dielectric liner 380 on the sidewalls of the trench 379 protects the silicon of the substrate 318 from isotropic etching. Isotropic etching has a much higher etch yield than can be achieved by using the BOSCH process or by using the BOSCH process with limitations. An isotropic etch process etches through fill material 381 and any portion of substrate 318 beneath trench 379. Thus, the isotropic etch quickly etches through the trench 379 and any underlying portions of the substrate 318, thereby singulating the dies 35-37. Fast etching increases throughput and reduces production costs. It will be appreciated by those skilled in the art that the fill material 381 of silicon-based material also reduces stress on the dielectric liner 380 and the material of the substrate 319.

Singulation of die 35-37 along singulation region 49 through trench 379 results in the singulation region occupying very little space of the semiconductor wafer. For example, the width of trench 379, including fill material 381, is typically only about three (3) microns wide. Thus, the singulation zone 49 may be only about 3 microns wide rather than 100 microns wide in other methods of singulating dies (e.g., dicing or wafer sawing). It will be apparent to those skilled in the art that the step of thinning wafer 30 may be omitted and the etching of material 381 may continue until openings 382 and 383 are extended through wafer 30.

Those skilled in the art will appreciate that layer 391 and AlN393 may be used as a singulation mask, as described in the explanation of fig. 10-13.

Fig. 23 shows an enlarged plan view of an example of an embodiment of a plurality of non-rectangular shaped dies (e.g., dies 233, 237, and 241) formed on the portion of wafer 30 identified by dashed line 230 in fig. 1 and 23. The dies 233, 237, and 241 have corners that do not meet at right angles. Die 233 has corners 234 formed as diagonal corners (diagonals) having straight lines running diagonally from side 236 to side 231. Thus, the corner is a diagonal corner rather than a right angle. The diagonally opposite portion of corner 234 may be used as an alignment key (alignment key) for die 233 to determine corner 234 from the right angle of corner 235. The alignment key facilitates orienting the die 233 during manufacturing operations to attach the die 233 to a substrate or package.

Die 237 has corners 238 forming right angles and corners 239 having a curvilinear shape. The curved shape reduces stress at the corners and thus improves reliability of the die 237 over a die having right angle corners. In some embodiments, since corner 239 is different than corner 238, corner 239 may also be used as an alignment key. Although the corner 239 is shown as a convex curve shape, the corner 239 may have any type of curved shape.

The die 241 forms all corners 242 into a curvilinear shape. The curved shape reduces stress and improves reliability of the die 241.

Those skilled in the art will appreciate that the dies 233 and 237 are formed as dies having one corner (e.g., corners 234 and 239) that is shaped differently than other corners of the dies. The shape of corners 234 and 239 are used to illustrate examples of different corner shapes that may be used, however, the corner shapes are not limited to diagonally-angled curves and any corner may be different from any other corner of the die in order to form an alignment key that identifies one corner of the die. Additionally, the other corners (e.g., corner 235) need not be right angles but can be any shape other than the identified corner, such as corner 234.

In addition to being non-rectangular, the die 237 and 241 have a singulated die with an outer perimeter having a shape that includes at least one curvilinear segment.

Those skilled in the art will appreciate that the explanations included herein teach those skilled in the art a method of forming a semiconductor die, including: the perimeter of the top surface of a semiconductor die, such as one of any of the dies of fig. 2-10 and 23, has a shape that is one of non-rectangular, multiply connected, has a protrusion extending outwardly along the perimeter, is asymmetrically shaped, or has at least one curvilinear portion.

One skilled in the art will also appreciate that the non-rectangular shape may include one of a triangular shape, a parallelogram shape, a shape with protrusions extending outwardly along the perimeter, a multiply connected shape, or a shape in which a portion of the perimeter has a curvilinear shape.

Those skilled in the art will also appreciate that the semiconductor die may have one corner shaped differently from the other corners, such as illustrated by die 233, or the semiconductor die may have at least one corner having a curved shape, such as illustrated by die 237 or 241.

Those skilled in the art will also appreciate that a method of forming a semiconductor die may include forming a plurality of semiconductor die on a top surface of a semiconductor wafer, wherein two or more of the plurality of semiconductor die have a perimeter that is one of a non-rectangular shape, a shape having at least one protrusion along the perimeter, a multiply connected shape, a shape having at least one curvilinear portion, an asymmetrical shape, different values of distance around the perimeter (such as shown by die 34-42151 and 157), or an irregular shape (such as shown by die 34-42, 51-56, 86-91, 71-74136 and 142), wherein the irregular shape prevents singulation of the irregular shape using singulation lines extending axially across the semiconductor wafer; forming singulation regions as regions of the semiconductor wafer between the semiconductor dies; and simultaneously singulating the plurality of semiconductor dies using dry etching.

Those skilled in the art will also appreciate that the method of forming a semiconductor die may comprise forming a plurality of semiconductor die on a top surface of a semiconductor wafer, wherein at least two semiconductor die of the plurality of semiconductor die are arranged in an irregular pattern such that singulation of the plurality of semiconductor die using axial singulation lines extending only axially across portions of the semiconductor wafer in which the plurality of semiconductor die are formed is prevented, for example, a pattern formed by die 151-15734-4251-5686-9199-127124-115136-142; and simultaneously singulating the plurality of semiconductor dies using dry etching.

Fig. 24 shows a plan view of an embodiment of an example of a semiconductor device 500 including a semiconductor die 504.

Fig. 25 illustrates a cross-sectional view of device 500 along section line 25-25 of fig. 24. The description refers to fig. 24 and 25. The die 504 is formed to have a socket 506 for receiving another element 510. The element 510 may be another active electrical element, such as a semiconductor die, or an active electrical element not formed on a semiconductor substrate, such as a gallium nitride light emitting diode, or a passive electrical element, such as a resistor, capacitor, inductor, or may be another type of element, such as a heat sink, mold lock or alignment pin or key that improves power dissipation of the die 504, or other type of orientation element. For example, the die 504 may be paired with a package or other device having alignment pins or orientation elements that allow the die 504 to be in only one orientation suitable for the mating device.

In one example, element 510 may be a semiconductor die and socket 506 may be an opening through die 504. For this embodiment, the element 510 along with the die 504 may be packaged within a semiconductor package 501, such as a package having a plastic package. Package 501 may include a lead frame having a plurality of connection terminals and a plurality of leads 520 and 523. Some of the leads 520 and 523, such as leads 520 and 522, may be electrically connected to die 504 and other leads, such as leads 521 and 523, may be electrically connected to the semiconductor die of element 510. The leadframe of the package 501 may also include a flag 527 to which the die 504 may be attached and another flag 528 to which the semiconductor die of the element 510 may be attached. In another embodiment, the die 504 and the semiconductor die of the element 510 may be attached to a flag as shown by the dashed line in fig. 25. The electrical connections between the leads 520-523, the die 504, and the element 510 may be any type of connection known in the art, such as wire bonds, wire clips, cable bonds, and the like. Element 510 generally includes connection pads, such as pad 512, that facilitate forming an electrical connection with element 510.

Fig. 26 shows a plan view of an embodiment of an example of a semiconductor device 550 that is an alternative embodiment of the device 500 of fig. 24. For this embodiment, the die 504 has an element 546 in the socket 506. Element 546 may be similar to element 510. In this embodiment, element 546 is a semiconductor die that includes connection pads 547 that facilitate forming electrical connections to element 546. Element 546 may be electrically connected to die 504 rather than to leads 521 and 523 as shown in fig. 24. In other embodiments, the element 510 or 546 may have some connections to the die 504 and other connections to some of the leads 520 and 523. Element 546 is similar to element 510.

Positioning the semiconductor die of the example embodiment of element 510 or 546 within socket 506 facilitates placing two different types of semiconductor die within one package. The arrangement of elements 546 facilitates the formation of short electrical connections between two semiconductor dies that cannot normally be formed on one semiconductor substrate. Such as a silicon semiconductor die and a gallium arsenide die, or a power semiconductor die and a logic semiconductor die for controlling the power semiconductor.

Those skilled in the art will appreciate that although the die 504 is shown as a rectangular multiply-connected die, the die 504 may be any of the dies explained in the description of fig. 2-10 and 23. Likewise, the socket 506 may be any protrusion or curvilinear shape of the opening or die perimeter of a multi-connected die similar to those explained in the description of fig. 2-6.

Fig. 27 shows a plan view of a portion of another embodiment that may be used for devices 500 and 550. Fig. 27 includes dies 34 and 35 (see fig. 2), where one of the dies 34 or 35 may represent a die 504 having a socket for receiving the other of the dies 34 or 35. For example, the die 34 may represent a die 504 having a die 35 with protrusions that form sockets for receiving the die 34. The dies 34 and 35 may be interconnected together as explained in the description of fig. 26 (e.g., as shown by connections 495) or may be connected to leads as explained in the description of fig. 25 or may be connected in conjunction with both connection configurations.

Fig. 28 shows an enlarged plan view of a die 534 with multiple connections through an opening 535 of the die 534. The opening 535 is positioned to isolate a high frequency portion 536 of the die 534 from the remainder of the die 534. The silicon removed from the openings 535 can range from a minimum dielectric constant of about 11.7 for conductive silicon (e.g., doped silicon) to intrinsic silicon. By removing silicon from the openings 535, the dielectric constant (e.g., between the protrusions of the die 534 on opposite sides of the openings 535) can be drastically reduced to approximately 1.0, which is the dielectric constant of air or vacuum. A separate portion 536 of lower dielectric material from the remainder of the die 534 can be used to minimize capacitive or inductive coupling between the regions.

In view of the explanation herein, one skilled in the art will appreciate that one example of a method of forming a semiconductor device may include providing a first semiconductor die (e.g., die 504) having a socket (e.g., example socket 506) for receiving a second semiconductor die; positioning a second semiconductor die (e.g., die 510) within the socket; connecting a first semiconductor die to a first connection terminal (e.g., example terminal 520), and a second semiconductor die to a second connection terminal (e.g., connection terminal 521); and packaging the first semiconductor die and the second semiconductor die within a semiconductor package (e.g., package 500).

The example method may also include forming the socket through one of an opening of the first semiconductor die, a protrusion along a perimeter of the first semiconductor die, or a curvilinear shape along the perimeter of the first semiconductor die.

It will also be understood by those skilled in the art that the explanations herein include one example of a method of forming a semiconductor die, including, providing a first semiconductor die (e.g., example with respect to die 504) having a socket (e.g., socket 506) for receiving a second semiconductor die; positioning a component (e.g., example component 510/546) within the socket; connecting the first semiconductor die to a first connection terminal (e.g., terminal 520); connecting the component to one of the first semiconductor die or the second connection terminal (e.g., instance terminal 522); and packaging the first semiconductor die and the component, for example, within a ceramic body.

Those skilled in the art will appreciate that the method may further include forming the socket through one of an opening of the first semiconductor die, a protrusion along a perimeter of the first semiconductor die, or a curvilinear shape along a perimeter of the first semiconductor die.

The method may further include positioning one of an alignment key, a heat sink, a gallium arsenide active device, a non-semiconductor active device, a gallium nitride active or passive electrical component within the socket.

As will be understood by those skilled in the art in light of the explanation herein, a semiconductor device may include a first semiconductor die (e.g., example die 504) having a socket (e.g., example socket 506) for receiving an element; and a component (e.g., component 546) positioned within the receptacle.

In other embodiments, an opening through the die, such as opening 535 or the opening explained in the description of fig. 3-6, may function as a mold lock. For mold locks, during the process of packaging the die with the mold compound, some of the mold compound may extend into the opening to help lock the mold compound to the die. Those skilled in the art will appreciate that the openings in the die, such as openings 58 (fig. 3), 104 (fig. 5), 77 and 75 (fig. 6) and 535, may be formed both during singulation and prior to singulation. Those skilled in the art will appreciate that other well known packaging techniques or devices may be used in place of the molding compound, including a glop-top compound, a ceramic body (e.g., part of a ceramic semiconductor package), or other well known packaging devices.

Although die 504 is shown with four connections or terminals and die 510 and 546 are shown with two connections or terminals, one skilled in the art will appreciate that any die may have any number of connections or terminals.

From the foregoing, it should be apparent that the present invention discloses a novel shaped die and a novel method of forming the novel shaped die. Including forming dies having various shapes and maximizing the number of dies that can be formed on a wafer, among other features, including positioning the dies to minimize the number of wafers wasted.

While the present subject matter has been described with specific preferred embodiments and examples of various embodiments, the foregoing figures and their description depict only typical and exemplary embodiments of the present subject matter and are not therefore to be considered to limit its scope, for the various alternatives and modifications will be apparent to those skilled in the art. Those skilled in the art will appreciate that not all of region 49 should be removed to singulate the die but only the portion surrounding the outer periphery, e.g., section 67 may not be removed. In addition, a section similar to section 67 or 68 may be used for any die on wafer 30. Any protective layer, such as a singulation mask, or a selectively etched layer, such as a dielectric layer or layer 324 described herein, may be used to protect the enhancement regions so that they are not etched during simultaneous singulation of the semiconductor die. The exemplary forms of die depicted in fig. 2-10 and 23, such as die 35-37, are used as vehicles to describe the various methods of singulating die shapes explained herein; however, one skilled in the art will recognize that the method explained for singulating any of the dies explained herein is applicable to all of the dies described herein. In addition, the grouping of die shown in fig. 2-10 and 23 is not intended to limit the die to being formed in conjunction with any other particular die shape but any combination of die shapes may be used together.

Claims (10)

1. A method of forming a semiconductor device, comprising:

providing a first semiconductor die having a socket for receiving a second semiconductor die;

placing a second semiconductor die within the socket;

connecting the first semiconductor die to a first connection terminal and the second semiconductor die to a second connection terminal; and

the first semiconductor die and the second semiconductor die are packaged within a semiconductor package.

2. The method of claim 1, wherein the step of providing the first semiconductor die with the socket comprises: providing the first semiconductor die with the socket, the socket being one of through an opening of the first semiconductor die, a protrusion along a perimeter of the first semiconductor die, or a curvilinear shape along the perimeter of the first semiconductor die.

3. The method of claim 1, wherein the step of placing the second semiconductor die within the socket comprises: placing the second semiconductor die formed on a different substrate than the silicon substrate.

4. The method of claim 1, further comprising singulating the first semiconductor die from a semiconductor wafer and simultaneously forming the socket using a dry etch process.

5. A method of forming a semiconductor device, comprising:

providing a first semiconductor die having a socket for receiving a second semiconductor die;

placing a component within the socket;

connecting the first semiconductor die to a first connection terminal;

connecting the electrical element to one of the first semiconductor die or the second connection terminal; and

encapsulating the first semiconductor die and the element.

6. The method of claim 5, wherein the step of placing the component within the socket comprises: placing one of a heat sink, an alignment key, a gallium arsenide active device, a non-silicon active device, a gallium nitride active device, or a passive electrical component.

7. The method of claim 5, further comprising forming the socket when singulating the first semiconductor die from a semiconductor wafer.

8. A semiconductor device, comprising:

a first semiconductor device having a socket for receiving an electrical component; and

a component placed within the socket.

9. The semiconductor die of claim 8, wherein the first semiconductor die has a multiply-connected topology.

10. The semiconductor die of claim 8, wherein the element is a mold lock.