HK1158414B - Method for video processing and system for data processing - Google Patents
Method for video processing and system for data processing Download PDFInfo
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- HK1158414B HK1158414B HK11112585.3A HK11112585A HK1158414B HK 1158414 B HK1158414 B HK 1158414B HK 11112585 A HK11112585 A HK 11112585A HK 1158414 B HK1158414 B HK 1158414B
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Description
The present application is a divisional application of the chinese invention application having an application date of 2008/7/200810128383.5 and entitled "video processing method and system for processing data".
Technical Field
The present invention relates to video signal processing, and more particularly, to a method and system for signaling and decoding different versions of an AVS1-P2 bitstream.
Background
The Chinese audio video coding standard (AVS) is a novel and efficient video coding scheme, and provides high-definition and high-quality video services by adopting the latest video coding tool. The video coding algorithm provided by AVS is optimized between absolute coding performance and implementation complexity. Typical AVS applications include broadcast TV, HD-DVD, and broadband video networks.
AVS is a set of standards including AVS1-P1 (broadcast system), AVS1-P2 (high definition video), AVS1-P3 (audio, 2 and 5.1 channels), AVS1-P6(DRM), AVS1-P8 (mobile video), AVS1-P9 (file format). The AVS1-P2 reference frame has been standardized, while other parts of the AVS are under development. The AVS1-P2 video codec has a very wide range of applications, covering various forms of digitally compressed video, from low bit rate internet data streams to HDTV broadcast and digital cinema applications with almost lossless coding.
The AVS1-P2 specification defines the AVS1-P2 bit stream syntax (bitstream syntax) and specifies the complete processing required to decode a bit stream. The AVS1-P2 bitstream is defined as a layered hierarchy having as the outermost layer a video sequence layer, a picture layer, a slice layer, a macroblock layer, and a block layer. Start code based bitstream structures have been used in the AVS1-P2 specification. Each layer of the AVS1-P2 bitstream starts with a unique start code so that the decoder's parser can find each layer within the AVS1-P2 bitstream.
The AVS working group provides two reference models of AVS1-P2 bitstreams within AVS1-P2Rm52j-r1 and AVS1-P2 versions of the AVS specification, respectively. The reference model for the AVS1-P2 bitstream provided in AVS1-P2Rm52j-r1 version of the AVS specification does not fully comply with AVS1-P2 version of the AVS specification. For example, in the direct mode of the AVS specification AVS1-P2Rm52j-r1 version, for the derivation process of DistanceIndexRef, the current picture is field coded and then the reference picture is frame coded. This is different from the derivation process within the AVS1-P2 version of the AVS specification.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.
Disclosure of Invention
A method and/or system for signaling and decoding different versions of an AVS1-P2 bitstream, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.
According to an aspect of the present invention, there is provided a video processing method comprising:
decoding an AVS bitstream based on decoding version information within the AVS bitstream, wherein the decoding version information has been inserted into the AVS bitstream during a coding process (coding) of the AVS bitstream.
Preferably, the decoding version information specifies a particular AVS format used to encode the AVS bitstream.
Preferably, the decoding version information has been inserted into the AVS bitstream during encoding (encoding) of the AVS bitstream.
Preferably, the decoding version information has been inserted into the AVS bitstream during transcoding (transcoding) of the AVS bitstream.
Preferably, the AVS bitstream is a bitstream in AVS1-P2 format.
Preferably, the AVS bitstream is a bitstream in AVS1-P2Rm52j-r1 format.
Preferably, the method includes decoding the AVS bitstream based on default decoding version information when decoding version information is not found.
Preferably, the decoding version information includes sequence-specific user data (sequence user data).
Preferably, the specific sequence of user data is located at the end of a sequence header portion of the bitstream.
Preferably, the method comprises parsing the AVS bitstream to determine the decoding version information.
According to an aspect of the present invention, there is also provided a system for processing data, comprising:
one or more processors configured to decode an AVS bitstream based on decoding version information within the AVS bitstream, wherein the decoding version information has been inserted into the AVS bitstream during an encoding process of the AVS bitstream.
Preferably, the decoding version information specifies a particular AVS format used to encode the AVS bitstream.
Preferably, the decoding version information has been inserted into the AVS bitstream during encoding of the AVS bitstream.
Preferably, the decoding version information has been inserted into the AVS bitstream during transcoding of the AVS bitstream.
Preferably, the AVS bitstream is a bitstream in AVS1-P2 format.
Preferably, the AVS bitstream is a bitstream in AVS1-P2Rm52j-r1 format.
Preferably, the one or more processors decode the AVS bitstream based on default decoding version information when no decoding version information is found.
Preferably, the decoding version information includes a specific sequence of user data.
Preferably, the specific sequence of user data is located at the end of a sequence header portion of the bitstream.
Preferably, the one or more processors parse the AVS bitstream to determine the decoding version information.
According to one aspect of the present invention, there is also provided a machine-readable storage, having stored thereon, a computer program comprising at least one code section for performing video processing, the at least one code section being executable by a machine for causing the machine to perform the steps of:
decoding the AVS bitstream based on decoding version information within the AVS bitstream, wherein the decoding version information has been inserted into the AVS bitstream during an encoding process of the AVS bitstream.
Preferably, the decoding version information specifies a particular AVS format used to encode the AVS bitstream.
Preferably, the decoding version information has been inserted into the AVS bitstream during encoding of the AVS bitstream.
Preferably, the decoding version information has been inserted into the AVS bitstream during transcoding of the AVS bitstream.
Preferably, the AVS bitstream is a bitstream in AVS1-P2 format.
Preferably, the AVS bitstream is a bitstream in AVS1-P2Rm52j-r1 format.
Preferably, the at least one code segment comprises code for decoding the AVS bitstream based on default decoding version information when no decoding version information is found.
Preferably, the decoding version information includes a specific sequence of user data.
Preferably, the specific sequence of user data is located at the end of a sequence header portion of the bitstream.
Preferably, the at least one code segment comprises code to parse the AVS bitstream to determine the decoding version information.
Various advantages, aspects and novel features of the invention, as well as details of an illustrated embodiment thereof, will be more fully described with reference to the following description and drawings.
Drawings
FIG. 1 is a block diagram of a video encoding system according to one embodiment of the present invention;
FIG. 2 is a schematic diagram of an AVS1-P2 bitstream structure according to one embodiment of the present invention;
FIG. 3 is a block diagram of a video decoder according to one embodiment of the present invention;
FIG. 4 is a schematic diagram of AVS1-P2 bitstream transcoding according to one embodiment of the present invention.
Detailed Description
The invention will be further explained with reference to the following figures and examples:
the present invention relates to a method and system for signaling and decoding different versions of an AVS1-P2 bitstream. Aspects of the invention include inserting decoding version information, such as a decoding version identifier, within an AVS1-P2 bitstream. The AVS1-P2 bitstream can be decoded based on the inserted decoding version information. The decoding version information may be inserted into the AVS1-P2 bitstream during AVS encoding or during AVS1-P2 bitstream transcoding. The AVS1-P2 bitstream may conform to a decoded version of AVS1-P2Rm52j-r1 or AVS 1-P2. In a video decoder, the AVS1-P2 bitstream is first parsed to detect and extract decoded version information within the received AVS1-P2 bitstream. The extracted decoding version information will be evaluated to determine the decoding version ID. The video decoder may decode the received encoded AVS1-P2 bitstream based on the decoding revision ID. When no specific decoding version ID is available, the video decoder will use the default decoding version ID. The decoding version information may be represented as a specific sequence of user data and may be inserted into a tail of a sequence header of a corresponding AVS1-P2 bitstream.
Fig. 1 is a block diagram of a video encoding system according to one embodiment of the present invention. As shown in fig. 1, a video source 102, a video encoder 104, a video decoder 106, and a video display 108 are shown. The video encoder may include an encoding processor (Enc _ processor)104a and an encoding memory (Enc _ memory)104 b. The video decoder 106 may include a decoding processor (Dec _ processor)106a and a decoding memory (Dec _ memory)106 b.
The video source 102 may comprise suitable logic, circuitry and/or code that may be operable to provide a video stream from, for example, a video camera, a VCR, a CCD camera or from an internet video stream.
The encoding processor 104a may comprise suitable logic, circuitry, and/or code that may be enabled to convert a video stream from the video source 102 into a compressed format while maintaining acceptable visual effects while using as few bits as possible. In this regard, a user data sequence containing decoding version information may be inserted into the encoded bitstream for decoding the encoded bitstream syntax (syntax) to generate a displayable sequence of video images.
The code memory 104b may comprise suitable logic, circuitry, and/or code that may enable execution of instructions by, for example, the code processor 104 a. The user data sequence containing the decoding version information may be stored in the encoding memory 104 b. The encoding memory 104b is connected to the encoding processor 104a, and may be a flash memory, an electrically erasable programmable memory (EEPROM), or a DRAM.
The decode memory 106a may comprise suitable logic, circuitry, and/or code that may enable conversion of a compressed video stream back to an uncompressed format. The video decoder 106 may decode the encoded bitstream based on the decoded version information within the received video data and reconstruct the sequence of video images.
The decode memory 106b may comprise suitable logic, circuitry, and/or code that may enable execution of instructions by the decode processor 106 a. A user data sequence containing decoding version information may be stored in the decoding memory 106 b. The decoding memory 106b is connected to the decoding processor 106a, which may be a flash memory, an electrically erasable programmable memory (EEPROM), or a DRAM.
The video display 108 may comprise suitable logic, circuitry, and/or code and may be a device that renders visual images using analog or digital video input, such as a computer output device.
In operation, the video source 102 provides a video stream from a video camera or from an internet video stream. The video encoder 104 performs various AVS-specific prediction, transformation, and/or encoding processes to generate an encoded AVS bitstream. In this regard, the encoded AVS bitstream may be extended by inserting a particular user data sequence. The particular user data sequence may carry syntax information for the encoded AVS bitstream, e.g., a particular AVS specification version, e.g., AVS1-P2Rm52j-r1 or AVS 1-P2. The particular AVS specification version may identify which AVS version the encoded AVS bitstream conforms to. The extended encoded AVS bitstream is transmitted to decoder 106 via an intermediate medium such as a wireless channel or DVD. The video decoder 106 decodes the encoded AVS bitstream based on the syntax information for the particular user data sequence and generates a decoded video sequence. The video display 108 renders the decoded video sequence as a visual image.
FIG. 2 is a schematic diagram of an AVS1-P2 bitstream structure according to one embodiment of the present invention. Referring to fig. 2, a sequence header start code 202, a sequence header 204, sequence user data 206, and a video data payload 208 are shown.
The start code 202 may be a unique code with a value of 0x 000001. The start code 202 may be byte aligned for providing AVS encoded bitstream synchronization.
The sequence header 204 may be placed within the AVS1-P2 bitstream to provide the necessary information needed to decode the data payload and support for proper access to a particular distribution medium. For example, the sequence header 204 may be placed at the start of each section on a DVD to facilitate random access, or may be placed every 1/2 seconds of broadcast TV to facilitate changing channels.
The serial user data 206 may be used to provide certain vendor specific information, for example. In this regard, vendor specific sequence user data may be defined to indicate which specific AVS specification version the corresponding AVS1-P2 bitstream conforms to, such as AVS1-P2Rm52j-r1 or AVS 1-P2. The sequence user data 206 may be inserted within the AVS1-P2 bitstream, for example, after the sequence header. An example of the sequential user data 206 is as follows:
sequence user data 206- "AVS 1P2RM52JR 1"
000001B2415653315032524D 35324A 52316
Or
Sequence user data 206- "AVS 1P2 SPEC"
000001B241565331503253504543
The video data payload 208 may include the actual video data information.
Fig. 3 is a block diagram of a video decoder according to one embodiment of the present invention. Referring to fig. 3, a parser 302, comparator 304 and AVS decoder 306 are shown.
The parser 302 may comprise suitable logic, circuitry, and/or code that may enable analysis and classification of a received AVS1-P2 bitstream. For example, a start code within a received AVS bitstream may be parsed for resynchronization and identification. The parser 302 may detect and extract the unique sequence user data 206 within the received AVS bitstream. The parser 302 may pass the extracted unique sequence user data information to the comparator 304 and the encoded AVS bitstream to the AVS decoder 306.
The comparator 304 may comprise suitable logic, circuitry, and/or code that may enable comparing the unique sequence user data information extracted from the parser 302 with a stored list of AVS decoded versions. Based on the comparison, decoding version information for decoding the encoded AVS bitstream can be determined. The AVS decoding version list includes a mapping of the ordered sequence of user data (e.g., AVS1P2RM52JR1 or AVS1P2SPEC) to a decoding version ID (e.g., 0 or 1). The comparator 304 may pass the decoded version ID to the AVS decoder 306. In the event that no valid sequence user data information is available within the received AVS bitstream, the default decoded version ID is passed to the AVS decoder 306.
The AVS decoder 306 may comprise suitable logic, circuitry, and/or code that may be enabled to decode the encoded AVS bitstream based on the decoded version provided by the comparator 304.
In operation, upon receiving the encoded AVS1-P2 bitstream, the parser 302 analyzes and classifies the received AVS1-P2 bitstream. Upon detection of the sequential user data within the received encoded AVS1-P2 bitstream, the parser 302 extracts the detected sequential user data and passes it to the comparator 304. The comparator 304 compares the received sequence user data with the decoded version list to determine the decoded version ID and passes it to the AVS decoder 306. The AVS decoder 306 decodes the encoded AVS1-P2 bitstream based on the decoded version ID. In the event that the received encoded AVS1-P2 bitstream does not contain sequential user data or does not contain sequential user data that does not match a valid decoding version ID, the comparator 304 passes the default decoding version ID to the decoder 306 to decode the encoded AVS bitstream accordingly.
FIG. 4 is a schematic diagram of AVS1-P2 bitstream transcoding according to one embodiment of the present invention. Referring to fig. 4, a typical state machine having state 0, state 1, state 2, state 3, state 4, and state 5 is shown.
The state machine can transition between different states depending on different input byte values. The state machine may be reset and start from state 0. In state 0, an input of "00" may result in a transition from state 0 to state 1. Otherwise, the state machine remains in state 0. In state 1, the state machine transitions from state 1 to state 2 with an input of "00". Otherwise, the state machine will reset from state 1 to state 0. In state 2, an input of "00" will cause the state machine to remain in state 2. An input of "01" will cause the state machine to transition from state 2 to state 3. Otherwise, the state machine will reset from state 2 to state 0.
In state 3, the state machine detects the start code. An input of "B0" will result in a transition from state 3 to state 4. Otherwise, the state machine transitions to state 5. In state 4, the state machine may assert that a sequence header is detected. A counter is set to the number of bytes of a portion of the sequence header. When the counter counts down to zero, a particular sequence of user data containing decoding version information may be inserted and the state machine reset to state 0. Otherwise, the state machine will remain in state 4. In state 5, the state machine may determine that neither a sequence header nor a start code is detected, and transition to state 0 regardless of the byte value to be entered.
The present invention provides a method and system for signaling and decoding different versions of an AVS1-P2 bitstream. According to various embodiments of the invention, decoding version information may be inserted within the AVS1-P2 bitstream. The AVS1-P2 bitstream may then be decoded based on the decoding version information. The decoding version information may be inserted into the AVS1-P2 bitstream during AVS encoding (FIG. 2) or during AVS1-P2 bitstream transcoding (FIG. 4). The AVS1-P2 bitstream may conform to AVS1-P2Rm52j-r1 or AVS1-P2 decoded versions. Before being decoded, the AVS1-P2 bitstream may be parsed within the parser 302 to identify and extract decoded version information within the received AVS1-P2 bitstream. The extracted decoding version information may be evaluated in the comparator 304 to determine a decoding version ID and passed to the AVS decoder 306. When the received AVS1-P2 bitstream does not contain a decoding version ID or contains an invalid decoding version ID, the comparator 304 passes the default decoding version ID to the AVS decoder 306 for decoding the received encoded AVS1-P2 bitstream. The decoding version information may be indicated by a particular sequence of user data 206. The specific sequence user data 206 may be inserted at the end of the sequence header 204 of the AVS1-P2 bitstream.
Another embodiment of the present invention provides a machine-readable storage and/or storage medium having stored therein a machine code and/or a computer program having at least one code section for execution by a machine and/or a computer to cause the machine and/or computer to perform the steps described herein for signaling and decoding different versions of an AVS1-P2 bitstream.
Accordingly, the present invention can be realized in hardware, software, or a combination of hardware and software. The present invention can be realized in a centralized fashion in at least one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods of the present invention is suited. A typical combination of hardware and software could be a general purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.
The present invention may also be implemented by a computer program product, comprising all the features enabling the implementation of the methods of the invention, when loaded in a computer system. The computer program in this document refers to: any expression, in any programming language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to other languages, codes or symbols; b) reproduced in a different format.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (4)
1. A video processing method, comprising:
detecting and extracting sequential user data within the received AVS1-P2 bitstream;
comparing the extracted sequence user data to a stored AVS decoding version list, the AVS decoding version list including a mapping of the sequence user data to decoding version information;
determining decoding version information for decoding the AVS1-P2 bitstream based on the comparison result;
decoding the AVS1-P2 bitstream based on the determined decoding version information, wherein the decoding version information has been inserted within the AVS1-P2 bitstream during transcoding of the AVS1-P2 bitstream.
2. The method of claim 1, wherein the decoding version information specifies a particular AVS format used to encode the AVS1-P2 bitstream.
3. A system for processing data, comprising:
a first module for detecting and extracting sequential user data within a received AVS1-P2 bitstream;
a second module for comparing the extracted sequence user data with a stored AVS decoding version list, the AVS decoding version list including a mapping of the sequence user data to decoding version information;
a third module for determining decoding version information for decoding the AVS1-P2 bitstream based on the comparison result;
a fourth module for decoding the AVS1-P2 bitstream based on the determined decoding version information, wherein the decoding version information has been inserted into the AVS1-P2 bitstream during transcoding of the AVS1-P2 bitstream.
4. The system of claim 3, wherein the decoding version information specifies a particular AVS format used to encode the AVS1-P2 bitstream.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US94855307P | 2007-07-09 | 2007-07-09 | |
US60/948,553 | 2007-07-09 | ||
US12/142,409 | 2008-06-19 | ||
US12/142,409 US8576918B2 (en) | 2007-07-09 | 2008-06-19 | Method and apparatus for signaling and decoding AVS1-P2 bitstreams of different versions |
Publications (2)
Publication Number | Publication Date |
---|---|
HK1158414A1 HK1158414A1 (en) | 2012-07-13 |
HK1158414B true HK1158414B (en) | 2014-03-14 |
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