HK1157499B - Ground fault circuit interrupter and method - Google Patents

Description

Ground fault circuit interrupter and method therefor

Technical Field

The present invention relates generally to measurement systems, and more particularly to measurement systems relating to electrical signals.

Background

Circuits for measuring or calculating electrical signals such as current, voltage, and power, and circuits for measuring and calculating electrical parameters such as impedance, admittance, phase relationships are used in a variety of applications, including impedance measurement, load detection and calibration, security systems, smart grids, sensor interfaces, automotive systems, self-test systems, and the like. For example, the circuit used to determine the system impedance may include a resistor placed in series with the load such that the current flowing through the resistor can be used to determine the current flowing through the load. The disadvantages of this technique are the reduced range of input voltages, the large area of semiconductor material used to fabricate the circuit, the limited frequency of the circuit elements, and the need for extremely precise circuit elements.

In some applications, it may be desirable to detect a ground fault condition. One technique for detecting this condition is to establish a resonance in the inductor-resistor-capacitor network when it is exposed to a ground-to-neutral condition. Resonance may be established by delivering a pulse to a positive feedback system including an operational amplifier. Alternatively, steady state excitation can be delivered to a circuit that then monitors for significant changes in the waveform profile. A disadvantage of these techniques is that they are prone to temperature drift and manufacturing drift (shift) that can reduce detection accuracy.

Accordingly, it would be advantageous to have a circuit and method for determining electrical parameters and electrical signals of a circuit element. It would be further advantageous for the circuit and method to be cost effective.

Drawings

The invention will be better understood from a reading of the following detailed description taken in conjunction with the accompanying schematic drawings in which like reference symbols indicate like elements, and in which:

FIG. 1 is a block diagram of a measurement circuit according to an embodiment of the present invention;

FIG. 2 is a block diagram of a portion of a measurement circuit according to an embodiment of the present invention;

FIG. 3 is a block diagram of a circuit block for randomizing the timing of ground to neutral measurements according to an embodiment of the present invention;

FIG. 4 is a waveform diagram of timing of a randomized ground to neutral measurement according to an embodiment of the invention;

FIG. 5 is a timing diagram for a portion of the circuit block of FIG. 1;

FIG. 6 illustrates a graph of threshold values for a portion of the circuit blocks of FIG. 1;

FIG. 7 is a schematic diagram of a measurement circuit according to another embodiment of the present invention;

FIG. 8 is a schematic diagram of a measurement circuit according to another embodiment of the present invention;

FIG. 9 is a schematic diagram of a measurement circuit according to another embodiment of the present invention;

FIG. 10 is a schematic diagram of a measurement circuit according to another embodiment of the invention;

FIG. 11 is a schematic diagram of a measurement circuit according to another embodiment of the invention;

FIG. 12 is a schematic diagram of a measurement circuit according to another embodiment of the invention;

FIG. 13 is a schematic diagram of a measurement circuit according to another embodiment of the present invention; and

FIG. 14 is a schematic diagram of a measurement circuit according to another embodiment of the invention.

Detailed Description

In general, the present invention provides a ground fault circuit interrupter with different components, including an impedance measurement circuit. According to embodiments of the present invention, a transconductance operational amplifier (OTA) generates a plurality of output signals. For example, the OTA may generate multiple output currents where the second, third, fourth, etc. currents are a backup of the first current. Alternatively, the OTA may generate a plurality of output voltages, where each of the plurality of output voltages is proportional to the output current of the OTA. When the OTA generates multiple output currents, they may be input as currents to the respective mixers, or they may be converted to output voltages, which are input into the respective mixers. The modulator may be used to modulate at least one current or voltage signal from the OTA by an in-phase signal resulting in a modulated signal that is filtered by a low-pass filter to pass the baseband voltage of the mixed signal. Preferably, the in-phase signal is in phase with the input signal to the OTA. The output signal of the low pass filter is digitized by an analog-to-digital converter to determine a plurality of real impedance levels, or a specific real impedance is determined by a comparator. Further, a modulator may be used to modulate at least one current or voltage signal from the OTA by a phase shifted signal resulting in a modulated signal filtered by a low pass filter, where the modulated signal is indicative of the reactive impedance of the load. The reactive component is digitized by an analog-to-digital converter or comparator. Preferably, the phase shifted signal is phase shifted by 90 degrees from the signal on the OTA input terminal.

According to alternative embodiments, the circuit can be configured to measure only in-phase impedance or only quadrature-axis impedance (quadrature impedance). Furthermore, by performing measurements at different times, a single modulator may be used to measure in-phase impedance and quadrature-axis impedance.

Furthermore, embodiments of the present invention are suitable for use in GFCI circuits associated with single wound single current transformer circuits, thereby forming single wound single current transformer based impedance measurement circuits. An advantage of using single wound single current transformer circuits is that they can be implemented relatively inexpensively.

Fig. 1, 2, and 3 are block diagrams of a Ground Fault Circuit Interrupter (GFCI) module 10 according to an embodiment of the invention. For purposes of clarity, fig. 1, 2, and 3 are described together. GFCI module 10 includes a digital control circuit 12, a ground-to-neutral (G-N) detection random number generator 16, and a digital filter 18, where digital control circuit 12 is coupled to receive an input signal from a power supply level/zero crossing detector circuit 14. The signal received from digital filter 18 may be transmitted over a bus connection having N interconnects, where N is an integer, and the signal received from power level detector circuit 14 may be transmitted over a bus connection having M interconnects, where M is an integer. The integers N and M may be the same as each other, or they may be different from each other. Digital control circuit 12 is coupled for transmitting signals to digital filter 18, to excitation waveform generator 20, to switch 22, and to offset correction circuit 24. Although filter 18 is described as a digital filter, it is not a limitation of the present invention. The filter 18 may be an analog filter.

According to an embodiment, the power supply level/zero crossing detector circuit 14 is connected to the slope detector 29 via a bus connection having K interconnects, where K is an integer. Slope detector 29 is connected to self-test controller 15 by connections 29A and 29B, where a slope detection FAULT signal (SD _ FAULT) is transmitted to self-test controller 15 by connection 29A and a slope detection enable signal (SD _ EN) is received from self-test controller 15 by connection 29B. The slope detector 29 is connected to the solenoid controller 17, which is connected to the solenoid or to the power supply via the solenoid/power connector 19. The connection between the slope detector 29 and the solenoid controller 17 transmits a solenoid enable signal (SOL _ EN) to the solenoid controller 17. Self-test controller 15 is connected to G-N detector 56 through output terminal 15A and to differential current detector 58 through output terminal 15B. Further, the self-test controller 15 has an output terminal 15C through which an internal or external ground fault excitation enable signal is transmitted and an output terminal 15D through which an internal G-N impedance enable signal is transmitted, respectively. Alternatively, slope detector 29 may be omitted, in which case power supply level/zero crossing detector circuit 14 is connected to self test controller 15 through a bus connection having K interconnects. In this embodiment, the self-test controller 15 is connected to the solenoid controller 17. The power level/zero crossing detector 14 is connected to the solenoid/power connector 19 through a current limiter 21 and to a voltage limiter 23.

The input terminals of power/line level detector circuit 14 are connected to the line level of the power supply or circuit being monitored by GFCI module 10. May be connected by a protective structure such as the flow restrictor 21 shown in fig. 2. The current limiter 21 is, for example, a resistor. The power supply level detector circuit 14 passes the power supply level to the digital control circuit 12 and can indicate when the power supply level crosses the neutral level during a polarity switch, or it can indicate when other levels are used. During a self-test, the power level detector circuit 14 can indicate when it is safe for the digital control circuit 12 to activate an external device, such as a Silicon Controlled Rectifier (SCR), to test the GFCI solenoid. In addition, the power level detector circuit 14 can be used to determine whether the external device is operating properly by monitoring the effect of a trip (trip) of the external device on the power supply voltage level. For example, the digital control circuit 12 may activate an external transistor or SCR to pull current through an external solenoid. As current is pulled through the transistor or SCR, the supply voltage decreases or drops (drop) at a different rate than the steady state operating rate, i.e., the slope of the supply voltage changes. The rate at which the power supply voltage is reduced can be measured by the power level detector circuit 14 to determine whether the external device is operating properly. Introducing a small change in slope increases the window (window) after the zero crossing during which the circuit can be tested and indicates when the SCR can be activated. Thus, level detector circuit 14 generates an operating condition signal that indicates whether the circuit is operating properly or whether it is safe for digital control circuit 12 to activate an external device, depending on the rate at which the power supply voltage level is decreasing.

Ground-to-neutral detection random number generator 16 is used to determine when GFCI module 10 should check for ground-to-neutral faults. If multiple GFCI modules 10 are used on the same power circuit and if one GFCI module 10 and another GFCI module 10 operate ground to neutral measurements at the same time, one GFCI module 10 may interfere with another GFCI module 10. It is therefore advantageous to randomize the timing of the ground to neutral measurements. The G-N probing randomizer 16 randomizes the timing between ground to neutral measurements to minimize the possibility of interference with them. Fig. 3 is a block diagram of a circuit block 31 for randomizing the timing of ground to neutral measurements. The internal clock based half-wave period counter 33 is connected for transmitting the random number seed to the random number generator 35, which is connected for transmitting the random number generation signal to the G-N timing control circuit 37. In addition, a G-N timing control circuit 37 is connected to receive the zero crossing count signal from the zero crossing counter 38 and generate a G-N test enable signal. The G-N timing control circuit 37 may be a sub-module within the G-N probing random number generator 16. The randomization may be based on the number of clock oscillations in a given period of the power cycle as shown in fig. 4. Shown in fig. 4 is a graph 41 showing a power cycle with three zero crossings and a random number seed based on a counter that counts within a half cycle of the power cycle.

Offset correction circuit 24 is used to minimize the effective offset of transconductance operational amplifier (OTA) 28. If a blocking capacitor is not used in series with current transformer 51, the offset voltage in OTA28 will generate a DC current through current transformer 51. This DC current will affect the accuracy of the differential current measurements made by the differential current detector circuit 58. Offset correction detector 24 removes the offset of OTA28 and protects the accuracy of the differential current measurement. Another reason for the advantage is that it allows the current transformer 51 to be implemented with fewer windings.

GFCI module 10 also includes a circuit element parameter measurement network 26 that includes an offset correction circuit 24, a transconductance operational amplifier (OTA)28, an in-phase impedance detector 30, and a reactive impedance detector 32. For example, circuit element parameter measurement network 26 is an impedance measurement network, i.e., the circuit element parameter measured by network 26 is an impedance. The inverting input terminal of offset correction circuit 24 is commonly connected to output terminal 25 of OTA28 and to terminal 52 of primary winding 50 of current transformer 51, and the non-inverting input terminal of offset correction circuit 24 is connected to a terminal of switch 22. The output terminals of offset correction circuit 24 are connected to respective input terminals of OTA 28. More specifically, an output terminal of offset correction circuit 24 is connected to an inverting input terminal of OTA28, and another output terminal of offset correction circuit 24 is connected to a non-inverting input terminal of OTA 28. Control terminal of switch 22Is coupled for receiving a control signal from digital control circuit 12, and the other terminal of switch 22 is coupled for receiving a bias voltage V_BIASAnd to terminal 54 of primary winding 50.

Output terminal 34 of in-phase impedance detector 30 is connected to ground to neutral (G-N) detector 56 and output terminal 36 of reactive impedance detector 32 is connected to digital filter 18. Output terminals 34 and 36 serve as output terminals of circuit element parameter measurement network 26. Output terminal 27 of OTA28_JIs connected to the input terminals of the differential current detector 58 and the output terminals of the differential current detector 58 may be connected to the input terminals of the digital filter 18 by a bus connection having P interconnects, where P is an integer. It should be noted that reference character "J" denotes an integer and has been appended to reference character 27 to indicate one or more output terminals, e.g., output terminal 27₁、27₂、27₃Etc., which may extend from OTA 28. In some embodiments, where the electrical signal output from OTA28 is a current, it is preferred that each of in-phase impedance detector 30, reactive impedance detector 32, and differential current detector 58 be connected to its own output terminal from OTA 28. For example, when the output signal of OTA28 is a current, output terminal 27₁Connected to an in-phase impedance detector 30, an output terminal 27₂Is connected to the reactive impedance probe 32 and has an output terminal 27₃Connected to a differential current detector 58.

GFCI module 10 includes sub-modules capable of performing: impedance measurements, which include ground-to-neutral resistance measurements and current transformer reactive impedance measurements, i.e., self-detection; differential current measurement level detection; OTA offset correction; detecting the level of a neutral point by a grounding point; power/line voltage level detection; generating an excitation; the grounding point generates a random number for detecting the neutral point; digital fault filtering; or similar tasks.

According to an embodiment in which impedance is measured, waveform stimulus generator 20 generates an electrical signal or waveform that is transmitted through switch 22 to a non-inverting input terminal of offset correction circuit 24. It should be noted that the waveform stimulus generator 20 may generate a waveform having a single frequency, or a plurality of waveforms having different frequencies from each other. For example, to determine whether a true fault has occurred, the waveform stimulus generator 20 may generate three waveforms each having a different frequency. GFCI 10 includes a voting (voting) algorithm to determine when a fault has occurred. More specifically, GFCI 10 determines that a fault has occurred based on most of the waveform frequencies, e.g., if a fault condition is detected using two of the three waveforms, GFCI 10 indicates the occurrence of a fault. This type of algorithm protects against false trips that may occur if there is a perfectly aligned (aligned) noise signal on the system.

Offset correction circuit 24 transmits the electrical signal to the non-inverting input terminal of OTA 28. Because OTA28 is configured as a follower, the electrical signal on its output terminal 25 follows the electrical signal at its non-inverting input terminal. Thus, the electrical signal appearing on the non-inverting input terminal of OTA28 is transmitted to output terminal 25 and input terminal 52 of current transformer 51. An input terminal 54 of the current transformer 51 is coupled for receiving a bias voltage V_BIAS. OTA28 generates an electrical signal proportional to the electrical signal appearing on output terminal 25 and outputs the proportional electrical signal from output terminal 27_JTo the in-phase impedance detector 30, the quadrature or reactive impedance detector 32, and the differential current detector 58. It should be noted that reference character "J" has been appended to reference character 27 to indicate that one or more output terminals may extend from OTA28 and provide a copy of the current appearing on output terminal 25. As discussed above, when the electrical signal output from OTA28 is a current, it is preferable to have output terminals 27 that extend from OTA28 to in-phase impedance detector 30, reactive impedance detector 32, and differential current detector 58, respectively₁、27₂And 27₃. Alternatively, the output terminal 27₁、27₂And 27₃May be replaced by a single output terminal connected to a switch (not shown) that switches reactive resistance from the in-phase impedance detector 30Current flow to a single output terminal between the anti-probe 32 and the differential current probe 58.

The in-phase impedance detector 30 detects a real component or portion of the impedance of the current transformer load with respect to the current transformer 51 and transmits a current or voltage signal to the G-N detector 56 that is proportional to the component or portion of the impedance of the current transformer 51. The G-N detector 56 determines whether the impedance would cause a fault. Reactive or quadrature impedance detector 32 detects a reactive component or portion of the impedance of the current transformer load with respect to current transformer 51 and transmits a current or voltage signal to digital filter 18 that is proportional to the component or portion of the impedance of current transformer 51. The digital filter 18 determines whether the reactive component is within an acceptable range. For example, too low a reactive impedance may indicate that the current transformer is not properly connected to network 26.

According to an embodiment, differential current measurement may be achieved by operating switch 22 such that the non-inverting input terminal of offset correction circuit 24 is connected to bias voltage V_BIAS. The electrical signal on output terminal 25 is driven to voltage V by the feedback configuration of OTA28_BIAS. In this configuration, input terminals 52 and 54 of current transformer 51 are driven to voltage level V_BIAS. Any differential current through the secondary winding of current transformer 51 will induce a current through the primary winding of current transformer 51. The induced current is supplied to the output terminal 25 to maintain the voltage on the output terminal 25 at the voltage V_BIASThe above. OTA28 generation or generation and output terminal 27₃A copy of the proportional induced current that is transmitted to the input terminal of the differential current detector 58. The differential current detector 58 generates an output current that is transmitted to the digital filter 18, which determines whether a differential current fault has occurred based on the differential current level and the amount of time that the current level exists. The filter timing of digital filter 18 may be dynamically adjusted based on the condition of circuit 10. For example, at initial start-up, it may be advantageous to minimize the filter timing to quickly catch line faults. However, it is not limited toIt may be advantageous to increase the filtering timing during normal operation to minimize the effect of noise on the power supply lines. Fig. 5 and 6 show the timing of the digital filter 18 according to an embodiment of the present invention. Fig. 5 is a timing diagram 43 showing a graph 45 of differential fault current versus time that allows the GFCI module 10 to react to a fault by releasing electrical contact. Fig. 6 shows a rolling window for each piecewise linear portion of the differential current being monitored. More specifically, digital filter 18 is capable of monitoring several states in which GFCI module 10 can operate. Each state is associated with a different threshold level for identifying a ground fault. The start fault threshold counter, which may be a sub-module within the digital filter 18, is programmed with a start fault threshold count during the start state or phase. During a steady state or steady state phase of operation, the digital filter 18 may have a fault threshold counter programmed to have a steady state fault threshold count that is different from and preferably higher than a start-up fault threshold count during a start-up state or phase. It should be noted that the fault threshold counter may be a timer such that a line fault occurs when the fault exceeds the fault threshold for a predetermined period of time. The number of states is not limited to the number of startup states and steady states. For example, GFCI module 10 may operate in a state or phase determined by environmental or external conditions. For example, GFCI module 10 may operate in non-ideal environmental conditions, such as a partial power outage condition, i.e., during a low supply voltage or negative half wave, or the module 10 may operate in a condition where it is not necessary to maintain power to a portion of the circuitry, such as an analog portion of the circuitry. Thus, part of the circuit may be powered down. When the power-off condition is over, or the portion of the circuit that was powered off returns to a powered-on state, a portion of the output signal from digital filter 18 may be lost. Accordingly, it may be desirable to start the GFCI module 10 such that the digital filter 18 is in the on state, i.e., programmed to have an on fault threshold count, or the digital filter 18 may be programmed to have a fault threshold count that is below the on fault threshold count, below the steady state fault threshold count, at the on fault threshold count and at the steady state fault threshold countOr greater than the steady state fault threshold count to meet a particular specified set of timing requirements. Accordingly, there can be one state, two states, three states, four states, or more states. Further, the steady state may include one or more states that depend on the circuit configuration and external conditions.

Although the fault threshold count has been described as including a fixed number of counts that trigger a fault, it is not a limitation of the present invention. Alternatively, the fault threshold value can be based on a decimal rate value. For example, the fault threshold may be a ratio of a count of the over-threshold counter to a count of the half-wave period counter, or a ratio of a count of the over-threshold counter to the power frequency. The use of the decimal rate approach is advantageous in that it provides immunity to variations in the AC source.

Fig. 6 shows a rolling time window 47 on which the linear portion of the graph 45 is monitored with respect to differential fault current. For example, digital filter 18 has four fault threshold counters 53, 55, 57, and 59. However, it is not a limitation of the present invention. There may be P fault threshold counters, where P is an integer. The failure threshold counter 53 is a start threshold counter. The failure threshold counter 53 is a start threshold counter. The fault produces fault pulses 61 in the rolling time window 47 that have different amplitudes, different pulse widths, and different pulse thresholds. These pulses have different widths for each fault impedance value. Fig. 6 also shows a fault current waveform 63 with fault threshold count or timing levels Fth-1, Fth-2. When a minimum threshold for the time to failure or number of failures is reached, the GFCI module 10 indicates that a fault has occurred, i.e., a line fault has occurred if the time to failure or number of counts exceeds the fault threshold for the first time period or number of counts. Digital filter 18 monitors GFCI module 10 for a predetermined minimum period of time and if no fault pulse is detected, GFCI module 10 continues the normal mode of operation. If a fault pulse is detected, GFCI module 10 measures the duration and strength of the pulse and generates an operating condition signal based on the rate at which the supply level voltage decreases.

Although the electrical signal generated by OTA28 and transmitted to differential current detector 58 has been described as a current, it is not a limitation of the present invention. Alternatively, the electrical signal transmitted from OTA28 may be a voltage that is directly proportional to the induced current.

Fig. 7-14 illustrate embodiments of circuit component parameter measurement networks included in GFCI module 10. The circuit element parameter measurement networks in fig. 7-14 measure impedance. It should be understood, however, that it is not a limitation of the present invention. When GFCI module 10 measures impedance and is coupled to a single wound single current transformer, it is referred to as a single wound single current transformer impedance measurement circuit.

FIG. 7 is a block diagram of a circuit element parameter measurement network 200 according to an embodiment of the present invention. Shown in fig. 7 is a transconductance operational amplifier (OTA)202 having a non-inverting input terminal 204, an inverting input terminal 206, and output terminals 210 and 212. It should be noted that OTA202 is similar to OTA28 shown and described with respect to fig. 1. Non-inverting input terminal 204 is coupled to receive an electrical signal V having a frequency fc_IN(fc), and inverting input terminal 206 is connected to output terminal 210. Preferably, the electronic input signal V_IN(fc) is a voltage signal. More preferably, the electrical signal V_IN(fc) is a periodic voltage signal, such as a sine wave. It should be noted that the electrical signal V_IN(fc) may be a DC signal, i.e. the frequency fc equals zero. The output terminal 210 of the OTA202 is coupled to a load 216 through a capacitor 214. For example, load 216 is a load impedance having circuit element parameters with a real component and a reactive component. For example, when the load 216 is an impedance, the impedance has an amplitude and a phase. Note that the capacitor 214 is an optional circuit element that may be omitted.

Output terminal 212 of OTA202 is coupled to modulators 220 and 222 through a current-to-voltage (I/V) converter 218. The input terminal 226 of the modulator 220 and the input terminal 228 of the modulator 222 are connected to the I/V converter 218To form node 224. The I/V converter 218 may be, for example, a resistor through which the current I passes_rx(fc) flow generated Voltage V_rx(fc). The modulator 220 further has an input terminal 230 and an output terminal 232, the output terminal 230 being coupled for receiving the modulated signal V_S(fc) and output terminal 232 is connected to input terminal 234 of Low Pass Filter (LPF) 236. Modulated signal V_S(fc) may be a periodic signal, such as a sine wave, square wave, sawtooth, etc. It should be noted that the modulation signal V_S(fc) is related to the input signal V_IN(fc) the same type of signal and having the same input signal V_IN(fc) the same frequency. Preferably, the modulation signal V_S(fc) is a sine wave. An analog-to-digital converter (ADC)238 is connected to the output terminal of the LPF 236. Output signal Z_MAG216Appearing on the output terminal 239 of the ADC 238. The modulator 220 and the LPF236 form an in-phase or real impedance detector 280.

The modulator 222 has an input terminal 240 and an output terminal 242, the input terminal 240 being coupled for receiving a modulated signal V through a phase shift element 244_SP(fc), output terminal 242 is coupled to input terminal 246 of LPF 248. Phase shift element 244 shifts the modulated signal V_S(fc) to generate a phase-shifted modulated signal V_SP(fc) with a modulation signal V_S(fc) the same frequency and amplitude, but different phase. For example, the signal V_S(fc) and V_SP(fc) may have a phase difference of 90 degrees, e.g. signal V_SP(fc) and signal V_S(fc) has a phase difference of 90 degrees. The ADC 250 is connected to the output terminal of the LPF 248. Output signal Z_PHASE216Appearing on output terminal 252 of ADC 250. The modulator 222 and the LPF248 form a quadrature impedance detector 282. The quadrature impedance detector 282 is also referred to as a virtual impedance detector or a reactive impedance detector.

In operation, input voltage V_IN(fc) is applied to input terminal 204 of OTA 202. Responsive to input voltage V_IN(fc), OTA202 generates a current I_tx(fc) flowing from output terminal 210 through capacitor 214 and into load 216, therebyGenerating a voltage V at the output terminal 210_tx(fc). Since the output terminal 210 is connected to the input terminal 206, the voltage V_tx(fc) appears on input terminal 206. Thus, OTA202 buffers input signal V to load 216_IN(fc). In addition, OTA202 generates a current I_tx(fc) and conducts the current through output terminal 212. Current I_txCopy of (fc) with current I_rx(fc) is a label and is referred to as a copy current or a replica current. Current I_rx(fc) is transmitted to I/V converter 218, which generates a voltage V on node 224_rx(fc)。

In response to a voltage V_rx(fc) and V_s(fc), modulator 220 generates an output voltage V at output terminal 232_{MOD_I}. Output voltage V_{MOD_I}Equal to the current I shifted down to baseband (i.e., shifted down to DC)_txThe amplitude or real part of (fc). LPF236 filters the output voltage V_{MOD_I}To remove any high frequency noise and the ADC 238 digitizes the filtered output voltage V_{MOD_I}To form a digital code Z_MAG216Which represents the magnitude of the impedance of the load 216, i.e., the digitized signal represents the magnitude of the component of the impedance of the load 216.

In response to a voltage V_rx(fc) and V_SP(fc), modulator 222 generates an output voltage V on output terminal 242_{MOD_Q}. LPF248 filters the output voltage V_{MOD_Q}To remove any high frequency noise and ADC 250 digitizes the filtered output voltage V_{MOD_Q}To form a digital code Z_PHASE216Which represents the phase of the load 216 impedance, i.e., the digitized signal represents the quadrature component of the load 216 impedance.

Fig. 8 is a schematic diagram of a circuit element parameter measurement network 270 according to another embodiment of the present invention. Network 270 includes OTA202, capacitor 214, load 216, LPFs 236 and 248, and ADCs 238 and 250, which were described above with respect to fig. 2. In addition, network 270 includes a voltage/current copier and inverter block 218A having an output terminal 217 and an output terminal 219, the output terminal 217 being commonly connectedTo input terminal 288 of switch 284 and to input terminal 316 of switch 312 to form node 223, and output terminal 219 is commonly connected to terminal 300 of switch 296 and to terminal 308 of switch 304 to form node 271. The network 270 also includes a switch 284 having a control terminal 286, a terminal 288 connected to the node 223, and a terminal 290 connected to the input terminal 234 of the LPF 236. Control terminal 286 is coupled to receive modulation signal V through inverter 292_SB (fc), i.e., the input terminal of inverter 292 is coupled for receiving modulation signal V_S(fc), and the output terminal of the inverter 292 is connected to the control terminal 286 of the switch 284 for transmitting the inverted modulation signal V_SB (fc). Node 271 is coupled to the input terminal 234 of LPF236 through a switch 296, switch 296 having a control terminal 298 and terminals 300 and 302. Control terminal 298 is coupled for receiving modulated signal V_S(fc), terminal 300 is connected to node 271, and terminal 302 is connected to input terminal 234 of LPF 236.

Further, node 271 is coupled to input terminal 246 of LPF248 through switch 304, switch 304 having control terminal 306 and terminals 308 and 310. More specifically, control terminal 306 is coupled to receive modulated signal V_SP(fc), terminal 308 is connected to node 271, and terminal 310 is connected to input terminal 246 of LPF 248. Switch 312 has control terminals 314, 316 and 318, terminal 314 being coupled to receive modulation signal V from inverter 320_SPB (fc), said terminal 316 being commonly connected to terminal 288 of switch 284 and to terminal 217 of current-to-voltage converter 218A, said terminal 318 being commonly connected to input terminal 246 of LPF248 and to terminal 310 of switch 304.

In operation, input signal V_IN(fc) is received on input terminal 204 of OTA 202. Responsive to an input signal V_IN(fc), OTA202 generates a current I_tx(fc) that flows from output terminal 210 through capacitor 214 and into load 216, thereby generating voltage V on output terminal 210_tx(fc). Since the output terminal 210 is connected to the input terminal 206, the voltage V_tx(fc) appearing at the input terminal206. Thus, OTA202 buffers input signal V to load 216_IN(fc). In addition, OTA202 generates a current I_tx(fc) and conducts the current through output terminal 212. Current I_txCopy of (fc) with current I_rx(fc) is a label and is referred to as a copy current or a replica current. Current I_rx(fc) is transmitted to I/V converter 218A and converted to a voltage V appearing on node 271_rxp(fc) and the voltage V appearing on node 223_rxn(fc)。

It should be noted that the modulation signal V_S(fc) controls switches 284 and 296 and modulates signal V_SP(fc) controls switches 304 and 312. When modulating signal V_S(fc) is a logic high voltage level, switch 284 is closed and switch 296 is open, and when modulation signal V is present_S(fc) is a logic low voltage level, switch 284 is open and switch 296 is closed. When modulating signal V_SP(fc) is at a logic high voltage level, switch 304 is closed and switch 312 is open, and when modulation signal V is present_SP(fc) at a logic low voltage level, switch 304 is open and switch 312 is closed. Thus, the switches 284 and 296 are opened and closed to couple the signal V_rxn(fc) and V_SB (fc) are multiplied by each other and the signal V is_rxp(fc) and V_S(fc) are multiplied by each other. Multiplication of these signals forms a product signal that is combined to form the voltage signal V on the input terminal 234 of the LPF236_{MOD_I}. Output voltage V_{MOD_I}Equal to the current I shifted down to baseband (i.e., shifted down to DC)_txThe amplitude or real part of (fc). Because of the signal V_rxn(fc) and V_rxp(fc) is a fully differential signal, then the input signal V_INThe DC component of (fc) is removed, thereby increasing the noise immunity of the network 270. LPF236 filters the output voltage V_{MOD_I}To remove any high frequency noise and the ADC 238 digitizes the filtered output voltage V_{MOD_I}To form a digital code Z_MAG216Which represents the magnitude of the impedance of the load 216, i.e., the digitized signal represents the magnitude of the in-phase component of the impedance of the load 216. Switches 284 and 296, inverter 292, andLPF236 forms an in-phase or real impedance detector 280A.

Similarly, switches 304 and 312 are opened and closed to couple signal V_rxn(fc) and V_SPB (fc) are multiplied by each other and the signal V is_rxp(fc) and V_SP (fc) are multiplied by each other. The multiplication of these signals forms a product signal that is combined to form the voltage signal V on the input terminal 246 of the LPF248_{MOD_Q}. LPF248 filters the output voltage V_{MOD_Q}To remove any high frequency noise and ADC 250 digitizes the filtered output voltage V_{MOD_Q}To form a digital code Z_PHASE216Which represents the phase of the impedance of the load 216, i.e., the digitized signal represents the quadrature component of the impedance of the load 216. Switches 304 and 312, inverter 320, phase shift element 244, and LPF248 form quadrature impedance detector 282A. The quadrature impedance detector 282A is also referred to as a virtual impedance detector or a reactive impedance detector.

Fig. 9 is a schematic diagram of a circuit element parameter measurement network 350 according to another embodiment of the present invention. Shown in fig. 9 is OTA202A coupled to load 216 through capacitor 214. OTA202A is similar to OTA202 but has three output terminals 210, 212, and 215 instead of the two output terminals 210 and 212 of OTA 202. Because OTA202A has three output terminals, reference character "a" has been appended to reference character "202" to distinguish between OTA202 in fig. 2 and the transconductance operational amplifier in fig. 8. Similar to network 270 described with respect to fig. 7, output 210 of OTA202A is coupled to load 216 through capacitor 214. The network 350 includes a node 223 coupled to the input terminal 234 of the LPF236 and to the output terminal 217A of the current-to-voltage converter 218A through a switch 284. More specifically, the switch 284 has a control terminal 286, a terminal 288 connected to the node 223, and a terminal 290 connected to the input terminal 234 of the LPF 236. Control terminal 286 is coupled to receive modulation signal V from inverter 292_SB (fc), i.e., the input terminal of inverter 292 is coupled for receiving modulation signal V_S(fc), and the output terminal of the inverter 292 is connected to the control terminal 286 of the switch 284 for transmitting the inverterModulated signal V_SB (fc). The input terminal 234 of the LPF236 is coupled to the output terminal 219A of the current-to-voltage converter 218A through a switch 296, the switch 296 having a control terminal 298 and terminals 300 and 302. Control terminal 298 is coupled for receiving modulated signal V_S(fc), terminal 300 is connected to output terminal 219A of current-to-voltage converter 218A, and terminal 302 is commonly connected to input terminal 234 of LPF236 and to terminal 290 of switch 284.

Output terminal 215 of OTA202A is coupled to LPF248 through switch 312 and current-to-voltage converter 218B. More specifically, output terminal 215 is connected to an input terminal of current-to-voltage converter 218B, and output terminal 217B of current-to-voltage converter 218B is connected to terminal 316 to form node 223A. Output terminal 219B of current-to-voltage converter 218B is connected to terminal 308 of switch 304. Switch 304 also has a control terminal 306 and a terminal 310, terminal 306 being coupled for receiving a modulated signal V_SP(fc), said terminal 310 is normally connected to input terminal 246 of LPF248 and to terminal 318 of switch 312. Output terminal 217B is coupled to input terminal 246 of LPF248 and to terminal 310 of switch 304 through switch 312. More specifically, switch 312 has a control terminal 314, a terminal 316 connected to output terminal 217B, and a terminal 318, which is commonly connected to input terminal 246 of LPF248 and to terminal 310 of switch 304. Control terminal 314 is coupled to receive modulation signal V from inverter 320_SPB (fc), i.e., the input terminal of inverter 320 is coupled for receiving modulation signal V_SP(fc), and the output terminal of inverter 320 is connected to terminal 314 of switch 312 for transmitting the inverted modulation signal V_SPB(fc)。

In operation, input voltage V_IN(fc) is applied to input terminal 204 of OTA 202A. Responsive to input voltage V_IN(fc), OTA202A generates a current I_tx(fc) that flows from output terminal 210 through capacitor 214 and into load 216, thereby generating voltage V on output terminal 210_tx(fc). Since the output terminal 210 is connected to the input terminal 206, the voltage V_tx(fc) appearing at the inputOn the seed 206. Thus, OTA202A buffers input signal V to load 216_IN(fc). In addition, OTA202 generates a current I_txCopy of (fc) I_{rx_I}(fc) and I_{rx_Q}(fc) and respectively conduct a current I_{rx_I}(fc) and I_{rx_Q}(fc) through output terminals 212 and 215. Current I_tx(fc) in the form of a copy of I_{rx_I}(fc) and I_{rx_Q}(fc) is the label and each current is referred to as a copy current or a replica current. Current I_{rx_I}(fc) is transmitted to current-to-voltage converter 218A, which generates voltage signal V on node 223_{rxp_I}(fc). Current I_{rx_Q}(fc) is transmitted to current-to-voltage converter 218B, which generates voltage signal V on node 223A_{rxp_Q}(fc)。

It should be noted that the modulation signal V_S(fc) controls switches 284 and 296 and modulates signal V_SP(fc) controls switches 304 and 312. When modulating signal V_S(fc) is at a logic high voltage level, switch 284 is closed and switch 296 is open, and when modulation signal V is on_S(fc) is at a logic low voltage level, switch 284 is open and switch 296 is closed. When modulating signal V_SP(fc) is at a logic high voltage level, switch 304 is closed and switch 312 is open, and when modulation signal V is on_SP(fc) at a logic low voltage level, switch 304 is open and switch 312 is closed. Thus, switches 284 and 296 are opened and closed to couple signal V_{rxn_I}(fc) with inverted signal V_SB (fc) are multiplied by each other and the signal V is_{rxp_I}(fc) and V_S(fc) are multiplied by each other. Multiplication of these signals forms a product signal that is combined to form the voltage signal V on the input terminal 234 of the LPF236_{MOD_I}. Output voltage V_{MOD_I}Equal to the current I shifted down to baseband (i.e., shifted down to DC)_txThe amplitude or real part of (fc). Because of the signal V_{rxn_I}(fc) and V_{rxp_I}(fc) is the fully differential signal, input signal V_INThe DC component of (fc) is removed, thereby increasing the noise immunity of network 350. LPF236 filters the output voltage V_{MOD_I}To remove any high frequency noise and the ADC 238 digitization is passedFiltered output voltage V_{MOD_I}So as to form a digital code Z on the output terminal 239_MAG216Which represents the magnitude of the impedance of the load 216, i.e., the digitized signal represents the magnitude of the in-phase component of the impedance of the load 216.

Similarly, switches 304 and 312 are opened and closed to couple signal V_{rxn_Q}(fc) with inverted signal V_SPB (fc) are multiplied by each other and the signal V is_{rxp_Q}(fc) and V_SP(fc) are multiplied by each other. The multiplication of these signals forms a product signal that is combined to form the voltage signal V on the input terminal 246 of the LPF248_{MOD_Q}. LPF248 filters the output voltage V_{MOD_Q}To remove any high frequency noise and ADC 250 digitizes the filtered output voltage V_{MOD_Q}So as to form a digital code Z on the output terminal 252_PHASE216Which represents the phase of the impedance of the load 216, i.e., the digitized signal represents the quadrature component of the impedance of the load 216.

Fig. 10 is a schematic diagram of a circuit element parameter measurement network 370 according to another embodiment of the present invention. Network 370 is similar to network 200 except that OTA202 is replaced with OTA202A and current-to-voltage converter 218 is absent from network 370. In addition, modulators 220 and 222 are replaced by modulators 220A and 222A, which modulators 220A and 222A are configured to receive a current rather than a voltage. The operation of network 370 is similar to the operation of network 200, except that mixers 220A and 222A mix current instead of voltage. Modulator 220A and LPF236 form an in-phase or real impedance detector 280B. Modulator 222A and LPF248 form a quadrature impedance detector 282B. The quadrature impedance detector 282B is also referred to as a virtual impedance detector or a reactive impedance detector.

FIG. 11 is a schematic diagram of a circuit element parameter measurement network 400 according to another embodiment of the present invention. Shown in fig. 11 is OTA202A coupled to load 216 through capacitor 214. The configuration of network 400 is similar to that of network 350, except that switches 284 and 296 and inverter 292 are replaced by a digital-to-analog converter (DAC)402, and switches 304 and 312 and inverter 320 are replaced by a DAC 404. More specifically, DAC402 has an input terminal 406 connected to the output terminal 212 of the OTA202A, coupled to receive an input signal D_SIN[N:0]And an output terminal 410 connected to the input terminal 234 of the LPF 236. DAC 404 has an input terminal 412 connected to output terminal 215 of OTA202A, coupled to receive an input signal D_COS[N:0]And an output terminal 416 connected to the input terminal 246 of the LPF 248. Signal D_SIN[N:0]And D_COS[N:0]Also known as digital codes.

In operation, input voltage V_IN(fc) is applied to input terminal 204 of OTA 202A. Responsive to input voltage V_IN(fc), OTA202A generates a current I_tx(fc) that flows from output terminal 210 through capacitor 214 and into load 216, thereby generating voltage V on output terminal 210_tx(fc). Since the output terminal 210 is connected to the input terminal 206, the voltage V_tx(fc) appears on input terminal 206. Thus, OTA202A buffers input signal V to load 216_IN(fc). In addition, OTA202 generates a current I_txCopy of (fc) I_{rx_I}(fc) and I_{rx_Q}(fc) and respectively conduct a current I_{rx_I}(fc) and I_{rx_Q}(fc) through output terminals 212 and 215. Current I_tx(fc) in the form of a copy of I_{rx_I}(fc) and I_{rx_Q}(fc) is the label and each current is referred to as a copy current or a replica current. Current I_{rx_I}(fc) is transferred to DAC 402, which passes the digital input code D_SIN[N:0]Modulating the current I_{rx_I}(fc) and generates a voltage V appearing on output terminal 410_{MOD_I}. LPF236 filters the output voltage V_{MOD_I}To remove any high frequency noise and the ADC 238 digitizes the filtered output voltage V_{MOD_I}So as to form a digital code Z on the output terminal 239_MAG216Which represents the magnitude of the impedance of the load 216, i.e., the digitized signal represents the magnitude of the in-phase component of the impedance of the load 216.

Current I_{rx_Q}(fc) is transferred to DAC 404, which encodes D by digital input_COS[N:0]Modulating the current I_{rx_Q}(fc) and generates a voltage V appearing on output terminal 416_{MOD_Q}. LPF248 filters the output voltage V_{MOD_Q}To remove any high frequency noise and ADC 250 digitizes the filtered output voltage V_{MOD_Q}So as to form a digital code Z on the output terminal 252_PHASE216Which represents the phase of the impedance of the load 216, i.e., the digitized signal represents the quadrature component of the impedance of the load 216.

It should be noted that network 400 has been shown to modulate current I using a sinusoidal current input code_{rx_I}(fc) and I_{rx_Q}(fc). However, the current I_{rx_I}(fc) and I_{rx_Q}(fc) may be converted to a voltage signal such that DACs 402 and 404 modulate the voltage signal with a sinusoidal digital voltage input code, i.e., in this embodiment, digital code D_SIN[N:0]And D_COS[N:0]Is a digital voltage signal.

FIG. 12 is a schematic diagram of a circuit element parameter measurement network 500 according to another embodiment of the present invention. Network 500 includes OTA202, capacitor 214, and load 216, which were described above with respect to fig. 2. In addition, network 500 includes a bandpass filter 502 having an input terminal 504 connected to output terminal 212 of OTA202 and an output terminal 506 connected to an input terminal 512 of an analog-to-digital converter (ADC) 510. ADC 510 has an output terminal 514 connected to modulators 520 and 522. An input terminal 524 of modulator 520 and an input terminal 526 of modulator 522 are connected to output terminal 514 to form a node 528. The modulator 520 further has an input terminal 530 and an output terminal 532, the input terminal 530 being coupled for receiving a modulated signal V_S(n), the output terminal 532 is connected to the input terminal 536 of the Low Pass Filter (LPF) 534. Modulated signal V_S(n) may be a periodic signal that is digitized, such as a sine wave, square wave, sawtooth, and so forth. Preferably, the modulation signal V_S(n) is a digitized sine wave. It should be noted that the modulation signal V_S(n) is the sum of the input signal V_IN(fc) of the same type and having the same input signal V_IN(fc) the same frequency. Output signal Z_MAG216AppearOn the output terminal 539 of the LPF 534, the signal Z is output here_MAG216Representing the magnitude of the impedance with respect to the load 216, i.e., the digitized signal represents the magnitude of the in-phase component of the impedance of the load 216. Modulator 520 and LPF 534 form an in-phase or real impedance detector 280C.

Modulator 522 has an input terminal 529 and an output terminal 527, with input terminal 529 coupled to receive modulated signal V through phase shift element 544_SP(n), the output terminal 527 coupled to the input terminal 540 of LPF 536. Phase shift element 544 shifts the modulated signal V_S(n) to generate a phase-shifted modulated signal V_SP(n) having a modulation signal V_S(n) the same frequency and amplitude, but different phase. For example, the signal V_S(n) and V_SP(n) may have a phase difference of 90 degrees, e.g. signal V_SP(n) and the signal V_S(n) has a phase difference of 90 degrees. Output signal Z_PHASE216Appears at output terminal 552 of LPF 536, where output signal Z is_PHASE216The phase representing the impedance with respect to the load 216, i.e., the digitized signal represents the quadrature component of the impedance of the load 216. Modulator 522 and LPF 536 form a quadrature impedance detector 282C. The quadrature impedance detector 282C is also referred to as a virtual impedance detector or a reactive impedance detector.

FIG. 13 is a schematic diagram of a circuit element parameter measurement network 430 according to another embodiment of the present invention. Shown in fig. 13 is OTA202A, which has input terminals 204 and 206 and output terminals 210, 212, and 215. Input terminal 204 is coupled for receiving an input signal V_IN(fc) and input terminal 206 is coupled to output terminal 210, which is connected to input/output node 431. Output terminal 215 is coupled to input/output node 433 through switch 432, and output terminal 212 is coupled to input/output node 433 through switch 440. More specifically, switch 432 has a switch coupled to receive input signal V through inverter 448_SControl terminal 434 of (fc), terminal 436 connected to output terminal 215, and terminal 438 connected to input/output node 433. Inverter 448 converts signal V_S(fc) is inverted to generate a signal appearing at terminal 434Number V_SB (fc). The switch 440 has a switch coupled to receive an input signal V_SControl terminal 442 of (fc), terminal 444 connected to output terminal 212, and terminal 446 connected to input/output node 433 and to terminal 438 of switch 432.

The network 430 further includes an operational amplifier 450 having a non-inverting input terminal 452, an inverting input terminal 454, and an output terminal 456, where the non-inverting input terminal 452 is coupled to receive a bias voltage V_BIASAnd an inverting input terminal 454 is coupled to an output terminal 456 and to the input/output node 435. Output terminal 456 of operational amplifier 450 is coupled to output terminals 438 and 446 through resistor 458 and to input/output node 433. A filter capacitor 460 is connected between input/output node 433 and input/output node 435. In addition, input/output nodes 431 and 435 are connected to terminals 462 and 464 of a current transformer 466. Preferably, current transformer 466 is a single wound, single current transformer circuit. Although resistor 458 and filtering capacitor 460 have been shown as resistors and capacitors external to the semiconductor chip on which OTA202A, operational amplifier 450, and switches 432 and 440, and inverter 448 are fabricated, this is not a limitation of the present invention. The resistor 458 may be an on-chip resistor and the filtering capacitor 460 may be an on-chip capacitor, or one of the resistor 458 and the filtering capacitor 460 may be a filtering capacitor. It should be noted that input/output nodes 431, 433 and 435 may be input/output pins of a packaged semiconductor chip.

In operation, the sinusoidal signal V_IN(fc) is applied to input terminal 204. Responsive to a sinusoidal input signal V_IN(fc), OTA202A generates I_tx(fc) which flows from output terminal 210 to terminal 462 of current transformer 466. In addition, OTA202A generates a current I_txCopy of (fc) I_nx(fc) and I_px(fc) and respectively conduct a current I_nx(fc) and I_px(fc) through output terminals 212 and 215. Voltage V_BIASIs connected to the input terminal 452 of the operational amplifier 450 and is transmitted to the output terminal 456. Bias voltage V_BIASTo terminal 464 of current transformer 466. Switches 432 and 440 are responsive to an input voltage V input to a control terminal 442_S(fc) is opened and closed.

Fig. 14 is a schematic diagram of a circuit element parameter measurement network 470 according to another embodiment of the present invention. Shown in fig. 14 is OTA202A, operational amplifier 450, and switches 432 and 440. Output terminal 210 is connected to an input/output node 492 which is connected to a terminal 496 of a current transformer 497 through a series resistor 493 and a capacitor 494. It should be noted that capacitor 494 is an optional component that may be omitted. The connection of output terminals 212 and 215 to switches 432 and 440 has been described with respect to network 430 shown in fig. 13. It should be noted that the connection of terminals 438 and 440 of switches 432 and 440, respectively, is different from that described above with respect to fig. 13 and will be described below.

Network 470 also includes an operational amplifier 472 having a non-inverting input terminal 474 coupled to an output terminal 478 through a resistor 480. Output terminal 478 is coupled to input/output node 490 through resistor 308. Input/output node 490 is coupled to ground through, for example, capacitor 498. Operational amplifier 472 has an inverting input terminal 476 commonly connected to output terminal 456, an input/output node 435, and a terminal 496. Terminals 438 and 446 of switches 432 and 440, respectively, are commonly connected to terminal 486 of switch 482 and to non-inverting input terminal 474. Switch 482 has a coupling for receiving an input signal V_CNTLTo node 491, and a terminal 486, which terminal 486 is commonly connected to the non-inverting input terminal 474 of operational amplifier 472 and to the terminal 438 of switch 432. A terminal of resistor 493, a terminal of a capacitor, and a terminal 495 of current transformer 497. The other terminal of capacitor 494 is commonly connected to input/output pad 435 and to input terminal 496 of current transformer 497. Preferably, current transformer 497 is a single wound single current transformer circuit. Input/output pads 435, 490, 491, and 492 are input/output pins of a packaged semiconductor chip.

Although specific embodiments are disclosed herein, there is no intention to limit the invention to the embodiments disclosed. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. The invention is intended to embrace all such modifications and variations as fall within the scope of the appended claims.

Claims (6)

1. A circuit (200) for determining a circuit element parameter of a current transformer, comprising:

a transconductance amplifier (202) having first and second input terminals and first and second output terminals, the first output terminal of the transconductance amplifier being coupled to the input terminal of the current transformer;

a current-to-voltage converter having an input and an output, the input of the current-to-voltage converter being coupled to the second output terminal of the transconductance amplifier;

a first multiplier (220) having a first input terminal and a second input terminal and an output terminal, the first input terminal being coupled to the output terminal of the current-to-voltage converter and the second input terminal being coupled for receiving a first electrical signal (V)_S(fc)); and

a second multiplier (222) having first and second input terminals and an output terminal, the first input terminal being coupled to the output terminal of the current-to-voltage converter.

2. The circuit (200) of claim 1, wherein the circuit (200) is a single-winding, single-current transformer impedance measurement circuit.

3. The circuit (200) of claim 1 or 2, further comprising a phase shift element (244) having an input terminal and an output terminal, the input terminal being coupled for receiving the first electrical signal (vs (fc)) and the output terminal being coupled to the second input terminal of the second multiplier (222).

4. A method for determining a circuit element parameter using the circuit of claim 1, comprising:

providing a first voltage signal (V) at a first input terminal of the transconductance amplifier_IN(fc))；

Generating a first current signal (I) at a first output terminal of the transconductance amplifier in response to the first voltage signal at the first input terminal of the transconductance amplifier_tx(fc))；

From said first current signal (I)_tx(fc)) generates a second current signal (I)_rx(fc))；

Generating a second voltage signal (V) in response to the second current signal_rx(fc)); and

applying the second voltage signal (V)_rx(fc)) is input to a first multiplier (220) and a second multiplier (222).

5. A method for determining a circuit element parameter using the circuit of claim 1, comprising:

providing a first voltage signal (V) at a first input terminal of the transconductance amplifier_IN(fc))；

Generating a first current signal (I) at an output terminal of the transconductance amplifier in response to the first voltage signal at a first input terminal of the transconductance amplifier_tx(fc))；

From said first current signal (I)_tx(fc)) generates a second current signal (I)_rx(fc))；

Generating a second voltage signal (V) in response to the second current signal_rx(fc))；

Applying the second voltage signal (V)_rx(fc)) to a first multiplier (220) and a second multiplier (222);

applying the second voltage signal (V)_rx(fc)) and a third voltage signal (V)_S(fc)) to generate a fourth voltage signal (V)_{MOD_I})；

Applying the fourth voltage signal (V)_rx(fc)) and a fifth voltage signal (V)_SP(fc)) to generate a sixth voltage signal (V)_{MOD_Q})；

Applying the fourth voltage signal (V)_{MOD_I}) And the sixth voltage signal (V)_{MOD_Q}) Inputting a first low pass filter (236) and a second low pass filter (248) to generate a first filtered electrical signal and a second filtered electrical signal, respectively, the first low pass filter coupled to the output terminal of the first multiplier and the second low pass filter coupled to the output terminal of the second multiplier; and

converting the first filtered electrical signal and the second filtered electrical signal into a first digitally filtered electrical signal (Z)_MAG216) And a second digitally filtered electrical signal (Z)_PHASE216)。

6. A method for determining a circuit element parameter using the circuit of claim 1, comprising:

providing a first voltage signal (V) at a first input terminal of the transconductance amplifier_IN(fc))；

Generating a first current signal (I) at an output terminal of the transconductance amplifier in response to the first voltage signal at a first input terminal of the transconductance amplifier_tx(fc))；

From said first current signal (I)_tx(fc)) generates a second current signal (I)_rx(fc))；

Generating a second voltage signal (V) in response to the second current signal_rx(fc))；

Providing a third voltage signal (V)_S(fc))；

By the third voltage signal (V)_S(fc)) generates a fourth voltage signal (V)_SP(fc)), wherein the fourth voltage signal (V)_SP(fc)) and the third voltage signal (V)_S(fc)) are out of phase with each other;

applying the second voltage signal (V)_rx(fc)) and the third voltage signal (V)_S(fc)) are combined together to form a first modulated signal (V)_{MOD_I}) (ii) a And

applying the second voltage signal (V)_rx(fc)) and the fourth voltage signal (V)_SP(fc)) are combined together to form a second modulated signal (V)_{MOD_Q})。