HK1156155B - Capacitor test method and circuit therefor - Google Patents

Description

Capacitor testing method and circuit thereof

Technical Field

The present invention relates generally to electronic devices, and more particularly to semiconductors, structures thereof, and methods of forming semiconductor devices.

Background

In the past, the semiconductor industry used various methods and structures to form voltage regulator circuits that could be used to provide a regulated voltage to a load. In applications where a regulator is used to supply power to a load, a filter capacitor is typically connected to the output of the voltage regulator in order to filter noise from the voltage and provide stored energy to the load or to form a dominant pole in the regulator control loop. In some cases, the equivalent series resistance of the capacitor increases or the capacitor value decreases, which results in an increase in the amount of noise in the output voltage or may also result in instability of the control loop. In other cases, the connection between the capacitor and the output of the voltage regulator may become damaged such that the capacitor is no longer connected, thereby also causing an increase in the amount of noise on the output voltage or control loop instability because the filtering action of the capacitor is no longer effective.

Fig. 1 schematically shows a prior art circuit for detecting a missing capacitor. The circuit of fig. 1 uses a peak detector to detect when the ac portion of the output voltage increases above a certain value. The regulator includes a feedback circuit illustrated by resistors R1-R3. At periodic time intervals, a periodic pulse is applied to transistor T1 to periodically activate transistor T1 and short the value of resistor R3, thereby periodically changing the values of the resistive divider and the feedback voltage. During the time interval that the periodic pulse is applied to transistor T1, the peak detector will check the output voltage for an increasing value of the alternating part of the output voltage. If an increase is detected, the capacitor is assumed to be absent. However, periodically changing the value of the resistive divider also results in undesirable changes and overshoots in the output voltage. Another problem is that EMI may also cause an alternating signal on the output voltage and the circuit of fig. 1 cannot detect the difference between EMI interference and the missing capacitor.

Accordingly, it is desirable to have a method and circuit that detects the missing capacitor and determines the difference between the externally coupled EMI interference and the missing capacitor.

Disclosure of Invention

According to one aspect of the present invention, there is provided a voltage regulator having a component test circuit, comprising: the voltage regulator arranged to receive an input voltage and form an output current to charge an output capacitor so as to form an output voltage on an output on the voltage regulator, the voltage regulator having a normal mode of operation and an open loop mode of operation; an error amplifier coupled to receive a feedback voltage representative of the output voltage and to form an error signal on an output of the error amplifier, the voltage regulator being arranged to regulate the output voltage in response to the feedback voltage during the normal mode of operation; a current control circuit arranged to receive the error signal from the error amplifier and to store a value of the error signal during the normal mode of operation, the current control circuit being arranged to form an output signal representative of the stored value of the error signal during the open loop mode of operation; an output circuit arranged to receive the output signal from the current control circuit during the open loop mode of operation and to form the output current representative of the output signal; a first circuit arranged to receive the output voltage and to detect an alternating current signal at a direct current value of the output voltage, the first circuit being arranged to form a first control signal indicative of the detection of the alternating current signal; and logic circuitry coupled to receive the first control signal and to assert a second control signal using the first control signal and to set the operating mode of the voltage regulator to the open loop operating mode, the logic circuitry being arranged to detect a component fault using the first control signal and to responsively assert a third control signal after the component fault is detected.

According to another aspect of the invention, there is provided a method of forming a voltage regulator having a component test circuit, comprising: setting the voltage regulator to receive an input voltage and form an output current to charge a capacitor in order to regulate an output voltage on an output of the voltage regulator, the voltage regulator having a normal mode of operation and an open loop mode of operation; setting the voltage regulator to receive a feedback signal representative of the output voltage and to regulate the output voltage in response to the feedback signal during the normal mode of operation; setting a first circuit to detect an alternating current signal of the output voltage; setting a second circuit to set the voltage regulator to operate in the open-loop operating mode in response to the first circuit detecting the alternating current signal on the output voltage within a first time interval; and setting the second circuit to detect a component fault in response to the first circuit not detecting an ac signal on the output voltage in response to the voltage regulator operating in the open loop mode of operation and to detect an absence of the component fault in response to the first circuit detecting a presence of an ac signal on the output voltage while operating in the open loop mode of operation.

According to yet another aspect of the present invention, there is provided a method of forming a test circuit, comprising: setting a control circuit to operate in an analog mode to receive an input voltage and form an output current to charge an output capacitor so as to form an output signal on an output of the control circuit, the control circuit having a normal mode of operation and an open loop mode of operation; setting the control circuit to receive a feedback signal representative of the output signal and to adjust the output signal in response to the feedback signal during the normal mode of operation; setting the control circuit to detect an alternating current signal on the output signal and responsively set the control circuit to operate in an open loop mode of operation; and setting the control circuit to determine a component fault by determining whether the alternating current signal is discontinuous while operating in the open loop mode of operation.

Drawings

FIG. 1 is a schematic diagram showing a portion of a prior art voltage regulator;

FIG. 2 schematically illustrates an example of a voltage regulation system that includes a portion of an embodiment of an example of a voltage regulator in accordance with this invention;

FIG. 3 is a graph having plots illustrating portions of some signals formed during operation of the regulator of FIG. 2 in accordance with the present invention;

FIG. 4 is a simplified flow diagram illustrating some of the operations performed by the voltage regulator of FIG. 2 in accordance with the present invention;

FIG. 5 schematically illustrates a block diagram of an example of a closed loop control circuit in accordance with the present invention;

FIG. 6 is an example of a simplified flow chart showing some of the operations performed by the circuits of FIGS. 2 and 5 in accordance with the present invention; and

fig. 7 illustrates an enlarged plan view of a semiconductor device including the voltage regulator of fig. 2 in accordance with the present invention.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. In addition, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, current carrying electrode means an element of a device that carries current through the device, such as a source or drain of an MOS transistor or an emitter or collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device, such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel devices or P-channel devices, one of ordinary skill in the art will recognize that complementary devices are also possible in accordance with the present invention. Those skilled in the art will recognize that the word "during, at, and when used herein in relation to the operation of a circuit" is not an exact term indicating that an action will occur as soon as there is an initiating action, but rather that there may be some small but reasonable delay, such as a propagation delay between reactions instigated by the initiating action. In addition, the term "simultaneously" means that a certain action occurs at least for a certain part of the duration of the initiating action. Use of the word "about" or "substantially" means that the parameter of the value of an element is expected to be very close to a specified value or position. However, as is well known in the art, there is always a small difference preventing the value or position from being exactly as specified. It is well established in the art that differences of up to at least ten percent (10%) (and up to twenty percent (20%) for semiconductor dopant concentrations) are reasonable differences from the ideal target exactly as described. When used with reference to the state of a signal, the word "active" means the active state of the signal, and "inactive" means the inactive state of the signal. The actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used. Thus, "active" may be high voltage or high logic or low voltage or low logic, depending on whether positive or negative logic is used, and "inactive" may be low voltage or low logic or high voltage or high logic, depending on whether positive or negative logic is used. A positive logic convention is used herein, but those skilled in the art will appreciate that a negative logic convention may also be used.

Detailed Description

Fig. 2 schematically illustrates an example of a voltage regulation system 20 that includes a portion of an embodiment of an example of a voltage regulator 25. The voltage regulator 25 is configured with a component test circuit that, among other functions, detects a missing output capacitor on the output of the regulator 25 and determines the difference between the missing output capacitor and the ac signal caused by the EMI interference on the dc value of the output voltage. As will be seen further hereinafter, the regulator 25 and the included component test circuit are also configured to detect various component faults that may cause instability in the control loop including the regulator 25, wherein these component faults may cause an ac signal to appear at the dc value of the output voltage. These component failures include, among other things, a lack of an output capacitor, a lack of connection between the output capacitor and the output of regulator 25, a change in the value of the capacitor, an increase in the equivalent series resistance value of the capacitor, or an increase in the resistance of any connection between the output of regulator 25 and the load connected to the output, including an increase in the resistance between the output of regulator 25 and the output capacitor. As used herein, the term "component failure" refers to these types of component failures. The regulator 25 is also arranged to detect differences between such component failures and the ac signal caused by EMI interference on the dc output voltage.

The regulator 25 comprises an input terminal or input 26 arranged to receive an input voltage, for example a DC voltage, from the voltage source 18. Regulator 25 also includes a common voltage return terminal or return 27 that is commonly connected to a common voltage value, such as the negative voltage of source 18. Regulator 25 is configured to form a regulated output voltage on output 57 to provide power to a load, such as load 17. An output capacitor 16 is connected to output 57 to filter out some noise on the output voltage and provide a storage element to help supply power to load 17. Regulator 25 generally includes an error amplifier 82 coupled to receive a feedback (EB) signal representative of the output voltage formed on output 57 such that regulator 25 may regulate the value of the output voltage in response to the value of the feedback signal. Accordingly, amplifier 82 also receives a reference voltage from a reference generator circuit (shown as Ref 1), and regulator 25 regulates the output voltage such that the FB signal is substantially equal to the reference voltage. Regulator 25 also includes a detection circuit 60, a current control circuit 33, an evaluation circuit 90, and an output circuit including transistors 48, 51, 53, 54, 86, and 87, and an inverter 88. The multiplexer circuit 85 of the output circuit includes transistors 86 and 87 along with an inverter 88. In most embodiments, regulator 25 also includes Over Voltage (OV) and Under Voltage (UV) detection circuits that form respective Over Voltage (OV) and Under Voltage (UV) signals. For the embodiment of regulator 25 shown in fig. 2, comparator 95 is shown as an Under Voltage (UV) detection circuit and comparator 96 is shown as an Over Voltage (OV) detection circuit. Those skilled in the art will recognize that resistors 97-99 and reference voltage generator (Ref 3) are also part of the OV and UV detection circuits. In some embodiments, regulator 25 may also include an internal voltage regulator 30 coupled to receive an input voltage from input 26 and form an internal operating voltage on output 31 for operating some elements of regulator 25.

Those skilled in the art will recognize that the output capacitor 16 forms the dominant pole affecting the stability of the control loop of the system 20 including the regulator 25. In some embodiments, the amplifier 82 may also include a stability compensation element to compensate for the frequency response of the control loop so that the control loop is stable for the frequency range over which the control loop operates, and in other embodiments the amplifier 82 may not have such a compensation element. If the capacitor 16 is missing or not connected, the frequency compensation variations and the control loop may become unstable and form an ac signal at the dc value of the output voltage. Additionally, other component failures can also change the center frequency of the dominant pole and cause it to shift in frequency, which can also cause instability and result in an ac signal at the dc value of the output voltage. The ac signal on the output voltage caused by the component failure may result in improper operation of the load 17 or may damage the load 17. Accordingly, it may be desirable to detect such component failures and to distinguish such failures from EMI-induced ac signals.

The detection circuit 60 is arranged to detect an alternating current signal developed on the output voltage and includes an output forming a Detected (DT) control signal. For the exemplary embodiment of regulator 25 shown in fig. 2, circuit 60 includes an amplifier 68, a transistor 69, capacitors 62, 73, and 74, resistors 63, 64, 75, and 72, a comparator 78, and a reference generator circuit (shown as Ref 2). The current control circuit 33 is arranged to form a control signal having a substantially fixed value at the output of the circuit 33. An exemplary embodiment of current control circuit 33 includes an output 45, a switch (e.g., transistor 44), resistors 35 and 38, a storage element (e.g., capacitor 36), and a voltage-to-current converter such as amplifier 40 and transistor 42. Some elements of regulator 25, such as amplifier 82 and Ref 3, operate from the internal operating voltage on output 31 of regulator 30. Most of the components of regulator 25, such as circuits 33 and 60, use an operating voltage substantially equal to the value of the output voltage on output 57. Although not shown in fig. 2 for clarity of the drawing, amplifier 40, comparators 95 and 96, and evaluation circuit 90 also typically operate from voltages substantially equal to the value of the output voltage. Those skilled in the art will recognize that circuits 33 and 60 operate from a voltage substantially equal to the output voltage because it is regulated more than the internal operating voltage of regulator 30. However, the source of the operating voltage may be different as long as the operating voltage is sufficiently adjusted.

As will be seen further hereinafter, the regulator 25 is formed to include two modes of operation-a normal mode of operation and an open loop mode of operation. Regulator 25 forms an output current 56 for charging capacitor 16 and providing current to load 17. In the normal operating mode, regulator 25 operates as a closed loop control system and regulates the value of the output voltage and the value of current 56 in response to the feedback signal. The regulator 25 regulates the output voltage to a target value within a range of values near the target value. For example, the target value may be five volts (5v), and the range of values may be five volts plus or minus five percent (5%). When operating in the open loop operating mode, regulator 25 operates as an open loop system and does not use the value of the FB signal to form the output voltage or to regulate the output voltage. In a preferred embodiment, the open loop mode of operation of regulator 25 forms output voltage and current 56 in response to a signal having a substantially fixed value rather than in response to a feedback signal. In other embodiments, regulator 25 may not provide current 56 during the open loop mode of operation.

The evaluation circuit 90 is configured to operate the regulator 25 in an open loop mode of operation or a normal mode of operation, and is further configured to determine the absence or presence of a component fault and determine a difference between the signal caused by EMI and the component fault. For the exemplary embodiment of regulator 25 shown in fig. 2, circuit 90 includes an output that forms an open loop control signal or OL signal and another output that forms a Fault (FL) control signal or FL signal. In the preferred embodiment, the circuit 90 is a digital logic circuit.

Fig. 3 is a graph having plots illustrating some states or values of some signals formed during operation of regulator 25. The abscissa indicates time and the ordinate indicates the increasing value of the signal shown. Curve 105 shows the value of the output voltage on output 57. Curve 108 shows the value of the DT signal on the output of circuit 60. Curve 111 shows the OL signal of circuit 90 and curve 119 shows the FL signal of circuit 90. Plot 117 shows the state of the TBT control bit or flag bit, which is typically internal to circuit 90. Curve 124 shows the OV signal on the output of comparator 96 and curve 127 outputs the UV signal on the output of comparator 95. Those skilled in the art will recognize that the ac signal formed on the output voltage on output 57 may not be a periodic ac signal with a smooth amplitude and period, but may have a different frequency and amplitude. Therefore, the curve 105 shows the alternating current signal as a regular alternating current signal only for the sake of clarity of the drawing, and the shape of the waveform shown by the curve 105 is not expected to represent the waveform of the alternating current signal formed at the direct current value of the output voltage.

Fig. 4 is a simplified flowchart showing some operations performed by the regulator 25 or the operation state of the regulator 25. This description makes reference to fig. 2, 3 and 4 in order to explain the operation of the regulator 25.

After power is supplied to the regulator 25, for example from the voltage source 18, the regulator 25 is initialized to operate in a normal operation mode. This can be seen in the flow chart of fig. 4, where regulator 25 disables the OL and FL signals on the output of circuit 90 when enabled, followed by a settling time in block 203 to allow the circuitry of regulator 25 to settle, shown in flow chart blocks 200, 202 and 203. Assuming a positive logic convention is used, the circuit 90 forces the OL signal on the OL output of the circuit 90 low to negate the OL signal. The low OL signal disables transistor 87 and enables transistor 86 through inverter 88. Enabling transistor 86 couples the error signal from the output of amplifier 82 to node 49, which causes current 50 to flow through transistor 48. The error signal on the output of amplifier 82 forms a current 80 on the output of amplifier 82 such that current 80 represents the error signal. Current 80 flows through transistor 48 as current 50. Transistor 48 is connected to transistor 51 in a current mirror arrangement, so current 50 in transistor 48 causes current 52 to flow through both transistors 51 and 53. Due to the current mirror arrangement, current 52 is proportional to the value of current 50 and therefore current 80. Transistor 53 is connected to output transistor 54 in a current mirror arrangement such that current 55 flows through transistor 54, and thus current 55 is proportional to current 52 and proportional to current 50, and thus proportional to the value of the error signal. A small portion of current 55 flows through resistors 13 and 14 to form the FB signal; however, a majority of current 55 flows through output 57 as output current 56. Those skilled in the art will recognize that the value of current 56 may become smaller when load 17 is in the de-energized state, and thus, the value flowing through resistors 13 and 14 may be a larger percentage of current 55, but current 56 is still greater than the current flowing through resistors 13 and 14. As can be seen, as the value of the output voltage on output 57 changes during the normal operating mode, the value of the feedback signal on node 15 changes, causing the value of output current 56 to also change in order to adjust the value of the output voltage. Thus, the regulator 25 is not a switching regulator and does not switch the output current 56 between the on state and the off state to regulate the output voltage.

Transistor 48 is also connected to transistor 47 in a current mirror arrangement, thereby forming a current 46 through transistor 47 that is proportional to the value of current 50 and thus to the value of current 80. Current 46 also flows through resistor 35 of circuit 33, forming a voltage across resistor 35 that is representative of the error signal formed by error amplifier 82. Because transistor 44 of circuit 33 is a P-channel transistor, the low OL signal from circuit 90 also enables transistor 44. Enabling transistor 44 allows capacitor 36 to be charged to substantially the same voltage formed across resistor 35, thus forming a voltage on capacitor 36 that is representative of the average value of the error signal formed by amplifier 82. Amplifier 40, transistor 42, and resistor 38 form a voltage-to-current converter circuit that forms a current 43 through an output 45 of circuit 33 that is representative of the error signal from amplifier 82. However, the low OL signal from current 90 holds transistor 87 disabled so that current 43 is not connected to affect the value of the output voltage on output 57.

Circuit 60 receives an output voltage from output 57 on input 61 of circuit 60. Capacitor 74 and resistor 75 form a voltage source for providing an operating voltage to operate the elements of circuit 60 including amplifier 68 and comparator 78. Capacitor 74 receives the input voltage from input 61 through resistor 75, which charges capacitor 74 to a voltage substantially equal to the output voltage on output 57. Capacitor 74 thus forms an operating voltage for the elements of circuit 60 on node 77. Resistor 75 and capacitor 74 form a filter that reduces noise on node 77, thereby improving the quality of the voltage. Those skilled in the art will recognize that there may be some small voltage drop across resistor 75, but the voltage at node 77 is substantially equal to the value of the output voltage on output 57. Circuit 60 also receives an input voltage on input 61 to detect an ac signal that may develop on, and thus affect, the dc value of the output voltage on output 57. Capacitor 62 decouples the detection circuit of circuit 60 from the dc value of the output voltage on output 57, allowing only the ac component or ac signal of the output voltage to be coupled to amplifier 68. Resistors 63 and 64 provide a bias voltage at node 65 to bias the non-inverting input of amplifier 68 to a value that facilitates detection of the ac signal from capacitor 62. If no ac signal is formed on the output voltage, amplifier 68 forms a voltage on node 70 that is substantially equal to the bias voltage on node 65, and thus capacitor 73 is charged to a voltage that is substantially equal to the voltage on node 65. The value of the voltage from Ref 2 is selected such that the output of comparator 78 is invalid for this value of the voltage on capacitor 73. If there is an ac signal on the dc value of the output voltage on output 57, the ac component of the ac signal is coupled across capacitor 62 to the non-inverting input of amplifier 68, causing amplifier 68 to increase the value of the voltage on node 70, which increases the voltage on capacitor 73 to a value substantially equal to the bias voltage on node 65 plus the peak value of the ac signal. The additional voltage added to the voltage of capacitor 73 forces the output of comparator 78 high, asserting the Detected (DT) control signal. Thus, the circuit 60 detects the presence of an ac signal on the output voltage and responsively asserts the DT control signal. Those skilled in the art will recognize that other values besides the peak value of the ac signal may be used to detect the presence of the ac signal.

In a preferred embodiment, capacitor 62 together with resistors 63 and 64 form a high pass filter having a corner frequency below the frequency of the alternating signal to be detected. Capacitor 73 and resistor 72 form a low pass filter that filters the ac signal from the signal formed on node 70. The gain-bandwidth product of amplifier 68 limits the maximum frequency of the ac signal that can be detected by circuit 60. In an exemplary embodiment, the frequency of the AC signal formed at the output voltage has a frequency of approximately two to five megahertz (2-5MHz), and the frequency range of the circuit 60 is approximately one to ten megahertz (1-10 MHz). For this example. The corner frequency of the filter formed by capacitor 62 and resistors 63 and 64 is approximately six hundred kilohertz (600 kHz). Because the circuit 60 uses peak detection, the detector 60 typically detects the AC signal within one or two (1-2) cycles of the AC signal.

The settling time developed at flowchart block 203 is generally used to provide time for circuits 33 and 60 to settle in addition to multiplexer 85 to allow the control loop and output voltage to settle. As illustrated by the flow diagram 205, after the settling delay illustrated by the flow diagram 203, the regulator 25 operates in the normal operating mode and adjusts the value of the output voltage in response to the FB signal, and the circuit 60 monitors the output voltage of the ac signal at the dc value of the output voltage.

Referring again to fig. 3, assume that at time T the ac signal begins to appear in the output voltage. The ac signal may be caused as a result of EMI causing a signal on the output voltage or may be caused by a component failure including capacitor 16 not connected to output 57. For purposes of this exemplary explanation, it is assumed that capacitor 16 is connected and there is no component failure. As curve 108 illustrates at time T0, detection circuit 60 detects the ac signal and asserts the DT signal. The circuit 90 receives the active DT signal and uses the state of the DT signal to determine whether the ac signal is occurring continuously during the time interval shown by time interval T1 in block 207 and 209. If the AC signal stops at any time during this time interval, circuit 60 deasserts the DT signal and regulator 25 continues to adjust the value of the output voltage in response to the FB signal, as illustrated by flow blocks 205 and 208. If the AC signals are present for less than the T1 time interval, they are assumed to be transient external disturbances, such as those caused by EMI, and are not further evaluated.

If the ac signal is substantially continuous during the T1 time interval as illustrated by time intervals T0 through T1 in fig. 3, the ac signal may result from a component failure including capacitor 16 not connected to output 57 or from EMI interference. To determine the cause of the ac signal, circuit 90 asserts the OL signal to set regulator 25 to operate in an open loop operating mode, as illustrated by flow block 211. The high OL signal disables transistor 44 of circuit 33 thereby decoupling capacitor 36 from resistor 35 so that capacitor 36 remains charged to a voltage representative of the average value of the error signal while the OL signal is active. Thus, the capacitor 36 stores the average value of the error signal. As a result, when the preferred embodiment of regulator 25 operates in the open-loop mode of operation, the voltage across capacitor 36, and therefore the value of current 43, remains substantially fixed regardless of the value of the output voltage. The high OL signal also disables transistor 86 through inverter 88, thereby decoupling circuit 33 from receiving a signal representative of the error signal. The high OL signal also enables transistor 87 which couples current 43 to transistor 48. Because the current through transistor 48 is now current 43, the current mirror settings of transistors 48 and 51 and the current mirror settings of transistors 53 and 54 cause output current 56 to have a substantially constant value that is proportional to the value of current 43. Thus, current 56 has a substantially constant value. As will be appreciated by those skilled in the art, the exemplary embodiment of circuit 33 uses capacitor 36 to store the average value of the error signal. When an ac signal is present at the output voltage, the average value of the error signal comprises an average value of the undesired ac signal. Thus, the stored value of the error signal may be too large for the desired value of the output voltage. Thus, in a preferred embodiment, current 56 is formed to represent less than the error signal and, therefore, is formed to be proportional to the value of such error signal. The lower value of current 56 helps to keep the output voltage at a value that does not increase to a value that can damage load 17. For example, the current 56 may be formed to represent a value proportional to the value of the error signal, such as about eighty percent (80%) of the value of the error signal. The ratio between the regions of current mirror transistors 47 and 48 may be selected to form the ratio. In other embodiments, current 56 may have a different ratio than the value of the error signal just prior to operating in the open loop mode of operation or may have a substantially constant value representative of the value of the error signal, or may have other fixed values. For example, current 56 may be fixed to some value representative of the general power consumption of load 17. In other embodiments, the current 56 may not be formed during the open loop mode of operation, or may be formed for only a portion of the open loop mode of operation.

As illustrated by flow block 213, the circuit 90 initializes a stabilization delay (Ts, see fig. 3) after asserting the OL signal to allow the circuitry of the regulator 25 to stabilize and avoid transients. The OV and UV signals are checked during the settling time to ensure that the output voltage remains within the desired operating range. Because capacitor 16 is assumed to be connected for this example, the value of the output voltage is not expected to cause OV and UV to occur. However, if OV or UV is active during the settling delay time interval, circuit 90 asserts the Fault (FL) control signal on output 91 as a high signal as shown by dashed line 120 in plot 119 and returns regulator 25 to operating in the normal operating mode. This sequence of operations is illustrated by the flow block 214 in the settling delay sequence.

Referring back to the waveforms of fig. 3, after time T1 regulator 25 begins operating in the open loop mode of operation. If none of the component failures occur, the AC signal on the output voltage will continue while regulator 25 is operating in the open loop mode of operation and detector 60 will detect the AC signal. Therefore, the DT signal will remain active because the ac signal is continuing. However, if a component failure occurs, including the capacitor 16 being missing or simply no longer connected to the output 57, then the ac signal will cease because no more dominant pole is connected to the output 57 causing the ac signal, or because the frequency of the dominant pole shifts such that the ac signal is no longer formed. Circuit 90 determines whether a component fault exists by determining whether the ac signal continues substantially unchanged for the second time interval or whether a component fault does not exist by determining whether the ac signal does not exist at any time during the second time interval. To determine whether the ac signal is present substantially continuously during the second time interval, a preferred embodiment of circuit 90 includes storing a Test Bit (TBT) or flag that will be used to indicate a condition of presence or absence of a component fault. Block 218 indicates that circuit 90 ensures that the TBT is reset at the beginning of the sequence of determining the presence or absence of a component fault. Block 219 shows the circuit 90 developing a fault time interval (Tc) in evaluating the presence of the ac signal. During the Tc time interval shown by the loop of block 221-225, the circuit 90 also checks for OV or UV signals as will be seen further hereinafter. If the DT signal remains active substantially unchanged during the Tc time interval, it is assumed that none of the component failures occurred and the ac signal must be the result of an external disturbance such as EMI. Blocks 222 and 224 show that if the DT signal remains active, the circuit 90 maintains the Test Bit (TBT) reset, but if DT becomes inactive at any time during the Tc time interval, the circuit 90 sets the TBT to indicate the absence of an ac signal and the presence of a component fault. After the expiration of the Tc time interval, the circuit 90 deasserts the OL signal and causes the regulator 25 to again operate in the normal operating mode, as illustrated by block 227 and by curve 111 at time T1+ Ts + Tc in fig. 3. Because the ac signal is substantially constant during the Tc time interval, TBT is reset and circuit 90 ensures that the Fault (FL) control signal remains inactive and operation returns to the normal operating mode, as illustrated by flow blocks 230 and 204.

Referring again to fig. 3, assume that the ac signal begins to appear within the output voltage at time TA. The ac signal may be caused as a result of EMI causing a signal on the output voltage or may be caused by a component failure including capacitor 16 not connected to output 57. For purposes of this exemplary explanation, assume that a failure mode occurs, such as capacitor 16 being missing or not connected to output 57.

Regulator 25 again causes the DT signal to be at time T₀₁Valid and determines whether the ac signal occurred substantially unchanged within the time interval T1, as explained above with respect to block 205 and 209. As explained previously, if the regulator 25 determines the presence of an AC signal substantially continuously within the time interval T1, the regulator 25 is at block211 begin operating in an open loop mode of operation, such as time T in FIG. 3₀₁Shown near + T1, and then delayed by the settling time shown in flow blocks 213-215. After the stabilization delay, the sequence of operations of block 218 and 225 is performed as explained above. However, because one component failure occurs, the ac signal will not be present at some time after the OL signal is asserted. Circuit 60 detects the absence of the AC signal and disables the DT signal, e.g., at time T₀₁The time after + T1 is shown by curve 108. In the operational sequence of block 218 and 225, the circuit 90 ensures that the TBT is reset and the Tc interval begins as previously described. Because the DT signal is inactive, the circuit 90 sets the TBT bit as shown in block 224 and curve 117 of fig. 3. After the expiration of the Tc time interval in block 225, circuit 90 deasserts the OL signal and sets regulator 25 to operate again in the normal mode (block 227 and curve 111 at time T)₀₁Around + T1+ Ts + Tc) in order to prevent excessive variation in the output voltage. Circuit 90 also determines that the TBT bit is set and asserts the FL control signal indicating the presence of a component fault, as illustrated by flow blocks 228 and 233 and curves 117 and 119 in fig. 3.

In addition to detecting the ac signal to determine component failure, regulator 25 may also use the OV and UV signals to determine whether capacitor 16 is connected to output 57 or whether capacitor 16 is missing. When regulator 25 operates in an open loop mode of operation, the fixed value of current 56 may change the value of the output voltage. If capacitor 16 is not connected to output 57, the output voltage may increase or decrease rapidly. As a result, the output voltage may rapidly increase or decrease to a value that renders the OV or UV signal effective, as illustrated by dashed lines 126 or 129 in fig. 3. If either of the OV or UV signals are active during the settling delay shown in block 214, the circuit 90 determines that this is due to the absence or absence of a capacitor 16 and immediately disables the OL signal and enables the FL signal as shown in blocks 214, 231 and 233 and also shown in FIG. 3 by dashed lines 126 and 129 and 120 of respective curves 124, 127 and 119. It is also possible that the capacitor 16 may be connected in block 213-215 but thereafter become absent or that the OV or UV signal may not become active until the current 90 operates within the Tc time interval of block 221-225 even if the capacitor 16 is absent or unconnected during the stabilization delay of block 213-215. Thus, block 221 also checks for valid OV or UV signals. If OV or UV becomes active during the Tc time interval, circuit 90 determines that this is due to the absence or absence of capacitor 16 connected to output 57 and immediately disables the OL signal and enables the FL signal, as illustrated by flow blocks 221, 231 and 233.

Those skilled in the art will appreciate that the circuit 90 may also use the assertion of the OV or UV signal when operating in the open loop mode of operation to assert a separate control signal (not shown) that represents only the component failure of the capacitor 16 that is missing or not connected to the output 57, where the FL signal may represent various component failures, including the capacitor 16 being missing or not connected as determined by the detection of the absence of the ac signal in the open loop mode of operation.

It will be apparent to those skilled in the art that regulator 25 continuously cycles through the sequence of flow blocks 200- _ 233 so that component failures may not be detected on one pass through the sequence, but will be detected on the next pass through the sequence. In a preferred embodiment, the time required to complete a pass sequence once is typically less than about half a millisecond (0.5 milliseconds). In this preferred embodiment, the T1 time interval is about five hundred (500) microseconds and the Tc time interval is about two (2) microseconds. Those skilled in the art will recognize that the Ts time interval is dependent on the circuitry used and may be omitted in some embodiments.

Those skilled in the art will recognize that the waveforms of fig. 3 and the flow chart of fig. 4 may be used as inputs into a computer-aided design (CAD) system, such that the CAD system may generate logic circuits that implement the logic as well as the states and waveforms shown in fig. 3 and 4. Such CAD systems typically use a high level description language (HDL) as input. Such CAD and HDL systems are well known to those skilled in the art.

To facilitate the function of regulator 25 described in the foregoing, input 26 is connected to a source of transistor 53 and to a source of transistor 54. A drain of transistor 53 is commonly connected to a gate of transistor 53, a gate of transistor 54, and a drain of transistor 51. A drain of transistor 54 is commonly connected to output 57, a first terminal of resistor 13, an input of circuit 33, input 61 of circuit 60, and a first terminal of resistor 97. A second terminal of resistor 97 is commonly connected to an inverting input of comparator 95 and a first terminal of resistor 98. A second terminal of resistor 98 is commonly connected to a non-inverting input of comparator 96 and a first terminal of resistor 99, resistor 99 having a second terminal connected to return 27. The output of ref.3 is commonly connected to the non-inverting input of comparator 95 and the inverting input of comparator 96. An output of comparator 96 is connected to a first input of circuit 90, and an output of comparator 95 is connected to a second input of circuit 90. The FL output of circuit 90 is connected to output 91 of regulator 25. An OL output of circuit 90 is commonly connected to a control input of circuit 33 and a control input of multiplexer 85. A control input of multiplexer 85 is commonly connected to a gate of transistor 87 and an input of inverter 88. The output of inverter 88 is connected to the gate of transistor 86. A drain of transistor 86 is connected to the output of amplifier 82. A source of transistor 86 is commonly connected to a source of transistor 87 and node 49. A drain of transistor 87 is connected to output 45 of circuit 33. A control input of circuit 33 is connected to the gate of transistor 44. A drain of transistor 44 is commonly connected to a first terminal of capacitor 36 and a non-inverting input of amplifier 40. The output of amplifier 40 is connected to the gate of transistor 42, transistor 42 having a drain connected to output 45. A source of transistor 42 is connected to an inverting input of amplifier 40 and to a first terminal of resistor 38. A second terminal of resistor 38 is commonly connected to output 57, a second terminal of capacitor 36, and a first terminal of resistor 35. A second terminal of resistor 35 is commonly connected to a source of transistor 44 and a drain of transistor 47, transistor 47 having a source connected to return 27. A gate of transistor 47 is commonly connected to a gate of transistor 48, node 49, a drain of transistor 48, and a gate of transistor 51. A source of transistor 48 is commonly connected to a source of transistor 51, return 27, and a first terminal of resistor 14. A second terminal of resistor 14 is connected to node 15, a second terminal of resistor 13, and an inverting input of amplifier 82. The non-inverting input of amplifier 82 is connected to the output of ref.1. Input 61 of circuit 60 is commonly connected to a first terminal of resistor 75 and a first terminal of capacitor 62. A second terminal of resistor 75 is commonly connected to a first terminal of capacitor 74, a first terminal of resistor 63, a power supply input of amplifier 68, a drain of transistor 69, and a power supply input of comparator 78. A second terminal of capacitor 74 is commonly connected to return 27, a first terminal of resistor 64, a common supply terminal of amplifier 68, a first terminal of resistor 72, a first terminal of capacitor 73, and a common supply terminal of comparator 78. A second terminal of resistor 63 is commonly connected to node 65, a second terminal of resistor 64, and a non-inverting input of amplifier 68. An inverting input of amplifier 68 is commonly connected to node 70, a second terminal of resistor 72, a source of transistor 69, a second terminal of capacitor 73, and a non-inverting input of comparator 78. A gate of transistor 69 is connected to the output of amplifier 68. The output of comparator 78 is connected to the DT output of circuit 60 and to the DT input of circuit 90. Regulator 30 is connected between input 26 and return 27. Output 31 of regulator 30 is connected to supply power to the power input of amplifier 82.

Fig. 5 schematically illustrates an example of a closed-loop control system 300 that includes a closed-loop control circuit 325. Circuit 325 is a generalized block diagram of an analog control circuit that receives an input signal Vin and forms a control output signal Vo to operate a load during a normal operating mode. For example, the circuit 325 may control the speed of a motor or other type of load. The circuit 325 is configured to open the control loop and operate in an open loop mode and detect the presence or absence of an ac signal during development loop operation to determine a stable element of the control loop, such as the output capacitor C_oPresence or absence of. Circuit 325 is a generalized block diagram illustrating that the current element of fig. 2 may have various other implementations. Circuit 325 includes an output circuit that forms an output signal. In the normal stateIn the operating mode, the output circuit forms the output signal from the output of the amplifier of the control loop, while in the open loop operating mode, the output circuit forms the output signal from a fixed value. The detection circuit detects an alternating current signal on the output signal. The evaluation circuit evaluates whether the alternating current signal continues in the open operating mode.

Fig. 6 is a simplified flowchart 400 illustrating some of the operations performed by circuit 325 and that may be performed by regulator 25. As can be seen in fig. 2-6, in one embodiment, circuit 325 and regulator 25 comprise a method of forming a test circuit comprising: setting a control circuit, such as circuit 325 or regulator 25, to operate in an analog mode to receive an input voltage and form an output current, such as current 56, to charge an output capacitor, such as capacitor 16, to form an output signal, such as an output voltage, on an output, such as output 57, of the control circuit, the control circuit having a normal mode of operation and an open loop mode of operation; setting a control circuit to receive a feedback signal representative of the output signal, e.g., the FB signal, and to adjust the output signal in response to the feedback signal during the normal mode of operation; setting the control circuit to detect an alternating current signal on the output signal and responsively setting the control circuit to operate in an open loop mode of operation; and setting the control circuit to determine whether the component fault is not present by determining whether the alternating current signal is discontinuous when operating in the open loop mode of operation.

Another embodiment of circuit 325 or regulator 25 includes setting the control circuit to form the output current in an open loop mode of operation in response to a signal having a substantially fixed value instead of the feedback signal.

Fig. 7 illustrates an enlarged plan view of a portion of an embodiment of a semiconductor device or integrated circuit 500 formed on a semiconductor chip 501. Regulator 25 or circuit 325 may be formed on chip 501. In one embodiment, regulator 25 or circuit 325 is part of an ASIC circuit formed on chip 501. Thus, the chip 501 may also include other circuits that are not shown in fig. 6/7 for simplicity of illustration. In another embodiment, regulator 25 may be formed on chip 501 and packaged in a four terminal semiconductor package. Regulator 25 or circuit 325 and device or integrated circuit 500 are formed on chip 501 by semiconductor fabrication techniques that are well known to those skilled in the art.

Accordingly, as will be recognized by those skilled in the art from the explanation of fig. 5 and fig. 2-4 and 5-7, a voltage regulator having a component test circuit according to another embodiment may include: a voltage regulator arranged to receive an input voltage and form an output current to charge an output capacitor so as to form an output voltage on an output of the voltage regulator, the voltage regulator having a normal mode of operation and an open loop mode of operation; an error amplifier, such as amplifier 82, coupled to receive a feedback voltage representative of the output voltage and to form an error signal on an output of the error amplifier, the voltage regulator being arranged to regulate the output voltage in response to the feedback voltage during the normal mode of operation; a current control circuit, such as circuit 33, configured to receive the error signal from the error amplifier and store a value of the error signal during the normal mode of operation, the current control circuit configured to form an output signal representative of the stored value of the error signal during the open loop mode of operation; the output circuit is configured to receive the output signal from the current control circuit and form an output current representative of the output signal during an open loop mode of operation; a first circuit, such as circuit 60, configured to receive the output voltage and to detect an alternating current signal at a direct current value of the output voltage, wherein the first circuit is configured to form a first control signal, such as a DT control signal, indicative of the detection of the alternating current signal; and a logic circuit, such as circuit 90, coupled to receive the first control signal and to assert the second control signal, such as the OL control signal, using the first control signal and to set the operating mode of the voltage regulator to an open loop operating mode, the logic circuit being arranged to detect a component failure using the first control signal and to responsively assert a third control signal, such as the FL control signal, after the component failure is detected.

According to another embodiment, the logic circuit sets the operating mode to an open loop operating mode and asserts the second control signal if the ac signal continues for at least one time interval, such as the T1 time interval, during the normal operating mode. According to yet another embodiment, the logic circuit is configured to receive the first control signal and responsively assert the second control signal if the first control signal remains asserted for a time interval and to set the voltage regulator to operate in an open loop mode of operation.

Those skilled in the art will also recognize that, according to another embodiment, a method of forming a voltage regulator having a component test circuit may include: setting a voltage regulator to receive an input voltage and form an output current to charge a capacitor to regulate the output voltage at an output of the voltage regulator, the voltage regulator having a normal mode of operation and an open loop mode of operation; setting a voltage regulator to receive a feedback signal representative of the output voltage and to regulate the output voltage in response to the feedback signal during a normal mode of operation; a first circuit such as circuit 60 is provided to detect the ac signal of the output voltage; setting a second circuit, such as circuit 90, to set the voltage regulator to operate in an open loop mode of operation in response to the first circuit detecting an ac signal on the output voltage for a first time interval; and the second circuit is arranged to detect the component fault in response to the first circuit detecting no ac signal on the output voltage in response to the voltage regulator operating in an open loop mode of operation and to detect an absence of the component fault in response to the first circuit detecting a presence of a dc signal on the output voltage when operating in the open loop mode of operation.

In view of all of the above, it is evident that novel devices and methods are disclosed. Including, among other features, operating the closed loop control system in an open loop setting and then detecting the presence or absence of an alternating current signal in the output signal of the control loop at some time during open loop operation to detect the presence or absence of a component fault. The advantage of this method is that the ac signal can be correctly detected also in harsh environments with a lot of EMI disturbances, such as in the environment of controlling an internal combustion engine. Additionally, the presence of EMI-induced noise may also be detected and distinguished from component failures. Thus, the system may continue to operate in the event that the ac signal is generated from EMI interference rather than from component failure.

While the present subject matter has been described in connection with specific preferred embodiments, the foregoing drawings and the description thereof depict only typical and exemplary embodiments of the present subject matter and are not therefore to be considered to be limiting of its scope. It is evident that many modifications and variations will be apparent to those skilled in the art. As will be appreciated by those skilled in the art, the exemplary form of regulator 25 serves as a means of explaining a method of detecting the absence of an element in a closed-loop control system. Many of the circuit elements of regulator 25 explained in the description of fig. 2-4 are exemplary implementations, and the circuit elements may be implemented by various alternative circuits. For example, circuit 60 is shown with a certain circuit implementation; however, other circuit elements may be used as long as the circuit detects the presence or absence of an alternating signal of the output voltage. The circuit 33 is also shown as having a particular circuit implementation, but other circuit implementations may be used as long as the circuit forms a fixed signal that is used when operating in an open loop mode of operation. The storage element of the circuit 33 is shown as a capacitor 36, but it may also be any other type of well-known storage element. The circuit 33 may even be just a fixed reference signal from a reference generator, for example of the type illustrated by ref.1 in fig. 2. Also, circuit 33 may be omitted and regulator 25 may be set to not provide an output current during the open loop mode of operation, but still use the presence or absence of the ac signal to determine the presence or absence of the capacitor. Although load 17 is shown external to the circuitry of regulator 25 or circuitry 325, the load along with regulator 25 and circuitry 325 may be formed on a semiconductor chip.

The output circuit of fig. 2 may also have other implementations as long as the output circuit uses a closed loop regulator to form current 56 in the normal operating mode and a fixed signal in the open loop operating mode. Also, the capacitors 73 and 36 may be controlled to charge to a value different from the average value of the received signal.

The evaluation circuit 90 may also have different circuit implementations. The circuit 90 may be a combinational digital logic, or state machine, or high speed microprocessor, or even an analog control circuit, so long as the circuit receives signals similar to the OD, OV and UV signals, forms the time intervals described in the flow chart of fig. 4, evaluates the presence or absence of the ac signal for the time intervals as explained, and causes the regulator to operate in a normal or open loop mode of operation as explained above.

Also, the settling delay shown in the flow chart of fig. 4 may be omitted in some systems.

Additionally, the feedback signal is shown as a voltage in the exemplary embodiment, but a current or other type of signal may be used.

Additionally, one skilled in the art will recognize that the principle of using an alternating current signal in the signal formed by the closed loop control system to detect a fault in a system component may be extended to any closed loop system where any external component may affect the stability of the system. In the exemplary embodiment described in the description of fig. 2-4, the closed-loop control system is an analog closed-loop voltage regulator, but the functionality provided by the system described in fig. 2-4 may be applied to any of the closed-loop control systems shown by fig. 5 and 6.

The word "connected" is used throughout for clarity of description, but is intended to have the same meaning as the word "coupled". Accordingly, "connected" should be interpreted to include direct connections or indirect connections.

Claims (10)

1. A voltage regulator having a component test circuit, comprising:

the voltage regulator arranged to receive an input voltage and form an output current to charge an output capacitor so as to form an output voltage on an output on the voltage regulator, the voltage regulator having a normal mode of operation and an open loop mode of operation;

an error amplifier coupled to receive a feedback signal representative of the output voltage and to form an error signal on an output of the error amplifier, the voltage regulator being arranged to regulate the output voltage in response to the feedback signal during the normal mode of operation;

a current control circuit arranged to receive the error signal from the error amplifier and to store a value of the error signal during the normal mode of operation, the current control circuit being arranged to form an output signal representative of the stored value of the error signal during the open loop mode of operation;

an output circuit arranged to receive the output signal from the current control circuit during the open loop mode of operation and to form the output current representative of the output signal;

a first circuit arranged to receive the output voltage and to detect an alternating current signal at a direct current value of the output voltage, the first circuit being arranged to form a first control signal indicative of the detection of the alternating current signal; and

logic circuitry coupled to receive the first control signal and to use the first control signal to assert a second control signal that controls operation in an open loop mode of operation and to set the mode of operation of the voltage regulator to the open loop mode of operation, the logic circuitry being arranged to use the first control signal to detect a component fault and to responsively assert a third control signal indicative of the component fault after the component fault is detected.

2. The voltage regulator of claim 1, wherein the voltage regulator regulates the output voltage as a linear voltage regulator that regulates the output voltage in a linear manner, and wherein the voltage regulator is not a switching regulator that switches the output current between an on state and an off state in order to regulate a value of the output voltage during the normal operating mode.

3. The voltage regulator of claim 1, wherein the current control circuit comprises a storage capacitor coupled to store a voltage representative of the error signal of the error amplifier, a switch to decouple the storage capacitor from the output of the error amplifier in response to operating in the open loop mode of operation, and a voltage-to-current conversion circuit to form the output signal of the current control circuit as a substantially constant current on an output of the current control circuit.

4. A method of forming a voltage regulator having a component test circuit, comprising:

setting the voltage regulator to receive an input voltage and form an output current to charge a capacitor in order to regulate an output voltage on an output of the voltage regulator, the voltage regulator having a normal mode of operation and an open loop mode of operation;

setting the voltage regulator to receive a feedback signal representative of the output voltage and to regulate the output voltage in response to the feedback signal during the normal mode of operation;

setting a first circuit to detect an alternating current signal of the output voltage;

setting a second circuit to set the voltage regulator to operate in the open-loop operating mode in response to the first circuit detecting the alternating current signal on the output voltage within a first time interval; and

the second circuit is configured to detect a component fault in response to the first circuit not detecting an AC signal on the output voltage when the voltage regulator operates in the open loop mode of operation and to detect an absence of the component fault in response to the first circuit detecting a presence of an AC signal on the output voltage when the voltage regulator operates in the open loop mode of operation.

5. The method of claim 4, wherein setting the second circuit to set the voltage regulator to operate in the open-loop operating mode comprises: setting the second circuit to set the voltage regulator to operate in the open loop operating mode in response to the first circuit detecting the alternating current signal within a time interval while operating in a normal operating mode.

6. The method of claim 4, further comprising setting the second circuit to determine an absence of a connection between the capacitor and the output of the voltage regulator in response to receiving an over-voltage or under-voltage condition while operating in an open loop mode of operation.

7. A method of forming a test circuit, comprising:

setting a control circuit to operate in an analog mode to receive an input voltage and form an output current to charge an output capacitor so as to form an output signal on an output of the control circuit, the control circuit having a normal mode of operation and an open loop mode of operation;

setting the control circuit to receive a feedback signal representative of the output signal and to adjust the output signal in response to the feedback signal during the normal mode of operation;

setting the control circuit to detect an alternating current signal on the output signal and responsively set the control circuit to operate in an open loop mode of operation; and

the control circuit is configured to determine whether a component fault exists by determining whether the alternating current signal is discontinuous when operating in the open loop mode of operation to form an output signal but not in response to the feedback signal.

8. The method of claim 7, further comprising configuring the control circuit to determine whether the component fault is not present by determining whether the ac signal continues to be detected while operating in the open loop operating mode.

9. The method of claim 8, wherein configuring the control circuit to determine whether the output capacitor is present comprises: the control circuit is configured to determine whether the AC signal continues to be detected for a second time interval while operating in the open loop mode of operation.

10. The method of claim 9, wherein setting the control circuit to determine whether the output capacitor is not present comprises: the control circuit is configured to determine whether the AC signal is absent during the second time interval when operating in the open loop mode of operation.