HK1151628A - Multi-directional trenching of a die in manufacturing superjunction devices - Google Patents

Description

Multi-directional trenching of die in manufacturing superjunction devices

Technical Field

Embodiments of the invention relate generally to methods of manufacturing semiconductor devices and, more particularly, to methods of manufacturing superjunction devices having a first plurality of trenches including one orientation and a second plurality of trenches having a second orientation different from the first orientation.

Background

Semiconductor wafer fabrication generally refers to the process of making integrated circuits on a silicon wafer. A typical semiconductor wafer is generally circular in plan view. Individual electronic circuits or devices are formed on at least one surface of a wafer, which is then typically diced (sawed or diced) into a plurality of individual "dies" for packaging into individual Integrated Circuits (ICs).

Since the invention of the superjunction device disclosed in U.S. patent No.5,216,275, incorporated by reference herein by doctor Xingbi Chen, many efforts have been made to expand and improve the superjunction effect of its invention. U.S. Pat. Nos. 6,410,958, 6,300,171, and 6,307,246 are examples of such efforts and are incorporated herein by reference.

Trench-type superjunction devices are expected to replace multi-epitaxial superjunction devices due to potentially lower processing costs. Fig. 1A shows a top plan view of wafer 10 used in the fabrication of a plurality of trench-type superjunction devices or dies 20. Fig. 1B shows an enlarged view of two dies 20 representing a plurality of dies 20 located on the wafer 10. Each die 20 includes a plurality of trenches 22, each trench 22 traversing die 20 in a generally horizontal orientation. Fig. 1C shows an alternative configuration in which a plurality of trenches 22 each oriented generally vertically on die 20. In each case, all trenches 22 on all dies 20 of wafer 10 have the same orientation. Fig. 1D shows an enlarged partial cross-sectional view of die 20 having a plurality of trenches 22 formed in silicon layer 12 disposed on substrate 11. Thereby forming a plurality of respective mesas (mesas) 24, each mesa 24 being covered by an oxide layer 26. The trenches 22 are typically filled with a refill material 28.

In general, semiconductor device manufacturing costs have been reduced by compressing design rules (recommended parameters) and expanding the diameter of the process wafer. As described in co-pending U.S. patent application No.11/962,530, design rule reduction may be applied to trench-type superjunction technology. However, conventional notching methods often cause wafer bowing and warping. Such deformation is particularly prevalent when grooving large diameter wafers (e.g., greater than about six inches). Once bowing and warping occurs, the wafer is generally no longer efficiently processed, if at all. Furthermore, even if the wafer is still capable of being processed, there is a high risk of chipping or breakage. When deep trenching is used, such as when a deep trenching type is used, for example, in forming superjunction devices, the degree of bowing and/or warping is greater. Thus, the use of conventional trenching methods for manufacturing superjunction devices does not allow for cost reduction by increasing the wafer diameter.

It is desirable to provide a method of manufacturing a trench-type superjunction device that minimizes and/or eliminates the effects of bowing and warping. It is also desirable to provide a method of manufacturing a trench-type superjunction device that reduces manufacturing costs by enabling the use of larger wafer diameters.

Disclosure of Invention

Briefly, embodiments of the invention include methods of manufacturing superjunction devices. One embodiment of the method includes providing a semiconductor wafer having at least one die. The method also includes forming at least one first trench in the at least one die, the at least one first trench having a first orientation. The method also includes forming at least one second trench in the at least one die, the at least one second trench having a second orientation different from the first orientation. In a preferred embodiment, at least one additional trench is formed in the at least one die, each additional trench having an orientation different from at least one of the first orientation and the second orientation.

Another embodiment of the present invention includes a method of manufacturing a superjunction device. The method includes providing a semiconductor wafer having at least one die. The method also includes forming a first plurality of trenches in the at least one die, each of the first plurality of trenches having a first orientation. The method also includes forming a second plurality of trenches in the at least one die, each of the second plurality of trenches having a second orientation different from the first orientation.

Embodiments of the invention also include superjunction devices. In one embodiment, the superjunction device includes a semiconductor wafer having at least one die. At least one first trench is formed in the at least one die, the at least one first trench having a first orientation. Forming at least one second trench in the at least one die, the at least one second trench having a second orientation different from the first orientation.

Still other embodiments of the present invention include other types of semiconductor devices formed on or in a semiconductor wafer. The semiconductor wafer includes at least one die. At least one first trench is formed in the at least one die, the at least one first trench having a first orientation. Forming at least one second trench in the at least one die, the at least one second trench having a second orientation different from the first orientation.

Drawings

The foregoing summary, as well as the following detailed description of preferred embodiments of the present invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustration, there is shown in the drawings embodiments that are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.

In the drawings:

FIG. 1A is a top plan view of a prior art semiconductor wafer having a plurality of dies formed thereon;

FIG. 1B is a high magnification top plan view of two adjacent dies from the prior art wafer of FIG. 1A;

FIG. 1C is a high magnification top plan view of two alternating adjacent dies from the prior art wafer of FIG. 1A;

fig. 1D is an enlarged partial cross-sectional front view of one of the dies from either of fig. 1B or 1C.

Fig. 2A-2C are high magnification top plan views of a die fabricated in accordance with a preferred embodiment of the present invention.

FIGS. 3A and 3B are high magnification top plan views of adjacent dies on a wafer made in accordance with a preferred embodiment of the present invention;

fig. 4A is an enlarged cross-sectional front view of a portion of a die after an oxide layer is disposed on a silicon layer in accordance with a preferred embodiment;

fig. 4B is an enlarged cross-sectional view front view of a portion of the die of fig. 4A after forming trenches thereon in accordance with a preferred embodiment; and

fig. 4C is an enlarged cross-sectional front view of a portion of the die of fig. 4B after filling the trench with a refill material in accordance with a preferred embodiment.

Detailed Description

Certain terminology is used in the following description for convenience only and is not limiting. The words "right", "left", "lower", and "upper" designate directions in the drawings to which reference is made. The words "inwardly" and "outwardly" refer to directions toward and away from, respectively, the geometric center of the device and designated parts thereof. The term includes the words listed above, derivatives thereof and words of similar import. In addition, the words "a" and "an" as used in the claims and the corresponding portions of the specification mean "at least one".

As used herein, reference to conductivity is not limited to the described embodiments. However, those skilled in the art know that p-type conductivity can be switched with n-type conductivity and that the device will still be functionally correct (i.e., first or second conductivity type). Thus, as used herein, reference to n or p may also mean either n or p, or it may be substituted for p and n.

Further, n is⁺And p⁺Referred to as heavily doped n and p regions, respectively; n is⁺⁺And p⁺⁺Respectively referred to as very heavily doped n and p regions; n is^-And p^-Respectively, lightly doped n and p regions; and n^--And p^--Respectively, refer to very lightly doped n and p regions. However, such relative doping terms should not be construed as limiting.

Referring in detail to the drawings, wherein like reference numerals indicate like elements throughout, there is shown in fig. 2A top plan view of a respective die 220a manufactured in accordance with a preferred embodiment of the present invention. A plurality of trenches 222A are formed on die 220a, trenches 222A having a first orientation, depicted as vertical in fig. 2A. An additional plurality of trenches 223a are also formed on die 220a, trenches 223a having a second orientation, depicted as horizontal in fig. 2A. In the embodiment depicted in fig. 2A, the first and second trench orientations differ by about 90 °, but the trenches 222A, 223a may be formed at other angles, such as 45 °, with respect to each other, for example. By utilizing more than one trench direction within die 220a, stress on die 220a and on the entire wafer is reduced.

Embodiments of the present invention are not limited to the example shown in fig. 2A. There are no limitations on the orientation, angle, length, width and/or shape of the grooves 222a, 223 a. There is also no limit to the available combinations on die 220a or to the number of trenches 222a, 223 a.

In a preferred embodiment, the size of the area occupied by one orientation of the grooves 222a should generally be equal to the area occupied by the other orientation of the grooves 223 a. Preferably, the trenches 222a, 223a are generally symmetrically located on the die 220 a. The configuration of trenches 222a, 223a reduces the mechanical stress exerted on die 220a and the entire wafer, thereby reducing wafer bow or warpage. Fig. 2B shows a second embodiment of die 220B including vertical trenches 222B and horizontal trenches 223B. Despite the irregular configuration, die 220b maintains an area ratio of about 1: 1 (as described above) for trenches 222b, 223 b.

Fig. 2C shows another embodiment of a die 220C featuring a different type of grooving pattern. Die 220c includes a plurality of trenches 222c angled at about 45 deg. from horizontal and a plurality of trenches 223c angled at about 135 deg. from horizontal. Trenches 222c, 223c are grouped with similarly oriented trenches to form a square pattern on die 220 c. Fig. 2C thus illustrates an example where die 220C may include trenches 222C, 223C of various lengths while continuing to maintain an area ratio of about 1: 1 in order to facilitate minimizing stress on the wafer.

Fig. 3A shows an alternative embodiment of the present invention. The illustrated dies 320a, 321A are formed adjacent to each other on a wafer, such as the wafer 10 shown in fig. 1A. A plurality of trenches 323a oriented in a horizontal direction are formed in each die 320 a. A plurality of trenches 322a oriented in the vertical direction are formed in each die 321 a. Unlike in the previous embodiments of fig. 2A-2C, each die 320a, 321a in fig. 3A includes trenches 323A, 322A formed in only one orientation. As shown in fig. 3A, thereby reducing mechanical stress across the wafer by placing the dies 320a, 321a having trenches 323A, 322a oriented in different directions adjacent to each other. Although the length of each groove 322a is greater than the length of each groove 323a, the number of grooves 323a is greater than the number of grooves 322 a. As a result, the total area covered by the trenches 322a and 323a is about the same. Specifically, in fig. 3A, the wafer will include a pattern of dies 320a, 321a, where each other die 320a, 321a on the wafer in the horizontal and vertical directions will include the same trench orientation.

Fig. 3B depicts the construction of the dies 320B, 321B as an alternative to the construction shown in fig. 3A. Extending the fig. 3B configuration across the entire wafer would result in a row (or column) of die 320B with horizontally oriented trenches 323B, a row (or column) of die 321B with vertically oriented trenches 322B, etc.

It will be appreciated by those skilled in the art that the orientation of the trenches 322, 323 in each die 320, 321 is not limited to the embodiments described above. The shape of the dies 320, 321 is also not limited to rectangular and may be designed in any manner convenient for use in superjunction devices, such as square, rectangular, circular, polygonal, and the like.

Embodiments of the present invention may be used not only for superjunction Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices, but also for schottky devices or any device that requires deep, refilled trenches, including micro-electromechanical systems (MEMS).

Embodiments of the present invention, such as those shown in fig. 2A-2C and 3A-3B, allow for the fabrication of larger diameter semiconductor wafers having bow of less than 100 microns. Preferably, the wafer bow is reduced to below 50 microns on, for example, an eight inch diameter wafer.

Referring to fig. 4A-4C, a process for manufacturing a superjunction device according to an embodiment of the present invention is described. Fig. 4A shows a partial cross-sectional front view of a die 420 as part of a wafer (not shown). Die 420 includes a layer 412 of semiconductor material that may be doped as desired. Preferably, the semiconductor material layer 412 is silicon. However, the semiconductor material layer 412 may be formed of other materials such as silicon carbide, gallium arsenide, germanium, and the like. In the example of fig. 4A-4C, semiconductor material layer 412 is an n-type epitaxial silicon layer disposed on heavily doped substrate layer 411. Although both layers 411, 412 are shown in fig. 4A as having n-type conductivity, it should be understood that one or both of layers 411, 412 may alternatively have p-type conductivity. Other layers not shown may be included in die 420 as desired. A temporary layer for processing the entire wafer may also be included.

An oxide or other dielectric layer 426 is disposed on the silicon layer 412. The oxide layer 426 is applied using one of thermal growth, Low Pressure (LP) Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Atmospheric Pressure Chemical Vapor Deposition (APCVD), and deposition or other processes. The oxide layer 426 is preferably formed of an oxide. Alternatively, oxide layer 426 may be a nitride, silicon oxynitride, or other known dielectric.

Known processing techniques such as grinding, polishing, and etching may be performed to obtain the desired thicknesses of the substrate 411, the silicon layer 412, the oxide layer 426, and any additional layers. Typically, the semiconductor wafer is coarsely thinned with a grinder having a coarse grinding wheel or pad such as diamond or a carbide wheel or pad such as diamond impregnated resin teeth. Grinding the wafer also makes the IC package thinner and therefore smaller. Generally, polishing is a finer process using a wet silica particle slurry that is rinsed on the surface of a wafer at a predetermined flow rate, and is called Chemical Mechanical Polishing (CMP). Optionally, the surface of the wafer is thinned by grinding and then polishing.

Referring to fig. 4B, trenches 422 are formed in die 420 through oxide layer 426 and at least partially through silicon layer 412, forming mesas 424. In the example of fig. 4B, the trench 422 extends completely through the silicon layer 412 to the substrate 411, but the trench 422 may extend to any desired depth. A photoresist patterning layer (not shown) may be disposed over the oxide layer 426 to provide a pattern for etching the trenches 422. Preferably, the trench 422 is formed by utilizing known techniques such as plasma etching, Reactive Ion Etching (RIE), sputter etching, vapor phase etching, chemical etching, deep RIE, or the like. The deep RIE technique may allow for deeper trenches 422 with straighter sidewalls. Furthermore, forming deeper trenches 422 with straighter sidewalls than conventionally etched or formed trenches, in addition to other steps in the process, results in a final superjunction device with enhanced avalanche breakdown voltage (Vb) characteristics compared to conventional semiconductor-transistor devices.

If desired, the sidewalls of each trench 422 may be smoothed using, for example, one or more of the following process steps: (i) an isotropic plasma etch may be used to remove a thin layer of silicon from the surface of the trench 422 (typically 100-. The use of a smoothing technique may produce a smooth trench 422 surface with rounded corners while removing residual stress and unwanted contamination. However, where it is desired to have vertical sidewalls and square corners, an anisotropic etch process may be used rather than the isotropic etch process discussed above. Anisotropic etching generally means that the material is etched at different etch rates in different directions, as compared to isotropic etching.

The trench 422 shown in fig. 4B is formed in accordance with the embodiments of the present invention described above. That is, the groups of trenches 422 on each die 420 are formed to have different orientations, or alternatively, the trenches 422 formed on one die 420 have a different orientation than the trenches 422 formed on an adjacent die 420.

The sidewalls of the trenches 422 are then implanted or doped with a P-dopant, such as boron (P), using any technique known in the art. In some cases, however, the mesas 424 may need to be n-doped before the sidewalls of the trenches 422 are p-doped. Preferably, the implantation is performed at a high energy level in the range of about 40 kilo-electron-volts (KeV) to several mega-electron-volts, e.g., without the aid of a masking step, at an implantation angle Φ (not shown) determined by the width and depth of the trench 422. Preferably, the energy level is in the range of about 200KeV to 1MeV, but it should be appreciated that the energy level should be selected to adequately implant the dopant. The use of the predetermined implant angle Φ ensures that only the sidewalls of the trenches 422 are implanted, not the bottom.

In the fabrication of prior art devices, the implant angle Φ is typically between 2 ° and 12 °. The wafer may also be oriented at one or often two "twist angles," i.e., the relative orientation of the wafer in a plane defined by the ion beam. The most common angles are 0 ° and 180 °. However, according to a preferred embodiment, a larger twist angle may be required, e.g., the wafer may be oriented at 45 °, 135 °, 225 °, and 315 ° during processing. The twist angle required for ion implantation is often controlled by limitations imposed by the fabrication equipment. Accordingly, embodiments of the present invention are in no way limited to the values or numbers of twist angles described above.

After implanting a p-type implant on the sidewalls of the trench 422, a drive-in step (i.e., diffusion) is performed using any known technique to create a p-type doped region proximate to the sidewalls of the trench 422 (see fig. 4C). Preferably, the temperature and time period for the drive-in step are selected to adequately drive the implanted dopants into the mesas 424. For example, for p-type doping, the drive-in step (i.e., diffusion) may be performed at a temperature of about 1150-1200 deg.C for about 1-2 hours. Alternatively, for n-type doping, the drive-in step may be performed at a temperature of up to about 1200 ℃ for up to about 24 hours.

An optional oxidation step, typically performed in a vapor or oxygen ambient, may also be performed with or after the drive-in step, which forms a silicon dioxide layer (not shown) on the sidewalls or bottom of the trench 422. A thin layer of silicon nitride (not shown) may also be deposited on the sidewalls and bottom of the trench 422. Silicon nitride deposition on thermally oxidized silicon wafers does not affect Si-SiO₂The basic nature of the interface. The presence of silicon nitride makes the surface potential according to the structure stable or unstable due in part to the presence of hydrogen in the silicon nitride. Hydrogen can affect electrical characteristics. The silicon nitride layer also serves to isolate and protect the silicon and silicon oxide from the refill material deposited in the trench 422.

Lining trench 422 with silicon nitride may be typically performed by CVD (thermal or plasma). Lining the trench 422 with silicon dioxide is typically performed by CVD (thermal, plasma, or Spin On Glass (SOG)). Because of the better uniformity achieved by TEOSThe lining of the trenches 422 with silicon dioxide and/or silicon nitride may preferably be performed using a coating of Tetraethylorthosilicate (TEOS). Preferably, the silicon nitride is about thickTo about

Referring to fig. 4C, the trench 422 is then filled with a temporary or permanent refill material 428, such as a semiconductor insulating material, an insulating material, or a combination thereof. The refill material 428 may be polysilicon, recrystallized polysilicon, single crystal silicon, or semi-insulating polysilicon (SIPOS). The trench 422 may be filled using SOG techniques, CVD, surface reflow, or other methods known in the art. For example, trench 422 may be refilled with SIPOS. The amount of oxygen content of SIPOS may be selectively selected to be between 2% and 80% to improve electrical characteristics in die 420. For electrical properties, it is desirable to increase the amount of oxygen content, but changing the oxygen content also results in changes in the material properties. The higher oxygen content SIPOS thermally expands and contracts differently than the surrounding silicon, which can lead to undesirable cracking or fissuring especially near the interface of the different materials. Therefore, the oxygen content of SIPOS is optimally selected to achieve the most desirable electrical characteristics without having undesirable effects on mechanical characteristics.

It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims.

Claims (14)

1. A method of manufacturing a superjunction device, the method comprising:

(a) providing a semiconductor wafer comprising at least one die;

(b) forming at least one first trench in the at least one die, the at least one first trench having a first orientation; and

(c) forming at least one second trench in the at least one die, the at least one second trench having a second orientation different from the first orientation.

2. The method of claim 1, wherein the at least one first trench defines a first area and the at least one second trench defines a second area.

3. The method of claim 2, wherein a ratio of the first area to the second area is 1: 1.

4. The method of claim 1, further comprising:

(d) forming at least one additional trench in the at least one die, each additional trench having an orientation different from at least one of the first orientation and the second orientation.

5. The method of claim 1, wherein steps (a) - (c) are performed sequentially.

6. The method of claim 1, wherein steps (b) and (c) are performed simultaneously.

7. The method of claim 1, wherein each of the preceding steps is substantially completed before each of (a) - (c) begins.

8. The method of claim 1, wherein each of the previous steps is completely completed before each of (a) - (c) begins.

9. A superjunction device formed according to the method of claim 1.

10. A method of manufacturing a superjunction device, the method comprising:

(a) providing a semiconductor wafer comprising at least one die;

(b) forming a first plurality of trenches in the at least one die, each of the first plurality of trenches having a first orientation; and

(c) forming a second plurality of trenches in the at least one die, each of the second plurality of trenches having a second orientation different from the first orientation.

11. The method of claim 10, wherein the first plurality of trenches defines a first area and the second plurality of trenches defines a second area.

12. The method of claim 10, wherein a ratio of the first area to the second area is 1: 1.

13. The method of claim 10, wherein

(i) Each of the first plurality of grooves having a length dimension, the length dimension of each of the first plurality of grooves being different from at least one other groove of the first plurality of grooves; and

(ii) each of the second plurality of grooves has a length dimension that is different from at least one other groove of the second plurality of grooves.

14. The method of claim 10, wherein

(i) Each of the first plurality of grooves has a length dimension, the length dimension of each of the first plurality of grooves being the same; and

(ii) each of the second plurality of grooves has a length dimension, and the length dimension of each of the second plurality of grooves is the same.