HK1148393B - Semiconductor device - Google Patents

Description

Semiconductor device with a plurality of transistors

The divisional application is based on the divisional application of Chinese patent application with the application number of 00816937.3, the application date of 12-21.2000 and the name of 'semiconductor device'. More specifically, the present divisional application is a divisional application again based on a divisional application having an application number of 200510072780.1, a filing date of 12/21/2000, and an invention title of "semiconductor device".

Technical Field

The present invention relates to a semiconductor device having a circuit operated by a low-voltage power supply and a circuit operated by a high-voltage power supply, and more particularly, to a semiconductor device having a level conversion circuit for transmitting an output of a circuit operated by a low-voltage power supply to a circuit operated by a high-voltage power supply.

Background

Conventionally, as such a level conversion circuit, a circuit for converting a signal having an amplitude of a low-voltage power supply VDD into a signal having an amplitude of a high-voltage power supply VDDQ is known as disclosed in page 71 of an 'ultra LSI memory' published by yokan Qing university in 1996 peifeng (hereinafter, referred to as prior art 1). Further, japanese patent application laid-open No. h 11-27137 discloses a level conversion circuit (hereinafter referred to as "conventional technology 2") that converts an input signal into a boosted amplitude and then converts the boosted amplitude into a voltage amplitude of a high-voltage power supply VDDQ in order to operate the level conversion circuit of conventional technology 1 with a low-voltage power supply VDD of a lower voltage.

Fig. 22 is a circuit diagram showing a level conversion circuit of the related art 2. The level conversion circuit includes a booster circuit VUC for boosting a signal having a low power supply voltage VDL amplitude inputted from an internal circuit CB using a power supply VDL as an operating power supply, and a level conversion circuit LS2201 of prior art 1 for converting the boosted signal into a signal having a high power supply voltage VDH amplitude. The level shift circuit LS2201 of the related art 1 is a so-called CMOS static circuit, and is composed of P-type MOSFETs (hereinafter, referred to as PMOS transistors) P2201 and P2202, and N-type MOSFETs (hereinafter, referred to as NMOS transistors) N2201 and N2202.

The output from the booster circuit VUC is received by the gates of a pair of differentially input NMOS transistors N2201, N2202, and is converted into a signal S2202 having an output amplitude of a high power supply voltage VDH level. PMOS transistors P2201, P2202 constituting a load to NMOS transistors N2201, N2202 for differential input are cross-coupled to each other such that the gate of one PMOS transistor is connected to the drain of the other PMOS transistor. Since a voltage higher than the input level VDL is applied to the gates of the NMOS transistors N2201 and N2202, the drive capability of the NMOS transistors N2201 and N2202 can be increased. With this, it is possible to operate with a lower voltage VDL than when the conventional technique 1 is used alone.

Here, a booster circuit disclosed in prior art 2 is shown in fig. 23. The booster circuit VUC can output only 2 × VDL levels temporarily. That is, in order not to apply the maximum VDL level to the gates of the PMOS transistors P2301 and P2302, the sides of the PMOS transistors P2301 and P2304 to which the capacitive elements C2301 and C2302 are connected are shifted from the drain state to the source state, so that the 2 × VDL level cannot be maintained constantly, and the voltage is lowered to a voltage higher than the power supply voltage VDL by the threshold value of the PMOS transistor.

Therefore, when the power supply voltage VDL becomes a low voltage such as 1V or less, for example, the level conversion circuit of the related art 1 may not be driven. In addition, in some of the MOS transistors constituting the circuit of fig. 23, the maximum applied voltage of some of the transistors instantaneously changes to 2 × VDL. Therefore, it is difficult to use a low-withstand-voltage MOS transistor device having a thin oxide film, and as a result, an integrated circuit is inevitably manufactured using a high-withstand-voltage MOS transistor having a thick oxide film. Therefore, it is sometimes difficult to increase the speed of the operation.

An example of a single circuit of the booster circuit is disclosed in Japanese patent laid-open No. 63-69455. This is an example of a level at which 2 × VCC-VT (VCC.. power supply voltage, VT... threshold voltage of N-type MOS transistor) can be obtained. Further, Japanese patent application laid-open No. 3-273594 discloses a booster circuit. This is a booster circuit that can obtain a 2 × VL-VT (VL... low voltage) level and a circuit that uses a 3-fold booster circuit to obtain a 2 × VL level.

Among the booster circuits disclosed herein, even if a booster circuit having a boosting level of 2 × VCC-VT is applied to the booster circuit portion of the conventional technique 2, the level conversion circuit of the conventional technique 1 may not operate due to the reduction in the power supply voltage VDL.

Further, in the case of using a booster circuit capable of obtaining a 2 × VL level as disclosed in japanese unexamined patent application publication No. h 3-273594, it is necessary to use a MOS transistor having a thick oxide film in the 3-fold booster circuit portion, and the number of MOS transistors is increased, so that it is inevitable to increase the area, and therefore, the cost is increased.

As a separate example of the level conversion circuit, there is an example disclosed in japanese patent laid-open No. 63-299409 (hereinafter, referred to as prior art 3). This is an example of level conversion using an input signal, a signal whose transition level is shifted by a resistance element, and a MOS transistor. Fig. 24 shows a level conversion circuit disclosed in prior art 3. Since this circuit performs level conversion using the potential at which the voltage drops due to the resistor R2401, for example, when the voltage VIN at the gate terminal of the NMOS transistor N2405 and the voltage VDD at the gate terminal of the NMOS transistor N2404 are VIN — VDD, a current always flows from the high potential terminal VDDQ to the low potential terminal VSSQ. This is unsatisfactory in a low voltage circuit from the viewpoint of very important low power consumption.

Although the above description has been made of the conventional examples of the level conversion circuit and the booster circuit, there is another problem to be considered in the level conversion circuit as described later. This is a problem that, when the power supply of a circuit block using the low voltage power supply VDD connected to the level conversion circuit as the power supply is cut off, a leakage current occurs in the logic circuit on the side of the high voltage power supply VDDQ. As a protection circuit for preventing this leakage current, japanese unexamined patent publication No. h 11-195975 discloses an output fixed type level conversion circuit in which an external signal is input and an output to a high voltage side is fixed to a voltage of a high voltage power supply VDDQ. Although this circuit is effective, it is desirable to use a leakage current prevention circuit that prevents leakage current by autonomous control without using an external control signal, in view of simplification of design.

In view of recent technological trends to reduce power consumption, a sub-1V low-voltage power supply for a low-voltage logic circuit is very active. On the other hand, the high voltage side still requires a high voltage of 3.3V or 2.5V, as represented by an I/O circuit or a dynamic read/write memory (DRAM). Therefore, the following 2 points need to be noted.

1. The difference between the supply voltage of the low voltage logic and the supply voltage of the high voltage logic increases.

2. When the level (for example, 0.7V) of the low-voltage side (low-voltage power supply VDD) and the threshold (VTH, for example, 0.7V) of the high-voltage side (high-voltage power supply VDDQ, for example, 3.3V) are at the same level, the level conversion circuit can be driven at the low-voltage power supply VDD level.

Due to these problems, there is a limit to the operation of the conventional level conversion circuit. As described above, the booster circuit disclosed in japanese unexamined patent application publication No. 11-27137 can obtain a level of 2 × VDD only instantaneously, and thus the operation of the level conversion circuit at a low voltage such as 1V or less of the low voltage power supply VDD is difficult in some cases. In addition, since the maximum applied voltage of the low-voltage circuit is 2 × VDD, a MOS transistor of the low-voltage circuit needs to have an oxide film thickness, which affects the high-speed operation.

Further, although there is a conventional example of a level conversion circuit that outputs a 2 × VDD level as a booster circuit (japanese unexamined patent application publication No. h 3-273594), since a 3-fold booster circuit is added to obtain a 2 × VDD level, a MOS transistor having a thicker oxide film is required, and there is a problem that the area increases due to the increase in the number of components.

In addition, although japanese patent application laid-open No. h 11-195975 also discloses that, when the low-voltage side power supply is cut off, there is a problem that a leakage current occurs in the high-voltage side circuit of the subsequent stage. The description in the examples can be seen in detail. In the same publication, if an external control signal is used to suppress the leakage current, and the leakage current can be autonomously controlled in the level conversion circuit, the circuit design is simplified, and the cost can be reduced.

Disclosure of Invention

The present invention provides a semiconductor device including a high-voltage side circuit operated by a high-voltage power supply, a low-voltage side circuit operated by a low-voltage power supply, and a level conversion circuit for converting a signal level of the low-voltage side circuit into a signal level of the high-voltage side circuit, wherein the level conversion circuit can operate even when the low-voltage power supply is converted into a sub-1V voltage.

Another object of the present invention is to provide a semiconductor device including a circuit for preventing a leakage current from occurring in a level conversion circuit in a sleep mode of the low-voltage side circuit.

To this end, the present invention provides a semiconductor device comprising: a 1 st circuit which outputs a 1 st signal having a 1 st power supply voltage amplitude by using a 1 st power supply voltage as an operating voltage, a 2 nd circuit which outputs a 2 nd power supply voltage higher than the 1 st power supply voltage as an operating voltage, and a level conversion circuit which converts the 1 st signal into a signal amplitude corresponding to the 2 nd power supply voltage by using the 1 st and2 nd power supply voltages as operating voltages and outputs the converted signal to the 2 nd circuit, wherein: the level conversion circuit includes a low-voltage circuit section which operates with the 1 st power supply voltage and outputs a differential signal with the 1 st signal as an input, a level conversion section which is composed of 2N-type MOSFETs which receive the differential signal from the low-voltage circuit section as an input, and 2P-type MOSFETs which respectively constitute loads of the N-type MOSFETs, and converts a signal amplitude into the 2 nd power supply voltage amplitude, and a leakage current prevention circuit which detects a decrease in the voltage level of the 1 st power supply and converts an output signal to be output to the 2 nd circuit into the 2 nd power supply voltage when the 1 st circuit is put into a sleep state by cutting off the 1 st power supply.

Another semiconductor device provided by the present invention includes: a 1 st circuit which outputs a 1 st signal having a 1 st power supply voltage amplitude by using a 1 st power supply voltage as an operating voltage, a 2 nd circuit which outputs a 2 nd power supply voltage higher than the 1 st power supply voltage as an operating voltage, and a level conversion circuit which converts the 1 st signal into a signal amplitude corresponding to the 2 nd power supply voltage by using the 1 st and2 nd power supply voltages as operating voltages and outputs the converted signal to the 2 nd circuit, wherein: the level shift circuit includes a level shift section for boosting a transition level of the 1 st signal by a capacitive element and generating a 3 rd signal which transitions between the 2 nd power supply voltage and a voltage lower than the 2 nd power supply voltage by only one 1 st power supply voltage, and an inversion signal of the 1 st power supply voltage level after inverting the 1 st signal; and the level determination part connects the inversion signal of the 1 st power voltage level to the gate of the N-type MOSFET of the circuit connecting the N-type MOSFET and the P-type MOSFET in series to the ground voltage and the 2 nd power voltage, and connects the 3 rd signal to the gate of the P-type MOSFET to perform level determination.

The present invention provides a semiconductor device including: a 1 st circuit which outputs a 1 st signal having a 1 st power supply voltage amplitude by using a 1 st power supply voltage as an operating voltage, a 2 nd circuit which outputs a 2 nd power supply voltage higher than the 1 st power supply voltage as an operating voltage, and a level conversion circuit which converts the 1 st signal into a signal amplitude corresponding to the 2 nd power supply voltage by using the 1 st and2 nd power supply voltages as operating voltages and outputs the converted signal to the 2 nd circuit, wherein: the level conversion circuit includes a level shift section for boosting a transition level of the 1 st signal by a capacitive element and generating a 4 th signal based on an intermediate voltage higher than the 1 st power supply voltage and lower than the 2 nd power supply voltage, and a level determination section for performing level determination by amplifying the 4 th signal.

The present invention provides a semiconductor device including: a 1 st circuit which outputs a 1 st signal having a 1 st power supply voltage amplitude by using a 1 st power supply voltage as an operating voltage, a 2 nd circuit which outputs a 2 nd power supply voltage higher than the 1 st power supply voltage as an operating voltage, and a level conversion circuit which converts the 1 st signal into a signal amplitude corresponding to the 2 nd power supply voltage by using the 1 st and2 nd power supply voltages as operating voltages and outputs the converted signal to the 2 nd circuit, wherein: the level shifter circuit is configured by a latch circuit including a main latch section and a sub latch section which perform a latch operation in synchronization with an external input signal.

The present invention also provides a semiconductor device comprising: a 1 st circuit for outputting a 1 st signal having a 1 st power supply voltage amplitude by using the 1 st power supply voltage as an operating voltage; a 2 nd circuit which takes a 2 nd power supply voltage higher than a 1 st power supply voltage as an operating voltage, and a level conversion circuit which converts the 1 st signal into a signal amplitude corresponding to the 2 nd power supply voltage and outputs the signal amplitude to the 2 nd circuit, taking the 1 st and2 nd power supply voltages as operating voltages, characterized in that: the level conversion circuit includes: an amplification part for amplifying the amplitude of the 1 st signal by using the 1 st power supply voltage as an operation voltage; a level conversion part for converting the output signal of the amplification part into the amplitude of the 2 nd power supply voltage by using the 2 nd power supply voltage as an operation voltage; and means for holding an output of the level conversion section.

The present invention also provides a semiconductor device including: a 1 st circuit which outputs a 1 st signal having a 1 st power supply voltage amplitude with a 1 st power supply voltage as an operating voltage, a 2 nd circuit which outputs a 2 nd power supply voltage higher than the 1 st power supply voltage as an operating voltage, and a level conversion circuit which converts the 1 st signal into a signal amplitude corresponding to the 2 nd power supply voltage with the 1 st and2 nd power supply voltages as operating voltages and outputs the converted signal to the 2 nd circuit, characterized in that: the level conversion circuit includes an amplification section for amplifying the amplitude of the 1 st signal using the 2 nd power supply voltage as an operating voltage, and a device for holding the output of the level conversion section.

When a level conversion circuit is configured in a case where the power supply voltage VDD on the low voltage side is 1V or less (sub-1V), the above configuration can solve the problem that cannot be avoided by the combination of the conventionally disclosed booster circuit and the level conversion circuit of the related art.

According to the present invention, a 2-fold booster circuit capable of obtaining a 2 × VDD level at any time is used, so that the operation can be performed even when the voltage of the low-voltage power supply VDD is 1V or less.

Further, the booster circuit is configured as a circuit which can be configured only by a MOS transistor having a thin gate oxide film thickness and capable of high-speed operation.

In order to facilitate circuit design for preventing leakage current generated in a sleep mode of a circuit block on the low-voltage power supply side, the invention designs a leakage current protection circuit which does not need an external control signal and performs leakage current control autonomously in the circuit block.

Drawings

Fig. 1 is a circuit diagram illustrating an embodiment of a level conversion circuit having a 2-fold boost circuit and a leakage current protection circuit.

Fig. 2 shows potential transitions of respective nodes of the level conversion circuit of fig. 1.

Fig. 3 is an explanatory diagram of an LSI having a sleep mode.

Fig. 4 is a circuit diagram illustrating one embodiment of a leakage current protection circuit using exclusive or.

Fig. 5 is an explanatory diagram for explaining a leak current generation state in the sleep mode.

Fig. 6 is a waveform diagram of the case where the leakage current protection circuit is controlled by exclusive or.

Fig. 7 shows another embodiment of a leakage current protection circuit using an exclusive or.

Fig. 8 shows yet another embodiment of a leakage current protection circuit using exclusive or.

Fig. 9 is a circuit diagram illustrating yet another embodiment of a leakage current protection circuit using an exclusive or.

Fig. 10 is a circuit diagram showing an example of a leakage current protection circuit configured with a latch circuit of a 2-stage inverter.

FIG. 11 is a circuit diagram illustrating one embodiment of power control for the inverter of FIG. 10.

Fig. 12 is a circuit diagram illustrating another embodiment of power control of the inverter of fig. 10.

Fig. 13 is a circuit diagram showing an embodiment of a circuit for cutting off a leakage current by using a power supply stepped down from a high voltage power supply VDDQ.

Fig. 14 is a circuit diagram showing another embodiment of a circuit for cutting off a leakage current by using a power supply stepped down from a high voltage power supply VDDQ.

Fig. 15 is a circuit diagram showing an example in which after an input signal is level-shifted, level conversion is performed using the input signal and the level-shifted signal.

Fig. 16 shows potential transitions of the respective nodes of the embodiment of fig. 15.

Fig. 17 is a circuit diagram showing an embodiment of a level conversion circuit using an intermediate potential.

Fig. 18 shows a transition of potentials of respective nodes of the level conversion circuit of fig. 17.

FIG. 19 is a block diagram illustrating one embodiment of a dynamically controlled level shifting circuit,

Fig. 20 shows (a) a waveform diagram of a control signal and (b) a potential transition diagram of each node in the level conversion circuit of fig. 19.

FIG. 21 is a circuit diagram illustrating one embodiment of implementing the level return circuit of FIG. 19.

Fig. 22 is a circuit diagram showing a conventional example of a level conversion circuit including a booster circuit.

Fig. 23 is a circuit diagram showing a booster circuit disclosed in the conventional example of fig. 22.

Fig. 24 is a circuit diagram showing a conventional example of a circuit for performing level conversion after level shifting.

Fig. 25 is a circuit diagram showing one embodiment of a level conversion circuit using an amplifier.

Fig. 26 is an operation waveform diagram of the embodiment of fig. 25.

Fig. 27 is a circuit diagram showing another embodiment of a level conversion circuit using an amplifier.

Fig. 28 is an operation waveform diagram of the embodiment of fig. 27.

Detailed Description

< example 1>

Fig. 1 shows an embodiment of a semiconductor device of the present invention. The semiconductor device shown in the figure is formed on a semiconductor substrate using CMOS integrated circuit technology. The level conversion circuit LSC is provided between the low voltage logic circuit CB1 driven by the 1 st power supply voltage VDD (for example, 0.7V) and the high voltage logic circuit CB2 driven by the 2 nd power supply voltage VDDQ (for example, 3.3V) relatively higher than the 1 st power supply voltage. The level conversion circuit LSC is composed of a booster circuit portion LSC1 powered by the 1 st power supply voltage VDD and a circuit portion LSC2 powered by the 2 nd power supply voltage VDDQ, and in the present embodiment, the circuit LSC1 includes a 2-fold booster circuit.

Here, reference numerals VSS and VSSQ are ground potentials corresponding to the power supply voltages VDD and VDDQ, respectively, and are usually 0V. In the MOS transistor symbols in the drawings, the gates are represented by a single line and are low-withstand-voltage MOS transistors (P-type and N-type), and the gates are represented by a square and are high-withstand-voltage MOS transistors (P-type and N-type). This notation is also applicable in the following embodiments.

A signal S101 is typically output from low voltage logic circuit CB1 in fig. 1. This is a signal that should be input to the high voltage logic circuit CB 2. The amplitude of the logic signal S101 is an amplitude ranging from the ground voltage VSS to the power supply voltage VDD. For example, the low (Lo) level is 0v (vss), and the high (Hi) level is the power supply voltage VDD. The inverter formed by the PMOS transistor P101 and the NMOS transistor N103 converts the input signal S101 into its complementary signal. The amplitude of the complementary signal is from the ground potential VSS to the power supply voltage VDD.

The boosting section LSC1 is a section for converting the Hi level (VDD) of the signal S101 and its complementary signal into a level 2 times the power supply voltage VDD (hereinafter, referred to as 2 × VDD) by means of a capacitive element constituted by an electrode and a gate for short-circuiting the sources and drains of the NMOS transistors N111, N112, for example. NMOS transistors N101 and N102 are connected to the gate of the capacitor element. The gate of the NMOS transistor N101 is connected to the drain of N102, the gate of N102 is connected to the drain of N101, forming a cross coupling, and the sources of the MOS transistors N101, N102 are connected to the power supply voltage VDD. With this, when the level of the signal S101 is the ground potential VSS, the node nd102 is set to 2 × VDD due to the turn-off of the MOS transistor N101 and the coupling of the capacitive element N112, and the node nd101 is set to the power supply voltage VDD due to the turn-on of the MOS transistor N101.

In the opposite case, that is, in the case where the signal S101 is the power supply voltage VDD, the node nd101 is set to the power supply voltage VDD due to the MOS transistor N101 being off, and the node nd102 is boosted to 2 × VDD due to the coupling of the capacitive element N111, due to the MOS transistor N102 being on.

This situation is shown in fig. 2 (a). Although the waveforms of the signal S101 and the node nd101 are shown in fig. 2(a), the complementary signal of S101 and the waveform of the node nd102 become the inverse of the same figure. The maximum applied voltage to each MOS transistor is indicated here.

The MOS transistors N101 and N102 have the source of the power supply voltage VDD, the gate of the power supply voltage VDD, and the drain of the power supply voltage VDD of 2 × VDD, or have the source of the power supply voltage VDD, the gate of the power supply voltage VDD of 2 × VDD, and the drain of the power supply voltage VDD, and therefore the maximum applied voltage is VDD. The MOS transistors N111 and N112 used as the capacitor elements have a source of 0V, a drain of 0V, and a gate of a power supply voltage VDD, or a source of VDD, a drain of VDD, and a gate of 2 × VDD, and therefore the maximum applied voltage is VDD.

In this stage, the power supply voltages at the nodes nd101 and nd102 are still the same as the amplitude between the ground potential VSS and the power supply voltage VDD. It is then necessary to convert the voltage amplitude to an amplitude between VSS and2 x Vdd. The circuits that implement this conversion are the 2-fold amplitude forming circuits DAFC1 and DAFC2 shown in fig. 1. Since the 2-time amplitude forming circuits DAFC1 and DAFC2 are identical circuits, the description will be made taking the 2-time amplitude forming circuit DAFC1 as an example. The circuit DAFC1 is composed of P-type MOS transistors P102 and P103 and N-type MOS transistors N104 and N105. The MOS transistors P103 and N105 form an inverter that inputs the signal S101 to the gate, and the output thereof is connected to the source of the MOS transistor N104 whose gate has been fixed to the power supply voltage VDD. The node nd102 is connected to the source of the MOS transistor P102 whose gate is fixed to the voltage VDD, and the drain of the MOS transistor P102 and the drain of the transistor N104 are connected to the node nd 103.

Inputs to this circuit DAFC1 are the output signal S101 from the low-voltage logic circuit CB1 and the potential of the node nd102, and possible combinations are that the level of the signal S101 is VSS and the potential of the node nd102 is 2 × VDD, or that the level of the signal S101 is VDD and the potential of the node nd102 is VDD.

In the former case, the source potential of the MOS transistor P102 becomes 2 × VDD, and the gate of the MOS transistor P102 is fixed to the power supply voltage VDD, so that the MOS transistor P102 becomes ON, and the potential of the node nd103 becomes 2 × VDD. At this time, the gates of MOS transistors P103 and N105 connected to signal S101 are at ground potential VSS, so that MOS transistor P103 is turned ON and MOS transistor N105 is turned OFF. As a result, the node nd104 becomes VDD, and if the node nd103 is considered to be 2 × VDD, the MOS transistor N104 becomes OFF.

In the latter case, the source potential of MOS transistor P102 is VDD, and the gate of MOS transistor P102 is fixed to power supply voltage VDD, so that MOS transistor P102 is OFF. At this time, the gates of the MOS transistors P103 and N105 connected to the signal S101 become VDD, the MOS transistor P103 becomes OFF, and the N105 becomes ON. As a result, the node nd104 becomes the ground potential VSS, and the node nd103 becomes VSS. Therefore, the node nd103 becomes the ground potential VSS. Fig. 2(b) shows a waveform diagram of the node nd 105. As described above, the amplitude is between the ground potential VSS and2 × VDD.

In the following, the voltages applied to the respective MOS transistors will be described. First, a case where the potential of the signal S101 is the ground level VSS and the potential of the node nd102 is 2 × VDD is considered. In this case, MOS transistor P102 has a gate of VDD, a source of 2 × VDD, a drain of 2 × VDD, and a maximum applied voltage of VDD, MOS transistor P103 has a gate of VSS, a source of VDD, a drain of VDD, and a maximum applied voltage of VDD. In addition, the MOS transistor N104 has a gate of VDD, a source of VDD, a drain of 2 × VDD, and a maximum applied voltage of VDD, and the MOS transistor N105 has a gate of VSS, a source of VSS, and a drain of VDD, and thus the maximum applied voltage of VDD.

On the other hand, when the level of the signal S101 is VDD and the node nd102 is VDD, the maximum applied voltage is VDD since the gate, the source and the drain of the MOS transistor P102 are VDD and VSS, and the MOS transistor P103, the gate and the source are VDD and VSS, respectively. Further, the MOS transistor N104 has a gate of VDD, a source of VSS, and a drain of VSS, so that the maximum applied voltage is VDD, and the MOS transistor N105 has a gate of VDD, a source of VSS, and a drain of VSS, so that the maximum applied voltage is VDD.

Therefore, the 2 × amplitude formation circuit DAFC1 can make the amplitude of the voltage at the output node nd103 become an amplitude between VSS and2 × VDD, and the maximum applied voltage to each MOS transistor can become VDD regardless of the maximum voltage 2 × VDD used. The 2-fold amplitude forming circuit DAFC2, which is configured in the same manner, outputs the voltage amplitude at the node nd105 in reverse phase with respect to the node nd103, but the basic operation is the same as that of the circuit DAFC1 described above.

The basic operation of the boosting section is as described above, and initialization of the nodes nd101 and nd102 will be described below. To drive the booster circuit LSC1, the nodes nd101 and nd102 must be charged to the power supply voltage VDD in advance. Therefore, it is necessary to use N-type MOS transistors N113 and N114 for pull-up so that the potentials of the nodes nd101 and nd102 become VDD-VTHN (VTHN: threshold voltage of NMOS transistor). However, when the voltage on the low voltage side becomes sub-1V, it is difficult to operate even when the charge level is changed to VDD-VTHN. In this case, embodiments are also conceivable in which: the nodes nd101 and nd102 are set to the power supply voltage VDD by PMOS transistors P111 and P112. The control signal for initializing the nodes nd101, nd102 by means of the MOS transistors P111, P112 is made at S103, so that the event of charging the nodes nd101, nd102 to the VDD level becomes possible surely. The MOS transistors P111 and P112 are also designed as high-voltage MOS transistors in some cases. This is effective in the case where the initialization signal of the level conversion circuit is controlled with a high voltage level (a signal having an amplitude in the range of VSSQ and VDDQ).

Next, a description will be given of a conversion section LSC2 that converts the output signals from the nodes nd103 and nd105 of the booster LSC1 into a signal S102 having a signal amplitude corresponding to the power supply voltage VDDQ. The output voltages from the nodes nd103 and nd105 of the boosting section are input to the conversion section LSC2, and input to the gates of a pair of N-type differential input MOS transistors N108 and N109 in the LSC 2. The conversion section LSC2 includes PMOS transistors P106 and P108 that form a load with respect to the differential input MOS transistors N108 and N109, and PMOS transistors P107 and P109 for breakdown voltage relaxation. PMOS transistors P106 and P107 are connected in series, and P108 and P109 are also connected in series. The PMOS transistor P106 has a source connected to the supply voltage VDDQ, a gate connected to the drain of P109, and a drain connected to the source of P107. The PMOS transistor P107 has a source connected to the drain of P106, a gate connected to the node nd103, and a drain connected to the drain of N108. The PMOS transistor P108 has a source connected to the supply voltage VDDQ, a gate connected to the drain of P107, and a drain connected to the source of P109. The PMOS transistor P109 has a source connected to the drain of P108, a gate connected to the node nd105, and a drain connected to the drain of N109. Thus, the PMOS transistors P106 and P108 are cross-connected. The output of the level conversion section is taken out from the node nd108, inputted to the inverter composed of the PMOS transistor P110 and the NMOS transistor N110 of the subsequent stage, and inputted to the high voltage logic circuit CB2 of the subsequent stage. As shown in fig. 2(c), the amplitude of the waveform at the node nd108 is the amplitude between the ground potential VSSQ and the power supply voltage VDDQ.

As described above, according to the present invention, even when the power supply voltage of the low-voltage logic circuit is significantly low and becomes about the threshold value of the MOS transistor of the high-voltage logic circuit, the power supply voltage on the low-voltage side is boosted by 2 times and then level conversion is performed, so that the level conversion circuit can be operated. In addition, since the maximum applied voltage of all MOS transistors in the circuit of the boosting section LSC1 shown here is VDD, the circuit can be designed with high-speed elements having a thin gate oxide film except for the case where the initialization signal of the level conversion circuit described above is controlled with a high voltage level, and thus has a characteristic that level conversion can be performed at high speed.

However, in such a latch type level conversion circuit, it is necessary to prevent a leakage current which occurs when the power supply on the side of the low voltage logic circuit CB1 is cut off. Here, the mode in which power is cut off in part of the chip in this manner is called a sleep mode. Fig. 3 is a system configuration diagram discussed before the present invention, for explaining the sleep mode. In the figure, in an LSI chip, there are provided a logic circuit CB1 driven by a power supply voltage VDD, an I/O circuit CB2 of an interface section driven by a power supply voltage VDDQ, and a level conversion circuit LSC in between. Examples of the LSI having such 2 kinds of power supplies include a real-time clock circuit, a word line booster circuit of a DRAM, and the like, in addition to an I/O circuit. In such an LSI, it is effective to cut off the power supply to the logic circuit CB1 when the logic circuit CB1 is not in use for the purpose of reducing power consumption, but at this time, the I/O circuit CB2 is tasked with the interface with the surrounding LSI, and therefore, the power supply cannot be cut off.

Further, the level conversion circuit LSC is constituted by the circuit part LSC1 for supplying the low voltage power supply VDD and the circuit part LSC2 for supplying the high voltage power supply VDDQ, and when the power supply of the logic circuit CB1 is cut off, the power supply on the circuit part LSC1 side may be cut off at the same time. At this time, the high voltage power supply VDDQ may be continuously applied on the side of the circuit part LSC 2.

The relationship between the nodes nd107 and nd108 of the latch section and the power supplies VDD and VDDQ in the case where the latch type level conversion circuit shown in fig. 1 is used in such a system is shown in fig. 5. Here, as an initial state, a case where the node nd107 is at the high-voltage power supply level VDDQ and the node nd108 is at the ground level 0V is considered. When the low-voltage power supply VDD is turned off at time T1, the potential of the power supply line connected to the low-voltage power supply VDD gradually drops as indicated by the broken line, and stabilizes at 0V, which is the ground level. At this time, since the MOS transistor N109 is turned OFF from ON, both the MOS transistors P108 and N109 are turned OFF. For this reason, the node nd108 cannot hold the ground level 0V initially held due to the leakage current of the MOS transistors P108 and N109, and the potential rises to the level of the logic threshold of the high-voltage side MOS transistor. As a result, a through current flows through the inverter including MOS transistors P110 and N110.

The main solution strategy is therefore to provide the leakage current protection circuit LPC at nodes nd107 and nd108 of the level shifter LSC. The leakage current protection circuit LPC performs the following operations: the potentials of the nodes nd107, nd108 are latched while ensuring that they are latched at a certain level.

An embodiment of such a leakage current protection circuit LPC is shown in the circuit diagram of fig. 4. The latch portion LTC is constituted by: the output of the inverter constituted by the PMOS transistor P401 and the NMOS transistor N401 is connected to the node nd107, and the output of the inverter constituted by the PMSO transistor P402 and the NMOS transistor N402 is connected to the node nd 108. The power supply to the latch LTC is controlled by a power supply control section PCC. The power control section PCC is controlled with a signal output by an exclusive or circuit EOR of the output signal S102 of the level conversion section LSC2 and the signal of the node nd 107. The power supply control section PCC is introduced for the purpose of reducing the drive current of the latch connected to the nodes nd107 and nd108 without deteriorating the conversion speed at the time of level conversion.

Here, the delay circuit DLY is provided for adjusting the time for performing control, and may be formed by a buffer composed of PMOS transistors P406 and P407 and NMOS transistors N406 and N407, for example, as shown in the drawing. The buffer is formed by an even number of inverters, the number of stages of which should be set to an optimum value by design.

Fig. 6 is a waveform diagram illustrating an operation of the leakage current protection circuit LPC. In fig. 6(a), the operation waveforms of the input signal S101 from the low voltage logic circuit CB1 and the node nd108 are shown, in fig. 6(b), the operation waveforms of the nodes nd107 and nd406 are shown, and in fig. 6(c), the operation waveforms of the nodes nd401 and nd402 are shown. When the input signal S101 becomes the Hi level at the timing of time T1, the nodes nd107 and nd108 start to invert. At this time, since the signal nd406 obtained by delaying the output signal S102 keeps the previous information, the output node nd401 of the exclusive or EOR of the nodes nd107 and nd406 approaches the ground level VSS. Therefore, the node nd401 starts to transit to the ground potential VSSQ, and the node nd402 starts to transit to the power supply voltage VDDQ, and the current of the latch section LTC is controlled to be reduced. When the current of the latch section LTC decreases, the inversion of the nodes nd107 and nd108 is accelerated and determined at the final values (node nd107 is VDDQ and nd108 is VSSQ). When the potential of the node nd108 is determined, and after a certain delay, the information of the node nd108 is also transmitted to the node nd406, the node nd406 becomes inverted with respect to the node nd107, and the output node nd401 of the exclusive or EOR becomes the power supply voltage VDDQ. For this reason, the power supply of the latch section LTC is turned ON completely, and information holding of the nodes nd107 and nd108 is performed. When the input signal S101 becomes Lo level at the timing of time T2, the processing is performed in a relationship in which the ground potential VSSQ and the power supply voltage VDDQ at the above levels are replaced.

As described above, since the level conversion circuit including the 2-time booster circuit and the leakage current protection circuit can perform high-speed level conversion corresponding to a reduction in the voltage of the low-voltage power supply VDD, and can suppress the leakage current generated in the sleep state of the low-voltage logic circuit CB1, a semiconductor device including the level conversion circuit which operates at high speed with low power consumption can be realized.

In addition, when the level conversion circuit described herein is used between a logic circuit operating at a low power supply voltage and an I/O circuit operating at a high power supply voltage, although not particularly limited, a MOS transistor having a thick oxide film used in the I/O circuit may be used as the MOS transistor for high withstand voltage, and a MOS transistor having a thin oxide film used in the logic circuit may be used as the MOS transistor for low withstand voltage. Due to this, the following effects are obtained: the process cost can be changed to the same as that in the case of using the gate oxide film thickness of 2 transistors used in the past.

< example 2>

Fig. 7 is a circuit diagram of an important part showing another embodiment of the leakage current protection circuit LPC of embodiment 1, and the configuration of the power supply control section PCC of fig. 4 is different. Here, illustration of the delay circuit DLY is omitted. That is, fig. 7 is drawn to illustrate the exclusive or circuit EOR and the latch section LTC and the power control section PCC connected to the nodes nd401, nd107, nd 108.

The present embodiment is different from the embodiment of fig. 4 in the constitution of the gate driver circuit of the MOS transistor connected to the power supply of the latch section LTC. That is, in the present embodiment, the features are: inverters supplying power with a low voltage level are connected to the gates of the PMOS transistors P403, P404 and the NMOS transistors N403, N404, respectively. This is an embodiment in which a so-called 'power supply voltage threshold falling' effect is obtained by connecting an NMOS transistor with a short-circuited gate and drain and diode-connected to the source side of a PMOS transistor P703 of an inverter (formed by the PMOS transistor P703 and an NMOS transistor N703) connected to the PMOS transistors P403 and P404 and connecting a PMOS transistor P705 with a short-circuited gate and drain and diode-connected to the source side of one NMOS transistor N703.

The inverter formed by the PMOS transistor P701 and the NMOS transistor N701 is an inverter for matching logic. Due to this, although the MOS transistors P403, P404, N403, N404 become impossible to be completely OFF, the current supplied to the latch section LTC can be suppressed low. Therefore, since the load of the latch section LTC on the level conversion circuit is reduced, there is an advantage that a reduction in the level conversion speed can be suppressed. Even if the MOS transistors P403, P404, N403, and N404 do not become completely OFF, the logic is already determined in the internal latch portion LTC, and therefore, no penetration current occurs during latch holding other than during operation.

In fig. 7, the MOS transistors P403, P404, N403, and N404 for power supply control connected to the latch portion are connected to the respective sources of the inverters constituting the latch, but the MOS transistors P403 and P404 may be integrated into one PMOS transistor and the MOS transistors N403 and N404 may be integrated into one NMOS transistor.

Similarly, the MOS transistors N704, N705, P704, and P705 connected to the source sides of the MOS transistors P702, P703, N702, and N703 may be collectively arranged in one NMOS transistor, and the MOS transistors P704 and P705 may be collectively arranged in one PMOS transistor. Due to this, there is an effect that reduction in layout area can be achieved.

< example 3>

Fig. 8 is a circuit diagram of an important part showing another embodiment of the leakage current protection circuit LPC of embodiment 2, and the configuration of the power supply control section PCC of fig. 7 is different. This embodiment differs from the embodiment of fig. 7 in that such a substitution is made: an NMOS transistor N705 connected to the PMOS transistor P703 is connected to the PMOS transistor P802, an NMOS transistor N704 connected to the PMOS transistor P702 is connected to the PNMOS transistor P801, a PMOS transistor P705 connected to the NMOS transistor N703 is connected to the NMOS transistor N802, and a PMOS transistor P704 connected to the NMOS transistor N702 is connected to the NMOS transistor N801.

These MOS transistors N801, N802, P801, and P802 are diode-connected with their gates and drains short-circuited, respectively. Due to this, the same effect as in example 2 of fig. 7 can be obtained. Further, since the diode-connected NMOS transistor is connected to the NMOS transistor side and the diode-connected PMOS transistor is connected to the PMOS transistor side, it is possible to easily control the process variation.

Similarly to embodiment 2 of fig. 7, the MOS transistors N801, N802, P801, and P802 connected to the source sides of the MOS transistors P702, P703, N702, and N703 may be collectively arranged in one NMOS transistor and P801 and P802 may be collectively arranged in one PMOS transistor. Due to this, there is an effect that reduction in layout area can be achieved.

< example 4>

Fig. 9 is a circuit diagram of an important part showing another embodiment of the leakage current protection circuit LPC of embodiment 1, and the configuration of the power supply control section PCC of fig. 4 is different. This is an embodiment in which the number of MOS transistors is reduced as compared with the embodiment of fig. 7 and 8, and in fig. 4 of embodiment 1, the PMOS transistor P901 having its gate grounded is newly connected to the source sides of the PMOS transistors P403 and P404, and the NMOS transistor N901 having its gate supplied with the power supply voltage VDDQ is newly connected to the source sides of the NMOS transistors N403 and N404. The method is characterized in that: due to the ON resistance in the linear region (non-saturation region) using the drain currents of the PMOS transistor P901 and the NMOS transistor N901, it is possible to reduce the supply current to the latch portion LTC and perform integration with a small area.

< example 5>

Fig. 10 is a circuit diagram of an important part showing still another embodiment of the leakage current protection circuit LPC of embodiment 1. The present embodiment is a leakage current protection circuit LPC constituted only by the latch portion LTC, and does not require the delay circuit DLY, the exclusive or EOR, and the power supply control circuit PCC of fig. 4. The leakage current protection circuit LPC of fig. 10 may be connected to the nodes nd107 and nd108 of fig. 1. This is the simplest leakage current protection circuit, and is effective because the area is the smallest when the reduction in conversion speed does not become a problem.

< example 6>

Fig. 11 is an embodiment in which the leakage current protection circuit LPC shown in fig. 10 of embodiment 5 is provided with a power supply control circuit PCC. The method is characterized in that: the PMOS transistor P1101 is again connected in series to the sources of the PMOS transistors P401, P402 constituting the latch section LTC and the ground potential VSSQ is applied to the gate of P1101, and then the NMOS transistor N1101 is connected in series to the sources of the NMOS transistors N401, N402 and the power supply voltage VDDQ is applied to the gate of N1101.

Due to such a configuration, the following effects are obtained: while the capacitance appearing ON the nodes nd107 and nd108 can be suppressed, since the ON resistance can be increased due to the increase in the gate length Lg of the MOS transistors P1101 and N1101, the current flowing in the latch section LTC is suppressed, and the trouble of lowering the level conversion speed can be avoided.

< example 7>

Fig. 12 is a circuit diagram showing another embodiment of the power supply control circuit PCC in the leakage current protection circuit LPC shown in fig. 11 of embodiment 6. The present embodiment is characterized in that: a voltage higher than the ground potential VSSQ by the threshold voltage of only one PMOS transistor P1201 is supplied to the gate of the PMOS transistor P1101, and a voltage lower than the power supply voltage VDDQ by the threshold voltage of only one NMOS transistor is supplied to the gate of the NMOS transistor N1101. The PMOS transistor P1201 is diode-connected with its gate and drain short-circuited, and the NMOS transistor N1201 is also diode-connected with its source and drain short-circuited. Because of this, since the supply current to the latch portion LTC can be suppressed, there is an effect that the possibility of lowering the level conversion speed can be avoided.

< example 8>

Fig. 13 shows another embodiment of a circuit which can suppress a leak current occurring at the time of sleep of the low-voltage power supply VDD side circuit CB1 in a level conversion circuit having no 2-fold booster circuit. Since the high-voltage side power supply VDDQ is continuously supplied even when the circuit CB1 is in a sleep state, a new power supply VDD2 of the low-voltage power supply VDD level is generated by the step-down power supply generation circuit VDC, and control for preventing a leakage current is performed by this power supply.

The power supply VDD2 output from the step-down power supply generation circuit VDC is input to the power supply selection circuit PSC. In the power supply selection circuit PSC, when the low voltage power supply VDD is disconnected, the selection power supply VDD2 is controlled. The power supply VDD2 inputted to the power supply selection circuit PSC is inputted to the source of the PMOS transistor P1302. The low-voltage power supply VDD is input to the source of the PMOS transistor P1303 and the inverter composed of the PMOS transistor P1301 and the NMOS transistor N1301. The output of the inverter constituted by the PMOS transistor 1301 and the NMOS transistor N1301 is input to the gate of the PMOS transistor P1303, and due to this, when the low-voltage power supply VDD is being supplied, the low-voltage power supply VDD can be selected because the PMOS transistor P1303 will be turned ON and the PMOS transistor P1302 will be turned OFF. When the low voltage power supply is turned OFF, the PMOS transistor P1303 is turned OFF and the PMOS transistor P1302 is turned ON, so that the power supply VDD2 can be selected. Selected ones of these power supplies VDD and VDD2 are output as low voltage power supplies VDD 3.

The low-voltage power supply VDD3 output from the power supply selection circuit PSC is input to the circuit LSC1, the source of the PMOS transistor of the NAND gate circuit including the PMOS transistors P1304 and P1305 and the NMOS transistors N1302 and N1303, and the source of the PMOS transistor P1306 of the inverter including the PMOS transistor P1306 and the NMOS transistor N1304, respectively. The NAND gate circuit is configured with a 2-input 1-output, and receives a signal S1301 output from the VDD side circuit CB1 and a power supply voltage VDD. The output of the NAND gate circuit is input to the gates of MOS transistors P109 and N109 of circuit portion LSC2 after logical inversion by means of the gates of MOS transistors P107 and N108 of circuit portion LSC2 and the inverter constituted by MOS transistors P1306 and N1304.

When the circuit LSC1 is configured as described above, the node nd107 is forcibly converted to the ground potential VSS1 and the node nd108 is forcibly converted to the power supply voltage VDDQ when the low voltage power supply VDD is cut off. Therefore, since the node nd107 can always be set to a node at which logic becomes indeterminate when the low-voltage power supply VDD is turned off, a leak current generated in the inverter of the subsequent stage connected to the node nd108 can be prevented. This circuit can be operated only in a short period of time when the low voltage power supply VDD is turned off or when the high voltage power supply VDDQ is turned on when the circuit is powered on (normally, the low voltage power supply VDD side can be turned on after the high voltage power supply VDDQ is turned on), and therefore, the ability to maintain the power supply voltage VDD2 of the step-down power supply generation circuit VDC is not problematic even if it is low.

The configuration of this embodiment eliminates the need for providing a latch in the signal transmission path in the level conversion circuit, and thus allows high-speed level conversion without causing a problem of leakage current.

< example 9>

Fig. 14 is still another embodiment of the leakage current protection circuit shown in embodiment 8. The difference from fig. 13 is that an inverter composed of MOS transistors P1401 and N1401 is provided instead of the NAND gate circuit so that the low-voltage power supply VDD3 can be input to the source of the PMOS transistor P1401 constituting the inverter. Due to this, even if the low voltage power supply VDD is cut off, since power is supplied to the inverter composed of the MOS transistors P1306 and N1304 of the previous stage connected to the circuit LSC2, a leakage current occurring in the inverter composed of the MOS transistors P110 and N110 does not occur.

At this time, the node nd1401 falls to the ground potential VSS level, and the node nd108 becomes the high voltage power supply VDDQ, so that the leakage current is cut off with high safety. A latch circuit powered by the low-voltage power supply VDD3 (for example, a latch circuit in which a 2-stage inverter is looped as shown in fig. 10) may be provided at the node nd401 to which a signal from the low-voltage side circuit CB1 is input. In this case, since the logic of the inverter constituted by the MOS transistors P1401 and N1401 is continuously determined, the leakage current is cut off with high safety.

< example 10>

Fig. 15 shows a further embodiment of the semiconductor device of the invention. This embodiment is an embodiment of a semiconductor device including a level conversion circuit effective in a case where a difference between a low-voltage-side power supply VDD (for example, 1V) and a high-voltage-side power supply VDDQ (for example, 3.3V) is very large.

When the difference between the low-voltage power supply VDD and the high-voltage power supply VDDQ is very large, if a conventional latch-type level conversion circuit is used, it is necessary to invert the contents of the latch in order to transmit a logic inversion signal of an already input signal. When the low-voltage power supply VDD has a low amplitude, the driving force of the NMOS transistor required for inverting the latch content cannot be sufficiently obtained, and thus the level shift becomes a problem of a low speed. Thus, in the present embodiment, a constitution will be disclosed in which: a method of performing level conversion using an input signal and a signal having the same transition amplitude with which the transition level of the input signal is shifted, instead of using level conversion in a latch section, is adopted to avoid a reduction in conversion speed.

The semiconductor device shown in fig. 15 is formed on a semiconductor substrate by CMOS integrated circuit technology. The level conversion circuit LSC is composed of a level shift section LVSFT and a level determination section LVDET, and is provided between a low-voltage logic circuit CB1 driven by a 1 st power supply Voltage (VDD) and a high-voltage logic circuit CB2 driven by a 2 nd power supply Voltage (VDDQ) relatively higher than the 1 st power supply voltage.

The level shift section LVSFT converts the signal S1501 output from the low voltage logic circuit CB1 and the signal Lo level (VSS) logically inverted by the inverter constituted by the PMOS transistor P1503 and the NMOS transistor N1501 are connected to, for example, electrodes for short-circuiting the sources and drains of the NMOS transistors N1504 and N1505 and a capacitor element constituted by gate electrodes to the VDDQ-VDD level. PMOS transistors P1501 and P1502 are connected to the other terminals of the capacitor element. The PMOS transistors P1501 and P1502 are cross-coupled by connecting the gate of P1501 and the drain of P1502, and connecting the gate of P1502 and the drain of P1501. The sources of the PMOS transistors P1501 and P1502 are connected to a high-voltage power supply VDDQ.

Due to such a configuration, when the signal S1501 is 0V and the node nd1503 is the low-voltage power supply voltage VDD, the node nd1501 is set to the VDDQ-VDD level by coupling of the capacitive element N1504, and the node nd1502 is set to the high-voltage power supply voltage VDDQ by turning ON the PMOS transistor P1502. In the opposite case, that is, in the case where the signal S1501 is VDD and the node nd1503 is 0V, the node nd1502 is set to the VDDQ-VDD level by the coupling of the capacitive element N1505, and at the same time, the node nd1501 is set to the high-voltage side power supply VDDQ due to the PMOS transistor P1501 becoming ON. Fig. 16(a) shows this operation state. In fig. 16(a), although the waveforms of the signal S1501 and the node nd1501 are shown, the waveforms of the nodes nd1503 and nd1502 become the inverse of those of the same figure.

The outputs from the level shift section LVSFT are nodes nd1502 and nd 1503. The node nd1502 is input to the gate of the PMOS transistor P1504 of the level determining section LVDET, and the node nd1503 is input to the gate of the NMOS transistor N1502 of the level determining section.

Here, the node nd1502 is a signal having an amplitude shifted from VDDQ-VDD to VDDQ VDD, and the node nd1503 is a signal having a VDD amplitude shifted from the ground level VSS to the low-voltage power supply VDD. Therefore, the node nd1502 is to turn the PMOS transistor P1504 to the full OFF or half ON state, and the node nd1503 is to turn the NMOS transistor N1502 to the full OFF or half ON state. Since the Hi level of the node nd1502 and the Hi level of the node nd1503 are completely inverted, the PMOS transistor P1504 and the NMOS transistor N1502 do not become a half ON state at the same time. The result is that the coupled drains of MOS transistors P1504 and N1502 will become VDDQ amplitude signals. The coupled signal provided by the drain is input to an inverter formed by a PMOS transistor P1505 and an NMOS transistor N1503, and the output signal S1502 is input to a high voltage logic circuit CB2 in the subsequent stage. Fig. 16(b) shows an operation state of the output signal S1502.

The circuit LPC including the inverter including the MOS transistors P1506 and N1504 and the inverter including the MOS transistors P1507 and N1505 in fig. 15 is a leakage current protection circuit including only the latch similar to the leakage current protection circuit LPC shown in fig. 10 of embodiment 5.

In the semiconductor device of this embodiment, since the PMOS transistor and the NMOS transistor of the logic circuit CB2 on the high voltage side are driven, level conversion with a larger voltage difference than that in the prior art can be performed at high speed.

< example 11>

Fig. 17 shows still another embodiment of the semiconductor device of the present invention. This embodiment is another embodiment of a semiconductor device including a level conversion circuit effective when the difference between a low-voltage-side power supply VDD (for example, 0.7V) and a high-voltage-side power supply VDDQ (for example, 3.3V) is very large. The level conversion circuit LSC is composed of a level shift section LVSFT and a level determination section LVDET, and is provided between a low-voltage logic circuit CB1 driven by a 1 st power supply Voltage (VDD) and a high-voltage logic circuit CB2 driven by a 2 nd power supply Voltage (VDDQ) relatively higher than the 1 st power supply voltage.

In fig. 17, the low voltage logic circuit CB1 representatively outputs a signal S1701. This is the signal to be input to the high voltage logic circuit. The amplitude of the logic signal S1701 ranges from the ground voltage VSS to the power supply voltage VDD. For example, the Lo level is 0V, and the Hi level is the power supply voltage VDD. The input signal S1701 is input to an inverter including a PMOS transistor P1703 and an NMOS transistor N1703 in the level determining section LVDET through the capacitive element N1701, and a signal after logic inversion is output to the node nd 1702. The level shift section LVSFT converts the Hi level (VDD) of the signal at the node nd1701 into VDM + VDD by means of a capacitive element constituted by, for example, an electrode for short-circuiting the source and drain of the NMOS transistor N1701 and a gate electrode. Here, VDM is an intermediate potential which is approximately half the voltage of the high-voltage power supply VDDQ, and may be obtained by either externally applying VDM or by lowering VDM from the high-voltage power supply VDDQ or raising VDM from the low-voltage power supply VDD in the semiconductor device. The gate of the capacitor element N1701 is connected to the drain of a PMOS transistor P1701. The PMOS transistor P1701 has become a diode connection with the gate and drain shorted, the source connected to the intermediate potential VDM.

Due to such a configuration, when the signal S1701 is 0V, the node nd1701 becomes VDM, and conversely, when the signal S1701 is VDD, the coupling of the node nd1701 by the capacitive element N1701 becomes VDM + VDD. Fig. 18(a) shows this operation state. Fig. 18(a) shows waveforms of a node nd1701 and a signal S1701.

The signal at the above-mentioned node nd1702 is also input to the inverter constituted by the PMOS transistor P1706 and the NMOS transistor N1706 through the gate of the inverter constituted by the PMOS transistor P1704 and the NMOS transistor N1704 in the level determining section LVDET. In view of its characteristics, the inverter can amplify and transmit even a minute signal having a level of about half of the power supply voltage VDDQ, and can perform level conversion at high speed. The waveform of the signal S1702, which is the conversion result output from the inverter including the PMOS transistor P1706 and the NMOS transistor N1706, is shown in fig. 18 (b).

However, in the case where the input of the inverter as in the present embodiment is a minute signal in the vicinity of the intermediate potential VDM, the NMOS transistor and the PMOS transistor of the inverter which have become the input of the signal as a result can be used in the half ON state. For this reason, in a general CMOS circuit, such a problem arises: due to the penetration current that is not found by completely turning OFF the MOS transistor on the P side or the N side, it occurs during standby in the case of the above-described configuration. This problem can be solved mainly by a latch means for latching the control signal for controlling the power supply from the inverter from the outside and the level-converted information.

For power supply control, it is conceivable to provide an NMOS transistor N1702 at the source of an NMOS transistor N1703 of an inverter receiving an input from a node nd1701, a PMOS transistor P1702 at the source of the PMOS transistor P1703, a gate of the PMOS transistor P1702 connected to an external signal S1703, and a gate of the NMOS transistor N1702 connected to the inverted signal of the external signal S1703, respectively, to perform switching control. The inversion signal is generated by an inverter composed of a PMOS transistor P1705 and an NMOS transistor N1705.

In addition, when sufficient level determination can be performed by using an inverter including the PMOS transistor P1703 and the NMOS transistor N1703, the inverter including the PMOS transistor P1704 and the NMOS transistor N1704 may be omitted. In this embodiment, although 2-stage inverters are assumed for simplicity, the number of inverters is determined to be as large as the number of optimum stages that can be added because the number of inverters is determined to be optimum in LSI design. The power supply for these inverters is characterized by: driving is performed with MOS transistors P1702 and N1702. In addition, as for other inverters in which leakage current is a concern, such an approach may also be considered: a PMOS transistor is connected in series to a source portion of a PMOS transistor constituting an inverter, and an NMOS transistor is also connected in series to a source portion of an NMOS transistor, and then a current supplied to the inverter is reduced. In this case, although the conversion speed is somewhat slow, the conversion speed has an effect of reducing power consumption.

When the power supply is cut off by the MOS transistors P1702 and N1702, although the conversion result needs to be held, this can be held by a latch circuit including an inverter formed by the MOS transistors P1506 and N1504 and an inverter formed by the MOS transistors P1507 and N1505. This latch circuit LPC is a leakage current protection circuit constituted only by a latch similar to the leakage current protection circuit LPC shown in fig. 10 of embodiment 5, similarly to embodiment 10, and can avoid generation of a penetration current due to uncertainty of the input level of the inverter at the time of power-off, owing to the conversion result of the holding node nd 1703.

When the latch circuit LPC is subjected to the power supply control described in embodiment 1 or embodiment 2, the conversion speed is not deteriorated, and the efficiency is high. In this case, for example, it is conceivable to xor the levels of the node nd1703 and the signal S1702.

< example 12>

Fig. 19 is a block diagram showing still another embodiment of the semiconductor device of the present invention. The present embodiment is an embodiment of a level conversion circuit in which the power supply VDD (for example, 0.5V) of the low-voltage circuit CB1 is effective to the same level as or less than the threshold value (for example, 0.7V) of the MOS transistor constituting the high-voltage circuit CB2 using VDDQ (for example, 3.3V) as the power supply.

The present embodiment is configured by a master latch MLTC having a precharge mechanism, a slave latch SLTC, a switch SW1 provided between a low-voltage circuit CB1 and the master latch MLTC, and a switch SW2 provided between the master latch MLTC and the slave latch SLTC. This is a dynamic level conversion circuit that performs level conversion in synchronization with an external signal (for example, a clock).

Here, the power supplies of the level conversion circuit LSC are VDDQ and VSSQ, and the power supply relationship with the high-voltage circuit CB2 of the subsequent stage is the same. In this embodiment, when the power supply VDD of the low voltage circuit CB1 becomes around or below the high voltage power supply VDDQ and the threshold of the high voltage side MOS transistor, the high voltage side MOS transistor cannot be directly driven. Thus, this embodiment is an embodiment that converts the VDD amplitude to the VDDQ amplitude with a sense amplifier of the type that may be used in a DRAM circuit. The sense amplifier is a differential input amplifier, and is configured to cause a pair of differential input lines to be in a quasi-stable state (precharge) in advance, and to input a VDD-amplitude signal and its inverted signal as a minute signal to each of the pair of differential input lines to perform differential amplification.

Fig. 21 shows a circuit for implementing such control. The clock CLK is input to an OR gate OR1, AND gates AND1 to AND3, AND an inverter INV 3.

First, a signal for controlling the circuit will be described. The state of the precharge signal PCH is determined by the output of an OR gate OR1 that performs the logical OR of the clock CLK and the sense enable signal SEN. The state of the signal SWE1 for turning on AND off the switch SW1 is determined by the result of the output of the exclusive or gate EXOR1 for performing exclusive or of the signal delayed by the precharge signal by the delay circuit DL1 AND the output of the AND gate AND2 for performing logical AND with the clock CLK.

The read enable signal SEN is determined by the output of the AND gate AND3 which outputs the logical AND of the signal PCH2 delayed by the execution delay circuits DL1 AND DL2 from the clock CLK AND the output of the AND gate AND4 which outputs the logical AND between the execution signal PCH2 AND the logical negation of the clock output by the inverter INV3, AND which is input to the OR circuit OR 2.

The signal SWE2 for controlling the on/off of the switch SW2 is determined by the output result of the AND gate AND1 that performs the logical AND between the clock CLK AND the read enable signal SEN delayed by the delay circuit DL 3.

Next, the operation of the master latch portion MLTC shown in fig. 21 will be described. The signal S2101 input from the low-voltage circuit CB1 is divided into positive logic or negative logic inverted by an inverter in the switch SW1, and then input to the analog switch formed by the PMOS transistor P2104 and the NMOS transistor N2104 and the analog switch formed by the PMOS transistor P2105 and the NMOS transistor N2105, respectively.

To the gates of these analog switches, a signal SWE1 is input to an NMOS transistor, and a signal obtained by inverting a signal SWE1 by an inverter INV2 is input to a PMOS transistor for control. The outputs from these analog switches are connected to the capacitance elements N2106 and N2107 being precharged by the NMOS transistors N2109 and N2110 in the precharge state. Capacitive elements N2106 and N2107 are connected to nodes nd2101 and nd2102 of the differential line pair. The differential line pair is precharged to VSSQ by NMOS transistors N2111, N2112, and N2113.

The precharge is controlled by driving the NMOS transistors N2109, N2110, N2111, N2112, and N2113 with the precharge signal PCH. A signal of low voltage amplitude is transmitted to the nodes nd2101 and nd2102 by means of the capacitive elements N2106, N2107. For example, if the signal S2101 is at a low (Lo) level, the node nd2101 is set to VSSQ, and the node nd2102 is set to VDD. The small signal is converted to VDDQ amplitude level by a sense amplifier including PMOS transistors P2101 and P2102 and NMOS transistors N2101 and N2102.

The sense amplifier can be started by operating the gates of the MOS transistors P2103, N2103 connected to the power supplies VDDQ and VSSQ, respectively. The start-up uses the read start signal SEN described above. The enable signal SEN is input to the gate of the PMOS transistor P2103, and a signal obtained by logically inverting the enable signal SEN by the inverter INV4 is input to the gate of the NMOS transistor N2103.

The signal converted to the level of the high voltage power supply VDDQ is transmitted to the sub latch unit SLTC of the subsequent stage through an analog switch SW2 including a PMOS transistor P2109 and an NMOS transistor N2108. Controlling the switch SW2 is the signal SWE 2. The signal SWE2 is connected to the gate of the NMOS transistor N2108, and the signal SWE2 is logically inverted by the inverter INV5 and is transmitted to the PMOS transistor P2109.

Next, the secondary latch unit SLTC is explained. This is a circuit which can hold the converted signal outputted by turning ON the switch SW2 even if the switch SW2 is turned OFF, and here, a latch constituted by 2 stages of inverters INV6 and INV7 is shown. The signal level-shifted by the master latch section MLTC and passed through the switch SW2 is input to the high voltage logic circuit CB2 through the slave latch SLTC.

An example of control of the dynamic level conversion circuit including the switch SW1, the main latch section MLTC, the sub latch section, and the switch SW2 as described above will be described with reference to the timing chart shown in fig. 20 (a). The level conversion circuit starts control of each section in synchronization with a rising edge of a clock. In the same figure, arrows denoted by numerals are added to sequentially show the state in which signals triggered by the rising edge of the clock signal propagate to each section.

First, at time T1, the precharge signal PCH becomes Lo level simultaneously with the rising edge of the clock CLK, and the precharge is ended (see arrow 1).

Next, by lowering precharge signal PCH, switch SW1 is turned ON, so that signal SWE1 becomes high (Hi) level (see arrow 2).

Then, the signal SWE1 briefly remains the same as the Hi level, but then becomes the Lo level. At the timing when the signal SWE1 rises and then becomes Lo (after a short delay), the readout start signal SEN becomes Hi level, and readout starts (see arrow 3).

In order to match the read end time, the rising edge of the read enable signal SEN is delayed by a delay circuit or the like, and the delayed read enable signal SEN is set to the Hi level, so that the signal SWE2 is set to the Hi level, and the switch SW2 is set to the ON state (see arrow 4).

At the falling edge of the clock CLK at time T2, the signal SWE2 transitions to the Lo level (see arrow 5). Due to this, the switch SW2 becomes OFF.

When the signal SWE2 is detected to be at Lo level, the enable signal SEN is at Lo level, and the readout is terminated (see arrow 6).

The precharge signal PCH becomes Hi level (see arrow 7) to start precharging due to the enable signal SEN becoming Lo level.

As described above, in one cycle of the clock CLK, the signal inputted from the low voltage logic circuit CB1 is changed in level and transmitted to the high voltage logic circuit CB 2.

Next, a signal transmission state during level conversion will be described with reference to fig. 20 (b). The times T1, T2, and T3 in fig. 20(b) are the same as the times T1, T2, and T3 in fig. 20 (a). It is assumed in the explanation that the signal S2101 from the low voltage logic circuit CB1 is in the Lo level state (VSS level) at the timing of time T1.

At the rising edge of the clock CLK, the operations of the respective sections are performed. The signal S2101 is transmitted to the nodes nd2101 and nd2102 by turning ON the switch SW1 from the precharge state. At this time, the node nd2102 is changed to VDD by the capacitive coupling, and the node nd2101 remains unchanged. When the sense amplifier is started up in this state, the node nd2102 is amplified to VDDQ, and the node nd2101 is amplified to VSSQ. After the amplification is completed, the switch SW2 is turned ON, and the signal is transmitted to the sub-latch unit SLTC and becomes the output signal S2102.

As described above, characterized in that: even when the low-voltage power supply VDD is very low in level and becomes equal to or lower than the threshold of the high-voltage MOS transistor, the level conversion can be performed at high speed. The dynamic level conversion circuit disclosed herein is not limited to the present embodiment, and can be applied to a level conversion circuit having such a control and precharge mechanism for dynamic operation.

< example 13>

Fig. 25 shows an embodiment of a level conversion circuit for converting an amplitude of an output signal after an input signal is amplified by an amplifier. The circuit is composed of the following parts: an amplifier section AMP that amplifies an input signal with an amplifier; a level determining section LVUP constituted by an existing type level converting circuit; a leakage current protection circuit LPC for holding the determined level of the level determining section and suppressing a leakage current generated in the inverter of the subsequent stage; a level down circuit LVDN for feeding back the output signal with large amplitude to the control circuit to reduce the amplitude of the signal; and a control section CTR for performing start and stop control of the amplifier. In the figure, the amplifier section connects power supplies VDDQ and VSSQ, and shows an example of a current mirror type operational amplifier. The operational amplifiers OP1 and OP2 must always flow a current to amplify a minute signal. However, in order to reduce power consumption, it is desirable that a current flows only when the level conversion circuit is operated. Therefore, the normal current must be reduced during non-operation. This control is generally realized by a control section CTR. The control section will be described later, and the features are: the gate voltages of the current control MOS transistors P2 and P3 of the operational amplifier are controlled such that a current is caused to flow to the operational amplifiers OP1 and OP2 only after the level transition of the input signal is detected, the input signal is propagated to the output signal via the level conversion circuit, and the current flowing to the operational amplifiers is cut off after the level transition of the output signal is detected.

Here, a method of converting a small-amplitude input signal into a large-amplitude signal will be described. First, an input signal is input to the operational amplifier for level conversion, and is also input to the control section CTR. The control part starts the operational amplifier after detecting that the input signal has changed. On the other hand, input signals input to the operational amplifier are divided into complementary signals i1 and/i 1 by inverters INV1 and INV 2. The complementary signals i1 and/i 1 are amplified, and then the complementary signals out1 and/out 1 are output from the operational amplifiers as output signals. The complementary signals out1 and/out 1 are input to a conventional level conversion circuit, and finally converted into output signals having VDDQ amplitudes. Then, the control section CTR performs control of cutting off the supply of current to the operational amplifier by using the change in the output signal.

The operational amplifier detects a state in which only the input signal transits and a state in which the level conversion circuit starts the transition of the output signal, using a delay generated until the input signal is transmitted to the output signal, and controls the operational amplifier. However, since the levels of signals are different before and after level conversion, comparison cannot be simply performed with a general logic circuit. For this purpose, a feedback signal fb is formed in which the amplitude of the output signal after level conversion is again reduced (level-reduced) to an amplitude equal to that of the input signal so that comparison with the input signal is performed by a logic circuit of low amplitude.

The comparison circuit may be implemented by an exclusive or EOR of the input signal and the feedback signal when the input signal and the feedback signal are logically identical. By means of which the operational amplifier control signal exout can be generated. The signal output becomes high level (VDD) only when the input signal has transitioned, and becomes low level (0V) immediately when the level conversion circuit starts the output transition.

Next, a method of activating the above-described operational amplifiers OP1 and OP2 will be described using the operational amplifier control signal. In the operational amplifiers OP1 and OP2 shown in fig. 25, there are PMSO transistors P3 and P4 for current control, and their gates are connected to the gate and drain of a PMOS transistor P1 forming a current mirror. The drain of the NMOS transistor N1 is connected to the drain, and the operational amplifier control signal is connected to the gate of the NMOS transistor N1. When the input signal transits, the operational amplifier enable signal becomes high (VDD). Therefore, the NMOS transistor N1 becomes ON, and the node nd2501 becomes low (0V). When the node nd2501 becomes low (0V), the current control PMOS transistors P3 and P4 of the operational amplifier turn ON, and thus the operational amplifier is turned ON by supplying a current to the operational amplifier. As a result, the input complementary signals in1,/in 1 are amplified by the op-amp to a voltage value determined by the gain of the op-amp. Here, even if the power supply voltage VDD of the input signal IN is low such as 1V or less, since the latch is not configured as IN the conventional level conversion circuit, the signal amplitude can be converted at a higher speed at a lower voltage than IN the conventional technique.

Then, the output complementary signals out1 and/out 1 are converted into logic of amplitude of VDDQ and VSSQ by a conventional level conversion circuit, and the output signal level is shifted and determined. When the output signal transitions, the level of the signal whose level has been lowered also transitions, and the output of the exclusive or EOR also becomes low (0V). Therefore, the NMOS transistor N1 becomes OFF, and the potential level of the node nd2501 changes to VDDQ. Due to this, the current control PMOS transistor of the operational amplifier is also turned OFF, and thus current does not flow to the operational amplifier any more. Thus, the current consumption is reduced.

In order to make the potential of the node nd2501 completely VDDQ, the PMOS transistor P2 is used in the present embodiment. The PMOS transistor P2 is sized so that the ratio to the NMOS transistor N1 becomes sufficiently small and VSSQ is always added to its gate. By designing in this way, the driving capability of the NMOS transistor N1 is large when the NMOS transistor N1 is turned ON, and therefore the node nd2501 is low, but only a path to VDDQ can be formed when the NMOS transistor N1 is turned OFF, and therefore the node nd2501 can be kept high (VDDQ). Here, although VSSQ is always applied to the gate of the PMOS transistor P2, the potential of the gate may be controlled by a control signal by another method. For example, if control is performed such that the PMOS transistor P2 can be turned OFF when the NMOS transistor N1 operates, the time for turning the node nd2501 to the low level (0V) at the time of starting the operational amplifier becomes faster although the control itself becomes complicated, and thus there is an effect that the level conversion becomes faster as a result.

However, as described above, when the current interruption control is performed when the operational amplifier is not in operation, the levels of the outputs out1 and/out 1 of the operational amplifier may be uncertain. This is because the voltage at the node at the high level (Vamp) gradually drops after the supply current of the operational amplifier is cut off, and the high level (Vamp) side potentials of the outputs out1 and/out 1 become unstable. When the high level of any of the output out1 and/out 1 of the operational amplifier falls, the output of the conventional level conversion circuit changes, and as a result, a current flows through the inverter in the subsequent stage. To avoid this, a leakage current protection circuit must be provided.

As the leakage current protection circuit, for example, a circuit in which 2 NMOS transistors are inserted between the node nd2502 and the node nd2503 is conceivable. Here, one MOS transistor has a gate connected to the node nd2502 and a drain connected to the node nd2503, and the other MOS transistor has a drain connected to the node nd2502 and a gate connected to the node nd 2503. Due to this, the levels of the nodes nd2502, nd2503 can be completely fixed to VDDQ or VSSQ. With this leakage current protection circuit, even if the input level of the conventional level conversion circuit drops from the high level (Vamp), the output of the conventional level conversion circuit can be kept at a constant level, and thus there is no possibility that leakage current occurs in the inverter at the subsequent stage.

Further, the leakage current protection circuit can also be realized with the circuits shown in embodiments 1 to 9. As described above, with this embodiment, even in the case where the power supply voltage of the low amplitude logic is as low as 1V or less, the conversion to the high amplitude logic can be performed after the input signal is amplified. In addition, in the present embodiment, since the differential amplifier is used to amplify the input signal, it is also effective to perform stable level conversion even at a low voltage.

Fig. 26 is an operation waveform diagram of the circuit of fig. 25. First, a case where the input transitions from the low level (0V) to the high level (time T1) will be described. Immediately after the state of the input signal IN transitions from the low level (0V) to the high level (VDD), the state of the feedback signal fb does not change. Therefore, when the time T1 elapses, the input signal IN is at the high level (VDD) and the feedback output signal fb is at the low level (0V), so that the output exout of the exclusive-or circuit becomes the high level (VDD).

When the output exout of the exclusive or circuit becomes high level (VDD), the gate of the current control MOS transistor of the operational amplifier (i.e., the node nd2501) becomes low level (0V). If the operational amplifier is started, the potential difference of the input complementary signals i1 and/i 1 is detected, the output complementary signal out1 of the operational amplifier is shifted to a low level (0V), and/out 1 is shifted to a high level (Vamp). The output complementary signals OUT1 and/OUT 1 are input to the conventional level conversion circuit, and the voltage level of the output signal OUT is shifted. When the output signal OUT is logically determined (time T2), the output fb of the level down circuit also changes from the low level (0V) to the high level (VDD), and the output exout of the exclusive or circuit also changes to the low level (0V) because the input signal in is high. When the output exout becomes low (0V), the gate (nd2501) of the current control MOS transistor of the operational amplifier becomes high (VDDQ), and the current supply to the operational amplifier is cut off. When the current supply to the operational amplifier is cut off, the high (Vamp) side of the output out1,/out 1 of the operational amplifier (here,/out 1) gradually falls. However, as described in fig. 25, since the leakage current protection circuit has been provided, the output OUT of the level conversion circuit can maintain the determination logic.

Next, a case (around time T3) where the input IN transitions from the high level (VDD) to the low level (0V) will be described. IN this case, the state of the feedback signal fb does not change immediately after the state of the input signal IN transitions from the high level (VDD) to the low level (0V). Therefore, when the input signal IN is at the low level (0V) and the feedback signal fb is at the high level (VDD) at a point of time T3, the output exout of the exclusive-or circuit becomes at the high level (VDD).

When the output exout of the exclusive or circuit becomes high level (VDD), the gate (nd2501) of the current control MOS transistor of the operational amplifier becomes low level (0V), and the operational amplifier is started. When the operational amplifier is activated, the potential difference of the input complementary signals i1 and/i 1 is detected, the output out1 of the operational amplifier is shifted to high level (Vamp), and the output/out 1 is shifted to low level (0V). The complementary signals OUT1 and/OUT 1 continue to be input to the conventional level conversion circuit, and the voltage level of the output signal OUT shifts. When the output signal OUT is logically determined (at time T4), the output fb of the level down circuit also changes from the high level (VDD) to the low level (0V), and the input signal IN becomes the low level (0V), so the output exout of the exclusive or circuit changes to the low level (0V). When the output exout becomes low (0V), the gate (nd2501) of the current control MOS transistor of the operational amplifier becomes high (VDDQ), and the current supply to the operational amplifier is cut off. When the current supply to the operational amplifier is cut off, the high (Vamp) side of the output out1,/out 1 of the operational amplifier (out 1 in this case) gradually falls. However, as described in fig. 25, since the leakage current protection circuit has been provided, the output OUT of the level conversion circuit can maintain the determination logic.

Since the NMOS transistor is used as the simplest circuit of the amplifier, the present embodiment has an effect that the design cost can be reduced.

< example 14>

Fig. 27 is an embodiment of a level conversion circuit using only an amplifier in converting an input signal to an output signal. The circuit is composed of an amplifier part AMP for amplifying an input signal by an amplifier, a leak current protection circuit LPC for holding a determined level after conversion and suppressing a leak current generated in an inverter of the subsequent stage, a level down circuit LVDN for feeding back an output signal, and a control part CTR for controlling the amplifier.

In the figure, the amplifier portion is constituted by the simplest NMOS transistor N2702, and the amplification operation is performed by discharging the node nd2702, which is precharged to VDDQ in advance by the switching of the NMOS transistor, to a low level (0V).

As a mechanism for precharging the node nd2702, a current mirror structure is used here. The precharge is performed when the input is at a low level (0V). At this time, the NMOS transistor N2701 is ON, so the node nd2701 becomes low level (0V), and the NMOS transistor N2702 is OFF and the PMOS transistor P2702 is ON, so the node nd2702 is precharged to high level (VDDQ). The discharge is performed when the input is at a high level (VDD). At this time, since the NMOS transistor N2701 becomes OFF and the node nd2701 becomes high (VDDQ), the PMOS transistor P2701 becomes OFF and the NMOS transistor N2702 becomes ON. Therefore, the node nd2702 is discharged to the low level (0V).

However, at the time of discharging, although current consumption does not occur because the PMOS transistor P2702 turns OFF, at the time of precharging, since the PMOS transistor P2701 and the NMOS transistor N2701 have already turned ON, current always flows, which is not desirable from the viewpoint of low power consumption. Thus, in the present embodiment, such control is programmed: at the same time when the precharge of the node nd2702 is ended, the NMOS transistor N2701 is turned OFF. The control is realized by a level down circuit LVDN, a leakage current protection circuit LPC and a control circuit CTR.

The control circuit CTR is supplied with a feedback signal fb and an input signal IN, which are obtained by converting the output signal OUT of the level conversion circuit from an amplitude signal of VDDQ to a VDD amplitude signal by a level down circuit LVDN. When the input is low and the feedback signal fb is low 0V, the control section starts precharging to invert the logic of the output OUT and the feedback signal fb, and performs control to terminate precharging upon receiving a change in the feedback signal fb to high (VDD). This control can be realized by a 2-input logic OR circuit OR to which the input signal IN and the feedback signal fb are input.

When the input signal IN is at the high level (VDD), the output of the OR circuit OR is at the high level (VDD), so that the node nd2702 is discharged and becomes the low level (0V), and the feedback signal fb also becomes the low level (0V). Next, when the input signal goes to low level (0V), the input signal IN goes to low level (0V) and the feedback signal fb goes to low level (0V), so that the output value goes to high level (VDD) and the NMOS transistor N2701 goes ON. Therefore, precharging can be performed. After the precharge is completed, since the node nd2702 becomes high level (VDDQ), the PMOS transistor P2703 of the leakage current protection circuit LPC becomes ON state, and the node nd2702 is kept as it is at high level (VDDQ). At this time, the feedback signal fb transitions to the high level (VDD) upon receiving the transition of the output signal OUT. Therefore, at the input of the OR circuit OR of the control section, the input signal IN becomes low level (0V), the feedback signal fb becomes high level (VDD), and thus the output value becomes low level (0V), and the NMOS transistor N2701 becomes OFF. At this time, although the node nd2701 becomes an indefinite value, the leakage current protection circuit LPC node nd2702 keeps the high level (VDDQ) as it is, and thus the leakage current generated in the inverter at the subsequent stage does not occur.

Fig. 28 shows an operation waveform of the circuit of fig. 27. First, when the input signal IN transitions from the low level (0V) to the high level (VDD), the node nd2703 also transitions from the low level (0V) to the high level (VDD). Since the level of the node nd2702, which has been precharged in advance, will become the low level (0V) due to this NMOS transistor N2702 becoming ON. Therefore, the output signal shifts from the low voltage (0V) to the high Voltage (VDDQ). Upon receiving that the output signal has transitioned from the low level (0V) to the high level (VDDQ), the feedback signal fb transitions from the high level (VDD) to the low level (0V). The output of the OR circuit remains at the low level (0V) after the state transition. Therefore, the node nd2701 becomes the intermediate level.

Next, when the input signal IN transitions from the high level (VDD) to the low level (0V), the NMOS transistor N2701 becomes ON and the node nd2701 becomes the low level (0V) due to the output of the logical sum circuit OR transitioning to the high level. Upon receiving that the node nd2701 has become low level (0V), the node nd2702 becomes high level (VDDQ) because the PMOS transistor P2702 becomes ON. Therefore, since the output OUT transits from the high level (VDDQ) to the low level (0V), the feedback signal fb transits from the low level (0V) to the high level (VDD). When the output of the OR circuit OR transits from the low level (0V) to the high level (VDD) after the transition of the feedback signal fb is received, the NMOS transistor N2701 is turned OFF, and the potential of the node nd2701 becomes an intermediate potential. At this time, since the leak current protection circuit LPC pulls up the node nd2702 to (VDDQ), the output signal is constant.

With the present invention, it is possible to realize a semiconductor device having a level conversion circuit capable of performing high-speed level conversion even when the power supply voltage on the low voltage side becomes sub-1V. In addition, the semiconductor device of the present invention can prevent a leakage current from occurring when the low-voltage power supply is turned off by performing autonomous control inside, instead of using an external signal, the low-voltage side circuit enters a sleep mode, and thus the design of the level conversion circuit is facilitated.

Claims (2)

1. A semiconductor device, comprising:

a 1 st circuit for outputting a 1 st signal having a 1 st power supply voltage amplitude, with the 1 st power supply voltage as an operating voltage;

a 2 nd circuit for setting a 2 nd power supply voltage higher than the 1 st power supply voltage as an operating voltage; and

a level conversion circuit for converting the 1 st signal into a signal amplitude corresponding to the 2 nd power supply voltage using the 1 st power supply voltage and the 2 nd power supply voltage as operating voltages and outputting the converted signal to the 2 nd circuit,

the method is characterized in that:

the level conversion circuit includes a level shift section and a level determination section,

a level shift section for boosting a transition level of the 1 st signal by a capacitive element, and generating a 3 rd signal which transitions between the 2 nd power supply voltage and a voltage lower than the 2 nd power supply voltage by the 1 st power supply voltage, and a 4 th signal which inverts the 1 st signal and has an amplitude of the first power supply voltage; and is

The level determining part connects the 4 th signal to the gate of the N-type MOSFET of a circuit connecting the N-type MOSFET and the P-type MOSFET in series to the ground voltage and the 2 nd power voltage, and connects the 3 rd signal to the gate of the P-type MOSFET to determine the level.

2. A semiconductor device, comprising:

a 1 st circuit for outputting a 1 st signal having a 1 st power supply voltage amplitude, with the 1 st power supply voltage as an operating voltage;

a 2 nd circuit for setting a 2 nd power supply voltage higher than the 1 st power supply voltage as an operating voltage; and

a level conversion circuit for converting the 1 st signal into a signal amplitude corresponding to the 2 nd power supply voltage and outputting the converted signal to the 2 nd circuit, with the 1 st power supply voltage, the 2 nd power supply voltage, and a 3 rd power supply voltage higher than the 1 st power supply voltage and lower than the 2 nd power supply voltage as operating voltages,

the method is characterized in that:

the level conversion circuit includes a level shift section and a level determination section,

the level shift part boosts the transition level of the 1 st signal through a capacitance element, and generates a 4 th signal with the 3 rd power supply voltage as a reference;

the level determination section performs level determination by amplifying the above-described 4 th signal.