HK1147641B - Technique for reducing the number of layers in a signal routing device - Google Patents

Description

Method for reducing the number of layers in a signal routing device

The present application is a divisional application of an invention patent application having an application number of 03159457.3, an application date of 2003, 9/25, and an invention name of "technique for reducing the number of layers in a signal wiring device".

Reference to related applications

This patent application is a continuation-in-part application of united states patent application No. 10/126700 (now assigned to us patent No. 6545876, granted on 8/4/2003), filed on day 4/2002, which is also a continuation-in-part application of united states patent application No. 09/651188 (now assigned to us patent No. 6388890, granted on 14/5/2002), filed on day 2000 on 30/8/2002, each of which is hereby incorporated by reference in its entirety.

This patent application is also a continuation-in-part application of U.S. patent No. US TBA, filed on 3/20/2002, patent application No. 10/101211, entitled to pending (TBD), which is also a continuation-in-part application of U.S. patent No. 09/651188 (now U.S. patent No. 6388890, entitled to 5/14/2002), filed on 8/2000, and which claims priority to U.S. provisional patent application No. 60/212387, filed on 6/2000/19/2002, each of which is hereby incorporated by reference in its entirety.

Technical Field

The present invention relates to a multilayer signal wiring device, and more particularly, to a technique of reducing the number of layers of a signal wiring device.

Background

Electrical connections between electronic components have long been accomplished through the use of printed circuit boards. The initial circuit boards had only one signal layer on the top surface for routing the electronic components mounted thereon. These single signal layer circuit boards have a significant limit on the number of electrical signals that can be routed between electronic components mounted on the same circuit board. That is, the number of electrical signals that can be routed between electronic components mounted on a single signal layer circuit board is limited by the size of the area of the single signal layer.

The area limitations associated with single signal layer circuit boards have led to the development of multilayer printed circuit boards. Such a multilayer printed circuit board may be single-sided or double-sided, and the surface of the multilayer printed circuit board or a buried portion thereof may have a plurality of signal layers. Thus, the number of electrical signals that can be routed between electronic components mounted on the same circuit board in such a multilayer printed circuit board is greatly increased.

The use of multilayer printed circuit boards is particularly advantageous when electronic components with high density packaging are used. That is, electronic components with high density packaging typically require multiple layers of a multi-layer printed circuit board to complete electrical connections with other electronic components mounted on the same circuit board. In fact, the density of electronic component packages typically dictates the number of layers that a multilayer printed circuit board on which the electronic components must be mounted must provide. Although there is no limit to the number of layers that a multilayer printed circuit board can provide in theory, problems arise when the number of layers of a multilayer printed circuit board exceeds a reasonable value, particularly when attempting to route high speed electrical signals between electronic components. For example, when making electrical connections between different layers of a multilayer printed circuit board, conductive vias are commonly used. While these conductive vias enable direct vertical electrical connections between different layers in a multilayer printed circuit board, there are inherent parasitics associated with these conductive vias that may negatively impact the performance of the signals propagating therein. That is, the conductive vias have intrinsic parasitic impedances, capacitive impedances, and inductive impedances that negatively impact the signal propagating along each conductive via. In addition, these intrinsic parasitics may also negatively impact the manufacture of the printed circuit board, thereby affecting its cost. These intrinsic parasitics may also limit the bandwidth of the signal propagating along each conductive via because of their negative impact on signal characteristics. These negative effects can only increase with increasing number of layers of the multilayer printed circuit board.

In view of the above, it is desirable to provide a technique for increasing the number of electrical connections between electronic components mounted on a multilayer printed circuit board without increasing the number of layers of the multilayer printed circuit board. More specifically, it is desirable to provide a technique for reducing the number of layers in a multilayer signal wiring device in an efficient and cost-effective manner.

Disclosure of Invention

According to the present invention, there is provided a technique of reducing the number of layers in a multilayer signal wiring device. In one particular exemplary embodiment, the present techniques may be realized as a method of reducing the number of layers in a multilayer signal routing device having a plurality of conductive signal path layers for routing electrical signals to and from at least one electronic component mounted on one surface of the multilayer signal routing device. In this case, the method includes receiving information of the electronic component (including a number characteristic of conductive contacts, a pitch characteristic of the conductive contacts, a signal type characteristic of the conductive contacts, a signal direction characteristic of the conductive contacts of the at least one electronic component). The method also includes identifying the electronic component with the high density conductive contact array package based at least in part on at least one of a characteristic of a number of conductive contacts of the electronic component and a characteristic of a pitch of the conductive contacts. The method further includes routing electrical signals in a plurality of conductive signal path layers in the multi-layer signal routing device to connect the high-density conductive contact array package inward and outward based at least in part on at least one of the signal type characteristics of the conductive contacts and the signal direction characteristics of the conductive contacts.

In accordance with other aspects of this particular exemplary embodiment of the present invention, the method may further comprise providing a plurality of conductive vias in the multilayer signal routing device, the vias extending from a surface of the multilayer signal routing device to one of the plurality of conductive signal path layers, wherein the plurality of conductive vias are arranged in a manner that forms a channel over one of the plurality of conductive signal path layers underlying the plurality of conductive vias. If this is the case, the channels may be arranged to have a linear, circular, diamond, curved, stepped or arbitrary shape, or a combination thereof. Also, the channels may be arranged in a vertical, horizontal, inclined or arbitrary orientation, or a combination thereof. Also, a plurality of conductive vias may extend from the multilayer signal routing device to different ones of the plurality of conductive signal path layers.

A plurality of conductive vias may form at least a portion of the conductive contact array to mate with a high density conductive contact array package of the electronic component, wherein at least a portion of the plurality of conductive vias may be disposed within the conductive contact array such that the vias are correspondingly formed within the conductive contact array. In addition, the multilayer signal routing device can have an array of conductive contacts on one of its surfaces to mate with a high density conductive contact array package of an electronic component, wherein at least a portion of the conductive vias can be formed outside of the array of conductive contacts, each conductive via being electrically connectable to a peripheral conductive contact on the surface of the multilayer signal routing device.

The plurality of conductive vias may form at least a portion of the conductive contact array to mate with a high density conductive contact array package of the electronic component, wherein at least a portion of the plurality of conductive vias may be positioned inside the conductive contact array such that the vias are capable of traversing the conductive contact array. Additionally, a plurality of conductive vias may form at least a portion of an array of conductive contacts to mate with a high density conductive contact array package of an electronic component, wherein the array of conductive contacts may have a square, triangular, circular, or any conductive contact shape or combination thereof. Also, the at least two electrical signals may be differential electrical signals that may be routed at least partially together in a channel formed in another multi-conductive signal path layer below the plurality of conductive vias.

According to another aspect of certain exemplary embodiments of the present invention, a multilayer signal wiring device may have at least one conductive power layer for providing power to electronic components mounted on a surface of the multilayer signal wiring device. In this case, the method may further comprise the steps of: a plurality of conductive vias are disposed in the multilayer signal routing device and extend from a surface of the multilayer signal routing device to at least one of the at least one conductive power layer, wherein each conductive via is electrically connectable to at least one separate conductive power contact on the surface of the multilayer signal routing device. Each of the at least one conductive power contact may form part of a portion of a conductive contact array to match a high density conductive contact array package of an electronic component. In this case, a via may be formed in each conductive signal path layer below the conductive power contact.

According to another aspect of certain exemplary embodiments of the present invention, a multilayer signal routing device may have at least one conductive ground layer for providing a ground reference for electronic components mounted on a surface of the multilayer signal routing device. In this case, the method may further comprise the steps of: a plurality of conductive vias are formed in the multilayer signal routing device, the vias extending from the surface of the multilayer signal routing device to at least one of the at least one conductive ground layer, wherein each conductive via is electrically connectable to at least one separate conductive ground contact on the surface of the multilayer signal routing device. Each of the at least one conductive ground contacts may form a portion of a conductive contact array to match a high density conductive contact array package of electronic components. In this case, a via may be formed in each conductive signal path layer below the conductive ground contact.

According to another aspect of certain exemplary embodiments of the present invention, a multilayer signal routing device may have at least one conductive utility/ground layer for providing power/ground to electronic components mounted on a surface of the multilayer signal routing device. In this case, the method may further comprise the steps of: a plurality of conductive vias are formed in the multilayer signal routing device, the vias extending from a surface of the multilayer signal routing device to at least one of the at least one conductive power/ground layer, wherein each conductive via is electrically connectable to at least one independent conductive power/ground contact on the surface of the multilayer signal routing device. Each of the at least one conductive power/ground contacts may form at least a portion of a conductive contact array to match a high density conductive contact array package of an electronic component. In this case, one via may be formed in each conductive signal path layer below each of the at least one conductive power/ground contact.

According to another aspect of certain exemplary embodiments of the present invention, the surface of the multilayer signal wiring device may be an inner surface of the multilayer signal wiring device, and at least one electronic component may be mounted on the inner surface of the multilayer signal wiring device. In this case, the at least one electronic component may have at least one first conductive contact on the first side thereof, and the at least one first conductive contact may be electrically connected to at least one corresponding first conductive contact formed on the inner surface of the multilayer signal routing device. Preferably, the at least one electronic component may have at least one second conductive contact formed on the second side, and the at least one second conductive contact may be electrically connected to at least one corresponding second conductive contact formed on another inner surface of the multilayer signal routing device.

Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Although the following description of the present invention refers to the accompanying drawings, it is to be understood that the invention is not limited to those embodiments. Those of ordinary skill in the art, having access to the teachings herein, will recognize additional embodiments, modifications, embodiments, and applications in other fields, which are within the scope of the present disclosure as described and claimed herein, and which are significant to the present disclosure.

Drawings

In order to facilitate a more complete understanding of the present invention, reference will now be made to the accompanying drawings. These drawings should not be construed as limiting the present invention, but are intended to be exemplary only.

FIG. 1 is a side cross-sectional view of a multilayer printed circuit board according to the present invention;

fig. 2 shows a surface mount grid array layout of an electronic component package having 1247 input/output (I/O) contacts;

FIG. 3 shows one quarter (e.g., the lower right quarter) of the layout shown in FIG. 2;

FIG. 4 shows a portion of a base layer of the multilayer printed circuit board of FIG. 1;

FIG. 5 illustrates a portion of a first power/ground plane layer of the multi-layer printed circuit board of FIG. 1;

FIG. 6 illustrates a portion of a first signal layer of the multi-layer printed circuit board of FIG. 1;

FIG. 7 illustrates a portion of a second power/ground plane layer of the multi-layer printed circuit board of FIG. 1;

FIG. 8 illustrates a portion of a second signal layer of the multi-layer printed circuit board of FIG. 1;

FIG. 9 illustrates a portion of a third power/ground plane layer of the multi-layer printed circuit board of FIG. 1;

fig. 10 illustrates a portion of a fourth power/ground plane layer of the multi-layer printed circuit board of fig. 1;

FIG. 11 illustrates a portion of a third signal layer of the multi-layer printed circuit board of FIG. 1;

fig. 12 illustrates a portion of a fifth power/ground plane layer of the multi-layer printed circuit board of fig. 1;

FIG. 13 illustrates a portion of a fourth signal layer of the multi-layer printed circuit board of FIG. 1;

FIG. 14 shows a portion of a sixth power/ground plane layer of the multi-layer printed circuit board of FIG. 1;

FIG. 15 shows a portion of a secondary layer of the multilayer printed circuit board of FIG. 1;

FIG. 16 illustrates an alternative embodiment of a portion of a base layer of the multi-layer printed circuit board of FIG. 1;

FIG. 17 is a side cross-sectional view of another multi-layer printed circuit board according to the present invention;

FIG. 18A shows an electronic component having conductive contacts on one side thereof for making connections with corresponding electrical contacts on a layer of the multilayer printed circuit board of FIG. 17;

fig. 18B shows an electronic component having conductive contacts on multiple sides thereof for making connections with corresponding electrical contacts on multiple layers of the multilayer printed circuit board of fig. 17.

Detailed Description

Referring to fig. 1, there is shown a side cross-sectional view of a multilayer printed circuit board 10 according to the present invention. That is, the multilayer printed circuit board 10 incorporates the idea of the present invention to reduce the number of layers of the multilayer printed circuit board 10.

The multilayer printed circuit board 10 includes a base layer (top layer) 12, a secondary layer (bottom layer) 14, a plurality of signal layers 16, and a plurality of power/ground plane layers 18. It should be noted that the base layer 12 and the secondary layer 14 are the primary power/ground plane layers, except for the path to the contact pads and test signals formed thereon. It should also be noted that the electronic components may be mounted on either one (single-sided board) or both (double-sided board) of the base layer 12 and the secondary layer 14.

The multilayer printed circuit board 10 also includes a first oversized via 20 for electrically connecting selected ones of the plurality of signal layers 16 (e.g., signal layers 16b and 16c), a second oversized via 22 for electrically connecting selected ones of the base layer 12, the secondary layer 14, and the plurality of power/ground planes 18 (e.g., power/ground planes 18a, 18c, 18e, and 18f), a buried via 24 for electrically connecting selected ones of the plurality of signal layers 16 (e.g., signal layers 16a and 16d), and a micro-via 26 for electrically connecting the signal layer 16a and a contact pad 28 formed on the base layer 12.

It should be noted that the buried vias 24 and/or the micro-vias 26 may also be used to electrically connect selected ones of the plurality of power/ground plane layers 18. It should also be noted that the micro-perforations 26 may also be one in-pad perforations, or some similar non-penetrating perforations, such that the micro-perforations 26 may be formed on either or both of the base layer 12 and the secondary layer 14, and the micro-perforations 26 may be electrically connected to other micro-perforations, super-perforations, buried perforations, etc., either directly or through a signal layer or a power/ground layer. It should also be noted that it is the micro-perforations 26 (or substantial equivalents thereof) that enable a substantial portion of the inventive technique to be implemented, as will be described in detail with reference to fig. 2-16, wherein fig. 4-16 correspond to 12 layers of the multi-layer printed circuit board 10.

Referring to fig. 2, there is shown a surface mount grid array of a package for an electronic component having 1247 input/output (I/O) contacts. FIG. 2 also shows a legend indicating the type of signals associated with the I/O contacts.

For purposes of better understanding this detailed description, fig. 3 shows one quarter (i.e., the bottom right quarter) 32 of the layout 30 in fig. 2 for increased resolution. Fig. 4-16 correspond directly to the quarter 32 shown in fig. 3. The signal type legend in fig. 2 also applies to fig. 3, as well as to fig. 4-16.

Referring to fig. 4, a portion 34 of the base layer 12 of the multilayer printed circuit board 10 is shown. As indicated above, this portion 34 of the base layer 12 directly coincides with the quarter 32 shown in fig. 3. That is, the portion 34 of the base layer 12 corresponds to a corresponding portion of the multilayer printed circuit board 10 on which an electronic component of a surface mount grid array package having 1247I/O contacts is mounted.

As indicated above, the base layer 12 is primarily a power/ground plane layer, except for the test signal paths and contact pads formed thereon. Specifically, the base layer 12 includes a ground plane that is electrically connected to a ground contact pad (i.e., GND in the illustration), but not to a power contact pad (i.e., Vdd and Vdd2 in the illustration), a signal contact pad (i.e., signal in the illustration), or a test contact pad (i.e., test in the illustration). The ground plane of the base layer 12 is not yet electrically connected to the plurality of test signal paths 36 formed on the base layer 12.

Also shown in fig. 4 is a region 38 of the multilayer printed circuit board 10 on which vias are formed in other layers of the multilayer printed circuit board 10 according to the present invention. These areas 38 also indicate where micro-perforations and intra-pad perforations are formed in the multilayer printed circuit board 10. That is, all of the contact pads in these areas 38 are formed in the form of tiny perforations or perforations within pads to facilitate the formation of vias in other layers of the multilayer printed circuit board 10 of the present invention.

Referring to fig. 5, a portion 40 of the power/ground plane layer 18a of the multilayer printed circuit board 10 is shown. As indicated above, this portion 40 of the power/ground plane layer 18a directly coincides with the quarter 32 shown in fig. 3. That is, the portion 40 of the power/ground plane layer 18a corresponds to a corresponding portion of the multi-layer printed circuit board 10 on which one-quarter of the surface mount grid array packaged electronic components having 1247I/O contacts are mounted on the multi-layer printed circuit board 10.

The power/ground plane layer 18a is primarily a ground plane layer, except for the perforations formed therein. More specifically, power/ground plane layer 18a includes a ground plane that is electrically connected to the ground vias (i.e., GND in the illustration), but not to the power vias (i.e., Vdd and Vdd2 in the illustration) or the signal vias (i.e., signals in the illustration). Note that no test vias are formed in the power/ground plane layer 18a because the test contact pads and test signal paths are formed only on the base layer 12.

Also shown in fig. 5 is a region 38 of the multilayer printed circuit board 10 on which vias are formed in other layers of the multilayer printed circuit board 10 in accordance with the present invention. These areas 38 also indicate where micro-vias and intra-pad vias are formed in the multilayer printed circuit board 10. That is, all of the contact pads in these areas 38 are formed as tiny perforations or perforations within pads to facilitate the formation of vias in other layers of the multilayer printed circuit board 10 of the present invention.

Referring to fig. 6, a portion 42 of the signal layer 16a of the multilayer printed circuit board 10 is shown. As indicated above, the portion 42 of the signal layer 16a directly coincides with the quarter 32 shown in fig. 3. That is, the portion 42 of the power/ground plane layer 18a corresponds to a corresponding portion of the multilayer printed circuit board 10 on which one-quarter of the surface mount grid array packaged electronic components having 1247I/O contacts are mounted on the multilayer printed circuit board 10.

The signal layer 16a includes a plurality of conductive signal paths 44 that are electrically connected to tiny or through-holes in the area 38 of the multilayer printed circuit board 10, wherein vias are formed in other layers of the multilayer printed circuit board 10 in accordance with the present invention. Typically, these signal paths 44 are pre-selected according to the characteristics of the signals they carry. That is, signal path 44 may carry high speed signals. Alternatively, the signal path 44 may carry a low speed signal. More importantly, the micro-or through-vias formed in the region 38 of the multilayer printed circuit board 10 do not extend deeper into the multilayer printed circuit board 10 than into the signal layer 16 a. This allows vias to be formed underneath these tiny or through-going perforations in other layers of the multilayer printed circuit board 10.

Referring to fig. 7, a portion 46 of the power/ground plane layer 18b of the multilayer printed circuit board 10 is shown. As indicated above, this portion 46 of the power/ground plane layer 18b directly coincides with the quarter 32 shown in fig. 3. That is, the portion 46 of the power/ground plane layer 18b corresponds to a corresponding portion of the multilayer printed circuit board 10 on which one-quarter of the surface mount grid array packaged electronic components having 1247I/O contacts are mounted on the multilayer printed circuit board 10.

The power/ground plane layer 18b is primarily a power plane layer, except for the perforations formed therein. More specifically, the power/ground plane layer 18b includes a power plane that is electrically connected to the power via (i.e., Vdd in the illustration), but not to the ground via (i.e., GND in the illustration) or the signal via (i.e., signal in the illustration). Note that no test vias are formed in the power/ground plane layer 18b, as the test contact pads and test signal paths are typically formed only on the base layer 12. It should also be noted that no perforations are formed in the power/ground plane layer 18b in the region 38 of the multilayer printed circuit board 10, so that channels are formed in these regions 38 in this and other layers of the multilayer printed circuit board 10 in accordance with the present invention. These areas 38 of the multilayer printed circuit board 10 are free of perforations in the power/ground plane layer 18b because the micro-perforations or through-perforations extend only from the base layer 12 to the signal layer 16a in these areas 38 of the multilayer printed circuit board 10, as described above.

Referring to fig. 8, a portion 48 of the signal layer 16b of the multilayer printed circuit board 10 is shown. As indicated above, the portion 48 of the signal layer 16b directly coincides with the quarter 32 shown in fig. 3. That is, the portion 48 of the signal layer 16b corresponds to a corresponding portion of the multilayer printed circuit board 10 on which one quarter of the electronic components of a surface mount grid array package having 1247I/O contacts are mounted.

The signal layer 16b includes a plurality of electrically conductive signal paths 50 that are electrically connected to vias formed in the signal layer 16b outside of the region 38 of the multilayer printed circuit board 10, wherein vias are formed in this and other layers of the multilayer printed circuit board 10. Many of these signal paths 50 are routed in these channels in accordance with the present invention. That is, the plurality of conductive signal paths 50 may be routed over channels formed by the signal layers 16b in the region 38 of the multilayer printed circuit board 10 without the use of perforations. Conversely, if there are perforations in these areas 38 in this and other layers of the multilayer printed circuit board 10, additional signal layers are needed to route the plurality of conductive signal paths 50. Therefore, no through-holes are used in these regions 38 in this layer and other layers of the multilayer printed circuit board 10, so that the number of signal layers required in the multilayer printed circuit board 10 as a whole can be reduced.

It should be noted at this point that the vias formed in region 38 of the multilayer printed circuit board 10 are preferably arranged to intersect at least one edge of the grid array. The benefit of this arrangement is that it allows the plurality of conductive signal paths 50 to be routed out in a grid array more easily. In fact, as shown in fig. 8, some of the vias formed in region 38 of the multilayer printed circuit board 10 cross-connect more than one edge of the grid array. Typically, these multi-edge intersecting channels are comprised of orthogonal rows and columns, but may be diagonal or in any pattern.

It should also be noted that the channels formed in region 38 of the multilayer printed circuit board 10 may have various widths. That is, although the via formed in the region 38 of the multilayer printed circuit board 10 shown in fig. 8 has a width of one contact pad or through-hole, the present invention is not limited thereto. For example, the width of the vias formed in region 38 of multilayer printed circuit board 10 may be the width of two or more contact pads or vias depending on how many tiny or through vias are used and how many are removed as described above in accordance with the practice of the present invention.

Referring to fig. 9, a portion 52 of the power/ground plane layer 18c of the multilayer printed circuit board 10 is shown. As indicated above, this portion 52 of the power/ground plane layer 18c directly coincides with the quarter 32 shown in fig. 3. That is, the portion 52 of the power/ground plane layer 18c corresponds to a corresponding portion of the multilayer printed circuit board 10 on which one quarter of the electronic components of a surface mount grid array package having 1247I/O contacts are mounted.

The power/ground plane layer 18c is primarily a ground plane layer, except for the perforations formed therein. More specifically, power/ground plane layer 18c includes a ground plane that is electrically connected to the ground vias (i.e., GND in the illustration), but not to the power vias (i.e., Vdd and Vdd2 in the illustration) or the signal vias (i.e., signals in the illustration). Note that no test vias are formed in the power/ground plane layer 18c because the test contact pads and test signal paths are formed only on the base layer 12. It should also be noted that no perforations are formed in the power/ground plane layer 18c in the region 38 of the multilayer printed circuit board 10, so that vias are formed in the region 38 in this and other layers of the multilayer printed circuit board 10 in accordance with the present invention. The area 38 of the multilayer printed circuit board 10 is not perforated on the power/ground plane layer 18c because the micro-perforations or through-perforations extend from the base layer 12 to the signal layer 16a only in the area 38 of the multilayer printed circuit board 10, as described above.

Referring to fig. 10, a portion 54 of the power/ground plane layer 18d of the multilayer printed circuit board 10 is shown. As indicated above, this portion 54 of the power/ground plane layer 18d directly coincides with the quarter 32 shown in fig. 3. That is, the portion 54 of the power/ground plane layer 18d corresponds to a corresponding portion of the multilayer printed circuit board 10 on which one quarter of the electronic components of a surface mount grid array package having 1247I/O contacts are mounted on the multilayer printed circuit board 10.

Similar to power/ground plane layer 18b, power/ground plane layer 18d is primarily a power plane layer, except for perforations formed therein. More specifically, the power/ground plane layer 18d includes a power plane that is electrically connected to the power via (i.e., Vdd2 in the illustration), but is not connected to the ground via (i.e., GND in the illustration) or the signal via (i.e., signal in the illustration). Note that no test vias are formed in the power/ground plane layer 18d, as the test contact pads and test signal paths are typically formed only on the base layer 12. It should also be noted that no perforations are formed in the power/ground plane layer 18d in the region 38 of the multilayer printed circuit board 10, so that vias are formed in the region 38 in this and other layers of the multilayer printed circuit board 10 in accordance with the present invention. The area 38 of the multilayer printed circuit board 10 is not perforated on the power/ground plane layer 18d because the micro-perforations or through-perforations extend from the base layer 12 to the signal layer 16a only in the area 38 of the multilayer printed circuit board 10, as described above.

Referring to fig. 11, a portion 56 of the signal layer 16c of the multilayer printed circuit board 10 is shown. As indicated above, this portion 56 of the signal layer 16c directly coincides with the quarter 32 shown in FIG. 3. That is, the portion 56 of the signal layer 16c corresponds to a corresponding portion of the multilayer printed circuit board 10 on which one quarter of the electronic components of a surface mount grid array package having 1247I/O contacts are mounted on the multilayer printed circuit board 10.

The signal layer 16c includes a plurality of electrically conductive signal paths 58 that are electrically connected to vias formed in the signal layer 16c outside of the region 38 of the multilayer printed circuit board 10, wherein vias are formed in this and other layers of the multilayer printed circuit board 10. Many of these signal paths 58 are routed in these channels in accordance with the present invention. That is, the plurality of conductive signal paths 58 may be routed over channels formed without the use of perforations in the signal layer 16c in the region 38 of the multilayer printed circuit board 10. Conversely, if there are perforations in the area 38 in this and other layers of the multilayer printed circuit board 10, additional signal layers are needed to route the plurality of conductive signal paths 58. Therefore, no through-hole is used in the region 38 in this layer and other layers of the multilayer printed circuit board 10, so that the number of signal layers required in the multilayer printed circuit board 10 as a whole can be reduced.

Referring to fig. 12, a portion 60 of the power/ground plane layer 18e of the multilayer printed circuit board 10 is shown. As indicated above, this portion 60 of the power/ground plane layer 18e directly coincides with the quarter 32 shown in fig. 3. That is, the portion 60 of the power/ground plane layer 18e corresponds to a corresponding portion of the multi-layer printed circuit board 10 in which one-fourth of the electronic components of a surface mount grid array package having 1247I/O contacts are mounted on the multi-layer printed circuit board 10.

Similar to power/ground plane layer 18c, power/ground plane layer 18e is primarily a ground plane layer, except for perforations formed therein. More specifically, power/ground plane layer 18e includes a ground plane that is electrically connected to the ground vias (i.e., GND in the illustration), but not to the power vias (i.e., Vdd and Vdd2 in the illustration) or the signal vias (i.e., signals in the illustration). Note that no test vias are formed in the power/ground plane layer 18e because the test contact pads and test signal paths are formed only on the base layer 12. It should also be noted that no perforations are formed in the power/ground plane layer 18e in the region 38 of the multilayer printed circuit board 10, so that vias are formed in the region 38 in this and other layers of the multilayer printed circuit board 10 in accordance with the present invention. The area 38 of the multilayer printed circuit board 10 is not perforated on the power/ground plane layer 18e because the micro-perforations or through-perforations extend from the base layer 12 to the signal layer 16a only in the area 38 of the multilayer printed circuit board 10, as described above.

Referring to fig. 13, a portion 62 of the signal layer 16d of the multilayer printed circuit board 10 is shown. As indicated above, this portion 62 of the signal layer 16d directly coincides with the quarter 32 shown in FIG. 3. That is, the portion 62 of the signal layer 16d corresponds to a corresponding portion of the multilayer printed circuit board 10 on which one quarter of the electronic components of a surface mount grid array package having 1247I/O contacts are mounted on the multilayer printed circuit board 10.

The signal layer 16d includes a plurality of electrically conductive signal paths 64 that are electrically connected to vias formed in the signal layer 16d outside of the region 38 of the multilayer printed circuit board 10, wherein vias are formed in this and other layers of the multilayer printed circuit board 10. Many of these signal paths 64 are routed in these channels in accordance with the present invention. That is, the plurality of conductive signal paths 64 may be routed thereon by vias formed without the use of perforations in the signal layers 16d in the region 38 of the multilayer printed circuit board 10. Conversely, if there are perforations in the area 38 in this and other layers of the multi-layer printed circuit board 10, additional signal layers are needed to route the plurality of conductive signal paths 64. Therefore, no through-holes are used in the area 38 in this and other layers of the multilayer printed circuit board 10, so that the number of signal layers required in the multilayer printed circuit board 10 as a whole can be reduced.

Referring to fig. 14, a portion 66 of the power/ground plane layer 18f of the multilayer printed circuit board 10 is shown. As indicated above, this portion 66 of the power/ground plane layer 18f directly coincides with the quarter 32 shown in fig. 3. That is, the portion 66 of the power/ground plane layer 18f corresponds to a corresponding portion of the multilayer printed circuit board 10 on which one-quarter of the electronic components of a surface mount grid array package having 1247I/O contacts are mounted.

Similar to power/ground plane layer 18c and power/ground plane layer 18e, power/ground plane layer 18f is primarily a ground plane layer, except for perforations formed therein. More specifically, power/ground plane layer 18f includes a ground plane that is electrically connected to the ground vias (i.e., GND in the illustration), but not to the power vias (i.e., Vdd and Vdd2 in the illustration) or the signal vias (i.e., signals in the illustration). Note that no test vias are formed in the power/ground plane layer 18f because the test contact pads and test signal paths are formed only on the base layer 12. It should also be noted that no perforations are formed in the power/ground plane layer 18f in the region 38 of the multilayer printed circuit board 10, thereby forming vias in the region 38 in this and other layers of the multilayer printed circuit board 10 in accordance with the present invention. The area 38 of the multilayer printed circuit board 10 is not perforated on the power/ground plane layer 18f because the micro-perforations or through-perforations extend from the base layer 12 to the signal layer 16a only in the area 38 of the multilayer printed circuit board 10, as described above.

Referring to fig. 15, a portion 68 of a secondary layer 14 of the multilayer printed circuit board 10 is shown. As indicated above, the portion 68 of the secondary layer 14 directly coincides with the quarter 32 shown in fig. 3. That is, the portion 68 of the secondary layer 14 corresponds to a corresponding portion of the multilayer printed circuit board 10 on which one quarter of the electronic components of a surface mount grid array package having 1247I/O contacts are mounted on the multilayer printed circuit board 10.

As indicated above, the secondary layer 14 is primarily a power/ground plane layer, except for the contact pads formed thereon. In particular, the secondary layer 14 includes a ground plane that is electrically connected to the ground contact pads (i.e., GND in the illustration), but not to the power contact pads (i.e., Vdd and Vdd2 in the illustration) or the signal contact pads (i.e., signals in the illustration). Note that the test penetration as the test contact pad is not formed in the sub-layer 14 because the test contact pad and the test signal path are formed only on the base layer 12. It should also be noted that there are no perforations in the secondary layer 14 in the region 38 of the multilayer printed circuit board 10, so that channels are formed in the region 38 in this and other layers of the multilayer printed circuit board 10 in accordance with the present invention. These areas 38 of the multilayer printed circuit board 10 are free of perforations in the secondary layer 14 because the micro-perforations or through-perforations extend only in the areas 38 of the multilayer printed circuit board 10 from the base layer 12 to the signal layer 16a, as described above.

At this point it should be noted that the above-described technique for reducing the number of layers in a multilayer printed circuit board is fully described in the above-referenced patent application US10/126700 (now patent number US 6545876). U.S. patent application No. US 09/651188 (now patent No. US6388890) and U.S. provisional patent application No. US 60/212387, which are incorporated herein by reference in their entirety. Also, related techniques for reducing the number of layers in a multilayer printed circuit board are fully described in the above-referenced U.S. patent application US 10/101211 (now U.S. Pat. No. US tba), US 09/651188 (now U.S. Pat. No. US6388890), and U.S. provisional patent application US 60/212387, which are all incorporated herein by reference in their entirety. All of these techniques may be implemented in a manual or automated manner. These techniques may be implemented in an automated fashion, for example, by receiving electronic component information from a design file (for example). That is, the design file may include a characteristic number of conductive contacts, a characteristic pitch of the conductive contacts, a characteristic signal type of the conductive contacts, and/or a characteristic signal direction of the conductive contacts of the one or more electronic components. An electronic component having a high density conductive contact array package is identified based at least in part on at least one of a characteristic of a number of conductive contacts of the electronic component and a pitch characteristic of the conductive contacts. Routing electrical signals in a plurality of conductive signal path layers in a multilayer signal routing device to connect each of a high density conductive contact array package mounted on a multilayer circuit board inward and outward based at least in part on at least one of a signal type characteristic of a conductive contact and a signal direction characteristic of a conductive contact.

Therefore, it should be noted at this point that the method of reducing the number of layers of a multilayer printed circuit board according to the present invention as described above includes, to some extent, processing input data and generating output data. This processing of input data and generation of output data may be implemented in hardware or software. For example, certain electronic and/or optical components may be used in a processing device or similar or related circuitry to perform the functions of reducing the number of layers in a multilayer printed circuit board according to the present invention as described above. Alternatively, one or more processors operating in accordance with stored instructions may also perform the functions of reducing the number of layers in a multilayer printed circuit board in accordance with the present invention as described above. If so, it is within the scope of the present invention that the instructions may be stored on one or more processor-readable carriers (e.g., a diskette) or transmitted to one or more processors via one or more signals.

It should be noted at this point that one or more micro-perforations 26 may be formed in the multilayer printed circuit board 10 extending from the base layer 12 of the multilayer printed circuit board 10 to one of the plurality of conductive signal path layers (e.g., 16b) in accordance with the concepts described in the above-referenced U.S. patent applications US10/126700, US 09/651188 (now U.S. patent number US6388890), and U.S. provisional patent application US 60/212387, all of which are incorporated herein by reference, wherein the micro-perforations 26 are arranged such that at least one via 38 is formed in another of the plurality of conductive signal layers (e.g., 16c) beneath the micro-perforations 26. That is, one or more micro-perforations 26 may extend from the surface 12 of the multi-layer printed circuit board 10 to a plurality of conductive signal path layers (e.g., 16b, 16c, 16d) other than the uppermost conductive signal path layer (e.g., 16 a).

It should be noted in this regard that the channels 38 may be configured to have a linear, circular, diamond, curvilinear, stepped, or arbitrary shape, or a combination thereof. Also, the channels 38 may be arranged in a vertical, horizontal, inclined or arbitrary orientation, or a combination thereof. Additionally, one or more vias 38 may also be formed that are completely contained within the conductive contact array formed on the multilayer printed circuit board 10 to match the conductive contacts of the electronic component (i.e., no portion of the via is formed on the periphery of the conductive contact array on the multilayer printed circuit board 10) (e.g., see via 38a in fig. 16). In addition, one or more vias 38 may be formed that extend through the array of conductive contacts formed on the multilayer printed circuit board 10 to match the conductive contacts of the electronic component (i.e., vias are formed to extend from one side of the array of conductive contacts formed on the multilayer printed circuit board 10 to the other). In addition, one or more vias 38 may be formed such that only a portion thereof extends to the periphery of the array of conductive contacts formed on the multilayer printed circuit board 10 to match the conductive contacts of the electronic component (i.e., at least a portion of the vias are formed along the periphery of the array of conductive contacts formed on the multilayer printed circuit board 10).

It should be noted at this point that the conductive contacts of the electronic component, as well as the conductive contact array created on the multilayer printed circuit board 10 for mating with the conductive contacts of the electronic component, may have a variety of contact array patterns. For example, the conductive contacts of the electronic component, as well as the conductive contact array formed on the multi-layer printed circuit board 10, may be square, triangular, circular, and/or any pattern of conductive contacts, or combinations thereof.

It should be noted at this point that at least some of the electrical signals to be routed may be differential electrical signals. If so, the differential electrical signals may be routed at least partially together over the vias 38 in the plurality of conductive signal path layers 16 beneath the micro-perforations 26, thereby enhancing signal quality.

It should be noted at this point that at least a portion of the micro-perforations 26 are formed outside of the conductive contact array formed on the multilayer printed circuit board 10 to match the conductive contacts of the electronic component. For example, referring to FIG. 16, there is shown an alternative embodiment of a portion 34a of the base layer 12 of the multilayer printed circuit board 10 in which a portion of the micro-perforations 26a are disposed outside of the array of conductive contacts on the multilayer printed circuit board 10 to match the conductive contacts of the electronic component. The micro-perforations 26a are point-connected by conductive connections 70 to corresponding peripheral contacts of a conductive array of contacts formed on the multilayer printed circuit board 10 to match the conductive contacts of the electronic component. As described above, the micro-perforations 26a may extend from the base layer 12 of the multilayer printed circuit board 10 to any one of the plurality of signal layers 16. However, the peripheral conductive array contacts associated with the micro-perforations 26a do not extend below the base layer 12 of the multilayer printed circuit board 10. Thus, additional and/or extended vias 38a may be provided in all of the signal path layers 16, including the uppermost conductive signal path layer (i.e., 16a), beneath these peripheral conductive array contacts.

It should be noted at this point that one or more conductive vias may be provided in the multilayer printed circuit board 10 extending from the base layer 12 of the multilayer printed circuit board 10 to at least one of the conductive power/ground layers (i.e., 18 and/or 14) in accordance with the concepts described in the above-referenced U.S. patent application US 10/101211 (now U.S. TBA), US 09/651188 (now U.S. 6388890), and U.S. provisional patent application US 60/212387 (all of which are incorporated by reference), wherein each conductive via is in electrical connection with at least one separate conductive power/ground contact provided on the base layer 12 of the multilayer printed circuit board 10. Each of which forms part of an array of conductive contacts formed on the base layer 12 of the multilayer printed circuit board 10 to match the conductive power/ground contacts of the electronic component. This allows one additional via to be formed in each of the plurality of signal path layers 16 below the conductive power/ground contact.

It should be noted at this point that all of the variations and benefits associated with the method of using microscopic perforations to reduce the number of layers in a multilayer printed circuit board can be realized and obtained by using the conductive perforations described above in electrical connection with the conductive power/ground contacts.

It should be noted at this point that although the above description is strictly limited to reducing the number of layers of a multilayer printed circuit board having electronic components mounted thereon, the scope of the present invention also includes applying the above-described techniques in a printed circuit board having a plurality of different embedded electronic components thereon. For example, referring to FIG. 17, there is shown a side cross-sectional view of an alternative multi-layer printed circuit board 10a according to the present invention. Similar to the multilayer printed circuit board 10 of fig. 1, the multilayer printed circuit board 10a of fig. 17 includes a base layer (top layer) 12, a secondary layer (bottom layer) 14, a plurality of signal layers 16, and a plurality of power/ground plane layers 18. The multi-layer printed circuit board 10a also includes a super-large via 20 for electrically connecting selected ones of the base layer 12, the secondary layer 14, and the power/ground plane layer 18. The multilayer printed circuit board 10a also includes a plurality of buried vias 24 for electrically connecting selected ones of the plurality of signal layers 16 and selected ones of the plurality of power/ground plane layers 18.

Unlike the multilayer printed circuit board 10 of fig. 1, the multilayer printed circuit board 10a of fig. 17 includes a blind via 74 for electrically connecting the secondary layer 14, selected ones of the plurality of signal layers 16, and selected ones of the plurality of power/ground plane layers 18. The multilayer printed circuit board 10a also includes an embedded electronic component 72 disposed between the power/ground plane layer 18a and the signal layer 16 a.

As described above, the embedded electronic component 72 may be one of a wide variety of possible electronic components. For example, referring to fig. 18A, there is shown an embedded electronic component 72a having conductive contacts 76 disposed thereon. In this case, the conductive contacts 76 may be electrically connected to corresponding conductive contacts disposed on a selected one of the plurality of signal layers 16 (i.e., layer 16a in fig. 17) or the plurality of power/ground plane layers 18 (i.e., layer 18a in fig. 17). Alternatively, referring to fig. 18B, there is shown an embedded electronic component 72 having conductive contacts 76 disposed on both sides thereof. In this case, the conductive contacts 76 may be electrically connected with corresponding conductive contacts on a selected one of the plurality of signal layers 16 (i.e., layer 16a in fig. 17) and a selected one of the plurality of power/ground plane layers 18 (i.e., layer 18a in fig. 17). Of course, other types of electronic components (e.g., digital components) may be embedded within the multilayer printed circuit board 10a of fig. 17, and these embedded electronic components may also be disposed between or on any of the plurality of signal layers 16 and/or any of the plurality of power/ground plane layers 18 in accordance with the present invention. In any case, when these embedded electronic components are used, the above-described technique for reducing the number of layers of the multilayer printed circuit board can be applied.

At this point it should be noted that although the above description is strictly limited to reducing the number of layers of a multilayer printed circuit board on which electronic components are mounted, the scope of the present invention also includes applying the above-described techniques in a wide variety of multilayer signal wiring devices. For example, the above-described techniques may be applied to a multi-layer integrated circuit hard mask packaging apparatus. Therefore, the present invention is more suitable for indicating a technique for reducing the number of layers of a multilayer signal wiring device.

The present invention is not to be limited in scope by the specific embodiments described herein. Indeed, various modifications of the invention in addition to those described herein will become apparent to those skilled in the art from the foregoing description and accompanying drawings. Such modifications are therefore intended to fall within the scope of the following appended claims. In addition, although the present invention has been described in the context of a particular implementation in a particular environment to achieve a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present invention can be beneficially implemented in any number of environments to achieve any number of goals. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present invention as disclosed herein.

Claims (50)

1. A method for reducing the number of layers of a multilayer signal wiring device having: a plurality of conductive signal path layers for conducting electrical signals in and out of at least one electronic component mounted on a surface of the multilayer signal routing device; and at least one of: at least one conductive power layer to provide power to at least one electronic component mounted on a surface of the multilayer signal wiring device; at least one conductive ground layer to provide a reference ground for at least one electronic component mounted on a surface of the multilayer signal routing device; at least one electrically conductive utility/ground layer for providing power/ground to at least one electronic component mounted on a surface of the multilayer signal routing device, the method comprising:

receiving electronic component information of at least one electronic component, wherein the electronic component information comprises the number characteristic of the conductive contacts, the distance characteristic of the conductive contacts, the signal type characteristic of the conductive contacts and the signal direction characteristic of the conductive contacts;

identifying an electronic component having a high density conductive contact array package based at least in part on at least one of a characteristic of the number of conductive contacts and a characteristic of the pitch of the conductive contacts;

routing electrical signals in a plurality of conductive signal path layers in a multi-layer signal routing device to connect the high-density conductive contact array package inward and outward based at least in part on at least one of a signal type characteristic of the conductive contacts and a signal direction characteristic of the conductive contacts; and

at least one of:

providing a plurality of conductive vias on the multilayer signal routing device, the conductive vias extending from a surface of the multilayer signal routing device to one of the plurality of conductive signal path layers, the plurality of conductive vias being arranged to form a channel under the plurality of conductive vias and in another of the plurality of conductive signal path layers;

providing a plurality of conductive vias in the multilayer signal routing device, the conductive vias extending from a surface of the multilayer signal routing device to at least one of the at least one conductive power layer, each of the plurality of conductive vias being electrically connected to at least one separate conductive power contact on the surface of the multilayer signal routing device, each of the at least one conductive power contact forming a portion of an array of conductive contacts to match a high density conductive contact array package of electronic components, wherein a channel is formed on each of the plurality of conductive signal path layers underlying the conductive power contacts;

providing a plurality of conductive vias in the multilayer signal routing device, the conductive vias extending from a surface of the multilayer signal routing device to at least one of the at least one conductive ground layer, each of the plurality of conductive vias being electrically connected to at least one separate conductive ground contact on the surface of the multilayer signal routing device, each of the at least one conductive ground contacts forming a portion of an array of conductive contacts to match a high density conductive contact array package of electronic components, wherein a channel is formed on each of the plurality of conductive signal path layers below the conductive ground contacts;

providing a plurality of conductive vias in the multilayer signal routing device, the conductive vias extending from a surface of the multilayer signal routing device to at least one of the at least one conductive utility/ground layer, each of the plurality of conductive vias being electrically connected to at least one separate conductive power/ground contact on the surface of the multilayer signal routing device, each of the at least one conductive power/ground contacts forming a portion of an array of conductive contacts to match a high density conductive contact array package of the electronic component, wherein vias are formed on each of the plurality of conductive signal path layers and below the at least one conductive power/ground contact.

2. The method of claim 1, wherein the channels are configured to have one or more linear, circular, diamond, curved, stepped, or any other shape, or combinations thereof.

3. The method of claim 1, wherein the channels are arranged to have one or more vertical, horizontal, inclined, or any other orientation, or a combination thereof.

4. The method of claim 1, wherein the plurality of conductive vias form at least a portion of an array of conductive contacts to match a high density conductive contact array package of the electronic component, and wherein at least a portion of the plurality of conductive vias are disposed within the array of conductive contacts such that the vias are correspondingly formed within the array of conductive contacts.

5. The method of claim 1, wherein the multilayer signal routing device has an array of conductive contacts formed on a surface thereof to match a high density conductive contact array package of the electronic component, wherein at least a portion of the plurality of conductive vias are disposed outside of the array of conductive contacts, wherein each of the portion of the plurality of conductive vias is electrically connected to a peripheral one of the conductive contacts on the surface of the multilayer signal routing device.

6. The method of claim 1, wherein the plurality of conductive vias further extend from a surface of the multi-layer signal routing device to a different layer of the plurality of conductive signal path layers.

7. The method of claim 1, wherein the plurality of conductive vias form at least a portion of an array of conductive contacts to match a high density conductive contact array package of the electronic component, and wherein at least a portion of the plurality of conductive vias are disposed within the array of conductive contacts such that vias can extend through the array of conductive contacts.

8. The method of claim 1, wherein the plurality of conductive vias form at least a portion of an array of conductive contacts to match a high density conductive contact array package of an electronic component, wherein the array of conductive contacts has one or more of a square, triangular, circular, and any other pattern of conductive contacts, or a combination thereof.

9. The method of claim 1, wherein the at least two electrical signals are differential electrical signals, wherein the differential electrical signals are routed at least partially together on a lane of another one of the plurality of conductive signal path layers below the plurality of conductive vias.

10. The method of claim 1, wherein at least a portion of the plurality of conductive power contacts are disposed within an array of conductive contacts such that vias are correspondingly formed within the array of conductive contacts.

11. The method of claim 1, wherein at least a portion of the plurality of conductive vias are disposed outside of the array of conductive contacts, wherein each of the portion of conductive vias is electrically connected to at least one independent conductive power contact located at a periphery of the array of conductive contacts.

12. The method of claim 1, wherein at least a portion of the plurality of conductive power contacts are disposed within an array of conductive contacts such that vias extend through the array of conductive contacts.

13. The method of claim 1, wherein at least two electrical signals are differential electrical signals, wherein the differential electrical signals are routed at least partially together beneath the conductive power contact and on a via in one of a plurality of conductive signal path layers.

14. The method of claim 1, wherein at least a portion of the plurality of conductive ground contacts are disposed within the array of conductive contacts such that vias are correspondingly formed within the array of conductive contacts.

15. The method of claim 1, wherein at least a portion of the plurality of conductive vias are disposed outside of the array of conductive contacts, wherein each of the portion of conductive vias is electrically connected to at least one independent conductive ground contact located at a periphery of the array of conductive contacts.

16. The method of claim 1, wherein at least a portion of the plurality of conductive ground contacts are disposed within an array of conductive contacts such that vias extend through the array of conductive contacts.

17. The method of claim 1, wherein at least two electrical signals are differential electrical signals, wherein the differential electrical signals are routed at least partially together underneath the conductive ground contact and on a via of one of the plurality of conductive signal path layers.

18. The method of claim 1, wherein the surface of the multilayer signal routing device is an interior surface of the multilayer signal routing device and the at least one electronic component is mounted on the interior surface of the multilayer signal routing device.

19. The method of claim 18, wherein at least one of the electronic components has at least one first electrically conductive contact formed on a first side thereof, wherein the at least one first electrically conductive contact is electrically connected to at least one first corresponding electrically conductive contact formed on the inner surface of the multilayer signal routing device.

20. The method of claim 19, wherein at least one of the electronic components has at least one second electrically conductive contact formed on a second side thereof, wherein the at least one second electrically conductive contact is electrically connected to at least one second corresponding electrically conductive contact formed on another interior surface of the multilayer signal routing device.

21. A method for reducing the number of layers of a multilayer signal wiring device having: a plurality of conductive signal path layers for conducting electrical signals in and out of at least one electronic component mounted on a surface of the multilayer signal routing device; and at least one of: at least one conductive power layer to provide power to at least one electronic component mounted on a surface of the multilayer signal wiring device; at least one conductive ground layer to provide a reference ground for at least one electronic component mounted on a surface of the multilayer signal routing device; at least one electrically conductive utility/ground layer for providing power/ground to at least one electronic component mounted on a surface of the multilayer signal routing device, the method comprising:

receiving electronic component information of at least one electronic component, wherein the electronic component information comprises the number characteristic of the conductive contacts, the distance characteristic of the conductive contacts, the signal type characteristic of the conductive contacts and the signal direction characteristic of the conductive contacts;

identifying an electronic component having a high density conductive contact array package based at least in part on at least one of a characteristic of the number of conductive contacts and a characteristic of the pitch of the conductive contacts;

routing electrical signals in a plurality of conductive signal path layers in a multi-layer signal routing device to connect the high-density conductive contact array package inward and outward based at least in part on at least one of a signal type characteristic of the conductive contacts and a signal direction characteristic of the conductive contacts.

22. The method of claim 21, further comprising:

a plurality of conductive vias are disposed on the multilayer signal routing device, the conductive vias extending from a surface of the multilayer signal routing device to one of the plurality of conductive signal path layers, the plurality of conductive vias being arranged to form a channel under the plurality of conductive vias and in another of the plurality of conductive signal path layers.

23. The method of claim 22, wherein the channels are configured to have one or more linear, circular, diamond, curved, stepped, or any other shape, or combinations thereof.

24. The method of claim 22, wherein the channels are arranged to have one or more vertical, horizontal, inclined, or any other orientation, or a combination thereof.

25. The method of claim 22, wherein the plurality of conductive vias form at least a portion of an array of conductive contacts to match a high density conductive contact array package of the electronic component, and wherein at least a portion of the plurality of conductive vias are disposed within the array of conductive contacts such that the vias are correspondingly formed within the array of conductive contacts.

26. The method of claim 22, wherein the multilayer signal routing device has an array of conductive contacts formed on a surface thereof to match a high density conductive contact array package of the electronic component, wherein at least a portion of the plurality of conductive vias are disposed outside of the array of conductive contacts, wherein each of the portion of the plurality of conductive vias is electrically connected to a peripheral one of the conductive contacts on the surface of the multilayer signal routing device.

27. The method of claim 22, wherein the plurality of conductive vias further extend from a surface of the multi-layer signal routing device to a different layer of the plurality of conductive signal path layers.

28. The method of claim 22, wherein the plurality of conductive vias form at least a portion of an array of conductive contacts to match a high density conductive contact array package of the electronic component, and wherein at least a portion of the plurality of conductive vias are disposed within the array of conductive contacts such that vias can extend through the array of conductive contacts.

29. The method of claim 22, wherein the plurality of conductive vias form at least a portion of an array of conductive contacts to match a high density conductive contact array package of an electronic component, wherein the array of conductive contacts has one or more of a square, triangular, circular, and any other pattern of conductive contacts, or a combination thereof.

30. The method of claim 22, wherein the at least two electrical signals are differential electrical signals, wherein the differential electrical signals are routed at least partially together on a lane of another one of the plurality of conductive signal path layers beneath the plurality of conductive vias.

31. The method of claim 21, wherein the multilayer signal routing device has at least one conductive power plane to provide power to electronic components mounted on a surface of the multilayer signal routing device, the method comprising:

providing a plurality of conductive vias in the multilayer signal routing device, the conductive vias extending from a surface of the multilayer signal routing device to at least one of the at least one conductive power layer, each of the plurality of conductive vias being electrically connected to at least one separate conductive power contact on the surface of the multilayer signal routing device, each of the at least one conductive power contact forming a portion of an array of conductive contacts to match a high density conductive contact array package of electronic components;

wherein a via is formed on each of the plurality of conductive signal path layers below the conductive power contact.

32. The method of claim 31, wherein the channels are configured to have one or more linear, circular, diamond, curved, stepped, or any other shape, or combinations thereof.

33. The method of claim 31, wherein the channels are arranged to have one or more vertical, horizontal, inclined or any other orientation, or a combination thereof.

34. The method of claim 31, wherein at least a portion of the plurality of conductive power contacts are disposed within the array of conductive contacts such that vias are correspondingly formed within the array of conductive contacts.

35. The method of claim 31, wherein at least a portion of the plurality of conductive vias are disposed outside of the array of conductive contacts, wherein each of the portion of conductive vias is electrically connected to at least one independent conductive power contact located at the periphery of the array of conductive contacts.

36. The method of claim 31, wherein at least a portion of the plurality of conductive power contacts are disposed within an array of conductive contacts such that vias extend through the array of conductive contacts.

37. The method of claim 31, wherein the array of conductive contacts has one or more of a square, triangular, circular, and any other pattern of conductive contacts, or a combination thereof.

38. The method of claim 31, wherein at least two electrical signals are differential electrical signals, wherein the differential electrical signals are routed at least partially together beneath the conductive power contact and on a via in one of a plurality of conductive signal path layers.

39. The method of claim 21, wherein the multilayer signal routing device has at least one conductive ground layer to provide a ground reference for electronic components mounted on a surface of the multilayer signal routing device, the method further comprising:

providing a plurality of conductive vias in the multilayer signal routing device, the conductive vias extending from a surface of the multilayer signal routing device to at least one of the at least one conductive ground layer, each of the plurality of conductive vias being electrically connected to at least one separate conductive ground contact on the surface of the multilayer signal routing device, each of the at least one conductive ground contacts forming a portion of an array of conductive contacts to match a high density conductive contact array package of electronic components;

wherein a via is formed on each of the plurality of conductive signal path layers below the conductive ground contact.

40. The method of claim 39, wherein the channels are configured to have one or more linear, circular, diamond, curved, stepped, or any other shape, or combinations thereof.

41. The method of claim 39, wherein the channels are arranged to have one or more vertical, horizontal, inclined or any other orientation, or a combination thereof.

42. The method of claim 39, wherein at least a portion of the plurality of conductive ground contacts are disposed within the array of conductive contacts such that vias are correspondingly formed within the array of conductive contacts.

43. The method of claim 39, wherein at least a portion of the plurality of conductive vias are disposed outside of the array of conductive contacts, wherein each of the portion of conductive vias is electrically connected to at least one independent conductive ground contact located at the periphery of the array of conductive contacts.

44. The method of claim 39, wherein at least a portion of the plurality of conductive ground contacts are disposed within an array of conductive contacts such that vias extend through the array of conductive contacts.

45. The method of claim 39, wherein the array of conductive contacts has one or more of a square, triangular, circular, and any other pattern of conductive contacts, or a combination thereof.

46. The method of claim 39, wherein at least two electrical signals are differential electrical signals, wherein the differential electrical signals are routed at least partially together underneath the conductive ground contact and on a via of one of the plurality of conductive signal path layers.

47. The method of claim 21, wherein the multilayer signal routing device has at least one conductive utility/ground layer for providing power/ground to electronic components mounted on a surface of the multilayer signal routing device, the method further comprising:

providing a plurality of conductive vias in the multilayer signal routing device, the conductive vias extending from a surface of the multilayer signal routing device to at least one of the at least one conductive utility/ground layer, each of the plurality of conductive vias being electrically connected to at least one separate conductive power/ground contact on the surface of the multilayer signal routing device, each of the at least one conductive power/ground contacts forming a portion of an array of conductive contacts to match a high density conductive contact array package of electronic components;

wherein a via is formed on each of the plurality of conductive signal path layers and beneath at least one conductive power/ground contact.

48. The method of claim 21, wherein the surface of the multilayer signal routing device is an interior surface of the multilayer signal routing device and the at least one electronic component is mounted on the interior surface of the multilayer signal routing device.

49. The method of claim 48, wherein at least one of the electronic components has at least one first electrically conductive contact formed on a first side thereof, wherein the at least one first electrically conductive contact is electrically connected to at least one first corresponding electrically conductive contact formed on the inner surface of the multilayer signal routing device.

50. The method of claim 49, wherein at least one of the electronic components has at least one second electrically conductive contact formed on a second side thereof, wherein the at least one second electrically conductive contact is electrically connected to at least one second corresponding electrically conductive contact formed on another interior surface of the multilayer signal routing device.