HK1147595B - Method of forming an eeprom device and structure therefor - Google Patents

Description

Method of forming an EEPROM device and structure therefor

Technical Field

The present invention relates generally to electronics, and more particularly to semiconductors, structures thereof, and methods of forming semiconductor devices.

Background

In the past, the semiconductor industry utilized various methods and structures to create Electrically Erasable Programmable Read Only Memory (EEPROM) devices that included a plurality of EEPROM cells. A typical EEPROM is described in U.S. patent No. 7,190,020 issued to Forbes et al on 3-13-2007. In forming an EEPROM device, the transistors within each EEPROM cell may have mismatched threshold voltages that result in improper operation of the EEPROM cell.

Accordingly, it is desirable to have an EEPROM cell with transistors having more closely matched threshold voltages, and to have a structure that facilitates the formation of transistors having more closely matched threshold voltages.

Disclosure of Invention

According to one aspect of the present invention, an EEPROM cell is provided. The EEPROM unit cell includes: a semiconductor substrate having a channel region of a first transistor formed thereon; a floating gate having a bit storage region and further having a gate electrode overlying a portion of the channel region, the bit storage region having an outer edge; a control gate overlying the floating gate, an outer edge of the control gate extending a first distance beyond an outer edge of the bit storage region of the floating gate; a metal layer overlying the first portion of the control gate and extending to overlap the first portion of the control gate by a second distance beyond an outer edge of the control gate; and an opening through the metal layer, the opening overlying the bit storage region, wherein outer edges of the opening are spaced apart a third distance beyond outer edges of the bit storage region, and wherein the opening overlies a second portion of the control gate.

In accordance with another aspect of the present invention, a method for forming an EEPROM cell of a semiconductor device is provided. The method comprises the following steps: providing a semiconductor substrate; forming a channel region of a first MOS transistor on the semiconductor substrate; forming a floating gate having a bit storage region and further having a gate electrode overlying at least a portion of the channel region; forming a control gate overlying the bit storage region; forming a metal layer covering the control grid; and forming an opening through the metal layer, wherein the opening overlies at least a portion of the bit storage region and also overlies a first portion of the control gate, and wherein the metal layer overlies a second portion of the control gate.

According to yet another aspect of the present invention, a method for forming an EEPROM cell of a semiconductor device is provided. The method comprises the following steps: providing a semiconductor substrate; forming a channel region of a first MOS transistor on the semiconductor substrate; forming a floating gate having a gate electrode overlying at least a portion of a channel region of the first MOS transistor, including forming a bit storage region of the floating gate having an outer edge; forming a control gate overlying at least a portion of the floating gate; and forming a metal layer having an opening through the metal layer, including forming the metal layer to overlie the first portion of the control gate and forming the opening to overlie the second portion of the control gate and overlie at least a portion of the bit storage region.

Drawings

FIG. 1 illustrates a cross-sectional isometric view of a portion of an embodiment of an EEPROM device including a plurality of EEPROM cells in accordance with the present invention;

FIG. 2 illustrates the EEPROM device of FIG. 1 at a stage in an embodiment of a method of forming the EEPROM device of FIG. 1; and

fig. 3 illustrates the EEPROM device of fig. 2 at a subsequent stage in an embodiment of a method of forming the EEPROM device.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Moreover, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, current carrying electrode means an element of a device, such as a source or drain of an MOS transistor, or an emitter or collector of a bipolar transistor, or a cathode or anode of a diode, that carries current through the device; and the control electrode represents an element of the device, such as the gate of a MOS transistor or the base of a bipolar transistor, which controls the current through the device. Although these devices are explained herein as certain N-channel or P-channel devices, or certain N-type or P-type doped regions, one of ordinary skill in the art will recognize that complementary devices are also possible in accordance with the present invention. Those skilled in the art will recognize that the words "during …", "at … simultaneously", "when …" as used herein with respect to circuit operation are not precise terms that indicate that a reaction will occur as soon as operation is initiated, but that there may be some slight but reasonable delay, such as a propagation delay, between reactions that are provoked by initial operation. Use of the word "about" or "substantially" means that the value of an element has a parameter that is expected to be very close to a specified value or position. However, as is well known in the art, there is always a slight variation in the blocking value or position exactly as specified. It is well established in the art that variations up to about 10% (and for semiconductor doping concentrations up to 20%) are reasonable variations from the ideal target exactly as described. For clarity of the drawings, the doped regions of the device structure are shown as having generally straight edges and precisely angled corners. However, those skilled in the art understand that the edges of the doped regions are generally not straight lines due to the diffusion and activation of the dopants, and that the corners may not be precise corners.

Detailed Description

Fig. 1 shows a cross-sectional isometric view of a portion of an embodiment of EEPROM device 10 that includes a plurality of EEPROM cells, including EEPROM cells 11, 12, and 13. The units 11, 12 and 13 are identified in a general manner by dashed boxes. Device 10 and cells 11, 12, and 13 are formed on a semiconductor substrate 16. In a preferred embodiment, substrate 16 has a P-type conductivity. Also in the preferred embodiment, each cell 11, 12 and 13 is a differential memory cell comprising a sense transistor 17 and 18 (as will be seen further below). The differential structure of the cells 11, 12 and 13 minimizes susceptibility to electric field disturbances. As will be appreciated by those skilled in the art, an EEPROM device such as device 10 typically includes more EEPROM cells than the three cells shown in fig. 1.

The following description relates to the unit 11 and units related thereto. Those skilled in the art will recognize that the description also applies to units 12 and 13.

Fig. 2 illustrates a cross-sectional isometric view of a portion of an embodiment of device 10 at a stage in an embodiment of a method of forming device 10. The description refers to fig. 1 and 2. In a preferred embodiment, transistor 17 is formed as a P-channel MOS transistor and transistor 18 is formed as an N-channel MOS transistor. Because the preferred embodiment of substrate 16 is of P-type conductivity, N-type doped regions 21 are formed on the surface of substrate 16 and P-type doped regions 22 and 23 are formed within regions 21 to form the respective source and drain regions of transistor 17. Region 23 is spaced apart from region 22 such that a portion of region 21 between regions 22 and 23 becomes the channel region of transistor 17. N-type regions 25 and 26 are formed on the surface of substrate 16 and spaced a distance from region 21 to form respective drain and source regions of transistor 18. Region 25 is spaced apart from region 26 such that a portion of substrate 16 between regions 25 and 26 becomes a channel region of transistor 18. Those skilled in the art will recognize that the source and drain regions of transistor 17 may be reversed, and the same applies to transistor 18.

Gate dielectric 28 is formed overlying the portions of transistors 17 and 18 where the channel regions will be formed. In one embodiment, dielectric 28 is formed to cover all of substrate 16 where cells 11, 12, and 13 are to be formed. In other embodiments, the dielectric 28 may be patterned (pattern) to locate the dielectric 28 only within the cells 11-13. Dielectric 28 is typically formed of silicon dioxide.

A floating gate 29 is formed within each cell 11-13 overlying dielectric 28. Gate 29 typically includes three regions: a bit storage (bit storage) region 70, a gate electrode 71 of one transistor, such as the electrodes of transistors 17, 61 and 67, and another gate electrode 72 of another transistor, such as the electrode of each of transistors 18, 60 and 66. Gate electrodes 71 and 72 extend from the bit storage region 70 to overlie channel regions of the respective transistors. For transistor 17, for example, gate electrode 71 extends to overlie the channel region of transistor 17. The floating gate 29 is typically formed by applying a layer of doped polysilicon on the surface of the dielectric 28 and patterning the doped polysilicon.

Fig. 3 illustrates device 10 at a subsequent stage of an embodiment of a method of forming device 10. A dielectric layer 31 is then formed generally over gate 29 and over transistors 17 and 18 to provide insulation from other elements of device 10. Gate 29, region 21, and regions 22, 23, 25, and 26 are shown in dashed lines in fig. 3 to illustrate that they are below layer 31 and are therefore hidden from view in fig. 3. In some embodiments, a conductor interconnect layer (not shown) may be formed on layer 31 to electrically connect to regions 22, 23, 25, or 26. This conductor layer is typically formed of metal and is often referred to as the first interconnect layer or sometimes as metal one (1). The first interconnect layer may facilitate forming an electrical connection to the sources or drains of transistors 17 and 18.

A control gate 32 is formed overlying at least a portion of floating gate 29. Typically, control gate 32 is formed by applying a layer of doped polysilicon on the surface of layer 31 and patterning the doped polysilicon. Control gate 32 has an outer edge that generally extends beyond the outer edge of bit storage region 70 closest to gate 29 of transistor 17. The other outer edge on the other side of gate 32 typically extends beyond the outer edge of region 70 closest to gate 29 of transistor 18. In a preferred embodiment, these outer edges of gate 32 are arranged to extend a distance 33 beyond the outer edges of region 70 of floating gate 29 so that gate 32 overlies region 70 of gate 29 and preferably extends at least a distance 33 beyond the outer edges of region 70. In a preferred embodiment, the other two edges of gate 32 (the two opposite transistors 17 and 18) are also arranged to extend a distance 33 beyond the outer edge of region 70 so that the entire gate 32 overlies at least distance 33 over the entire region 70.

Referring again to fig. 1, another dielectric layer 34 is typically formed overlying the control gate 32 and the first conductor interconnect layer in order to provide insulation from other elements of the device 10. In some embodiments, a second conductor interconnect layer (not shown) may be formed on the surface of layer 34 to make electrical contact through layer 31 to portions of the underlying first conductor interconnect layer or to other portions of transistors 17 and 18. This second conductor interconnect layer is typically formed of metal and is often referred to as metal two (2). Such conductor interconnect layers are well known to those skilled in the art. In some embodiments, a third conductor interconnect layer (not shown) may be formed on the surface of layer 34. In such embodiments, another optional dielectric layer (not shown) may be formed overlying the third conductor interconnect layer to provide insulation from other elements of device 10. In other embodiments, layer 36 may be omitted.

Subsequently, a metallic shield layer or layer 39 is formed to include a plurality of openings 45 through layer 39. Layer 39 is formed over layer 34 (or optionally over an optional dielectric layer) such that openings 45 are disposed overlying the first portion of floating gate 29, and thus, each cell 11-13 includes an opening 45. In a preferred embodiment, outer edge 47 of opening 45 is positioned to extend a distance beyond the outer edge of region 70 of floating gate 29 such that opening 45 overlies region 70 and such that layer 39 does not overlie region 70 of gate 29. In a preferred embodiment, outer edge 47 is also configured to extend to overlie gate 32 a distance 41 from the outer edge of gate 32 so that a portion of layer 39 does not overlie the first portion of gate 32 a distance 41 beyond the outer edge of gate 32. Thus, opening 45 overlies a second portion of gate 32, such as the portion of gate 32 overlying region 70. Thus, it can be seen that edges 47 of opening 45 are spaced a third distance beyond the outer edge of region 70.

Those skilled in the art will recognize that the area of region 70 is selected to provide sufficient charge storage capacity in dielectric 28 to facilitate reliable readout of the voltages provided by transistors 17 and 18. Because gate 32 is used during the programming process, some charge may also be stored in gate 32 and the portion of dielectric 29 under electrodes 71 and 72. However, the portions of electrodes 71 and 72 that underlie gate 32 are so small that region 70 effectively acts as a bit storage region for each cell 11, 12, and 13.

Layer 39 acts as a shield against electromagnetic interference (EMI) and exposure to visible and ultraviolet light. Those skilled in the art will recognize that the metal of layer 39 acts as a shield to terminate electromagnetic waves, thereby minimizing the impact on device 10. In addition, the control gate 32 also acts as an EMI shield. During a readout operation, a low potential such as a common potential or a ground potential is applied to the gate 32. During a programming operation, a high potential is applied to the gate 32. Due to the potential (either high or low) applied to gate 32, gate 32 acts as an EMI shield to any electromagnetic fields propagating through opening 45. Thus, layer 39 and gate 32 provide EMI protection for device 10.

During operation, the device 10 may also be exposed to visible or ultraviolet light. Light energy from the light can create an electrical potential on gates 29 and 32. The metal of layer 39 shields device 10 from these photons. Due to the potential applied to the gate 32, the gate 32 also acts as a shield to prevent photons from affecting the gate 29 and thus the operation of the device 10. The distance 41 is selected to minimize any light from diffracting around the edges of the opening 45 and affecting the charge stored under the bit storage region 70. Further, distance 33 is selected to minimize any light from diffracting around the edges of gate 32 and affecting the charge stored under bit storage region 70. Preferably, distances 33 and 41 are no less than the wavelength of visible or ultraviolet light to which device 10 will be exposed.

During the process of forming device 10, dangling bonds are typically formed on gates 29 and 32. These dangling bonds form voltage potentials that can affect the threshold of transistors 17 and 18 and cause incorrect operation of transistors 17 and 18. To minimize the influence of these dangling bonds, an annealing operation is performed that minimizes the number of dangling bonds. This repair is aided by the diffusion of the gas (used during the annealing operation) through the opening 45. Without the openings 45, the metal of layer 39 would impede this diffusion process and reduce the removal of dangling bonds. Thus, opening 45 provides a structure that helps form transistors 17 and 18 with more closely matched threshold voltages. Accordingly, those skilled in the art will recognize that in other embodiments, having opening 45 overlie a small portion of region 70 will aid in the annealing process. Thus, in other embodiments, edge 47 may extend to overlie portions of region 70 and still provide advantages. Accordingly, opening 45 may be formed to cover at least a portion of region 70, and may cover only 20% of the surface area of region 70 and still provide advantages.

Those skilled in the art will recognize that distance 33 may be reduced and may be zero (0) in some cases if distance 41 is sufficient to prevent light from affecting the operation of device 10. However, opening 45 preferably completely covers at least a portion (e.g., region 70) of gate 29 in order to provide a way to reduce dangling bonds and facilitate efficient annealing operations.

Subsequently, a passivation layer (not shown) is typically applied to cover layer 39. In some embodiments, a potting metal or gel coat or other similar material (not shown) may be applied on top of the passivation layer. Such passivation layers and gel coats are well known to those skilled in the art.

Those skilled in the art will recognize that units 11, 12 and 13 generally include other elements that are not shown in fig. 1-3 for clarity of the drawings. For example, cells 11, 12, and 13 typically include word lines and bit lines for programming and reading information from the cells. These word lines and bit lines are typically formed using the conductor interconnect layers described above.

From all the previous explanations, the person skilled in the art will understand that the unit 11 comprises:

a semiconductor substrate having a channel region of a first transistor formed thereon; a floating gate having a bit storage region and further having a gate electrode overlying a portion of the channel region, the bit storage region having an outer edge; a control gate overlying the floating gate, the control gate having an outer edge extending a first distance beyond an outer edge of a bit storage region of the floating gate; a metal layer overlying the first portion of the control gate and extending to overlap the first portion of the control gate by a second distance beyond an outer edge of the control gate; and an opening through the metal layer, the opening overlying the bit storage region, wherein an outer edge of the opening is spaced apart a third distance beyond an outer edge of the bit storage region, and wherein the opening overlies a second portion of the control gate.

From the description provided hereinabove, those skilled in the art will appreciate that the method of forming the cell 11 of the device 10 includes: providing a semiconductor substrate; forming a channel region of a first MOS transistor on a semiconductor substrate; forming a floating gate having a storage region and further having a gate electrode overlying at least a portion of the channel region; forming a control grid electrode covering the bit storage area; forming a metal layer covering the control grid; and forming an opening through the metal layer, wherein the opening overlies at least a portion of the bit storage region and also overlies the first portion of the control gate, and wherein the metal layer overlies the second portion of the control gate.

Furthermore, it will be understood by those skilled in the art that the foregoing explanation hereinabove includes a method of forming the cell 11 of the device 10, the method comprising: providing a semiconductor substrate; forming a channel region of a first MOS transistor on a semiconductor substrate; forming a floating gate having a gate electrode overlying at least a portion of a channel region of the first MOS transistor, including a bit storage region having an outer edge that forms the floating gate; forming a control gate overlying at least a portion of the floating gate; and forming a metal layer having an opening through the metal layer, including forming the metal layer to overlie the first portion of the control gate and forming the opening to overlie the second portion of the control gate and overlie at least a portion of the bit storage region.

In view of all of the above, it is evident that a new device and method is disclosed. Included, among other features, is forming an EEPROM cell by forming a metal layer having an opening through the metal layer, including forming the metal layer to overlie a first portion of the control gate and forming the opening to overlie a portion of the floating gate and a second portion of the control gate. As shown above, having the opening overlying a portion of the floating gate facilitates more accurately forming the threshold voltage of at least one transistor of the EEPROM cell. A further advantage of the openings is that the manufacturability of the EEPROM device is improved. Those skilled in the art will recognize that large metal layers may affect the etch rate of components proximate to the metal layer, which is slower than the etch rate of components not proximate to the metal layer (e.g., components in or near the scribe grid of a wafer in which EEPROM cells are formed). As a result, the etch time may have to be increased, which may lead to undercutting of metal layers or other components and various well-known problems. Opening 45 exhibits a more balanced etch profile that improves the etch operation, thereby improving the manufacturability of the EEPROM cell and the device that includes the EEPROM cell.

While the subject matter of the present invention has been described with specific preferred embodiments, it is evident that many alternatives and variations will be apparent to those skilled in the semiconductor arts. For example, although cells 11, 12, and 13 are shown as having two transistors, in other embodiments, cells 11, 12, and 13 may have only one transistor, and may or may not have a programming or control transistor. In such a case, the gate electrode of the floating gate 29 may overlie only the channel region of one transistor rather than the channel region of the control transistor. Although device 10 is shown as having three EEPROM cells 11, 12, and 13, other embodiments of device 10 may have more or fewer EEPROM cells. As will be appreciated by those skilled in the art, the exemplary forms of doped regions 21, 22, 23, 15, and 26 and substrate 16 are used as a means of explaining device 10, and other implementations are possible. For example, in other embodiments, an epitaxial layer may be formed on substrate 16, and regions 21, 22, 23, 15, and 26 may be formed in the epitaxial layer. The conductivity type of the epitaxial layers may be the same as or opposite to the conductivity type of substrate 16. For the case of opposite conductivity, regions 21, 22, 23, 15, and 26 typically have a conductivity opposite to that explained above for device 10. In another implementation, the outer edge of control gate 32 may extend a large distance beyond the outer edge of floating gate 29, and may be adjacent to or may even extend to overlap a portion of the channel region of one or more of transistors 17, 18, 60, 61, 66, or 67. The word "connect" is used throughout for clarity of description, but is intended to have the same meaning as the word "couple". Accordingly, "connected" should be interpreted to include direct connections or indirect connections.

Claims (10)

1. An EEPROM cell, comprising:

a semiconductor substrate having a channel region of a first transistor formed thereon;

a floating gate having a bit storage region and further having a gate electrode overlying a portion of the channel region, the bit storage region having an outer edge;

a control gate overlying the floating gate, an outer edge of the control gate extending a first distance beyond an outer edge of the bit storage region of the floating gate;

a metal layer overlying the first portion of the control gate and extending to overlap the first portion of the control gate by a second distance beyond an outer edge of the control gate; and

an opening through the metal layer, the opening overlying the bit storage region, wherein an outer edge of the opening is spaced apart a third distance beyond an outer edge of the bit storage region, and wherein the opening overlies a second portion of the control gate.

2. The EEPROM cell of claim 1, wherein the second distance is not less than a wavelength of light irradiating the EEPROM cell.

3. The EEPROM cell of claim 1, further comprising a gate dielectric between said floating gate and said semiconductor substrate.

4. A method for forming an EEPROM cell of a semiconductor device, the method comprising the steps of:

providing a semiconductor substrate;

forming a channel region of a first MOS transistor on the semiconductor substrate;

forming a floating gate having a bit storage region and further having a gate electrode overlying at least a portion of the channel region;

forming a control gate overlying the bit storage region;

forming a metal layer covering the control grid; and

forming an opening through the metal layer, wherein the opening overlies at least a portion of the bit storage region and also overlies a first portion of the control gate, and wherein the metal layer overlies a second portion of the control gate.

5. The method of claim 4, wherein forming the metal layer overlying the control gate comprises: forming the metal layer to cover the whole EEPROM unit cell which is not positioned under the opening.

6. The method of claim 4, wherein the step of forming the opening comprises:

the opening is formed to extend beyond an outer edge of the bit storage region but not beyond an outer edge of the control gate.

7. The method of claim 6, wherein forming the opening to extend beyond an outer edge of the bit storage region but not beyond an outer edge of the control gate comprises: the opening is formed such that the metal layer overlaps the control gate by a distance not less than a wavelength of visible light.

8. The method of claim 4, the step of forming the opening comprising: the opening is formed to cover at least 20% of a surface area of the bit storage region.

9. A method for forming an EEPROM cell of a semiconductor device, the method comprising the steps of:

providing a semiconductor substrate;

forming a channel region of a first MOS transistor on the semiconductor substrate;

forming a floating gate having a gate electrode overlying at least a portion of a channel region of the first MOS transistor, including forming a bit storage region of the floating gate having an outer edge;

forming a control gate overlying at least a portion of the floating gate; and

forming a metal layer having an opening through the metal layer includes forming the metal layer to overlie the first portion of the control gate and forming the opening to overlie the second portion of the control gate and overlie at least a portion of the bit storage region.

10. The method of claim 9, further comprising the steps of: forming a channel region of a second MOS transistor on the semiconductor substrate, and forming another gate electrode of the floating gate to overlie at least a portion of the channel region of the second MOS transistor.