HK1144125B - Semiconductor device having trench shield electrode structure - Google Patents

Description

Semiconductor device having trench shield electrode structure

Cross Reference to Related Applications

This application relates to an application entitled "CONTACT STRUCTURE for electronic device DEVICE HAVING TRENCH live electronic device AND METHOD" having the filing number ONS01163F1, having a common assignee AND common inventor, which application is filed concurrently herewith.

This application relates to an application entitled "TRENCH SHIELDING STRUCTURE FOR USE WITH MICRONICOTDUCTOR DEVICE AND METHOD" having the filing number ONS01163F3, having a common assignee and a common inventor, which is filed concurrently herewith.

Technical Field

This document relates generally to semiconductor devices and, more particularly, to insulated gate structures and methods of forming.

Background

Metal oxide field effect transistor (MOSFET) devices are used in many power conversion applications, such as dc-dc converters. In a typical MOSFET, the gate electrode provides the application of an appropriate gate voltage for turn-on and turn-off control. As an example, in an n-type enhancement mode MOSFET, turn-on occurs when a conducting n-type inversion layer (i.e., channel region) is formed in a p-type body region in response to application of a positive gate voltage that exceeds an intrinsic threshold voltage. The inversion layer connects the n-type source region to the n-type drain region and allows majority carrier conduction between these regions.

There is a class of MOSFET devices in which the gate electrode is formed in a trench extending downwardly from a major surface of a semiconductor material, such as silicon. The current in such devices is primarily vertical and as a result, the device cells may be more tightly packed. All else being equal, this increases the current carrying capacity and reduces the on-resistance of the device.

In some applications, high frequency switching characteristics are important, and certain design techniques are used to reduce capacitive effects, thereby improving switching performance. As an example, it is previously known to incorporate an additional electrode below the gate electrode in a trench MOSFET device and to connect this additional electrode to the source electrode or another biased source. This additional electrode is often referred to as a "shield electrode" and functions, inter alia, to reduce the gate-to-drain capacitance. Shield electrodes have also previously been used in planar MOSFET devices.

While shielding electrodes improve device performance, challenges still exist to more efficiently integrate them with other device structures. These challenges include avoiding additional masking steps, handling non-planar conditions, and avoiding additional consumption of die area. These challenges affect cost and manufacturability, among others. Furthermore, there is an opportunity to provide a device with a shielding electrode having an optimal and more reliable performance.

Accordingly, structures and fabrication methods are needed to effectively integrate shield electrode structures with other device structures and to provide optimal and more reliable performance.

Drawings

FIG. 1 illustrates a partial cross-sectional view of a first embodiment of a semiconductor structure taken along reference line I-I of FIG. 2;

FIG. 2 illustrates a top plan view of a first embodiment of a semiconductor device including the structure of FIG. 1;

FIG. 3 illustrates a top plan view of a second embodiment of a semiconductor device;

fig. 4 illustrates a partial cross-sectional view of a portion of the semiconductor device of fig. 2 taken along reference line IV-IV;

FIGS. 5-16 show partial cross-sectional views of the portion of FIG. 4 at various stages of manufacture;

FIG. 17 shows a partial top plan view of a contact structure according to a first embodiment;

FIG. 18 shows a partial top plan view of a contact structure according to a second embodiment;

FIG. 19 shows a partial top plan view of a contact structure according to a third embodiment;

fig. 20 illustrates a partial top plan view of the semiconductor device of fig. 2 including a first embodiment of a shield structure;

FIG. 21 shows a cross-sectional view of the shielding structure of FIG. 20 taken along reference line XXI-XXI;

fig. 22 illustrates a partial top plan view of the semiconductor device of fig. 2 including a second embodiment of a shield structure;

fig. 23 illustrates a partial top plan view of the semiconductor device of fig. 2 including a third embodiment of a shield structure;

fig. 24 illustrates a partial top plan view of a portion of the semiconductor device of fig. 2; and

fig. 25 illustrates a cross-sectional view of another embodiment of a semiconductor device.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures generally identify the same elements. Moreover, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device, such as the source or drain of a MOS transistor, or the collector or emitter of a bipolar transistor, or the cathode or anode of a diode; and the control electrode represents an element of the device that controls the current through the device, such as the gate of a MOS transistor or the base of a bipolar transistor. Although these devices are explained herein as certain N-channel devices, one of ordinary skill in the art will recognize that P-channel devices or complementary devices are also possible in accordance with the present invention. For clarity of the drawings, the doped regions of the device structure are shown as having generally straight edges and precisely angled corners. However, it will be appreciated by those skilled in the art that the edges of the doped regions are generally not straight lines due to diffusion and activation of the dopants, and the corners may not be precise corners.

Furthermore, the structures of the present description may embody a cellular base design (where the body region is a plurality of distinct and separate cellular or ribbon regions) or a single base design (single base design) (where the body region is a single region formed in an elongated pattern, typically in a serpentine pattern or a central portion with attached appendages). However, for ease of understanding, one embodiment of the present description is described throughout the specification as a cellular infrastructure design. It should be understood that the present disclosure is intended to include both cellular infrastructure designs and single infrastructure designs.

Detailed Description

In general, the present description relates to semiconductor device configurations having multiple control electrodes and multiple shield electrodes. The plurality of control electrodes are connected together using a control contact structure, a control pad, and a control runner (control runner). The plurality of shield electrodes are connected together using a shield electrode runner (shield electrode runner). In one embodiment, this configuration utilizes a single metal layer to achieve various connections and places the shield electrode contacts in a location offset from the central portion of the device.

Fig. 1 shows a partial cross-sectional view of a semiconductor device or cell 10 having a shielding electrode 21. The cross-section is taken, for example, along reference line I-I from active region 204 of device 20 shown in fig. 2. In this embodiment, the device 10 comprises a MOSFET structure, but it should be understood that the description also applies to Insulated Gate Bipolar Transistors (IGBTs), MOS-gated thyristors, etc.

Device 10 includes a region of semiconductor material, or semiconductor region 11 including, for example, a resistance having a range from about 0.001ohm-cm to about 0.005ohm-cmA coefficient n-type silicon substrate 12. Substrate 12 may be doped with phosphorus or arsenic. In the illustrated embodiment, substrate 12 provides a drain contact or first current carrying contact for device 10. A semiconductor layer, drift region or extended drain region 14 is formed in or on the substrate 12 or overlying the substrate 12. In one embodiment, semiconductor layer 14 is formed using conventional epitaxial growth techniques. Alternatively, semiconductor layer 14 is formed using conventional doping and diffusion techniques. In an embodiment suitable for a 50 volt device, semiconductor layer 14 is of about 1.0x10¹⁶Atom/cm³And has a thickness of from about 3 microns to about 5 microns. The thickness and dopant concentration of semiconductor layer 14 depends on the desired drain-to-source Breakdown Voltage (BV) of device 10_DSS) The rate is increased or decreased. It should be understood that other materials may be used for the semiconductor material 11 or portions thereof including silicon germanium, silicon germanium carbon, carbon doped silicon, silicon carbide, and the like. Furthermore, in an alternative embodiment, the conductivity type of substrate 12 is switched to be opposite to the conductivity type of semiconductor layer 14 to form, for example, an IGBT embodiment.

Device 10 also includes a body, bottom, PHV, or doped region 31 extending from major surface 18 of semiconductor material 11. Body region 31 has a conductivity type opposite to that of semiconductor layer 14. In this example, body region 31 is of p-type conductivity. Body region 31 has a dopant concentration suitable for forming an inversion layer that operates as a conduction channel or channel region 45 of device 10. Body region 31 extends from major surface 18 to a depth of, for example, from about 0.5 microns to about 2.0 microns. An n-type source, current conducting, or current carrying region 33 is formed in or in body region 31 or overlying body region 31 and extends from major surface 18 to a depth of, for example, from about 0.1 microns to about 0.5 microns. A p-type body contact or contact region 36 may be formed in body region 31 and configured to provide a lower contact resistance to body region 31.

The device 10 further comprises a trench control, trench gate or trench structure 19 extending in a substantially vertical direction from the main surface 18. Optionally, the slot control structure 19 or a portion thereof has a tapered shape. Trench structure 19 includes a trench 22 formed in semiconductor layer 14. For example, trenches 22 have a depth of from about 1.5 microns to about 2.5 microns or more. In one embodiment, trench 22 extends all the way through semiconductor layer 14 into substrate 12. In another embodiment, trench 22 terminates within semiconductor layer 14.

A passive layer, insulating layer, field insulating layer or region 24 is formed on the lower portion of the trenches 22 and comprises, for example, oxide, nitride, combinations thereof, and the like. In one embodiment, insulating layer 24 is silicon oxide and has a thickness of from about 0.1 microns to about 0.2 microns. The insulating layer 24 may be uniform in thickness or of variable thickness. In addition, the thickness of layer 24 may be based on the desired drain-to-source Breakdown Voltage (BV)_DSS) And (4) changing. A shield electrode 21 is formed overlying the insulating layer 24 in a substantially centrally located lower portion of the trench 22. In one embodiment, shield electrode 21 comprises a polycrystalline semiconductor material that may be doped. In another embodiment, shield electrode 21 may comprise other conductive materials. In the contact structure embodiments described below, the portion of the trench 22 in the contact structure region has an insulating layer 24 also along the upper sidewall portion.

A passive, dielectric or insulating layer 26 is formed along the upper sidewall portions of trenches 22 and is configured as a gate dielectric region or layer. By way of example, the insulating layer 26 includes an oxide, nitride, tantalum pentoxide, titanium dioxide, barium strontium titanate, combinations thereof, and the like. In one embodiment, insulating layer 26 is silicon oxide and has a thickness of from about 0.01 microns to about 0.1 microns. In one embodiment, insulating layer 24 is thicker than insulating layer 26. A passive, dielectric or insulating layer 27 is formed overlying shield electrode 21 and, in one embodiment, insulating layer 27 has a thickness between the thicknesses of insulating layer 24 and insulating layer 26. In one embodiment, insulating layer 27 has a thickness greater than the thickness of insulating layer 26, which improves oxide breakdown voltage performance.

Trench structure 19 further includes a control or gate electrode 28 formed overlying insulating layers 26 and 27. In one embodiment, gate electrode 28 comprises a doped polycrystalline semiconductor material, such as polysilicon doped with an n-type dopant. In one embodiment, trench structure 19 further includes a metal or silicide layer 29 formed adjacent to gate electrode 28 or an upper surface thereof. Layer 29 is configured to reduce gate resistance.

An interlayer dielectric (ILD), dielectric, insulating or passive layer 41 is formed overlying major surface 18 and above trench structures 19. In one embodiment, dielectric layer 41 comprises silicon oxide and has a thickness of from about 0.4 microns to about 1.0 microns. In one embodiment, dielectric layer 41 comprises a deposited silicon oxide doped with phosphorus or boron and phosphorus. In one embodiment, dielectric layer 41 is planarized to provide a more uniform surface condition, which improves manufacturability.

Conductive regions or plugs 43 are formed through openings or vias in dielectric layer 41 and portions of semiconductor layer 14 to provide electrical contact to source regions 33 and body regions 31 through contact regions 36. In one embodiment, conductive region 43 is a conductive plug or plug structure. In one embodiment, conductive region 43 comprises a conductive barrier structure or a liner plus a conductive fill material. In one embodiment, the barrier structure comprises a metal/metal nitride configuration, such as titanium/titanium nitride or the like. In another embodiment, the barrier structure further comprises a metal silicide structure. In one embodiment, the conductive fill material comprises tungsten. In one embodiment, conductive regions 43 are planarized to provide a more uniform surface condition.

Conductive layer 44 is formed overlying major surface 18 and conductive layer 46 is formed overlying a surface of semiconductor material 11 opposite major surface 18. Conductive layers 44 and 46 are configured to provide electrical connections between the various device components of device 10 and the next level of assembly. In one embodiment, conductive layer 44 is titanium/titanium nitride/aluminum copper or the like and is configured as a source electrode or terminal. In one embodiment, conductive layer 46 is a solderable metal structure such as titanium nickel silver, chromium nickel gold, or the like, and is configured as a drain electrode or terminal. In one embodiment, another passive layer (not shown) is formed overlying conductive layer 44. In one embodiment, shield electrode 21 is connected (in another plane) to conductive layer 44 such that shield electrode 21 is configured to be at the same potential as source region 33 when device 10 is in use. In another embodiment, shield electrodes 21 are configured to be independently biased.

In one embodiment, operation of device 10 proceeds as follows. Assume that the source electrode (or input terminal) 44 and the shielding electrode 21 are at a potential V of zero volts_SIn operation, gate electrode 28 receives a control voltage V of 2.5 volts greater than the conduction threshold of device 10_GAnd the drain electrode (or output terminal) 46 is at a drain potential V of 5.0 volts_DThe following operations are carried out. V_GAnd V_SIs such that body region 31 inverts adjacent gate electrode 28 to form channel 45, which electrically connects source region 33 to semiconductor layer 14. Device current I_DSFlows from drain electrode 46 and through source region 33, channel 45, and semiconductor layer 14 to source electrode 44. In one embodiment, I_DSApproximately 1.0 ampere. To transition device 10 to the off state, a control voltage V that is less than the conduction threshold of device 10_GIs applied to the gate electrode 28 (e.g., V)_G< 2.5 volts). This removes the trench 45, and I_DSNo longer through device 10.

Shield electrode 21 is configured to control the width of the depletion layer between body region 31 and semiconductor layer 14, which increases the source-to-drain breakdown voltage. In addition, shield electrode 21 helps reduce the gate-to-drain charge of device 10. In addition, the gate-to-drain capacitance of device 10 is reduced because there is less overlap of gate electrode 28 with semiconductor layer 14 than with other structures. These features enhance the switching characteristics of device 10.

Fig. 2 illustrates a top plan view of a semiconductor device, die, or die 20 that includes device 10 of fig. 1. For perspective, fig. 2 is generally looking down at major surface 18 of semiconductor material 11 shown in fig. 1. In this embodiment, device 20 is bounded by die edge 51, which when in wafer form, may be the center of a scribe line used to separate die 20 from other devices. Device 20 includes a control pad, gate metal pad, or gate pad 52 configured to electrically contact gate electrode 28 (shown in fig. 1) through gate metal runners or feed slots 53, 54, and 56. In this embodiment, gate metal pad 52 is placed in corner portion 238 of device 20. In one embodiment, gate runner 54 is adjacent to edge 202 of device 20, and gate runner 56 is adjacent to another edge 201 of device 20, edge 201 being opposite edge 202. In one embodiment, slot 22 extends in a direction from edge 201 to edge 202. In one embodiment, the central portion 203 of the device 20 is devoid of any gate runners. That is, in one embodiment, the gate runners are placed only in a peripheral or edge portion of device 20.

Conductive layer 44, which in this embodiment is configured as a source metal layer, is formed over active portions 204 and 206 of device 20. In one embodiment, portion 444 of conductive layer 44 wraps around end portion 541 of gate runner 54. Portion 446 of conductive layer 44 wraps around end portion 561 of gate runner 56 and is represented as structure 239. Structure 239 is further shown in more detail in fig. 24. Conductive layer 44 is further configured to form shield electrode contacts, runners or feed slots 64 and 66, which in this embodiment provide contact with shield electrode 21. In this configuration, conductive layer 44 is connected to shield electrode 21. In the wrap-around configuration described above, conductive layer 44, portions 444 and 446, shield electrode runners 64 and 66, and gate runners 54 and 56 are in the same plane and do not overlap one another. This configuration provides for the use of a single metal layer, which simplifies manufacturing.

In one embodiment, shield electrode runner 66 is placed between edge 201 of device 20 and gate runner 56, and shield electrode runner 64 is placed between edge 202 of device 20 and gate runner 54. In one embodiment, additional contacts to shield electrode 21 are made in shield contact region, contact region or strip 67, which divides the active region of device 20 into portions 204 and 206. Contact region 67 is another location on device 20 where contact between conductive layer 44 and shield electrode 21 is made. Contact region 67 is configured to divide gate electrode 28 into two portions within device 20. These two portions include one portion provided from gate runner 54 and the other portion provided from gate runner 56. In this configuration, gate electrode material 28 lacks contact region 67. That is, gate electrode 28 does not pass through contact region 67.

In embodiments where gate pad 52 is placed in a corner of device 20 (e.g., corner 23), the effects of gate resistance may be optimally distributed throughout a selected or predetermined arrangement of contact regions 67 within device 20. This predetermined arrangement provides a more uniform switching characteristic. In one embodiment, contact region 67 is offset from center 203 such that contact region 67 is closer to edge 202 than edge 201, and gate pad 52 is located in a corner portion 238 adjacent to edge 201. That is, contact region 67 is placed closer to the edge opposite the corner and edge where gate pad 52 is placed. This configuration reduces the length of gate electrode 28 in active region 206 and increases the length of gate electrode 28 in active region 204, which provides a more efficient distribution of the gate resistive load.

In one embodiment, contact region 67 is placed in an offset position on device 20 to reduce the gate resistance in active region 206 by approximately one-half the resistance of gate runner 53 and to increase the gate resistance in active region 204 by approximately one-half the resistance of gate runner 53. In this embodiment, the gate resistance of the active region 206 is given by:

2Rg_FET206+R₅₃-(R₅₃/2)

wherein Rg_FET206Is the resistance of gate electrode 28 in active region 206 when contact region 67 is placed in the center of device 20, and R₅₃Is the resistance of metal runner 53. The gate resistance of active region 204 is given by:

2Rg_FET204+R₅₃/2

wherein Rg_FET204Is the resistance of gate electrode 28 in active region 204 when contact region 67 is placed in the center of device 20. This is the contact area 6 which optimizes the distribution of the gate resistance7.

In another embodiment, shield contact region 67 is the only shield contact used to make contact to shield electrode 21 and is placed in an interior portion of device 20. That is, in this embodiment, the shield electrode runners 64 and 66 are not used. This embodiment is suitable, for example, when the switching speed is not important, but where the resurf effect of the shielding electrode is desired. In one embodiment, shield contact region 67 is disposed in the center of device 20. In another embodiment, shield contact region 67 is placed off-center from device 20. In these embodiments, shield contact region 67 provides contact with shield electrode 21 in or inside trench 22, while control electrode runners 54 and 56 make contact with control electrode 28 in or inside trench 22 near edges 201 and 202. This embodiment further saves space within the device 20. In another embodiment, control electrode 28 extends over and overlaps major surface 18, and control electrode runners 54 and 56 make contact with the control electrode outside of slot 22.

Fig. 3 is a top view of another embodiment of a semiconductor device, die or die 30. In this embodiment, similar to device 20, gate pad 52 is disposed in corner portion 238 of device 30. Device 30 is similar to device 20 except that gate runners 54 and 56 are configured to reduce the left-to-right disparity in gate resistance. In one embodiment, gate runner 56 opens to, connects to, or links to additional gate runner 560 at a substantially central location 562. Gate runner 560 is then connected to gate electrode 28 (shown in fig. 1) in active region 204. In another embodiment, gate runner 54 opens to, connects to, or links to gate runner 540 at a substantially central location 542. Gate runner 540 is then connected to gate electrode 28 (shown in fig. 1) in active region 206. It should be understood that one or both of gate runners 54 and 56 can be configured in this manner. Furthermore, shield contact region 67, if used, may be offset in device 30 as shown in fig. 2. In one embodiment, shield electrode runner 66 is positioned between gate runners 56 and 560 and edge 201, and shield electrode runner 64 is positioned between gate runners 54 and 540 and edge 202. The gate runner configuration of fig. 3 may also be used in devices that do not include shield electrodes to reduce the left-to-right disparity in gate resistance.

Fig. 4 illustrates an enlarged cross-sectional view of a gate/shield electrode contact structure, connection structure, or contact structure or region 40 taken along reference line IV-IV in fig. 2. In general, structure 40 is a contact region that creates contact between gate electrode 28 and gate runners 54 and 56, and between shield electrode 21 and shield electrode runners 64 and 66. In previously known gate/shield electrode contact structures, a double stack (doublestack) of polysilicon or other conductive material is placed on top of the major surface of the substrate in the peripheral or field region of the device to enable contact to be made. Such a double stack of materials may increase the surface condition by a thickness of more than 1.2 microns. The dual stacking of materials on the major surfaces creates problems including non-planar topography that affects subsequent lithography steps and manufacturability. These previously known structures also increase grain size.

Structure 40 is configured to address, among other things, the dual polysilicon stack problem of previously known devices. In particular, upper surface 210 of shield electrode 21 and upper surface 280 of gate electrode 28 are both recessed below major surface 18 of semiconductor material 11 to create contact with shield electrode 21 and gate electrode 28 within or directly within trenches 22. That is, in one embodiment, gate electrode 28 and shield electrode 21 do not overlap or extend over major surface 18. Conductive structure 431 connects gate runner 56 to gate electrode 28 and conductive structure 432 connects shield electrode runner 66 to shield electrode 21. Conductive structures 431 and 432 are similar to conductive structure 43 described in connection with fig. 1. Structure 40 uses planarized dielectric layer 41 and planarized conductive structures 431 and 432 to provide a flatter topography. The structure enables sub-micron lithography and global planarization in power device technology. Further, this configuration enables portion 444 of conductive layer 44 to wrap around end portion 541 of gate runner 54 (as shown in FIG. 2), and portion 446 to wrap around end portion 561 of gate runner 56 (as shown in FIG. 2), and does so without consuming too much die area.

In another embodiment, shield electrode 21 overlaps major surface 18 and contact is made there with shield electrode 21 while gate electrode 28 remains within trench 22 without overlapping upper surface 210 of shield layer 21 or major surface 18 and contact is made with gate electrode 28 within or on trench 22. This embodiment is shown in fig. 25, where fig. 25 is a cross-sectional view of structure 401, structure 401 being similar to structure 40 except that shield electrode 21 overlaps major surface 18, as described above. In this embodiment, shield electrode 21 and conductive layer 44 are wrapped around end portions 541 and 561 (shown in FIG. 2), and source metal 44 makes contact to shield electrode 21 through an opening in dielectric layer 41.

Another feature of structure 40 is insulating layers 24 and 27, which are thicker than insulating layer 26 (shown in fig. 1), even surrounding shielding electrode 21 too much where shielding electrode 21 is proximate major surface 18. In previously known structures, a thinner gate oxide separates the gate electrode from the shield electrode in the field or peripheral region. In previously known structures, the oxide was thinner at the top surface to trench interface creating two gate shield routing lines. However, such structures with thinned gate or shield oxide are susceptible to oxide breakdown and device failure. Structure 40 reduces this susceptibility by using thicker insulating layers 24 and 27. This feature is further illustrated in fig. 17-18.

Turning now to fig. 5-16 as partial cross-sectional views, a method of fabricating the structure 40 of fig. 4 is described. It should be understood that the processing steps used to form structure 40 may be the same steps used to form device 10 of fig. 1 and the shielding structures described in fig. 20-23. Fig. 5 shows structure 40 at an early manufacturing step. Dielectric layer 71 is formed on major surface 18 of semiconductor material 11. In one embodiment, dielectric layer 71 is an oxide layer, such as low temperature deposited silicon oxide, and has a thickness from about 0.25 microns to about 0.4 microns. Next, a masking layer, such as a patterned photoresist layer 72, is formed on dielectric layer 71, and then dielectric layer 71 is patterned to provide openings 73. In this embodiment, the opening 73 corresponds to one of many slot openings for forming the slot 22. The unmasked portions of dielectric layer 71 are then removed using conventional techniques, and then layer 72 is removed.

Fig. 6 shows structure 40 after one of trenches 22 is etched into semiconductor layer 14. For perspective, this view is parallel to the direction in which slot 22 extends over devices 20 and 30. That is, in fig. 6, the groove 22 extends from left to right. By way of example, the trenches 22 are etched using a plasma etching technique having a fluorocarbon chemistry. In one embodiment, trenches 22 have a depth of about 2.5 microns, and a portion of dielectric layer 71 is removed during the process used to form trenches 22. In one embodiment, trenches 22 have a width of about 0.4 microns and may be tapered or flared to 0.6 microns, with conductive structures 431 and 432 formed therein, for example, to electrically connect gate electrode 28 and shield electrode 21 to gate runner 54 or 56 and shield electrode runner 56 or 66, respectively. The surfaces of the grooves 22 may be cleaned after their formation using conventional techniques.

Fig. 7 shows structure 40 after additional processing. A sacrificial oxide layer having a thickness of about 0.1 microns is formed overlying the surfaces of trenches 22. The process is configured to provide a thicker oxide towards the top of the trench 22 compared to the lower portion of the trench 22, which arranges a ramp in the trench. This process also removes the damage and curves along the lower surface of the groove 22. The sacrificial oxide layer and dielectric layer 71 are then removed. An insulating layer 24 is then formed on the surface of the trenches 22. By way of example, insulating layer 24 is silicon oxide and has a thickness of from about 0.1 microns to about 0.2 microns. A layer of polycrystalline semiconductor material is then deposited overlying major surface 18 and within trenches 22. In one embodiment, the polycrystalline semiconductor material comprises polysilicon and is doped with phosphorus. In one embodiment, the polysilicon has a thickness from about 0.45 microns to about 0.5 microns. In one embodiment, the polysilicon is annealed at an elevated temperature to reduce or eliminate any voids. The polysilicon is then planarized to form region 215. In one embodiment, the polysilicon is planarized using a chemical mechanical planarization process that is preferentially selective to polysilicon. Region 215 is planarized to a portion 245 of insulating layer 24, insulating layer 24 configured as a barrier layer.

Fig. 8 shows structure 40 after subsequent processing. A masking layer (not shown) is formed overlying structure 40 and patterned to protect those portions of region 215 that will not be etched, such as portion 217. The exposed portions of region 215 are then etched so that the etched portions are recessed below major surface 18 to form shield electrode 21. In one embodiment, region 215 is etched to about 0.8 microns below major surface 18. In one embodiment, a selective isotropic etch is used for this step. The isotropic etch further provides a rounded portion 216 in which shield electrode 21 transitions into portion 217, portion 217 extending upward toward major surface 18. This step further removes polycrystalline semiconductor material from the exposed portions of the upper surface of trenches 22. Any remaining masking material may then be removed. In one embodiment, portion 245 of insulating layer 24 is exposed to an etchant to reduce its thickness. In one embodiment, about 0.05 microns are removed. Next, additional polycrystalline material is removed from shield electrode 21 such that upper surface 210 of shield electrode 21, including portion 217, is recessed below major surface 18, as shown in FIG. 9. In one embodiment, approximately 0.15 microns of material is removed.

Fig. 10 shows structure 40 after further processing. A portion of insulating layer 24 is removed with portion 217 of shield electrode 21 recessed. This forms an oxide stub structure 247 that is configured to reduce stress effects during subsequent processing steps. After the oxide stub structures 247 are formed, an oxide layer (not shown) is formed overlying the upper surfaces of shield electrodes 21 and trenches 22. In one embodiment, a thermal silicon oxide growth process is used that grows a thicker oxide overlying shield electrode 21 because shield electrode 21 is a polycrystalline material and a thinner oxide along the exposed sidewalls of trenches 22 because these sidewalls are substantially single crystal semiconductor material. In one embodiment, silicon oxide is grown and has a thickness of about 0.05 microns on the sidewalls of trenches 22. This oxide helps to smooth the upper surface of shield electrode 21. The oxide is then removed from the sidewalls of trenches 22 while leaving a portion of the oxide overlying shield electrode 21. Next, an insulating layer 26 is formed covering the upper side walls of the trenches 22, which also increases the thickness of the dielectric material that has been formed on the shield electrode 21 or on the shield electrode 21 to form an insulating layer 27 thereon. In one embodiment, silicon oxide is grown to form insulating layers 26 and 27. In one embodiment, insulating layer 26 has a thickness of about 0.05 microns and insulating layer 27 has a thickness greater than about 0.1 microns.

Fig. 11 illustrates structure 40 after formation of polycrystalline semiconductor material overlying major surface 18. In one embodiment, doped polysilicon is used, with phosphorus being a suitable dopant. In one embodiment, about 0.5 microns of polysilicon is deposited overlying major surface 18. In one embodiment, the polysilicon is then annealed at an elevated temperature to remove any voids. Any surface oxide is then removed using conventional techniques and the polysilicon is then planarized to form gate electrode 28. In one embodiment, an oxide overlies major surface 18 using chemical mechanical planarization to provide a barrier layer.

Gate electrode 28 is then subjected to an etching process to recess upper surface 280 below major surface 18, as shown in fig. 12. In one embodiment, a dry etch is used to recess the upper surface 280 with a chemistry selected relative to polysilicon and silicon oxide. In one embodiment, chlorine chemistry, bromine chemistry, or a mixture of both chemistries is used for this step. It is convenient to use this etching step to remove the polycrystalline semiconductor from the oxide layer on surface 210 of portion 217 so that when a silicide layer is used on gate electrode 28, it does not form on surface 210, which would complicate the contacting of shield electrode 21 in subsequent processing steps.

Fig. 13 shows structure 40 after formation of silicide layer 29 overlying surface 280. In one embodiment, silicide layer 29 is titanium. In another embodiment, the silicide layer 29 is cobalt. In a further embodiment, a self-aligned silicide (salicide) process is used to form layer 29. For example, in a first step, any residual oxide is removed from major surface 280. Titanium or cobalt is then deposited overlying structure 40. Next, a low temperature rapid thermal step (approximately 650 degrees celsius) is used to react the metal and the exposed polycrystalline semiconductor material. Structure 40 is then etched in a selective etchant to remove only the unreacted titanium or cobalt. A second rapid thermal step at high temperature (greater than about 750 degrees celsius) is then used to stabilize the film and lower its resistivity to form layer 29.

In the next sequence of steps, an ILD 41 is formed overlying structure 40, as shown in fig. 14. In one embodiment, atmospheric pressure chemical vapor deposition is used to deposit about 0.5 microns of phosphorous doped silicon oxide. Next, a plasma enhanced chemical vapor deposition oxide based on approximately 0.5 micron silane was formed on the phosphorus doped oxide. The oxide layer is then planarized back to a final thickness of about 0.7 microns using, for example, a chemical mechanical planarization to form ILD 41. In fig. 14, insulating layer 27 and stub 247 are shown no longer within ILD 41 because they both comprise oxide in this embodiment, but it is understood that they may be present in the final structure.

Fig. 15 shows structure 40 after trench openings 151 and 152 have been formed in ILD 41 to expose a portion of silicide layer 29 and shield electrode 21. Conventional photolithography and etching steps are used to form openings 151 and 152. The exposed portion of shield electrode 21 is then further etched to recess portions of portion 217 below surface 210.

Next, conductive structures or plugs 431 and 432 are formed within openings 151 and 152, respectively, as shown in fig. 16. In one embodiment, conductive structures 431 and 432 are titanium/titanium nitride/tungsten plug structures and are formed using conventional techniques. In one embodiment, conductive structures 431 and 432 are planarized using, for example, chemical mechanical planarization, so the upper surfaces of ILD 41 and conductive structures 431 and 432 are more uniform. Thereafter, a conductive layer is formed overlying structure 40 and patterned to form conductive gate runner 56, shield electrode runner 66, and source metal layer 44, as shown in fig. 4. In one embodiment, conductive layer 44 is titanium/titanium nitride/aluminum copper or the like. A feature of this embodiment is that the same conductive layers are used to form source electrode 44, gate runners 54 and 65, and shield electrodes 56 and 66, as shown in fig. 2. In addition, conductive layer 46 is formed adjacent to substrate 12, as shown in FIG. 4. In one embodiment, conductive layer 46 is a solderable metal structure such as titanium nickel silver, chromium nickel gold, or the like.

Fig. 17 is a partial top plan view of a contact or connection structure 170 according to a first embodiment, the contact or connection structure 170 being configured to provide a contact structure for making contact with the gate electrode 28 and the shield electrode 21 within or inside the trenches 22. That is, structure 170 is configured such that conductive contact to gate electrode 28 and shield electrode 21 may be made within or within trenches 22. For perspective, connection structure 170 is one embodiment of a top view of structure 40 without conductive gate runner 56, shield electrode runner 66, conductive structures 431 and 432, and ILD 41. This view also shows the insulating layer 26 adjacent to the gate electrode 28, as shown in fig. 1. Furthermore, this view shows one advantage of this embodiment. In particular, shield electrode 21 in connection structure 170 is surrounded by insulating layers 24 and 27, which are thicker than insulating layer 26. This feature reduces the oxide breakdown problem of previously known structures, which provides a more reliable device. In this embodiment, structure 170 is strip-like in shape and makes contact to gate electrode 28 and shield electrode 21 within wider or flared portion 171. The structure 170 then tapers to a narrower portion 172 as the structure 170 approaches, for example, the active region of the device. As shown in fig. 17, the gate electrode 28 has a width 174 in the flared portion 171 that is wider than a width 176 of the shield electrode 21 within the flared portion 171. In this embodiment, end portion 173 of trench 22 terminates in shield electrode 21, shield electrode 21 being surrounded by insulating layers 24 and 27 that are thicker than insulating layer or gate dielectric layer 26. In one embodiment, end portion 173 is adjacent or proximate to edge 201 or edge 202 of device 20 or device 30 shown in fig. 2 and 3.

Fig. 18 is a partial top plan view of a contact connection structure 180 according to a second embodiment, the contact connection structure 180 being configured to provide a contact structure for making contact with the gate electrode 28 and the shield electrode 21 within or inside the trenches 22. That is, structure 180 is configured such that conductive contact to gate electrode 28 and shield electrode 21 may be made within or within trenches 22. In this embodiment, the structure 180 includes a thin strip portion 221 and a flared portion 222 that is wider than the strip portion 221. In this embodiment, the flared portion 222 provides a wider contact portion for making contact with the shielding electrode 21. The structure 180 further comprises another separate flared portion 223 wider than the strip portion 221 for making contact with the gate electrode 28. Like structure 170, shield electrode 21 is surrounded by insulating layers 24 and 27, which are thicker than insulating layer 26. In one embodiment, the shield electrode 21 includes a narrow portion 211 within the strip portion 221 and a wider portion 212 within the flared portion 222. In this embodiment, the insulating layer 24 is within the flared portion 222 and extends further into the thin strip portion 221. In this embodiment, the insulating layer 26 is only within the thin strip portion 221 and the flared portion 223. In this embodiment, end portion 183 of slot 22 terminates in shield electrode 21, shield electrode 21 being surrounded by thicker insulating layers 24 and 27. In one embodiment, end portion 183 is adjacent or proximate to edge 201 or edge 202 of device 20 or device 30 shown in fig. 2 and 3.

Fig. 19 is a partial top plan view of a contact or connection structure 190 according to a third embodiment, the contact or connection structure 190 being configured to provide a contact structure for making contact with the gate electrode 28 and the shield electrode 21 within or inside the trenches 22. That is, structure 90 is configured such that conductive contact to gate electrode 28 and shield electrode 21 may be made within or within trenches 22. In this embodiment, the slot 22 includes a thin strip portion 224 and a flared portion 226 that is wider than the strip portion 224. In this embodiment, flared portion 226 provides a wider contact portion for making contact with gate electrode 28 and shield electrode 21. Shield electrode 21 is surrounded by insulating layers 24 and 27, which are thicker than insulating layer 26. In one embodiment, gate electrode 28 includes a narrow portion 286 within strip portion 224 and a wider portion 287 within flared portion 226. In this embodiment, insulating layer 26 is within thin strip portion 224 and extends further into flared portion 226. In this embodiment, the thicker insulating layers 24 and 27 are only within the flared portions 224. In one embodiment, shield electrode 21 is only in flared portion 226. It is understood that combinations of structures 170, 180, and 190 or structures 170, 180, and 190 alone may be used in structure 40 with devices 20 and 30. In this embodiment, the end portion 193 of the trench 22 terminates in a shield electrode 21, the shield electrode 21 being surrounded by thicker insulating layers 24 and 27. In one embodiment, end portion 193 is adjacent to or proximate to edge 201 or edge 202 of device 20 or device 30 shown in fig. 2 and 3.

Turning now to fig. 20-23, various shield structure embodiments are described. Fig. 20 shows a partial top plan view of a slot shield structure 261 according to a first embodiment. Shielding structure 261 is suitable for use on, for example, devices 20 and 30 and is conveniently formed using the processing steps used to form device or cell 10 and structure 40 described previously. Shield structure 261 is an embodiment of a shield structure that extends at least partially under or below gate pad 52 to better isolate or insulate gate pad 52 from semiconductor layer 14. Structure 261 includes a plurality of trenches 229 formed at least partially under gate pad 52. Slots 229 are conveniently formed simultaneously with slots 22. Portions of trenches 229 are shown in phantom to illustrate that they are under gate pad 52 and shield electrode runner 66.

Fig. 21 is a partial cross-sectional view of structure 261 taken along reference line XXI-XXI of fig. 20, as further shown in fig. 21, in structure 261 trenches 229 each line up insulating layer 24 and include shield electrodes 21. In one embodiment of structure 261, however, trenches 229 do not contain any gate electrode material 28. That is, in this embodiment, structure 261 does not include any gate or control electrodes. As shown in fig. 20, shield electrode 21 is connected to shield electrode runner 66, and in one embodiment is electrically connected to source metal 44. In another feature of this embodiment, ILD 41 separates shield electrode 21 from gate pad 52 without other intervening polycrystalline or other conductive layers overlying major surface 18 between gate pad 52 and structure 261. That is, structure 261 is configured to better isolate gate pad 52 from semiconductor region 11 without adding more shielding layers overlying the major surface, as used in previously known devices. This configuration helps to reduce the gate-to-drain capacitance and does so without additional masking and/or processing steps. In one embodiment, in structure 261, the spacing 88 between adjacent slots 229 is less than about 0.3 microns. In another embodiment, the spacing 88 is less than half the depth 89 (shown in FIG. 21) of the slots 22 to provide optimal shielding. In one embodiment, a spacing 88 of about 0.3 microns has been found to provide about a 15% reduction in gate-to-drain capacitance compared to a spacing 88 of 1.5 microns. In one embodiment of structure 261, trench 229 and shield electrode 21 do not pass all the way under gate pad 52. In another embodiment, structure 261 and shield electrode 21 pass all the way through gate pad 52. In yet another embodiment, gate pad 52 contacts gate electrode 28 at an edge portion 521 of gate pad 52, as shown in fig. 20.

Fig. 22 shows a partial top plan view of a slot shield structure 262 according to a second embodiment. Structure 262 is similar to structure 261 except that structure 262 is placed through a plurality of trenches 229 and shield electrodes 21 under or below gate pad 52 and gate runner 53 to further isolate gate pad 52 and gate runner 53 from semiconductor layer 14. In one embodiment of structure 262, contact to shield electrode 21 is made at shield electrode runners 64 and 66 as shown in fig. 22, shield electrode runners 64 and 66 further connecting to source metal 44. Structure 262 is configured to better isolate gate pad 52 and gate runner 53 from semiconductor region 11. In structure 262, a portion of trench 229 passes all the way through gate pad 52 or under at least a portion of gate pad 52. That is, in one embodiment, at least one trench 229 extends from at least one edge or side of gate pad 52 to another opposing edge of gate pad 52.

Fig. 23 shows a partial top plan view of a slot shield structure 263 according to a third embodiment. Structure 263 is similar to structure 261 except that structure 263 is placed through a plurality of trenches 229 and shield electrodes 21 under or below gate pad 52 and at least a portion of gate runner 56. In one embodiment, trench 229 and the portion of shield electrode 21 that is below gate runner 56 pass all the way under gate runner 56 or through gate runner 56. In another embodiment, trench 229 and the portion of shield electrode 21 under gate runner 56 pass only partially under gate runner 56. In another embodiment, a portion of gate runner 56 makes contact with gate electrode 28 at edge portion 568, as shown in FIG. 23. Structure 263 is configured to better isolate gate pad 52 and at least a portion of gate runner 56 from semiconductor layer 14. It is understood that one or a combination of structures 261, 262, and 263 may be used on devices 20 and 30, for example.

Fig. 24 illustrates a partial top plan view of structure 239 from device 20 shown in fig. 2. As shown in fig. 24, conductive layer 44 includes a portion 446 that wraps around end 561 of gate runner 56 and connects to shield electrode runner 66, where in shield electrode runner 66 contact is made with shield electrode 21. Fig. 24 further illustrates an example of the location of trenches 22 and gate electrodes 28 where contact between gate runner 56 and gate electrodes 28 is made. Further, fig. 24 shows trench 22, trench 22 having a stripe shape and extending in a direction from the active region to the contact region where conductive layer 44 is located, and gate runner 56 and shield runner 66 are located. It is understood that the attachment structures of fig. 17, 18, and 19 may be used for structure 239 individually or in combination. Structure 239 further illustrates embodiments that provide for the use of one metal layer to connect different structures.

In summary, a structure of a semiconductor device having a shield electrode is described. The structure includes a control pad, a control runner, a shield runner, and a control/shield electrode contact structure. The structure is configured to use a single layer of metal to connect various components together, which improves manufacturability. In another embodiment, the shield runners are placed offset from the center configuration to improve performance.

While the invention has been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to these illustrative embodiments. Those skilled in the art will recognize that changes and modifications may be made without departing from the spirit of the invention. It is therefore intended that the present invention include all such variations and modifications as fall within the scope of the appended claims.

Claims (6)

1. A semiconductor device structure, comprising:

a region of semiconductor material comprising a major surface, a first edge and an opposing second edge, and a first corner;

a first trench structure formed in an active region of a semiconductor device, wherein the first trench structure includes a first control electrode and a first shield electrode;

a first source region formed adjacent to the first trench structure in the active region;

a first contact structure formed adjacent to the first edge, wherein the first control electrode and the first shield electrode terminate in the first contact structure, and wherein the first trench structure extends from the active region to the first contact structure;

a control pad formed to cover the main surface;

a first control runner formed overlying the major surface and connected to the control pad and the first control electrode in the first contact arrangement, wherein the first control runner has a first end portion;

a first shield electrode runner formed overlying the major surface and connected to the first shield electrode in the first contact structure; and

a first conductive layer connected to the first source region in the active region and to the first shield electrode runner, wherein the first conductive layer further comprises a first portion surrounding the first end portion.

2. The structure of claim 1, wherein the control pad is formed adjacent to the first corner and the first edge, the semiconductor device structure further comprising a contact region for making contact to the first shield electrode in the active region, wherein the contact region is placed closer to the second edge than to the first edge.

3. The structure of claim 1, further comprising:

a second contact structure formed adjacent to the second edge, wherein the first shield electrode further extends from the active region to the second contact structure and terminates in the second contact structure;

a second control runner formed overlying the major surface and connected to the control pad and terminating in the second contact structure having a second end portion; and

a second shield electrode runner formed overlying the major surface and connected to the first shield electrode in the second contact configuration, wherein the first conductive layer is connected to the second shield electrode runner, and wherein the first conductive layer further includes a second portion surrounding the second end portion.

4. The structure of claim 1, further comprising a second control runner formed overlying the major surface, wherein the second control runner is connected to the control pad and is further connected to the first control runner at a location that is central to the semiconductor device structure.

5. A semiconductor device structure, comprising:

a region of semiconductor material comprising a major surface, a first edge and an opposing second edge, and a first corner;

a first trench structure formed in an active region of a semiconductor device, wherein the first trench structure includes a first control electrode and a first shield electrode;

a first source region formed adjacent to the first trench structure in the active region;

a first contact structure formed adjacent to the first edge, wherein the first control electrode and the first shield electrode terminate in the first contact structure, and wherein the first trench structure extends from the active region to the first contact structure;

a control pad formed to overlie the major surface adjacent the first corner and first edge;

a first control runner formed overlying the major surface and connected to the control pad and the first control electrode in the first contact arrangement, wherein the first control runner has a first end portion;

a first shield electrode runner formed overlying the major surface and connected to the first shield electrode in the first contact structure;

a first conductive layer connected to the first source region in the active region and to the first shield electrode runner, the first conductive layer further comprising a first portion surrounding the first end portion; and

a contact region for making contact to the first shield electrode in the active region, wherein the contact region is placed closer to the second edge than to the first edge.

6. The structure of claim 5, further comprising:

a second trench structure formed in an active region of the semiconductor device, wherein the second trench structure includes a second control electrode and a second shield electrode;

a second source region formed adjacent to the second trench structure in the active region;

a second contact structure formed adjacent to the second edge, wherein the second control electrode and the second shield electrode terminate in the second contact structure, and wherein the second trench structure extends from the active region to the second contact structure;

a second control runner formed overlying the major surface and connected to the control pad and the second control electrode in the second contact configuration, wherein the second control runner has a second end portion; and

a second shield electrode runner formed overlying the major surface and connected to the second shield electrode in the second contact structure, wherein the first conductive layer is connected to the second source region in the active region and to the second shield runner, and wherein the first conductive layer further includes a second portion surrounding the second end portion.